i386.c revision 1.46
1 /* $NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 155 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 156 * Architectures Software Developer's Manual, Volume 2A". 157 */ 158 static const char * const i386_intel_brand[] = { 159 "", /* Unsupported */ 160 "Celeron", /* Intel (R) Celeron (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 163 "Pentium III", /* Intel (R) Pentium (R) III processor */ 164 "", /* 0x05: Reserved */ 165 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Celeron", /* Intel (R) Celeron (TM) processor */ 170 "Xeon", /* Intel (R) Xeon (TM) processor */ 171 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 172 "", /* 0x0d: Reserved */ 173 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 174 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 175 "", /* 0x10: Reserved */ 176 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 177 "Celeron M", /* Intel (R) Celeron (R) M processor */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "Celeron", /* Intel (R) Celeron (R) processor */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Pentium M", /* Intel (R) Pentium (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 }; 184 185 /* 186 * AMD processors don't have Brand IDs, so we need these names for probe. 187 */ 188 static const char * const amd_brand[] = { 189 "", 190 "Duron", /* AMD Duron(tm) */ 191 "MP", /* AMD Athlon(tm) MP */ 192 "XP", /* AMD Athlon(tm) XP */ 193 "4" /* AMD Athlon(tm) 4 */ 194 }; 195 196 static int cpu_vendor; 197 static char cpu_brand_string[49]; 198 static char amd_brand_name[48]; 199 static int use_pae, largepagesize; 200 201 /* Setup functions */ 202 static void disable_tsc(struct cpu_info *); 203 static void amd_family5_setup(struct cpu_info *); /* alike cpu_probe_k5 */ 204 static void cyrix6x86_cpu_setup(struct cpu_info *); 205 static void winchip_cpu_setup(struct cpu_info *); 206 /* Brand/Model name functions */ 207 static const char *intel_family6_name(struct cpu_info *); 208 static const char *amd_amd64_name(struct cpu_info *); 209 /* Probe functions */ 210 static void amd_family6_probe(struct cpu_info *); 211 static void powernow_probe(struct cpu_info *); 212 static void intel_family_new_probe(struct cpu_info *); 213 static void via_cpu_probe(struct cpu_info *); 214 /* (Cache) Info functions */ 215 static void amd_cpu_cacheinfo(struct cpu_info *); /* alike */ 216 static void via_cpu_cacheinfo(struct cpu_info *); 217 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 218 static void transmeta_cpu_info(struct cpu_info *); 219 /* Common functions */ 220 static void cpu_probe_base_features(struct cpu_info *, const char *); 221 /* alike cpu_probe() */ 222 static void cpu_probe_features(struct cpu_info *); 223 static void print_bits(const char *, const char *, const char *, uint32_t); 224 /* XXX identifycpu alike cpu_identify */ 225 static void identifycpu_cpuids(struct cpu_info *); 226 static const char *print_cache_config(struct cpu_info *, int, const char *, 227 const char *); 228 static const char *print_tlb_config(struct cpu_info *, int, const char *, 229 const char *); 230 static const struct x86_cache_info *cache_info_lookup( /* XXX same */ 231 const struct x86_cache_info *, uint8_t); 232 static void x86_print_cacheinfo(struct cpu_info *); 233 234 /* 235 * Note: these are just the ones that may not have a cpuid instruction. 236 * We deal with the rest in a different way. 237 */ 238 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 239 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 240 NULL, NULL, NULL }, /* CPU_386SX */ 241 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 242 NULL, NULL, NULL }, /* CPU_386 */ 243 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 244 NULL, NULL, NULL }, /* CPU_486SX */ 245 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 246 NULL, NULL, NULL }, /* CPU_486 */ 247 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486DLC */ 249 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_6x86 */ 251 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 252 NULL, NULL, NULL }, /* CPU_NX586 */ 253 }; 254 255 const char *classnames[] = { 256 "386", 257 "486", 258 "586", 259 "686" 260 }; 261 262 const char *modifiers[] = { 263 "", 264 "OverDrive", 265 "Dual", 266 "" 267 }; 268 269 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 270 { 271 /* 272 * For Intel processors, check Chapter 35Model-specific 273 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 274 * Software Developer's Manual, Volume 3C". 275 */ 276 "GenuineIntel", 277 CPUVENDOR_INTEL, 278 "Intel", 279 /* Family 4 */ 280 { { 281 CPUCLASS_486, 282 { 283 "486DX", "486DX", "486SX", "486DX2", "486SL", 284 "486SX2", 0, "486DX2 W/B Enhanced", 285 "486DX4", 0, 0, 0, 0, 0, 0, 0, 286 }, 287 "486", /* Default */ 288 NULL, 289 NULL, 290 NULL, 291 }, 292 /* Family 5 */ 293 { 294 CPUCLASS_586, 295 { 296 "Pentium (P5 A-step)", "Pentium (P5)", 297 "Pentium (P54C)", "Pentium (P24T)", 298 "Pentium/MMX", "Pentium", 0, 299 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 300 0, 0, 0, 0, 0, 0, 0, 301 }, 302 "Pentium", /* Default */ 303 NULL, 304 NULL, 305 NULL, 306 }, 307 /* Family 6 */ 308 { 309 CPUCLASS_686, 310 { 311 [0x00] = "Pentium Pro (A-step)", 312 [0x01] = "Pentium Pro", 313 [0x03] = "Pentium II (Klamath)", 314 [0x04] = "Pentium Pro", 315 [0x05] = "Pentium II/Celeron (Deschutes)", 316 [0x06] = "Celeron (Mendocino)", 317 [0x07] = "Pentium III (Katmai)", 318 [0x08] = "Pentium III (Coppermine)", 319 [0x09] = "Pentium M (Banias)", 320 [0x0a] = "Pentium III Xeon (Cascades)", 321 [0x0b] = "Pentium III (Tualatin)", 322 [0x0d] = "Pentium M (Dothan)", 323 [0x0e] = "Pentium Core Duo, Core solo", 324 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 325 "Core 2 Quad 6xxx, " 326 "Core 2 Extreme 6xxx, " 327 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 328 "and Pentium DC", 329 [0x15] = "EP80579 Integrated Processor", 330 [0x16] = "Celeron (45nm)", 331 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 332 "Core 2 Quad 8xxx and 9xxx", 333 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 334 "(Nehalem)", 335 [0x1c] = "Atom Family", 336 [0x1d] = "XeonMP 74xx (Nehalem)", 337 [0x1e] = "Core i7 and i5", 338 [0x1f] = "Core i7 and i5", 339 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 340 [0x26] = "Atom Family", 341 [0x27] = "Atom Family", 342 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 343 "i3 2xxx", 344 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 345 [0x2d] = "Xeon E5 Sandy bridy family", 346 [0x2e] = "Xeon 75xx & 65xx", 347 [0x2f] = "Xeon E7 family", 348 [0x35] = "Atom Family", 349 [0x36] = "Atom S1000", 350 [0x37] = "Atom C2000, E3000", 351 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 352 "Ivy bridge", 353 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 354 "(Haswell)", 355 [0x3d] = "Next gen Core", 356 [0x3e] = "Next gen Xeon E5/E7, Ivy bridge", 357 [0x3f] = "Future gen Xeon", 358 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 359 "(Haswell)", 360 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 361 "(Haswell)", 362 [0x4d] = "Atom C2000, E3000", 363 }, 364 "Pentium Pro, II or III", /* Default */ 365 NULL, 366 intel_family_new_probe, 367 NULL, 368 }, 369 /* Family > 6 */ 370 { 371 CPUCLASS_686, 372 { 373 0, 0, 0, 0, 0, 0, 0, 0, 374 0, 0, 0, 0, 0, 0, 0, 0, 375 }, 376 "Pentium 4", /* Default */ 377 NULL, 378 intel_family_new_probe, 379 NULL, 380 } } 381 }, 382 { 383 "AuthenticAMD", 384 CPUVENDOR_AMD, 385 "AMD", 386 /* Family 4 */ 387 { { 388 CPUCLASS_486, 389 { 390 0, 0, 0, "Am486DX2 W/T", 391 0, 0, 0, "Am486DX2 W/B", 392 "Am486DX4 W/T or Am5x86 W/T 150", 393 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 394 0, 0, "Am5x86 W/T 133/160", 395 "Am5x86 W/B 133/160", 396 }, 397 "Am486 or Am5x86", /* Default */ 398 NULL, 399 NULL, 400 NULL, 401 }, 402 /* Family 5 */ 403 { 404 CPUCLASS_586, 405 { 406 "K5", "K5", "K5", "K5", 0, 0, "K6", 407 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 408 "K6-2+/III+", 0, 0, 409 }, 410 "K5 or K6", /* Default */ 411 amd_family5_setup, 412 NULL, 413 amd_cpu_cacheinfo, 414 }, 415 /* Family 6 */ 416 { 417 CPUCLASS_686, 418 { 419 0, "Athlon Model 1", "Athlon Model 2", 420 "Duron", "Athlon Model 4 (Thunderbird)", 421 0, "Athlon", "Duron", "Athlon", 0, 422 "Athlon", 0, 0, 0, 0, 0, 423 }, 424 "K7 (Athlon)", /* Default */ 425 NULL, 426 amd_family6_probe, 427 amd_cpu_cacheinfo, 428 }, 429 /* Family > 6 */ 430 { 431 CPUCLASS_686, 432 { 433 0, 0, 0, 0, 0, 0, 0, 0, 434 0, 0, 0, 0, 0, 0, 0, 0, 435 }, 436 "Unknown K8 (Athlon)", /* Default */ 437 NULL, 438 amd_family6_probe, 439 amd_cpu_cacheinfo, 440 } } 441 }, 442 { 443 "CyrixInstead", 444 CPUVENDOR_CYRIX, 445 "Cyrix", 446 /* Family 4 */ 447 { { 448 CPUCLASS_486, 449 { 450 0, 0, 0, 451 "MediaGX", 452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 453 }, 454 "486", /* Default */ 455 cyrix6x86_cpu_setup, /* XXX ?? */ 456 NULL, 457 NULL, 458 }, 459 /* Family 5 */ 460 { 461 CPUCLASS_586, 462 { 463 0, 0, "6x86", 0, 464 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 466 }, 467 "6x86", /* Default */ 468 cyrix6x86_cpu_setup, 469 NULL, 470 NULL, 471 }, 472 /* Family 6 */ 473 { 474 CPUCLASS_686, 475 { 476 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 477 0, 0, 0, 0, 0, 0, 0, 0, 478 }, 479 "6x86MX", /* Default */ 480 cyrix6x86_cpu_setup, 481 NULL, 482 NULL, 483 }, 484 /* Family > 6 */ 485 { 486 CPUCLASS_686, 487 { 488 0, 0, 0, 0, 0, 0, 0, 0, 489 0, 0, 0, 0, 0, 0, 0, 0, 490 }, 491 "Unknown 6x86MX", /* Default */ 492 NULL, 493 NULL, 494 NULL, 495 } } 496 }, 497 { /* MediaGX is now owned by National Semiconductor */ 498 "Geode by NSC", 499 CPUVENDOR_CYRIX, /* XXX */ 500 "National Semiconductor", 501 /* Family 4, NSC never had any of these */ 502 { { 503 CPUCLASS_486, 504 { 505 0, 0, 0, 0, 0, 0, 0, 0, 506 0, 0, 0, 0, 0, 0, 0, 0, 507 }, 508 "486 compatible", /* Default */ 509 NULL, 510 NULL, 511 NULL, 512 }, 513 /* Family 5: Geode family, formerly MediaGX */ 514 { 515 CPUCLASS_586, 516 { 517 0, 0, 0, 0, 518 "Geode GX1", 519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 520 }, 521 "Geode", /* Default */ 522 cyrix6x86_cpu_setup, 523 NULL, 524 amd_cpu_cacheinfo, 525 }, 526 /* Family 6, not yet available from NSC */ 527 { 528 CPUCLASS_686, 529 { 530 0, 0, 0, 0, 0, 0, 0, 0, 531 0, 0, 0, 0, 0, 0, 0, 0, 532 }, 533 "Pentium Pro compatible", /* Default */ 534 NULL, 535 NULL, 536 NULL, 537 }, 538 /* Family > 6, not yet available from NSC */ 539 { 540 CPUCLASS_686, 541 { 542 0, 0, 0, 0, 0, 0, 0, 0, 543 0, 0, 0, 0, 0, 0, 0, 0, 544 }, 545 "Pentium Pro compatible", /* Default */ 546 NULL, 547 NULL, 548 NULL, 549 } } 550 }, 551 { 552 "CentaurHauls", 553 CPUVENDOR_IDT, 554 "IDT", 555 /* Family 4, IDT never had any of these */ 556 { { 557 CPUCLASS_486, 558 { 559 0, 0, 0, 0, 0, 0, 0, 0, 560 0, 0, 0, 0, 0, 0, 0, 0, 561 }, 562 "486 compatible", /* Default */ 563 NULL, 564 NULL, 565 NULL, 566 }, 567 /* Family 5 */ 568 { 569 CPUCLASS_586, 570 { 571 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 572 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 573 }, 574 "WinChip", /* Default */ 575 winchip_cpu_setup, 576 NULL, 577 NULL, 578 }, 579 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 580 { 581 CPUCLASS_686, 582 { 583 0, 0, 0, 0, 0, 0, "C3 Samuel", 584 "C3 Samuel 2/Ezra", "C3 Ezra-T", 585 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 586 0, "VIA Nano", 587 }, 588 "Unknown VIA/IDT", /* Default */ 589 NULL, 590 via_cpu_probe, 591 via_cpu_cacheinfo, 592 }, 593 /* Family > 6, not yet available from VIA */ 594 { 595 CPUCLASS_686, 596 { 597 0, 0, 0, 0, 0, 0, 0, 0, 598 0, 0, 0, 0, 0, 0, 0, 0, 599 }, 600 "Pentium Pro compatible", /* Default */ 601 NULL, 602 NULL, 603 NULL, 604 } } 605 }, 606 { 607 "GenuineTMx86", 608 CPUVENDOR_TRANSMETA, 609 "Transmeta", 610 /* Family 4, Transmeta never had any of these */ 611 { { 612 CPUCLASS_486, 613 { 614 0, 0, 0, 0, 0, 0, 0, 0, 615 0, 0, 0, 0, 0, 0, 0, 0, 616 }, 617 "486 compatible", /* Default */ 618 NULL, 619 NULL, 620 NULL, 621 }, 622 /* Family 5 */ 623 { 624 CPUCLASS_586, 625 { 626 0, 0, 0, 0, 0, 0, 0, 0, 627 0, 0, 0, 0, 0, 0, 0, 0, 628 }, 629 "Crusoe", /* Default */ 630 NULL, 631 NULL, 632 transmeta_cpu_info, 633 }, 634 /* Family 6, not yet available from Transmeta */ 635 { 636 CPUCLASS_686, 637 { 638 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 640 }, 641 "Pentium Pro compatible", /* Default */ 642 NULL, 643 NULL, 644 NULL, 645 }, 646 /* Family > 6, not yet available from Transmeta */ 647 { 648 CPUCLASS_686, 649 { 650 0, 0, 0, 0, 0, 0, 0, 0, 651 0, 0, 0, 0, 0, 0, 0, 0, 652 }, 653 "Pentium Pro compatible", /* Default */ 654 NULL, 655 NULL, 656 NULL, 657 } } 658 } 659 }; 660 661 /* 662 * disable the TSC such that we don't use the TSC in microtime(9) 663 * because some CPUs got the implementation wrong. 664 */ 665 static void 666 disable_tsc(struct cpu_info *ci) 667 { 668 if (ci->ci_feat_val[0] & CPUID_TSC) { 669 ci->ci_feat_val[0] &= ~CPUID_TSC; 670 aprint_error("WARNING: broken TSC disabled\n"); 671 } 672 } 673 674 static void 675 amd_family5_setup(struct cpu_info *ci) 676 { 677 678 switch (ci->ci_model) { 679 case 0: /* AMD-K5 Model 0 */ 680 /* 681 * According to the AMD Processor Recognition App Note, 682 * the AMD-K5 Model 0 uses the wrong bit to indicate 683 * support for global PTEs, instead using bit 9 (APIC) 684 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 685 */ 686 if (ci->ci_feat_val[0] & CPUID_APIC) 687 ci->ci_feat_val[0] = 688 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 689 /* 690 * XXX But pmap_pg_g is already initialized -- need to kick 691 * XXX the pmap somehow. How does the MP branch do this? 692 */ 693 break; 694 } 695 } 696 697 static void 698 cyrix6x86_cpu_setup(struct cpu_info *ci) 699 { 700 701 /* 702 * Do not disable the TSC on the Geode GX, it's reported to 703 * work fine. 704 */ 705 if (ci->ci_signature != 0x552) 706 disable_tsc(ci); 707 } 708 709 static void 710 winchip_cpu_setup(struct cpu_info *ci) 711 { 712 switch (ci->ci_model) { 713 case 4: /* WinChip C6 */ 714 disable_tsc(ci); 715 } 716 } 717 718 719 static const char * 720 intel_family6_name(struct cpu_info *ci) 721 { 722 const char *ret = NULL; 723 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 724 725 if (ci->ci_model == 5) { 726 switch (l2cache) { 727 case 0: 728 case 128 * 1024: 729 ret = "Celeron (Covington)"; 730 break; 731 case 256 * 1024: 732 ret = "Mobile Pentium II (Dixon)"; 733 break; 734 case 512 * 1024: 735 ret = "Pentium II"; 736 break; 737 case 1 * 1024 * 1024: 738 case 2 * 1024 * 1024: 739 ret = "Pentium II Xeon"; 740 break; 741 } 742 } else if (ci->ci_model == 6) { 743 switch (l2cache) { 744 case 256 * 1024: 745 case 512 * 1024: 746 ret = "Mobile Pentium II"; 747 break; 748 } 749 } else if (ci->ci_model == 7) { 750 switch (l2cache) { 751 case 512 * 1024: 752 ret = "Pentium III"; 753 break; 754 case 1 * 1024 * 1024: 755 case 2 * 1024 * 1024: 756 ret = "Pentium III Xeon"; 757 break; 758 } 759 } else if (ci->ci_model >= 8) { 760 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 761 switch (ci->ci_brand_id) { 762 case 0x3: 763 if (ci->ci_signature == 0x6B1) 764 ret = "Celeron"; 765 break; 766 case 0x8: 767 if (ci->ci_signature >= 0xF13) 768 ret = "genuine processor"; 769 break; 770 case 0xB: 771 if (ci->ci_signature >= 0xF13) 772 ret = "Xeon MP"; 773 break; 774 case 0xE: 775 if (ci->ci_signature < 0xF13) 776 ret = "Xeon"; 777 break; 778 } 779 if (ret == NULL) 780 ret = i386_intel_brand[ci->ci_brand_id]; 781 } 782 } 783 784 return ret; 785 } 786 787 /* 788 * Identify AMD64 CPU names from cpuid. 789 * 790 * Based on: 791 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 792 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 793 * "Revision Guide for AMD NPT Family 0Fh Processors" 794 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 795 * and other miscellaneous reports. 796 * 797 * This is all rather pointless, these are cross 'brand' since the raw 798 * silicon is shared. 799 */ 800 static const char * 801 amd_amd64_name(struct cpu_info *ci) 802 { 803 static char family_str[32]; 804 805 /* Only called if family >= 15 */ 806 807 switch (ci->ci_family) { 808 case 15: 809 switch (ci->ci_model) { 810 case 0x21: /* rev JH-E1/E6 */ 811 case 0x41: /* rev JH-F2 */ 812 return "Dual-Core Opteron"; 813 case 0x23: /* rev JH-E6 (Toledo) */ 814 return "Dual-Core Opteron or Athlon 64 X2"; 815 case 0x43: /* rev JH-F2 (Windsor) */ 816 return "Athlon 64 FX or Athlon 64 X2"; 817 case 0x24: /* rev SH-E5 (Lancaster?) */ 818 return "Mobile Athlon 64 or Turion 64"; 819 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 820 return "Opteron or Athlon 64 FX"; 821 case 0x15: /* rev SH-D0 */ 822 case 0x25: /* rev SH-E4 */ 823 return "Opteron"; 824 case 0x27: /* rev DH-E4, SH-E4 */ 825 return "Athlon 64 or Athlon 64 FX or Opteron"; 826 case 0x48: /* rev BH-F2 */ 827 return "Turion 64 X2"; 828 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 829 case 0x07: /* rev SH-CG (ClawHammer) */ 830 case 0x0b: /* rev CH-CG */ 831 case 0x14: /* rev SH-D0 */ 832 case 0x17: /* rev SH-D0 */ 833 case 0x1b: /* rev CH-D0 */ 834 return "Athlon 64"; 835 case 0x2b: /* rev BH-E4 (Manchester) */ 836 case 0x4b: /* rev BH-F2 (Windsor) */ 837 return "Athlon 64 X2"; 838 case 0x6b: /* rev BH-G1 (Brisbane) */ 839 return "Athlon X2 or Athlon 64 X2"; 840 case 0x08: /* rev CH-CG */ 841 case 0x0c: /* rev DH-CG (Newcastle) */ 842 case 0x0e: /* rev DH-CG (Newcastle?) */ 843 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 844 case 0x18: /* rev CH-D0 */ 845 case 0x1c: /* rev DH-D0 (Winchester) */ 846 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 847 case 0x2c: /* rev DH-E3/E6 */ 848 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 849 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 850 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 851 case 0x6f: /* rev DH-G1 */ 852 return "Athlon 64 or Sempron"; 853 default: 854 break; 855 } 856 return "Unknown AMD64 CPU"; 857 858 #if 0 859 case 16: 860 return "Family 10h"; 861 case 17: 862 return "Family 11h"; 863 case 18: 864 return "Family 12h"; 865 case 19: 866 return "Family 14h"; 867 case 20: 868 return "Family 15h"; 869 #endif 870 871 default: 872 break; 873 } 874 875 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 876 return family_str; 877 } 878 879 static void 880 intel_family_new_probe(struct cpu_info *ci) 881 { 882 uint32_t descs[4]; 883 884 x86_cpuid(0x80000000, descs); 885 886 /* 887 * Determine extended feature flags. 888 */ 889 if (descs[0] >= 0x80000001) { 890 x86_cpuid(0x80000001, descs); 891 ci->ci_feat_val[2] |= descs[3]; 892 ci->ci_feat_val[3] |= descs[2]; 893 } 894 } 895 896 static void 897 via_cpu_probe(struct cpu_info *ci) 898 { 899 u_int stepping = CPUID2STEPPING(ci->ci_signature); 900 u_int descs[4]; 901 u_int lfunc; 902 903 /* 904 * Determine the largest extended function value. 905 */ 906 x86_cpuid(0x80000000, descs); 907 lfunc = descs[0]; 908 909 /* 910 * Determine the extended feature flags. 911 */ 912 if (lfunc >= 0x80000001) { 913 x86_cpuid(0x80000001, descs); 914 ci->ci_feat_val[2] |= descs[3]; 915 } 916 917 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 918 return; 919 920 /* Nehemiah or Esther */ 921 x86_cpuid(0xc0000000, descs); 922 lfunc = descs[0]; 923 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 924 return; 925 926 x86_cpuid(0xc0000001, descs); 927 lfunc = descs[3]; 928 ci->ci_feat_val[4] = lfunc; 929 } 930 931 static void 932 amd_family6_probe(struct cpu_info *ci) 933 { 934 uint32_t descs[4]; 935 char *p; 936 size_t i; 937 938 x86_cpuid(0x80000000, descs); 939 940 /* 941 * Determine the extended feature flags. 942 */ 943 if (descs[0] >= 0x80000001) { 944 x86_cpuid(0x80000001, descs); 945 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 946 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 947 } 948 949 if (*cpu_brand_string == '\0') 950 return; 951 952 for (i = 1; i < __arraycount(amd_brand); i++) 953 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 954 ci->ci_brand_id = i; 955 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 956 break; 957 } 958 } 959 960 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 961 AMD_L2CACHE_INFO; 962 963 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 964 AMD_L3CACHE_INFO; 965 966 static void 967 amd_cpu_cacheinfo(struct cpu_info *ci) 968 { 969 const struct x86_cache_info *cp; 970 struct x86_cache_info *cai; 971 u_int descs[4]; 972 u_int lfunc; 973 974 /* 975 * K5 model 0 has none of this info. 976 */ 977 if (ci->ci_family == 5 && ci->ci_model == 0) 978 return; 979 980 /* 981 * Determine the largest extended function value. 982 */ 983 x86_cpuid(0x80000000, descs); 984 lfunc = descs[0]; 985 986 /* 987 * Determine L1 cache/TLB info. 988 */ 989 if (lfunc < 0x80000005) { 990 /* No L1 cache info available. */ 991 return; 992 } 993 994 x86_cpuid(0x80000005, descs); 995 996 /* 997 * K6-III and higher have large page TLBs. 998 */ 999 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1000 cai = &ci->ci_cinfo[CAI_ITLB2]; 1001 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1002 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1003 cai->cai_linesize = largepagesize; 1004 1005 cai = &ci->ci_cinfo[CAI_DTLB2]; 1006 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1007 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1008 cai->cai_linesize = largepagesize; 1009 } 1010 1011 cai = &ci->ci_cinfo[CAI_ITLB]; 1012 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1013 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1014 cai->cai_linesize = (4 * 1024); 1015 1016 cai = &ci->ci_cinfo[CAI_DTLB]; 1017 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1018 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1019 cai->cai_linesize = (4 * 1024); 1020 1021 cai = &ci->ci_cinfo[CAI_DCACHE]; 1022 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1023 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1024 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1025 1026 cai = &ci->ci_cinfo[CAI_ICACHE]; 1027 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1028 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1029 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1030 1031 /* 1032 * Determine L2 cache/TLB info. 1033 */ 1034 if (lfunc < 0x80000006) { 1035 /* No L2 cache info available. */ 1036 return; 1037 } 1038 1039 x86_cpuid(0x80000006, descs); 1040 1041 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1042 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1043 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1044 cai->cai_linesize = (4 * 1024); 1045 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1046 cai->cai_associativity); 1047 if (cp != NULL) 1048 cai->cai_associativity = cp->cai_associativity; 1049 else 1050 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1051 1052 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1053 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1054 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1055 cai->cai_linesize = largepagesize; 1056 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1057 cai->cai_associativity); 1058 if (cp != NULL) 1059 cai->cai_associativity = cp->cai_associativity; 1060 else 1061 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1062 1063 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1064 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1065 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1066 cai->cai_linesize = (4 * 1024); 1067 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1068 cai->cai_associativity); 1069 if (cp != NULL) 1070 cai->cai_associativity = cp->cai_associativity; 1071 else 1072 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1073 1074 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1075 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1076 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1077 cai->cai_linesize = largepagesize; 1078 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1079 cai->cai_associativity); 1080 if (cp != NULL) 1081 cai->cai_associativity = cp->cai_associativity; 1082 else 1083 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1084 1085 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1086 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1087 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1088 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1089 1090 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1091 cai->cai_associativity); 1092 if (cp != NULL) 1093 cai->cai_associativity = cp->cai_associativity; 1094 else 1095 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1096 1097 /* 1098 * Determine L3 cache info on AMD Family 10h and newer processors 1099 */ 1100 if (ci->ci_family >= 0x10) { 1101 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1102 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1103 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1104 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1105 1106 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1107 cai->cai_associativity); 1108 if (cp != NULL) 1109 cai->cai_associativity = cp->cai_associativity; 1110 else 1111 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1112 } 1113 1114 /* 1115 * Determine 1GB TLB info. 1116 */ 1117 if (lfunc < 0x80000019) { 1118 /* No 1GB TLB info available. */ 1119 return; 1120 } 1121 1122 x86_cpuid(0x80000019, descs); 1123 1124 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1125 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1126 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1127 cai->cai_linesize = (1024 * 1024 * 1024); 1128 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1129 cai->cai_associativity); 1130 if (cp != NULL) 1131 cai->cai_associativity = cp->cai_associativity; 1132 else 1133 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1134 1135 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1136 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1137 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1138 cai->cai_linesize = (1024 * 1024 * 1024); 1139 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1140 cai->cai_associativity); 1141 if (cp != NULL) 1142 cai->cai_associativity = cp->cai_associativity; 1143 else 1144 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1145 1146 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1147 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1148 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1149 cai->cai_linesize = (1024 * 1024 * 1024); 1150 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1151 cai->cai_associativity); 1152 if (cp != NULL) 1153 cai->cai_associativity = cp->cai_associativity; 1154 else 1155 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1156 1157 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1158 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1159 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1160 cai->cai_linesize = (1024 * 1024 * 1024); 1161 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1162 cai->cai_associativity); 1163 if (cp != NULL) 1164 cai->cai_associativity = cp->cai_associativity; 1165 else 1166 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1167 } 1168 1169 static void 1170 via_cpu_cacheinfo(struct cpu_info *ci) 1171 { 1172 struct x86_cache_info *cai; 1173 int stepping; 1174 u_int descs[4]; 1175 u_int lfunc; 1176 1177 stepping = CPUID2STEPPING(ci->ci_signature); 1178 1179 /* 1180 * Determine the largest extended function value. 1181 */ 1182 x86_cpuid(0x80000000, descs); 1183 lfunc = descs[0]; 1184 1185 /* 1186 * Determine L1 cache/TLB info. 1187 */ 1188 if (lfunc < 0x80000005) { 1189 /* No L1 cache info available. */ 1190 return; 1191 } 1192 1193 x86_cpuid(0x80000005, descs); 1194 1195 cai = &ci->ci_cinfo[CAI_ITLB]; 1196 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1197 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1198 cai->cai_linesize = (4 * 1024); 1199 1200 cai = &ci->ci_cinfo[CAI_DTLB]; 1201 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1202 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1203 cai->cai_linesize = (4 * 1024); 1204 1205 cai = &ci->ci_cinfo[CAI_DCACHE]; 1206 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1207 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1208 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1209 if (ci->ci_model == 9 && stepping == 8) { 1210 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1211 cai->cai_associativity = 2; 1212 } 1213 1214 cai = &ci->ci_cinfo[CAI_ICACHE]; 1215 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1216 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1217 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1218 if (ci->ci_model == 9 && stepping == 8) { 1219 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1220 cai->cai_associativity = 2; 1221 } 1222 1223 /* 1224 * Determine L2 cache/TLB info. 1225 */ 1226 if (lfunc < 0x80000006) { 1227 /* No L2 cache info available. */ 1228 return; 1229 } 1230 1231 x86_cpuid(0x80000006, descs); 1232 1233 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1234 if (ci->ci_model >= 9) { 1235 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1236 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1237 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1238 } else { 1239 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1240 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1241 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1242 } 1243 } 1244 1245 static void 1246 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1247 { 1248 u_int descs[4]; 1249 1250 x86_cpuid(0x80860007, descs); 1251 *frequency = descs[0]; 1252 *voltage = descs[1]; 1253 *percentage = descs[2]; 1254 } 1255 1256 static void 1257 transmeta_cpu_info(struct cpu_info *ci) 1258 { 1259 u_int descs[4], nreg; 1260 u_int frequency, voltage, percentage; 1261 1262 x86_cpuid(0x80860000, descs); 1263 nreg = descs[0]; 1264 if (nreg >= 0x80860001) { 1265 x86_cpuid(0x80860001, descs); 1266 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1267 (descs[1] >> 24) & 0xff, 1268 (descs[1] >> 16) & 0xff, 1269 (descs[1] >> 8) & 0xff, 1270 descs[1] & 0xff); 1271 } 1272 if (nreg >= 0x80860002) { 1273 x86_cpuid(0x80860002, descs); 1274 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1275 (descs[1] >> 24) & 0xff, 1276 (descs[1] >> 16) & 0xff, 1277 (descs[1] >> 8) & 0xff, 1278 descs[1] & 0xff, 1279 descs[2]); 1280 } 1281 if (nreg >= 0x80860006) { 1282 union { 1283 char text[65]; 1284 u_int descs[4][4]; 1285 } info; 1286 int i; 1287 1288 for (i=0; i<4; i++) { 1289 x86_cpuid(0x80860003 + i, info.descs[i]); 1290 } 1291 info.text[64] = '\0'; 1292 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1293 } 1294 1295 if (nreg >= 0x80860007) { 1296 tmx86_get_longrun_status(&frequency, 1297 &voltage, &percentage); 1298 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1299 frequency, voltage, percentage); 1300 } 1301 } 1302 1303 static void 1304 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1305 { 1306 const struct x86_cache_info *cai; 1307 u_int descs[4]; 1308 int iterations, i, j; 1309 int type, level; 1310 int ways, partitions, linesize, sets; 1311 int caitype = -1; 1312 int totalsize; 1313 uint8_t desc; 1314 uint32_t brand[12]; 1315 1316 memset(ci, 0, sizeof(*ci)); 1317 ci->ci_dev = cpuname; 1318 1319 ci->ci_cpu_type = x86_identify(); 1320 if (ci->ci_cpu_type >= 0) { 1321 /* Old pre-cpuid instruction cpu */ 1322 ci->ci_cpuid_level = -1; 1323 return; 1324 } 1325 1326 x86_cpuid(0, descs); 1327 ci->ci_cpuid_level = descs[0]; 1328 ci->ci_vendor[0] = descs[1]; 1329 ci->ci_vendor[2] = descs[2]; 1330 ci->ci_vendor[1] = descs[3]; 1331 ci->ci_vendor[3] = 0; 1332 1333 x86_cpuid(0x80000000, brand); 1334 if (brand[0] >= 0x80000004) { 1335 x86_cpuid(0x80000002, brand); 1336 x86_cpuid(0x80000003, brand + 4); 1337 x86_cpuid(0x80000004, brand + 8); 1338 for (i = 0; i < 48; i++) 1339 if (((char *) brand)[i] != ' ') 1340 break; 1341 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1342 } 1343 1344 if (ci->ci_cpuid_level < 1) 1345 return; 1346 1347 x86_cpuid(1, descs); 1348 ci->ci_signature = descs[0]; 1349 1350 /* Extract full family/model values */ 1351 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 1352 ci->ci_model = CPUID2MODEL(ci->ci_signature); 1353 if (ci->ci_family == 15) 1354 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 1355 if (ci->ci_family == 6 || ci->ci_family == 15) 1356 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 1357 1358 /* Brand is low order 8 bits of ebx */ 1359 ci->ci_brand_id = descs[1] & 0xff; 1360 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1361 1362 ci->ci_feat_val[1] = descs[2]; 1363 ci->ci_feat_val[0] = descs[3]; 1364 1365 if (ci->ci_cpuid_level < 2) 1366 return; 1367 1368 /* 1369 * Parse the cache info from `cpuid leaf 2', if we have it. 1370 * XXX This is kinda ugly, but hey, so is the architecture... 1371 */ 1372 1373 x86_cpuid(2, descs); 1374 1375 iterations = descs[0] & 0xff; 1376 while (iterations-- > 0) { 1377 for (i = 0; i < 4; i++) { 1378 if (descs[i] & 0x80000000) 1379 continue; 1380 for (j = 0; j < 4; j++) { 1381 if (i == 0 && j == 0) 1382 continue; 1383 desc = (descs[i] >> (j * 8)) & 0xff; 1384 if (desc == 0) 1385 continue; 1386 cai = cache_info_lookup(intel_cpuid_cache_info, 1387 desc); 1388 if (cai != NULL) 1389 ci->ci_cinfo[cai->cai_index] = *cai; 1390 } 1391 } 1392 x86_cpuid(2, descs); 1393 } 1394 1395 if (ci->ci_cpuid_level < 3) 1396 return; 1397 1398 /* 1399 * If the processor serial number misfeature is present and supported, 1400 * extract it here. 1401 */ 1402 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1403 ci->ci_cpu_serial[0] = ci->ci_signature; 1404 x86_cpuid(3, descs); 1405 ci->ci_cpu_serial[2] = descs[2]; 1406 ci->ci_cpu_serial[1] = descs[3]; 1407 } 1408 1409 if (ci->ci_cpuid_level < 4) 1410 return; 1411 1412 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1413 for (i = 0; ; i++) { 1414 x86_cpuid2(4, i, descs); 1415 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1416 if (type == CPUID_DCP_CACHETYPE_N) 1417 break; 1418 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1419 switch (level) { 1420 case 1: 1421 if (type == CPUID_DCP_CACHETYPE_I) 1422 caitype = CAI_ICACHE; 1423 else if (type == CPUID_DCP_CACHETYPE_D) 1424 caitype = CAI_DCACHE; 1425 else 1426 caitype = -1; 1427 break; 1428 case 2: 1429 if (type == CPUID_DCP_CACHETYPE_U) 1430 caitype = CAI_L2CACHE; 1431 else 1432 caitype = -1; 1433 break; 1434 case 3: 1435 if (type == CPUID_DCP_CACHETYPE_U) 1436 caitype = CAI_L3CACHE; 1437 else 1438 caitype = -1; 1439 break; 1440 default: 1441 caitype = -1; 1442 break; 1443 } 1444 if (caitype == -1) { 1445 printf("unknown cache level&type (%d & %d)\n", 1446 level, type); 1447 continue; 1448 } 1449 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1450 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1451 + 1; 1452 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1453 + 1; 1454 sets = descs[2] + 1; 1455 totalsize = ways * partitions * linesize * sets; 1456 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1457 ci->ci_cinfo[caitype].cai_associativity = ways; 1458 ci->ci_cinfo[caitype].cai_linesize = linesize; 1459 } 1460 1461 if (ci->ci_cpuid_level < 0xd) 1462 return; 1463 1464 /* Get support XCR0 bits */ 1465 x86_cpuid2(0xd, 0, descs); 1466 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1467 ci->ci_cur_xsave = descs[1]; 1468 ci->ci_max_xsave = descs[2]; 1469 1470 /* Additional flags (eg xsaveopt support) */ 1471 x86_cpuid2(0xd, 1, descs); 1472 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1473 } 1474 1475 static void 1476 cpu_probe_features(struct cpu_info *ci) 1477 { 1478 const struct cpu_cpuid_nameclass *cpup = NULL; 1479 unsigned int i; 1480 1481 if (ci->ci_cpuid_level < 1) 1482 return; 1483 1484 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1485 if (!strncmp((char *)ci->ci_vendor, 1486 i386_cpuid_cpus[i].cpu_id, 12)) { 1487 cpup = &i386_cpuid_cpus[i]; 1488 break; 1489 } 1490 } 1491 1492 if (cpup == NULL) 1493 return; 1494 1495 i = ci->ci_family - CPU_MINFAMILY; 1496 1497 if (i >= __arraycount(cpup->cpu_family)) 1498 i = __arraycount(cpup->cpu_family) - 1; 1499 1500 if (cpup->cpu_family[i].cpu_probe == NULL) 1501 return; 1502 1503 (*cpup->cpu_family[i].cpu_probe)(ci); 1504 } 1505 1506 static void 1507 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1508 { 1509 char buf[32 * 16]; 1510 char *bp; 1511 1512 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1513 1514 if (val == 0 || fmt == NULL) 1515 return; 1516 1517 snprintb_m(buf, sizeof(buf), fmt, val, 1518 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1519 bp = buf; 1520 while (*bp != '\0') { 1521 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1522 bp += strlen(bp) + 1; 1523 } 1524 } 1525 1526 static void 1527 identifycpu_cpuids(struct cpu_info *ci) 1528 { 1529 const char *cpuname = ci->ci_dev; 1530 u_int lp_max = 1; /* logical processors per package */ 1531 u_int smt_max; /* smt per core */ 1532 u_int core_max = 1; /* core per package */ 1533 u_int smt_bits, core_bits; 1534 uint32_t descs[4]; 1535 uint32_t highest_basic_info; 1536 1537 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1538 ci->ci_packageid = ci->ci_initapicid; 1539 ci->ci_coreid = 0; 1540 ci->ci_smtid = 0; 1541 if (cpu_vendor != CPUVENDOR_INTEL) { 1542 return; 1543 } 1544 1545 /* 1546 * 253668.pdf 7.10.2 1547 */ 1548 1549 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1550 x86_cpuid(1, descs); 1551 lp_max = (descs[1] >> 16) & 0xff; 1552 } 1553 x86_cpuid(0, descs); 1554 highest_basic_info = descs[0]; 1555 if (highest_basic_info >= 4) { 1556 x86_cpuid2(4, 0, descs); 1557 core_max = (descs[0] >> 26) + 1; 1558 } 1559 assert(lp_max >= core_max); 1560 smt_max = lp_max / core_max; 1561 smt_bits = ilog2(smt_max - 1) + 1; 1562 core_bits = ilog2(core_max - 1) + 1; 1563 if (smt_bits + core_bits) { 1564 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1565 } 1566 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1567 ci->ci_packageid); 1568 if (core_bits) { 1569 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1570 1571 ci->ci_coreid = 1572 __SHIFTOUT(ci->ci_initapicid, core_mask); 1573 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1574 } 1575 if (smt_bits) { 1576 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1577 1578 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1579 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1580 } 1581 } 1582 1583 void 1584 identifycpu(int fd, const char *cpuname) 1585 { 1586 const char *name = "", *modifier, *vendorname, *brand = ""; 1587 int class = CPUCLASS_386; 1588 unsigned int i; 1589 int modif, family; 1590 const struct cpu_cpuid_nameclass *cpup = NULL; 1591 const struct cpu_cpuid_family *cpufam; 1592 struct cpu_info *ci, cistore; 1593 size_t sz; 1594 struct cpu_ucode_version ucode; 1595 union { 1596 struct cpu_ucode_version_amd amd; 1597 struct cpu_ucode_version_intel1 intel1; 1598 } ucvers; 1599 1600 ci = &cistore; 1601 cpu_probe_base_features(ci, cpuname); 1602 cpu_probe_features(ci); 1603 1604 if (ci->ci_cpu_type >= 0) { 1605 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1606 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1607 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1608 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1609 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1610 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1611 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1612 modifier = ""; 1613 } else { 1614 modif = (ci->ci_signature >> 12) & 0x3; 1615 family = ci->ci_family; 1616 if (family < CPU_MINFAMILY) 1617 errx(1, "identifycpu: strange family value"); 1618 if (family > CPU_MAXFAMILY) 1619 family = CPU_MAXFAMILY; 1620 1621 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1622 if (!strncmp((char *)ci->ci_vendor, 1623 i386_cpuid_cpus[i].cpu_id, 12)) { 1624 cpup = &i386_cpuid_cpus[i]; 1625 break; 1626 } 1627 } 1628 1629 if (cpup == NULL) { 1630 cpu_vendor = CPUVENDOR_UNKNOWN; 1631 if (ci->ci_vendor[0] != '\0') 1632 vendorname = (char *)&ci->ci_vendor[0]; 1633 else 1634 vendorname = "Unknown"; 1635 class = family - 3; 1636 modifier = ""; 1637 name = ""; 1638 ci->ci_info = NULL; 1639 } else { 1640 cpu_vendor = cpup->cpu_vendor; 1641 vendorname = cpup->cpu_vendorname; 1642 modifier = modifiers[modif]; 1643 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1644 name = cpufam->cpu_models[ci->ci_model]; 1645 if (name == NULL || *name == '\0') 1646 name = cpufam->cpu_model_default; 1647 class = cpufam->cpu_class; 1648 ci->ci_info = cpufam->cpu_info; 1649 1650 if (cpu_vendor == CPUVENDOR_INTEL) { 1651 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1652 const char *tmp; 1653 tmp = intel_family6_name(ci); 1654 if (tmp != NULL) 1655 name = tmp; 1656 } 1657 if (ci->ci_family == 15 && 1658 ci->ci_brand_id < 1659 __arraycount(i386_intel_brand) && 1660 i386_intel_brand[ci->ci_brand_id]) 1661 name = 1662 i386_intel_brand[ci->ci_brand_id]; 1663 } 1664 1665 if (cpu_vendor == CPUVENDOR_AMD) { 1666 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1667 if (ci->ci_brand_id == 1) 1668 /* 1669 * It's Duron. We override the 1670 * name, since it might have 1671 * been misidentified as Athlon. 1672 */ 1673 name = 1674 amd_brand[ci->ci_brand_id]; 1675 else 1676 brand = amd_brand_name; 1677 } 1678 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1679 /* Identify AMD64 CPU names. */ 1680 const char *tmp; 1681 tmp = amd_amd64_name(ci); 1682 if (tmp != NULL) 1683 name = tmp; 1684 } 1685 } 1686 1687 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1688 vendorname = "VIA"; 1689 } 1690 } 1691 1692 ci->ci_cpu_class = class; 1693 1694 sz = sizeof(ci->ci_tsc_freq); 1695 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1696 sz = sizeof(use_pae); 1697 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1698 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1699 1700 /* 1701 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1702 * we try to determine from the family/model values. 1703 */ 1704 if (*cpu_brand_string != '\0') 1705 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1706 1707 aprint_normal("%s: %s", cpuname, vendorname); 1708 if (*modifier) 1709 aprint_normal(" %s", modifier); 1710 if (*name) 1711 aprint_normal(" %s", name); 1712 if (*brand) 1713 aprint_normal(" %s", brand); 1714 aprint_normal(" (%s-class)", classnames[class]); 1715 1716 if (ci->ci_tsc_freq != 0) 1717 aprint_normal(", %ju.%02ju MHz\n", 1718 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1719 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1720 1721 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1722 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1723 if (ci->ci_signature != 0) 1724 aprint_normal(" (id %#x)", ci->ci_signature); 1725 aprint_normal("\n"); 1726 1727 if (ci->ci_info) 1728 (*ci->ci_info)(ci); 1729 1730 /* 1731 * display CPU feature flags 1732 */ 1733 1734 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1735 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1736 1737 /* These next two are actually common definitions! */ 1738 print_bits(cpuname, "features2", 1739 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1740 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1741 print_bits(cpuname, "features3", 1742 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1743 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1744 1745 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1746 ci->ci_feat_val[4]); 1747 1748 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1749 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1750 ci->ci_feat_val[6]); 1751 1752 if (ci->ci_max_xsave != 0) { 1753 aprint_normal("%s: xsave area size: current %d, maximum %d", 1754 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1755 aprint_normal(", xgetbv %sabled\n", 1756 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1757 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1758 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1759 x86_xgetbv()); 1760 } 1761 1762 x86_print_cacheinfo(ci); 1763 1764 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1765 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1766 cpuname, 1767 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1768 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1769 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1770 } 1771 1772 if (ci->ci_cpu_class == CPUCLASS_386) { 1773 errx(1, "NetBSD requires an 80486 or later processor"); 1774 } 1775 1776 if (ci->ci_cpu_type == CPU_486DLC) { 1777 #ifndef CYRIX_CACHE_WORKS 1778 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1779 #else 1780 #ifndef CYRIX_CACHE_REALLY_WORKS 1781 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1782 #else 1783 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1784 #endif 1785 #endif 1786 } 1787 1788 /* 1789 * Everything past this point requires a Pentium or later. 1790 */ 1791 if (ci->ci_cpuid_level < 0) 1792 return; 1793 1794 identifycpu_cpuids(ci); 1795 1796 #ifdef INTEL_CORETEMP 1797 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1798 coretemp_register(ci); 1799 #endif 1800 1801 if (cpu_vendor == CPUVENDOR_AMD) { 1802 uint32_t data[4]; 1803 1804 x86_cpuid(0x80000000, data); 1805 if (data[0] >= 0x80000007) 1806 powernow_probe(ci); 1807 1808 if ((data[0] >= 0x8000000a) 1809 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1810 x86_cpuid(0x8000000a, data); 1811 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1812 data[0] & 0xf); 1813 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1814 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1815 data[3]); 1816 } 1817 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1818 uint32_t data[4]; 1819 uint32_t highest_basic_info; 1820 uint32_t bi_index; 1821 1822 x86_cpuid(0x00000000, data); 1823 highest_basic_info = data[0]; 1824 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1825 highest_basic_info); 1826 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1827 x86_cpuid(bi_index, data); 1828 switch (bi_index) { 1829 case 6: 1830 print_bits(cpuname, "DSPM-eax", 1831 CPUID_DSPM_FLAGS, data[0]); 1832 print_bits(cpuname, "DSPM-ecx", 1833 CPUID_DSPM_FLAGS1, data[2]); 1834 break; 1835 case 7: 1836 aprint_verbose("%s: SEF highest subleaf %08x\n", 1837 cpuname, data[0]); 1838 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1839 data[1]); 1840 break; 1841 #if 0 1842 default: 1843 aprint_verbose("%s: basic %08x-eax %08x\n", 1844 cpuname, bi_index, data[0]); 1845 aprint_verbose("%s: basic %08x-ebx %08x\n", 1846 cpuname, bi_index, data[1]); 1847 aprint_verbose("%s: basic %08x-ecx %08x\n", 1848 cpuname, bi_index, data[2]); 1849 aprint_verbose("%s: basic %08x-edx %08x\n", 1850 cpuname, bi_index, data[3]); 1851 break; 1852 #endif 1853 } 1854 } 1855 } 1856 1857 #ifdef INTEL_ONDEMAND_CLOCKMOD 1858 clockmod_init(); 1859 #endif 1860 1861 if (cpu_vendor == CPUVENDOR_AMD) 1862 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1863 else if (cpu_vendor == CPUVENDOR_INTEL) 1864 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1865 else 1866 return; 1867 1868 ucode.data = &ucvers; 1869 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1870 #ifdef __i386__ 1871 struct cpu_ucode_version_64 ucode_64; 1872 if (errno != ENOTTY) 1873 return; 1874 /* Try the 64 bit ioctl */ 1875 memset(&ucode_64, 0, sizeof ucode_64); 1876 ucode_64.data = &ucvers; 1877 ucode_64.loader_version = ucode.loader_version; 1878 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1879 return; 1880 #endif 1881 } 1882 1883 if (cpu_vendor == CPUVENDOR_AMD) 1884 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1885 else if (cpu_vendor == CPUVENDOR_INTEL) 1886 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1887 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1888 } 1889 1890 static const char * 1891 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1892 const char *sep) 1893 { 1894 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1895 char human_num[HUMAN_BUFSIZE]; 1896 1897 if (cai->cai_totalsize == 0) 1898 return sep; 1899 1900 if (sep == NULL) 1901 aprint_verbose_dev(ci->ci_dev, ""); 1902 else 1903 aprint_verbose("%s", sep); 1904 if (name != NULL) 1905 aprint_verbose("%s ", name); 1906 1907 if (cai->cai_string != NULL) { 1908 aprint_verbose("%s ", cai->cai_string); 1909 } else { 1910 (void)humanize_number(human_num, sizeof(human_num), 1911 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1912 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1913 } 1914 switch (cai->cai_associativity) { 1915 case 0: 1916 aprint_verbose("disabled"); 1917 break; 1918 case 1: 1919 aprint_verbose("direct-mapped"); 1920 break; 1921 case 0xff: 1922 aprint_verbose("fully associative"); 1923 break; 1924 default: 1925 aprint_verbose("%d-way", cai->cai_associativity); 1926 break; 1927 } 1928 return ", "; 1929 } 1930 1931 static const char * 1932 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1933 const char *sep) 1934 { 1935 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1936 char human_num[HUMAN_BUFSIZE]; 1937 1938 if (cai->cai_totalsize == 0) 1939 return sep; 1940 1941 if (sep == NULL) 1942 aprint_verbose_dev(ci->ci_dev, ""); 1943 else 1944 aprint_verbose("%s", sep); 1945 if (name != NULL) 1946 aprint_verbose("%s ", name); 1947 1948 if (cai->cai_string != NULL) { 1949 aprint_verbose("%s", cai->cai_string); 1950 } else { 1951 (void)humanize_number(human_num, sizeof(human_num), 1952 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1953 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1954 human_num); 1955 switch (cai->cai_associativity) { 1956 case 0: 1957 aprint_verbose("disabled"); 1958 break; 1959 case 1: 1960 aprint_verbose("direct-mapped"); 1961 break; 1962 case 0xff: 1963 aprint_verbose("fully associative"); 1964 break; 1965 default: 1966 aprint_verbose("%d-way", cai->cai_associativity); 1967 break; 1968 } 1969 } 1970 return ", "; 1971 } 1972 1973 static const struct x86_cache_info * 1974 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1975 { 1976 int i; 1977 1978 for (i = 0; cai[i].cai_desc != 0; i++) { 1979 if (cai[i].cai_desc == desc) 1980 return (&cai[i]); 1981 } 1982 1983 return (NULL); 1984 } 1985 1986 static void 1987 x86_print_cacheinfo(struct cpu_info *ci) 1988 { 1989 const char *sep; 1990 1991 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1992 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1993 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1994 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1995 if (sep != NULL) 1996 aprint_verbose("\n"); 1997 } 1998 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1999 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2000 if (sep != NULL) 2001 aprint_verbose("\n"); 2002 } 2003 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2004 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2005 if (sep != NULL) 2006 aprint_verbose("\n"); 2007 } 2008 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2009 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2010 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2011 if (sep != NULL) 2012 aprint_verbose("\n"); 2013 } 2014 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2015 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2016 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2017 if (sep != NULL) 2018 aprint_verbose("\n"); 2019 } 2020 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2021 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2022 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2023 if (sep != NULL) 2024 aprint_verbose("\n"); 2025 } 2026 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2027 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2028 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2029 if (sep != NULL) 2030 aprint_verbose("\n"); 2031 } 2032 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2033 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2034 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2035 if (sep != NULL) 2036 aprint_verbose("\n"); 2037 } 2038 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2039 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2040 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2041 if (sep != NULL) 2042 aprint_verbose("\n"); 2043 } 2044 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2045 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2046 NULL); 2047 if (sep != NULL) 2048 aprint_verbose("\n"); 2049 } 2050 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2051 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2052 NULL); 2053 if (sep != NULL) 2054 aprint_verbose("\n"); 2055 } 2056 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2057 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2058 NULL); 2059 if (sep != NULL) 2060 aprint_verbose("\n"); 2061 } 2062 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2063 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2064 NULL); 2065 if (sep != NULL) 2066 aprint_verbose("\n"); 2067 } 2068 } 2069 2070 static void 2071 powernow_probe(struct cpu_info *ci) 2072 { 2073 uint32_t regs[4]; 2074 char buf[256]; 2075 2076 x86_cpuid(0x80000007, regs); 2077 2078 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2079 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2080 buf); 2081 } 2082 2083 int 2084 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2085 { 2086 struct cpu_info ci; 2087 int loader_version, res; 2088 struct cpu_ucode_version versreq; 2089 2090 cpu_probe_base_features(&ci, "unknown"); 2091 2092 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2093 loader_version = CPU_UCODE_LOADER_AMD; 2094 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2095 loader_version = CPU_UCODE_LOADER_INTEL1; 2096 else 2097 return -1; 2098 2099 /* check whether the kernel understands this loader version */ 2100 versreq.loader_version = loader_version; 2101 versreq.data = 0; 2102 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2103 if (res) 2104 return -1; 2105 2106 switch (loader_version) { 2107 case CPU_UCODE_LOADER_AMD: 2108 if (uc->cpu_nr != -1) { 2109 /* printf? */ 2110 return -1; 2111 } 2112 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2113 break; 2114 case CPU_UCODE_LOADER_INTEL1: 2115 if (uc->cpu_nr == -1) 2116 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2117 else 2118 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2119 break; 2120 default: /* can't happen */ 2121 return -1; 2122 } 2123 uc->loader_version = loader_version; 2124 return 0; 2125 } 2126
Indexes created Sun Sep 28 07:09:56 GMT 2025