i386.c revision 1.48
1 /* $NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 155 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 156 * Architectures Software Developer's Manual, Volume 2A". 157 */ 158 static const char * const i386_intel_brand[] = { 159 "", /* Unsupported */ 160 "Celeron", /* Intel (R) Celeron (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 163 "Pentium III", /* Intel (R) Pentium (R) III processor */ 164 "", /* 0x05: Reserved */ 165 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Celeron", /* Intel (R) Celeron (TM) processor */ 170 "Xeon", /* Intel (R) Xeon (TM) processor */ 171 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 172 "", /* 0x0d: Reserved */ 173 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 174 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 175 "", /* 0x10: Reserved */ 176 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 177 "Celeron M", /* Intel (R) Celeron (R) M processor */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "Celeron", /* Intel (R) Celeron (R) processor */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Pentium M", /* Intel (R) Pentium (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 }; 184 185 /* 186 * AMD processors don't have Brand IDs, so we need these names for probe. 187 */ 188 static const char * const amd_brand[] = { 189 "", 190 "Duron", /* AMD Duron(tm) */ 191 "MP", /* AMD Athlon(tm) MP */ 192 "XP", /* AMD Athlon(tm) XP */ 193 "4" /* AMD Athlon(tm) 4 */ 194 }; 195 196 static int cpu_vendor; 197 static char cpu_brand_string[49]; 198 static char amd_brand_name[48]; 199 static int use_pae, largepagesize; 200 201 /* Setup functions */ 202 static void disable_tsc(struct cpu_info *); 203 static void amd_family5_setup(struct cpu_info *); /* alike cpu_probe_k5 */ 204 static void cyrix6x86_cpu_setup(struct cpu_info *); 205 static void winchip_cpu_setup(struct cpu_info *); 206 /* Brand/Model name functions */ 207 static const char *intel_family6_name(struct cpu_info *); 208 static const char *amd_amd64_name(struct cpu_info *); 209 /* Probe functions */ 210 static void amd_family6_probe(struct cpu_info *); 211 static void powernow_probe(struct cpu_info *); 212 static void intel_family_new_probe(struct cpu_info *); 213 static void via_cpu_probe(struct cpu_info *); 214 /* (Cache) Info functions */ 215 static void amd_cpu_cacheinfo(struct cpu_info *); /* alike */ 216 static void via_cpu_cacheinfo(struct cpu_info *); 217 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 218 static void transmeta_cpu_info(struct cpu_info *); 219 /* Common functions */ 220 static void cpu_probe_base_features(struct cpu_info *, const char *); 221 /* alike cpu_probe() */ 222 static void cpu_probe_features(struct cpu_info *); 223 static void print_bits(const char *, const char *, const char *, uint32_t); 224 /* XXX identifycpu alike cpu_identify */ 225 static void identifycpu_cpuids(struct cpu_info *); 226 static const char *print_cache_config(struct cpu_info *, int, const char *, 227 const char *); 228 static const char *print_tlb_config(struct cpu_info *, int, const char *, 229 const char *); 230 static const struct x86_cache_info *cache_info_lookup( /* XXX same */ 231 const struct x86_cache_info *, uint8_t); 232 static void x86_print_cacheinfo(struct cpu_info *); 233 234 /* 235 * Note: these are just the ones that may not have a cpuid instruction. 236 * We deal with the rest in a different way. 237 */ 238 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 239 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 240 NULL, NULL, NULL }, /* CPU_386SX */ 241 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 242 NULL, NULL, NULL }, /* CPU_386 */ 243 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 244 NULL, NULL, NULL }, /* CPU_486SX */ 245 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 246 NULL, NULL, NULL }, /* CPU_486 */ 247 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486DLC */ 249 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_6x86 */ 251 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 252 NULL, NULL, NULL }, /* CPU_NX586 */ 253 }; 254 255 const char *classnames[] = { 256 "386", 257 "486", 258 "586", 259 "686" 260 }; 261 262 const char *modifiers[] = { 263 "", 264 "OverDrive", 265 "Dual", 266 "" 267 }; 268 269 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 270 { 271 /* 272 * For Intel processors, check Chapter 35Model-specific 273 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 274 * Software Developer's Manual, Volume 3C". 275 */ 276 "GenuineIntel", 277 CPUVENDOR_INTEL, 278 "Intel", 279 /* Family 4 */ 280 { { 281 CPUCLASS_486, 282 { 283 "486DX", "486DX", "486SX", "486DX2", "486SL", 284 "486SX2", 0, "486DX2 W/B Enhanced", 285 "486DX4", 0, 0, 0, 0, 0, 0, 0, 286 }, 287 "486", /* Default */ 288 NULL, 289 NULL, 290 NULL, 291 }, 292 /* Family 5 */ 293 { 294 CPUCLASS_586, 295 { 296 "Pentium (P5 A-step)", "Pentium (P5)", 297 "Pentium (P54C)", "Pentium (P24T)", 298 "Pentium/MMX", "Pentium", 0, 299 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 300 0, 0, 0, 0, 0, 0, 0, 301 }, 302 "Pentium", /* Default */ 303 NULL, 304 NULL, 305 NULL, 306 }, 307 /* Family 6 */ 308 { 309 CPUCLASS_686, 310 { 311 [0x00] = "Pentium Pro (A-step)", 312 [0x01] = "Pentium Pro", 313 [0x03] = "Pentium II (Klamath)", 314 [0x04] = "Pentium Pro", 315 [0x05] = "Pentium II/Celeron (Deschutes)", 316 [0x06] = "Celeron (Mendocino)", 317 [0x07] = "Pentium III (Katmai)", 318 [0x08] = "Pentium III (Coppermine)", 319 [0x09] = "Pentium M (Banias)", 320 [0x0a] = "Pentium III Xeon (Cascades)", 321 [0x0b] = "Pentium III (Tualatin)", 322 [0x0d] = "Pentium M (Dothan)", 323 [0x0e] = "Pentium Core Duo, Core solo", 324 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 325 "Core 2 Quad 6xxx, " 326 "Core 2 Extreme 6xxx, " 327 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 328 "and Pentium DC", 329 [0x15] = "EP80579 Integrated Processor", 330 [0x16] = "Celeron (45nm)", 331 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 332 "Core 2 Quad 8xxx and 9xxx", 333 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 334 "(Nehalem)", 335 [0x1c] = "Atom Family", 336 [0x1d] = "XeonMP 74xx (Nehalem)", 337 [0x1e] = "Core i7 and i5", 338 [0x1f] = "Core i7 and i5", 339 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 340 [0x26] = "Atom Family", 341 [0x27] = "Atom Family", 342 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 343 "i3 2xxx", 344 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 345 [0x2d] = "Xeon E5 Sandy Bridy family, " 346 "Core i7-39xx Extreme", 347 [0x2e] = "Xeon 75xx & 65xx", 348 [0x2f] = "Xeon E7 family", 349 [0x35] = "Atom Family", 350 [0x36] = "Atom S1000", 351 [0x37] = "Atom C2000, E3000", 352 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 353 "Ivy Bridge", 354 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 355 "(Haswell)", 356 [0x3d] = "Next gen Core", 357 [0x3e] = "Xeon E5/E7, Ivy Bridge-EP", 358 [0x3f] = "Future gen Xeon", 359 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 360 "(Haswell)", 361 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 362 "(Haswell)", 363 [0x4d] = "Atom C2000, E3000", 364 }, 365 "Pentium Pro, II or III", /* Default */ 366 NULL, 367 intel_family_new_probe, 368 NULL, 369 }, 370 /* Family > 6 */ 371 { 372 CPUCLASS_686, 373 { 374 0, 0, 0, 0, 0, 0, 0, 0, 375 0, 0, 0, 0, 0, 0, 0, 0, 376 }, 377 "Pentium 4", /* Default */ 378 NULL, 379 intel_family_new_probe, 380 NULL, 381 } } 382 }, 383 { 384 "AuthenticAMD", 385 CPUVENDOR_AMD, 386 "AMD", 387 /* Family 4 */ 388 { { 389 CPUCLASS_486, 390 { 391 0, 0, 0, "Am486DX2 W/T", 392 0, 0, 0, "Am486DX2 W/B", 393 "Am486DX4 W/T or Am5x86 W/T 150", 394 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 395 0, 0, "Am5x86 W/T 133/160", 396 "Am5x86 W/B 133/160", 397 }, 398 "Am486 or Am5x86", /* Default */ 399 NULL, 400 NULL, 401 NULL, 402 }, 403 /* Family 5 */ 404 { 405 CPUCLASS_586, 406 { 407 "K5", "K5", "K5", "K5", 0, 0, "K6", 408 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 409 "K6-2+/III+", 0, 0, 410 }, 411 "K5 or K6", /* Default */ 412 amd_family5_setup, 413 NULL, 414 amd_cpu_cacheinfo, 415 }, 416 /* Family 6 */ 417 { 418 CPUCLASS_686, 419 { 420 0, "Athlon Model 1", "Athlon Model 2", 421 "Duron", "Athlon Model 4 (Thunderbird)", 422 0, "Athlon", "Duron", "Athlon", 0, 423 "Athlon", 0, 0, 0, 0, 0, 424 }, 425 "K7 (Athlon)", /* Default */ 426 NULL, 427 amd_family6_probe, 428 amd_cpu_cacheinfo, 429 }, 430 /* Family > 6 */ 431 { 432 CPUCLASS_686, 433 { 434 0, 0, 0, 0, 0, 0, 0, 0, 435 0, 0, 0, 0, 0, 0, 0, 0, 436 }, 437 "Unknown K8 (Athlon)", /* Default */ 438 NULL, 439 amd_family6_probe, 440 amd_cpu_cacheinfo, 441 } } 442 }, 443 { 444 "CyrixInstead", 445 CPUVENDOR_CYRIX, 446 "Cyrix", 447 /* Family 4 */ 448 { { 449 CPUCLASS_486, 450 { 451 0, 0, 0, 452 "MediaGX", 453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 454 }, 455 "486", /* Default */ 456 cyrix6x86_cpu_setup, /* XXX ?? */ 457 NULL, 458 NULL, 459 }, 460 /* Family 5 */ 461 { 462 CPUCLASS_586, 463 { 464 0, 0, "6x86", 0, 465 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 467 }, 468 "6x86", /* Default */ 469 cyrix6x86_cpu_setup, 470 NULL, 471 NULL, 472 }, 473 /* Family 6 */ 474 { 475 CPUCLASS_686, 476 { 477 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 478 0, 0, 0, 0, 0, 0, 0, 0, 479 }, 480 "6x86MX", /* Default */ 481 cyrix6x86_cpu_setup, 482 NULL, 483 NULL, 484 }, 485 /* Family > 6 */ 486 { 487 CPUCLASS_686, 488 { 489 0, 0, 0, 0, 0, 0, 0, 0, 490 0, 0, 0, 0, 0, 0, 0, 0, 491 }, 492 "Unknown 6x86MX", /* Default */ 493 NULL, 494 NULL, 495 NULL, 496 } } 497 }, 498 { /* MediaGX is now owned by National Semiconductor */ 499 "Geode by NSC", 500 CPUVENDOR_CYRIX, /* XXX */ 501 "National Semiconductor", 502 /* Family 4, NSC never had any of these */ 503 { { 504 CPUCLASS_486, 505 { 506 0, 0, 0, 0, 0, 0, 0, 0, 507 0, 0, 0, 0, 0, 0, 0, 0, 508 }, 509 "486 compatible", /* Default */ 510 NULL, 511 NULL, 512 NULL, 513 }, 514 /* Family 5: Geode family, formerly MediaGX */ 515 { 516 CPUCLASS_586, 517 { 518 0, 0, 0, 0, 519 "Geode GX1", 520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 521 }, 522 "Geode", /* Default */ 523 cyrix6x86_cpu_setup, 524 NULL, 525 amd_cpu_cacheinfo, 526 }, 527 /* Family 6, not yet available from NSC */ 528 { 529 CPUCLASS_686, 530 { 531 0, 0, 0, 0, 0, 0, 0, 0, 532 0, 0, 0, 0, 0, 0, 0, 0, 533 }, 534 "Pentium Pro compatible", /* Default */ 535 NULL, 536 NULL, 537 NULL, 538 }, 539 /* Family > 6, not yet available from NSC */ 540 { 541 CPUCLASS_686, 542 { 543 0, 0, 0, 0, 0, 0, 0, 0, 544 0, 0, 0, 0, 0, 0, 0, 0, 545 }, 546 "Pentium Pro compatible", /* Default */ 547 NULL, 548 NULL, 549 NULL, 550 } } 551 }, 552 { 553 "CentaurHauls", 554 CPUVENDOR_IDT, 555 "IDT", 556 /* Family 4, IDT never had any of these */ 557 { { 558 CPUCLASS_486, 559 { 560 0, 0, 0, 0, 0, 0, 0, 0, 561 0, 0, 0, 0, 0, 0, 0, 0, 562 }, 563 "486 compatible", /* Default */ 564 NULL, 565 NULL, 566 NULL, 567 }, 568 /* Family 5 */ 569 { 570 CPUCLASS_586, 571 { 572 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 573 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 574 }, 575 "WinChip", /* Default */ 576 winchip_cpu_setup, 577 NULL, 578 NULL, 579 }, 580 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 581 { 582 CPUCLASS_686, 583 { 584 0, 0, 0, 0, 0, 0, "C3 Samuel", 585 "C3 Samuel 2/Ezra", "C3 Ezra-T", 586 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 587 0, "VIA Nano", 588 }, 589 "Unknown VIA/IDT", /* Default */ 590 NULL, 591 via_cpu_probe, 592 via_cpu_cacheinfo, 593 }, 594 /* Family > 6, not yet available from VIA */ 595 { 596 CPUCLASS_686, 597 { 598 0, 0, 0, 0, 0, 0, 0, 0, 599 0, 0, 0, 0, 0, 0, 0, 0, 600 }, 601 "Pentium Pro compatible", /* Default */ 602 NULL, 603 NULL, 604 NULL, 605 } } 606 }, 607 { 608 "GenuineTMx86", 609 CPUVENDOR_TRANSMETA, 610 "Transmeta", 611 /* Family 4, Transmeta never had any of these */ 612 { { 613 CPUCLASS_486, 614 { 615 0, 0, 0, 0, 0, 0, 0, 0, 616 0, 0, 0, 0, 0, 0, 0, 0, 617 }, 618 "486 compatible", /* Default */ 619 NULL, 620 NULL, 621 NULL, 622 }, 623 /* Family 5 */ 624 { 625 CPUCLASS_586, 626 { 627 0, 0, 0, 0, 0, 0, 0, 0, 628 0, 0, 0, 0, 0, 0, 0, 0, 629 }, 630 "Crusoe", /* Default */ 631 NULL, 632 NULL, 633 transmeta_cpu_info, 634 }, 635 /* Family 6, not yet available from Transmeta */ 636 { 637 CPUCLASS_686, 638 { 639 0, 0, 0, 0, 0, 0, 0, 0, 640 0, 0, 0, 0, 0, 0, 0, 0, 641 }, 642 "Pentium Pro compatible", /* Default */ 643 NULL, 644 NULL, 645 NULL, 646 }, 647 /* Family > 6, not yet available from Transmeta */ 648 { 649 CPUCLASS_686, 650 { 651 0, 0, 0, 0, 0, 0, 0, 0, 652 0, 0, 0, 0, 0, 0, 0, 0, 653 }, 654 "Pentium Pro compatible", /* Default */ 655 NULL, 656 NULL, 657 NULL, 658 } } 659 } 660 }; 661 662 /* 663 * disable the TSC such that we don't use the TSC in microtime(9) 664 * because some CPUs got the implementation wrong. 665 */ 666 static void 667 disable_tsc(struct cpu_info *ci) 668 { 669 if (ci->ci_feat_val[0] & CPUID_TSC) { 670 ci->ci_feat_val[0] &= ~CPUID_TSC; 671 aprint_error("WARNING: broken TSC disabled\n"); 672 } 673 } 674 675 static void 676 amd_family5_setup(struct cpu_info *ci) 677 { 678 679 switch (ci->ci_model) { 680 case 0: /* AMD-K5 Model 0 */ 681 /* 682 * According to the AMD Processor Recognition App Note, 683 * the AMD-K5 Model 0 uses the wrong bit to indicate 684 * support for global PTEs, instead using bit 9 (APIC) 685 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 686 */ 687 if (ci->ci_feat_val[0] & CPUID_APIC) 688 ci->ci_feat_val[0] = 689 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 690 /* 691 * XXX But pmap_pg_g is already initialized -- need to kick 692 * XXX the pmap somehow. How does the MP branch do this? 693 */ 694 break; 695 } 696 } 697 698 static void 699 cyrix6x86_cpu_setup(struct cpu_info *ci) 700 { 701 702 /* 703 * Do not disable the TSC on the Geode GX, it's reported to 704 * work fine. 705 */ 706 if (ci->ci_signature != 0x552) 707 disable_tsc(ci); 708 } 709 710 static void 711 winchip_cpu_setup(struct cpu_info *ci) 712 { 713 switch (ci->ci_model) { 714 case 4: /* WinChip C6 */ 715 disable_tsc(ci); 716 } 717 } 718 719 720 static const char * 721 intel_family6_name(struct cpu_info *ci) 722 { 723 const char *ret = NULL; 724 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 725 726 if (ci->ci_model == 5) { 727 switch (l2cache) { 728 case 0: 729 case 128 * 1024: 730 ret = "Celeron (Covington)"; 731 break; 732 case 256 * 1024: 733 ret = "Mobile Pentium II (Dixon)"; 734 break; 735 case 512 * 1024: 736 ret = "Pentium II"; 737 break; 738 case 1 * 1024 * 1024: 739 case 2 * 1024 * 1024: 740 ret = "Pentium II Xeon"; 741 break; 742 } 743 } else if (ci->ci_model == 6) { 744 switch (l2cache) { 745 case 256 * 1024: 746 case 512 * 1024: 747 ret = "Mobile Pentium II"; 748 break; 749 } 750 } else if (ci->ci_model == 7) { 751 switch (l2cache) { 752 case 512 * 1024: 753 ret = "Pentium III"; 754 break; 755 case 1 * 1024 * 1024: 756 case 2 * 1024 * 1024: 757 ret = "Pentium III Xeon"; 758 break; 759 } 760 } else if (ci->ci_model >= 8) { 761 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 762 switch (ci->ci_brand_id) { 763 case 0x3: 764 if (ci->ci_signature == 0x6B1) 765 ret = "Celeron"; 766 break; 767 case 0x8: 768 if (ci->ci_signature >= 0xF13) 769 ret = "genuine processor"; 770 break; 771 case 0xB: 772 if (ci->ci_signature >= 0xF13) 773 ret = "Xeon MP"; 774 break; 775 case 0xE: 776 if (ci->ci_signature < 0xF13) 777 ret = "Xeon"; 778 break; 779 } 780 if (ret == NULL) 781 ret = i386_intel_brand[ci->ci_brand_id]; 782 } 783 } 784 785 return ret; 786 } 787 788 /* 789 * Identify AMD64 CPU names from cpuid. 790 * 791 * Based on: 792 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 793 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 794 * "Revision Guide for AMD NPT Family 0Fh Processors" 795 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 796 * and other miscellaneous reports. 797 * 798 * This is all rather pointless, these are cross 'brand' since the raw 799 * silicon is shared. 800 */ 801 static const char * 802 amd_amd64_name(struct cpu_info *ci) 803 { 804 static char family_str[32]; 805 806 /* Only called if family >= 15 */ 807 808 switch (ci->ci_family) { 809 case 15: 810 switch (ci->ci_model) { 811 case 0x21: /* rev JH-E1/E6 */ 812 case 0x41: /* rev JH-F2 */ 813 return "Dual-Core Opteron"; 814 case 0x23: /* rev JH-E6 (Toledo) */ 815 return "Dual-Core Opteron or Athlon 64 X2"; 816 case 0x43: /* rev JH-F2 (Windsor) */ 817 return "Athlon 64 FX or Athlon 64 X2"; 818 case 0x24: /* rev SH-E5 (Lancaster?) */ 819 return "Mobile Athlon 64 or Turion 64"; 820 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 821 return "Opteron or Athlon 64 FX"; 822 case 0x15: /* rev SH-D0 */ 823 case 0x25: /* rev SH-E4 */ 824 return "Opteron"; 825 case 0x27: /* rev DH-E4, SH-E4 */ 826 return "Athlon 64 or Athlon 64 FX or Opteron"; 827 case 0x48: /* rev BH-F2 */ 828 return "Turion 64 X2"; 829 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 830 case 0x07: /* rev SH-CG (ClawHammer) */ 831 case 0x0b: /* rev CH-CG */ 832 case 0x14: /* rev SH-D0 */ 833 case 0x17: /* rev SH-D0 */ 834 case 0x1b: /* rev CH-D0 */ 835 return "Athlon 64"; 836 case 0x2b: /* rev BH-E4 (Manchester) */ 837 case 0x4b: /* rev BH-F2 (Windsor) */ 838 return "Athlon 64 X2"; 839 case 0x6b: /* rev BH-G1 (Brisbane) */ 840 return "Athlon X2 or Athlon 64 X2"; 841 case 0x08: /* rev CH-CG */ 842 case 0x0c: /* rev DH-CG (Newcastle) */ 843 case 0x0e: /* rev DH-CG (Newcastle?) */ 844 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 845 case 0x18: /* rev CH-D0 */ 846 case 0x1c: /* rev DH-D0 (Winchester) */ 847 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 848 case 0x2c: /* rev DH-E3/E6 */ 849 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 850 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 851 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 852 case 0x6f: /* rev DH-G1 */ 853 return "Athlon 64 or Sempron"; 854 default: 855 break; 856 } 857 return "Unknown AMD64 CPU"; 858 859 #if 0 860 case 16: 861 return "Family 10h"; 862 case 17: 863 return "Family 11h"; 864 case 18: 865 return "Family 12h"; 866 case 19: 867 return "Family 14h"; 868 case 20: 869 return "Family 15h"; 870 #endif 871 872 default: 873 break; 874 } 875 876 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 877 return family_str; 878 } 879 880 static void 881 intel_family_new_probe(struct cpu_info *ci) 882 { 883 uint32_t descs[4]; 884 885 x86_cpuid(0x80000000, descs); 886 887 /* 888 * Determine extended feature flags. 889 */ 890 if (descs[0] >= 0x80000001) { 891 x86_cpuid(0x80000001, descs); 892 ci->ci_feat_val[2] |= descs[3]; 893 ci->ci_feat_val[3] |= descs[2]; 894 } 895 } 896 897 static void 898 via_cpu_probe(struct cpu_info *ci) 899 { 900 u_int stepping = CPUID2STEPPING(ci->ci_signature); 901 u_int descs[4]; 902 u_int lfunc; 903 904 /* 905 * Determine the largest extended function value. 906 */ 907 x86_cpuid(0x80000000, descs); 908 lfunc = descs[0]; 909 910 /* 911 * Determine the extended feature flags. 912 */ 913 if (lfunc >= 0x80000001) { 914 x86_cpuid(0x80000001, descs); 915 ci->ci_feat_val[2] |= descs[3]; 916 } 917 918 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 919 return; 920 921 /* Nehemiah or Esther */ 922 x86_cpuid(0xc0000000, descs); 923 lfunc = descs[0]; 924 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 925 return; 926 927 x86_cpuid(0xc0000001, descs); 928 lfunc = descs[3]; 929 ci->ci_feat_val[4] = lfunc; 930 } 931 932 static void 933 amd_family6_probe(struct cpu_info *ci) 934 { 935 uint32_t descs[4]; 936 char *p; 937 size_t i; 938 939 x86_cpuid(0x80000000, descs); 940 941 /* 942 * Determine the extended feature flags. 943 */ 944 if (descs[0] >= 0x80000001) { 945 x86_cpuid(0x80000001, descs); 946 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 947 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 948 } 949 950 if (*cpu_brand_string == '\0') 951 return; 952 953 for (i = 1; i < __arraycount(amd_brand); i++) 954 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 955 ci->ci_brand_id = i; 956 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 957 break; 958 } 959 } 960 961 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 962 AMD_L2CACHE_INFO; 963 964 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 965 AMD_L3CACHE_INFO; 966 967 static void 968 amd_cpu_cacheinfo(struct cpu_info *ci) 969 { 970 const struct x86_cache_info *cp; 971 struct x86_cache_info *cai; 972 u_int descs[4]; 973 u_int lfunc; 974 975 /* 976 * K5 model 0 has none of this info. 977 */ 978 if (ci->ci_family == 5 && ci->ci_model == 0) 979 return; 980 981 /* 982 * Determine the largest extended function value. 983 */ 984 x86_cpuid(0x80000000, descs); 985 lfunc = descs[0]; 986 987 /* 988 * Determine L1 cache/TLB info. 989 */ 990 if (lfunc < 0x80000005) { 991 /* No L1 cache info available. */ 992 return; 993 } 994 995 x86_cpuid(0x80000005, descs); 996 997 /* 998 * K6-III and higher have large page TLBs. 999 */ 1000 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1001 cai = &ci->ci_cinfo[CAI_ITLB2]; 1002 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1003 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1004 cai->cai_linesize = largepagesize; 1005 1006 cai = &ci->ci_cinfo[CAI_DTLB2]; 1007 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1008 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1009 cai->cai_linesize = largepagesize; 1010 } 1011 1012 cai = &ci->ci_cinfo[CAI_ITLB]; 1013 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1014 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1015 cai->cai_linesize = (4 * 1024); 1016 1017 cai = &ci->ci_cinfo[CAI_DTLB]; 1018 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1019 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1020 cai->cai_linesize = (4 * 1024); 1021 1022 cai = &ci->ci_cinfo[CAI_DCACHE]; 1023 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1024 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1025 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1026 1027 cai = &ci->ci_cinfo[CAI_ICACHE]; 1028 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1029 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1030 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1031 1032 /* 1033 * Determine L2 cache/TLB info. 1034 */ 1035 if (lfunc < 0x80000006) { 1036 /* No L2 cache info available. */ 1037 return; 1038 } 1039 1040 x86_cpuid(0x80000006, descs); 1041 1042 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1043 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1044 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1045 cai->cai_linesize = (4 * 1024); 1046 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1047 cai->cai_associativity); 1048 if (cp != NULL) 1049 cai->cai_associativity = cp->cai_associativity; 1050 else 1051 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1052 1053 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1054 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1055 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1056 cai->cai_linesize = largepagesize; 1057 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1058 cai->cai_associativity); 1059 if (cp != NULL) 1060 cai->cai_associativity = cp->cai_associativity; 1061 else 1062 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1063 1064 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1065 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1066 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1067 cai->cai_linesize = (4 * 1024); 1068 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1069 cai->cai_associativity); 1070 if (cp != NULL) 1071 cai->cai_associativity = cp->cai_associativity; 1072 else 1073 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1074 1075 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1076 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1077 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1078 cai->cai_linesize = largepagesize; 1079 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1080 cai->cai_associativity); 1081 if (cp != NULL) 1082 cai->cai_associativity = cp->cai_associativity; 1083 else 1084 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1085 1086 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1087 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1088 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1089 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1090 1091 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1092 cai->cai_associativity); 1093 if (cp != NULL) 1094 cai->cai_associativity = cp->cai_associativity; 1095 else 1096 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1097 1098 /* 1099 * Determine L3 cache info on AMD Family 10h and newer processors 1100 */ 1101 if (ci->ci_family >= 0x10) { 1102 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1103 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1104 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1105 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1106 1107 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1108 cai->cai_associativity); 1109 if (cp != NULL) 1110 cai->cai_associativity = cp->cai_associativity; 1111 else 1112 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1113 } 1114 1115 /* 1116 * Determine 1GB TLB info. 1117 */ 1118 if (lfunc < 0x80000019) { 1119 /* No 1GB TLB info available. */ 1120 return; 1121 } 1122 1123 x86_cpuid(0x80000019, descs); 1124 1125 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1126 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1127 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1128 cai->cai_linesize = (1024 * 1024 * 1024); 1129 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1130 cai->cai_associativity); 1131 if (cp != NULL) 1132 cai->cai_associativity = cp->cai_associativity; 1133 else 1134 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1135 1136 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1137 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1138 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1139 cai->cai_linesize = (1024 * 1024 * 1024); 1140 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1141 cai->cai_associativity); 1142 if (cp != NULL) 1143 cai->cai_associativity = cp->cai_associativity; 1144 else 1145 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1146 1147 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1148 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1149 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1150 cai->cai_linesize = (1024 * 1024 * 1024); 1151 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1152 cai->cai_associativity); 1153 if (cp != NULL) 1154 cai->cai_associativity = cp->cai_associativity; 1155 else 1156 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1157 1158 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1159 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1160 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1161 cai->cai_linesize = (1024 * 1024 * 1024); 1162 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1163 cai->cai_associativity); 1164 if (cp != NULL) 1165 cai->cai_associativity = cp->cai_associativity; 1166 else 1167 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1168 } 1169 1170 static void 1171 via_cpu_cacheinfo(struct cpu_info *ci) 1172 { 1173 struct x86_cache_info *cai; 1174 int stepping; 1175 u_int descs[4]; 1176 u_int lfunc; 1177 1178 stepping = CPUID2STEPPING(ci->ci_signature); 1179 1180 /* 1181 * Determine the largest extended function value. 1182 */ 1183 x86_cpuid(0x80000000, descs); 1184 lfunc = descs[0]; 1185 1186 /* 1187 * Determine L1 cache/TLB info. 1188 */ 1189 if (lfunc < 0x80000005) { 1190 /* No L1 cache info available. */ 1191 return; 1192 } 1193 1194 x86_cpuid(0x80000005, descs); 1195 1196 cai = &ci->ci_cinfo[CAI_ITLB]; 1197 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1198 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1199 cai->cai_linesize = (4 * 1024); 1200 1201 cai = &ci->ci_cinfo[CAI_DTLB]; 1202 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1203 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1204 cai->cai_linesize = (4 * 1024); 1205 1206 cai = &ci->ci_cinfo[CAI_DCACHE]; 1207 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1208 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1209 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1210 if (ci->ci_model == 9 && stepping == 8) { 1211 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1212 cai->cai_associativity = 2; 1213 } 1214 1215 cai = &ci->ci_cinfo[CAI_ICACHE]; 1216 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1217 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1218 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1219 if (ci->ci_model == 9 && stepping == 8) { 1220 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1221 cai->cai_associativity = 2; 1222 } 1223 1224 /* 1225 * Determine L2 cache/TLB info. 1226 */ 1227 if (lfunc < 0x80000006) { 1228 /* No L2 cache info available. */ 1229 return; 1230 } 1231 1232 x86_cpuid(0x80000006, descs); 1233 1234 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1235 if (ci->ci_model >= 9) { 1236 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1237 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1238 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1239 } else { 1240 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1241 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1242 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1243 } 1244 } 1245 1246 static void 1247 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1248 { 1249 u_int descs[4]; 1250 1251 x86_cpuid(0x80860007, descs); 1252 *frequency = descs[0]; 1253 *voltage = descs[1]; 1254 *percentage = descs[2]; 1255 } 1256 1257 static void 1258 transmeta_cpu_info(struct cpu_info *ci) 1259 { 1260 u_int descs[4], nreg; 1261 u_int frequency, voltage, percentage; 1262 1263 x86_cpuid(0x80860000, descs); 1264 nreg = descs[0]; 1265 if (nreg >= 0x80860001) { 1266 x86_cpuid(0x80860001, descs); 1267 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1268 (descs[1] >> 24) & 0xff, 1269 (descs[1] >> 16) & 0xff, 1270 (descs[1] >> 8) & 0xff, 1271 descs[1] & 0xff); 1272 } 1273 if (nreg >= 0x80860002) { 1274 x86_cpuid(0x80860002, descs); 1275 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1276 (descs[1] >> 24) & 0xff, 1277 (descs[1] >> 16) & 0xff, 1278 (descs[1] >> 8) & 0xff, 1279 descs[1] & 0xff, 1280 descs[2]); 1281 } 1282 if (nreg >= 0x80860006) { 1283 union { 1284 char text[65]; 1285 u_int descs[4][4]; 1286 } info; 1287 int i; 1288 1289 for (i=0; i<4; i++) { 1290 x86_cpuid(0x80860003 + i, info.descs[i]); 1291 } 1292 info.text[64] = '\0'; 1293 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1294 } 1295 1296 if (nreg >= 0x80860007) { 1297 tmx86_get_longrun_status(&frequency, 1298 &voltage, &percentage); 1299 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1300 frequency, voltage, percentage); 1301 } 1302 } 1303 1304 static void 1305 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1306 { 1307 const struct x86_cache_info *cai; 1308 u_int descs[4]; 1309 int iterations, i, j; 1310 int type, level; 1311 int ways, partitions, linesize, sets; 1312 int caitype = -1; 1313 int totalsize; 1314 uint8_t desc; 1315 uint32_t brand[12]; 1316 1317 memset(ci, 0, sizeof(*ci)); 1318 ci->ci_dev = cpuname; 1319 1320 ci->ci_cpu_type = x86_identify(); 1321 if (ci->ci_cpu_type >= 0) { 1322 /* Old pre-cpuid instruction cpu */ 1323 ci->ci_cpuid_level = -1; 1324 return; 1325 } 1326 1327 x86_cpuid(0, descs); 1328 ci->ci_cpuid_level = descs[0]; 1329 ci->ci_vendor[0] = descs[1]; 1330 ci->ci_vendor[2] = descs[2]; 1331 ci->ci_vendor[1] = descs[3]; 1332 ci->ci_vendor[3] = 0; 1333 1334 x86_cpuid(0x80000000, brand); 1335 if (brand[0] >= 0x80000004) { 1336 x86_cpuid(0x80000002, brand); 1337 x86_cpuid(0x80000003, brand + 4); 1338 x86_cpuid(0x80000004, brand + 8); 1339 for (i = 0; i < 48; i++) 1340 if (((char *) brand)[i] != ' ') 1341 break; 1342 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1343 } 1344 1345 if (ci->ci_cpuid_level < 1) 1346 return; 1347 1348 x86_cpuid(1, descs); 1349 ci->ci_signature = descs[0]; 1350 1351 /* Extract full family/model values */ 1352 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 1353 ci->ci_model = CPUID2MODEL(ci->ci_signature); 1354 if (ci->ci_family == 15) 1355 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 1356 if (ci->ci_family == 6 || ci->ci_family == 15) 1357 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 1358 1359 /* Brand is low order 8 bits of ebx */ 1360 ci->ci_brand_id = descs[1] & 0xff; 1361 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1362 1363 ci->ci_feat_val[1] = descs[2]; 1364 ci->ci_feat_val[0] = descs[3]; 1365 1366 if (ci->ci_cpuid_level < 2) 1367 return; 1368 1369 /* 1370 * Parse the cache info from `cpuid leaf 2', if we have it. 1371 * XXX This is kinda ugly, but hey, so is the architecture... 1372 */ 1373 1374 x86_cpuid(2, descs); 1375 1376 iterations = descs[0] & 0xff; 1377 while (iterations-- > 0) { 1378 for (i = 0; i < 4; i++) { 1379 if (descs[i] & 0x80000000) 1380 continue; 1381 for (j = 0; j < 4; j++) { 1382 if (i == 0 && j == 0) 1383 continue; 1384 desc = (descs[i] >> (j * 8)) & 0xff; 1385 if (desc == 0) 1386 continue; 1387 cai = cache_info_lookup(intel_cpuid_cache_info, 1388 desc); 1389 if (cai != NULL) 1390 ci->ci_cinfo[cai->cai_index] = *cai; 1391 } 1392 } 1393 x86_cpuid(2, descs); 1394 } 1395 1396 if (ci->ci_cpuid_level < 3) 1397 return; 1398 1399 /* 1400 * If the processor serial number misfeature is present and supported, 1401 * extract it here. 1402 */ 1403 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1404 ci->ci_cpu_serial[0] = ci->ci_signature; 1405 x86_cpuid(3, descs); 1406 ci->ci_cpu_serial[2] = descs[2]; 1407 ci->ci_cpu_serial[1] = descs[3]; 1408 } 1409 1410 if (ci->ci_cpuid_level < 4) 1411 return; 1412 1413 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1414 for (i = 0; ; i++) { 1415 x86_cpuid2(4, i, descs); 1416 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1417 if (type == CPUID_DCP_CACHETYPE_N) 1418 break; 1419 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1420 switch (level) { 1421 case 1: 1422 if (type == CPUID_DCP_CACHETYPE_I) 1423 caitype = CAI_ICACHE; 1424 else if (type == CPUID_DCP_CACHETYPE_D) 1425 caitype = CAI_DCACHE; 1426 else 1427 caitype = -1; 1428 break; 1429 case 2: 1430 if (type == CPUID_DCP_CACHETYPE_U) 1431 caitype = CAI_L2CACHE; 1432 else 1433 caitype = -1; 1434 break; 1435 case 3: 1436 if (type == CPUID_DCP_CACHETYPE_U) 1437 caitype = CAI_L3CACHE; 1438 else 1439 caitype = -1; 1440 break; 1441 default: 1442 caitype = -1; 1443 break; 1444 } 1445 if (caitype == -1) { 1446 printf("unknown cache level&type (%d & %d)\n", 1447 level, type); 1448 continue; 1449 } 1450 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1451 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1452 + 1; 1453 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1454 + 1; 1455 sets = descs[2] + 1; 1456 totalsize = ways * partitions * linesize * sets; 1457 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1458 ci->ci_cinfo[caitype].cai_associativity = ways; 1459 ci->ci_cinfo[caitype].cai_linesize = linesize; 1460 } 1461 1462 if (ci->ci_cpuid_level < 0xd) 1463 return; 1464 1465 /* Get support XCR0 bits */ 1466 x86_cpuid2(0xd, 0, descs); 1467 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1468 ci->ci_cur_xsave = descs[1]; 1469 ci->ci_max_xsave = descs[2]; 1470 1471 /* Additional flags (eg xsaveopt support) */ 1472 x86_cpuid2(0xd, 1, descs); 1473 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1474 } 1475 1476 static void 1477 cpu_probe_features(struct cpu_info *ci) 1478 { 1479 const struct cpu_cpuid_nameclass *cpup = NULL; 1480 unsigned int i; 1481 1482 if (ci->ci_cpuid_level < 1) 1483 return; 1484 1485 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1486 if (!strncmp((char *)ci->ci_vendor, 1487 i386_cpuid_cpus[i].cpu_id, 12)) { 1488 cpup = &i386_cpuid_cpus[i]; 1489 break; 1490 } 1491 } 1492 1493 if (cpup == NULL) 1494 return; 1495 1496 i = ci->ci_family - CPU_MINFAMILY; 1497 1498 if (i >= __arraycount(cpup->cpu_family)) 1499 i = __arraycount(cpup->cpu_family) - 1; 1500 1501 if (cpup->cpu_family[i].cpu_probe == NULL) 1502 return; 1503 1504 (*cpup->cpu_family[i].cpu_probe)(ci); 1505 } 1506 1507 static void 1508 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1509 { 1510 char buf[32 * 16]; 1511 char *bp; 1512 1513 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1514 1515 if (val == 0 || fmt == NULL) 1516 return; 1517 1518 snprintb_m(buf, sizeof(buf), fmt, val, 1519 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1520 bp = buf; 1521 while (*bp != '\0') { 1522 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1523 bp += strlen(bp) + 1; 1524 } 1525 } 1526 1527 static void 1528 identifycpu_cpuids(struct cpu_info *ci) 1529 { 1530 const char *cpuname = ci->ci_dev; 1531 u_int lp_max = 1; /* logical processors per package */ 1532 u_int smt_max; /* smt per core */ 1533 u_int core_max = 1; /* core per package */ 1534 u_int smt_bits, core_bits; 1535 uint32_t descs[4]; 1536 uint32_t highest_basic_info; 1537 1538 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1539 ci->ci_packageid = ci->ci_initapicid; 1540 ci->ci_coreid = 0; 1541 ci->ci_smtid = 0; 1542 if (cpu_vendor != CPUVENDOR_INTEL) { 1543 return; 1544 } 1545 1546 /* 1547 * 253668.pdf 7.10.2 1548 */ 1549 1550 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1551 x86_cpuid(1, descs); 1552 lp_max = (descs[1] >> 16) & 0xff; 1553 } 1554 x86_cpuid(0, descs); 1555 highest_basic_info = descs[0]; 1556 if (highest_basic_info >= 4) { 1557 x86_cpuid2(4, 0, descs); 1558 core_max = (descs[0] >> 26) + 1; 1559 } 1560 assert(lp_max >= core_max); 1561 smt_max = lp_max / core_max; 1562 smt_bits = ilog2(smt_max - 1) + 1; 1563 core_bits = ilog2(core_max - 1) + 1; 1564 if (smt_bits + core_bits) { 1565 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1566 } 1567 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1568 ci->ci_packageid); 1569 if (core_bits) { 1570 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1571 1572 ci->ci_coreid = 1573 __SHIFTOUT(ci->ci_initapicid, core_mask); 1574 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1575 } 1576 if (smt_bits) { 1577 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1578 1579 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1580 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1581 } 1582 } 1583 1584 void 1585 identifycpu(int fd, const char *cpuname) 1586 { 1587 const char *name = "", *modifier, *vendorname, *brand = ""; 1588 int class = CPUCLASS_386; 1589 unsigned int i; 1590 int modif, family; 1591 const struct cpu_cpuid_nameclass *cpup = NULL; 1592 const struct cpu_cpuid_family *cpufam; 1593 struct cpu_info *ci, cistore; 1594 size_t sz; 1595 struct cpu_ucode_version ucode; 1596 union { 1597 struct cpu_ucode_version_amd amd; 1598 struct cpu_ucode_version_intel1 intel1; 1599 } ucvers; 1600 1601 ci = &cistore; 1602 cpu_probe_base_features(ci, cpuname); 1603 cpu_probe_features(ci); 1604 1605 if (ci->ci_cpu_type >= 0) { 1606 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1607 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1608 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1609 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1610 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1611 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1612 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1613 modifier = ""; 1614 } else { 1615 modif = (ci->ci_signature >> 12) & 0x3; 1616 family = ci->ci_family; 1617 if (family < CPU_MINFAMILY) 1618 errx(1, "identifycpu: strange family value"); 1619 if (family > CPU_MAXFAMILY) 1620 family = CPU_MAXFAMILY; 1621 1622 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1623 if (!strncmp((char *)ci->ci_vendor, 1624 i386_cpuid_cpus[i].cpu_id, 12)) { 1625 cpup = &i386_cpuid_cpus[i]; 1626 break; 1627 } 1628 } 1629 1630 if (cpup == NULL) { 1631 cpu_vendor = CPUVENDOR_UNKNOWN; 1632 if (ci->ci_vendor[0] != '\0') 1633 vendorname = (char *)&ci->ci_vendor[0]; 1634 else 1635 vendorname = "Unknown"; 1636 class = family - 3; 1637 modifier = ""; 1638 name = ""; 1639 ci->ci_info = NULL; 1640 } else { 1641 cpu_vendor = cpup->cpu_vendor; 1642 vendorname = cpup->cpu_vendorname; 1643 modifier = modifiers[modif]; 1644 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1645 name = cpufam->cpu_models[ci->ci_model]; 1646 if (name == NULL || *name == '\0') 1647 name = cpufam->cpu_model_default; 1648 class = cpufam->cpu_class; 1649 ci->ci_info = cpufam->cpu_info; 1650 1651 if (cpu_vendor == CPUVENDOR_INTEL) { 1652 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1653 const char *tmp; 1654 tmp = intel_family6_name(ci); 1655 if (tmp != NULL) 1656 name = tmp; 1657 } 1658 if (ci->ci_family == 15 && 1659 ci->ci_brand_id < 1660 __arraycount(i386_intel_brand) && 1661 i386_intel_brand[ci->ci_brand_id]) 1662 name = 1663 i386_intel_brand[ci->ci_brand_id]; 1664 } 1665 1666 if (cpu_vendor == CPUVENDOR_AMD) { 1667 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1668 if (ci->ci_brand_id == 1) 1669 /* 1670 * It's Duron. We override the 1671 * name, since it might have 1672 * been misidentified as Athlon. 1673 */ 1674 name = 1675 amd_brand[ci->ci_brand_id]; 1676 else 1677 brand = amd_brand_name; 1678 } 1679 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1680 /* Identify AMD64 CPU names. */ 1681 const char *tmp; 1682 tmp = amd_amd64_name(ci); 1683 if (tmp != NULL) 1684 name = tmp; 1685 } 1686 } 1687 1688 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1689 vendorname = "VIA"; 1690 } 1691 } 1692 1693 ci->ci_cpu_class = class; 1694 1695 sz = sizeof(ci->ci_tsc_freq); 1696 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1697 sz = sizeof(use_pae); 1698 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1699 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1700 1701 /* 1702 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1703 * we try to determine from the family/model values. 1704 */ 1705 if (*cpu_brand_string != '\0') 1706 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1707 1708 aprint_normal("%s: %s", cpuname, vendorname); 1709 if (*modifier) 1710 aprint_normal(" %s", modifier); 1711 if (*name) 1712 aprint_normal(" %s", name); 1713 if (*brand) 1714 aprint_normal(" %s", brand); 1715 aprint_normal(" (%s-class)", classnames[class]); 1716 1717 if (ci->ci_tsc_freq != 0) 1718 aprint_normal(", %ju.%02ju MHz\n", 1719 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1720 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1721 1722 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1723 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1724 if (ci->ci_signature != 0) 1725 aprint_normal(" (id %#x)", ci->ci_signature); 1726 aprint_normal("\n"); 1727 1728 if (ci->ci_info) 1729 (*ci->ci_info)(ci); 1730 1731 /* 1732 * display CPU feature flags 1733 */ 1734 1735 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1736 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1737 1738 /* These next two are actually common definitions! */ 1739 print_bits(cpuname, "features2", 1740 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1741 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1742 print_bits(cpuname, "features3", 1743 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1744 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1745 1746 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1747 ci->ci_feat_val[4]); 1748 1749 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1750 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1751 ci->ci_feat_val[6]); 1752 1753 if (ci->ci_max_xsave != 0) { 1754 aprint_normal("%s: xsave area size: current %d, maximum %d", 1755 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1756 aprint_normal(", xgetbv %sabled\n", 1757 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1758 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1759 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1760 x86_xgetbv()); 1761 } 1762 1763 x86_print_cacheinfo(ci); 1764 1765 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1766 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1767 cpuname, 1768 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1769 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1770 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1771 } 1772 1773 if (ci->ci_cpu_class == CPUCLASS_386) { 1774 errx(1, "NetBSD requires an 80486 or later processor"); 1775 } 1776 1777 if (ci->ci_cpu_type == CPU_486DLC) { 1778 #ifndef CYRIX_CACHE_WORKS 1779 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1780 #else 1781 #ifndef CYRIX_CACHE_REALLY_WORKS 1782 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1783 #else 1784 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1785 #endif 1786 #endif 1787 } 1788 1789 /* 1790 * Everything past this point requires a Pentium or later. 1791 */ 1792 if (ci->ci_cpuid_level < 0) 1793 return; 1794 1795 identifycpu_cpuids(ci); 1796 1797 #ifdef INTEL_CORETEMP 1798 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1799 coretemp_register(ci); 1800 #endif 1801 1802 if (cpu_vendor == CPUVENDOR_AMD) { 1803 uint32_t data[4]; 1804 1805 x86_cpuid(0x80000000, data); 1806 if (data[0] >= 0x80000007) 1807 powernow_probe(ci); 1808 1809 if ((data[0] >= 0x8000000a) 1810 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1811 x86_cpuid(0x8000000a, data); 1812 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1813 data[0] & 0xf); 1814 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1815 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1816 data[3]); 1817 } 1818 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1819 uint32_t data[4]; 1820 uint32_t highest_basic_info; 1821 uint32_t bi_index; 1822 1823 x86_cpuid(0x00000000, data); 1824 highest_basic_info = data[0]; 1825 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1826 highest_basic_info); 1827 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1828 x86_cpuid(bi_index, data); 1829 switch (bi_index) { 1830 case 6: 1831 print_bits(cpuname, "DSPM-eax", 1832 CPUID_DSPM_FLAGS, data[0]); 1833 print_bits(cpuname, "DSPM-ecx", 1834 CPUID_DSPM_FLAGS1, data[2]); 1835 break; 1836 case 7: 1837 aprint_verbose("%s: SEF highest subleaf %08x\n", 1838 cpuname, data[0]); 1839 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1840 data[1]); 1841 break; 1842 #if 0 1843 default: 1844 aprint_verbose("%s: basic %08x-eax %08x\n", 1845 cpuname, bi_index, data[0]); 1846 aprint_verbose("%s: basic %08x-ebx %08x\n", 1847 cpuname, bi_index, data[1]); 1848 aprint_verbose("%s: basic %08x-ecx %08x\n", 1849 cpuname, bi_index, data[2]); 1850 aprint_verbose("%s: basic %08x-edx %08x\n", 1851 cpuname, bi_index, data[3]); 1852 break; 1853 #endif 1854 } 1855 } 1856 } 1857 1858 #ifdef INTEL_ONDEMAND_CLOCKMOD 1859 clockmod_init(); 1860 #endif 1861 1862 if (cpu_vendor == CPUVENDOR_AMD) 1863 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1864 else if (cpu_vendor == CPUVENDOR_INTEL) 1865 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1866 else 1867 return; 1868 1869 ucode.data = &ucvers; 1870 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1871 #ifdef __i386__ 1872 struct cpu_ucode_version_64 ucode_64; 1873 if (errno != ENOTTY) 1874 return; 1875 /* Try the 64 bit ioctl */ 1876 memset(&ucode_64, 0, sizeof ucode_64); 1877 ucode_64.data = &ucvers; 1878 ucode_64.loader_version = ucode.loader_version; 1879 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1880 return; 1881 #endif 1882 } 1883 1884 if (cpu_vendor == CPUVENDOR_AMD) 1885 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1886 else if (cpu_vendor == CPUVENDOR_INTEL) 1887 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1888 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1889 } 1890 1891 static const char * 1892 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1893 const char *sep) 1894 { 1895 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1896 char human_num[HUMAN_BUFSIZE]; 1897 1898 if (cai->cai_totalsize == 0) 1899 return sep; 1900 1901 if (sep == NULL) 1902 aprint_verbose_dev(ci->ci_dev, ""); 1903 else 1904 aprint_verbose("%s", sep); 1905 if (name != NULL) 1906 aprint_verbose("%s ", name); 1907 1908 if (cai->cai_string != NULL) { 1909 aprint_verbose("%s ", cai->cai_string); 1910 } else { 1911 (void)humanize_number(human_num, sizeof(human_num), 1912 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1913 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1914 } 1915 switch (cai->cai_associativity) { 1916 case 0: 1917 aprint_verbose("disabled"); 1918 break; 1919 case 1: 1920 aprint_verbose("direct-mapped"); 1921 break; 1922 case 0xff: 1923 aprint_verbose("fully associative"); 1924 break; 1925 default: 1926 aprint_verbose("%d-way", cai->cai_associativity); 1927 break; 1928 } 1929 return ", "; 1930 } 1931 1932 static const char * 1933 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1934 const char *sep) 1935 { 1936 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1937 char human_num[HUMAN_BUFSIZE]; 1938 1939 if (cai->cai_totalsize == 0) 1940 return sep; 1941 1942 if (sep == NULL) 1943 aprint_verbose_dev(ci->ci_dev, ""); 1944 else 1945 aprint_verbose("%s", sep); 1946 if (name != NULL) 1947 aprint_verbose("%s ", name); 1948 1949 if (cai->cai_string != NULL) { 1950 aprint_verbose("%s", cai->cai_string); 1951 } else { 1952 (void)humanize_number(human_num, sizeof(human_num), 1953 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1954 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1955 human_num); 1956 switch (cai->cai_associativity) { 1957 case 0: 1958 aprint_verbose("disabled"); 1959 break; 1960 case 1: 1961 aprint_verbose("direct-mapped"); 1962 break; 1963 case 0xff: 1964 aprint_verbose("fully associative"); 1965 break; 1966 default: 1967 aprint_verbose("%d-way", cai->cai_associativity); 1968 break; 1969 } 1970 } 1971 return ", "; 1972 } 1973 1974 static const struct x86_cache_info * 1975 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1976 { 1977 int i; 1978 1979 for (i = 0; cai[i].cai_desc != 0; i++) { 1980 if (cai[i].cai_desc == desc) 1981 return (&cai[i]); 1982 } 1983 1984 return (NULL); 1985 } 1986 1987 static void 1988 x86_print_cacheinfo(struct cpu_info *ci) 1989 { 1990 const char *sep = NULL; 1991 1992 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1993 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1994 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1995 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1996 if (sep != NULL) 1997 aprint_verbose("\n"); 1998 } 1999 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2000 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2001 if (sep != NULL) 2002 aprint_verbose("\n"); 2003 } 2004 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2005 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2006 if (sep != NULL) 2007 aprint_verbose("\n"); 2008 } 2009 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2010 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2011 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2012 if (sep != NULL) 2013 aprint_verbose("\n"); 2014 } 2015 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2016 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2017 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2018 if (sep != NULL) 2019 aprint_verbose("\n"); 2020 } 2021 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2022 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2023 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2024 if (sep != NULL) 2025 aprint_verbose("\n"); 2026 } 2027 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2028 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2029 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2030 if (sep != NULL) 2031 aprint_verbose("\n"); 2032 } 2033 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2034 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2035 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2036 if (sep != NULL) 2037 aprint_verbose("\n"); 2038 } 2039 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2040 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2041 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2042 if (sep != NULL) 2043 aprint_verbose("\n"); 2044 } 2045 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2046 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2047 NULL); 2048 if (sep != NULL) 2049 aprint_verbose("\n"); 2050 } 2051 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2052 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2053 NULL); 2054 if (sep != NULL) 2055 aprint_verbose("\n"); 2056 } 2057 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2058 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2059 NULL); 2060 if (sep != NULL) 2061 aprint_verbose("\n"); 2062 } 2063 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2064 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2065 NULL); 2066 if (sep != NULL) 2067 aprint_verbose("\n"); 2068 } 2069 } 2070 2071 static void 2072 powernow_probe(struct cpu_info *ci) 2073 { 2074 uint32_t regs[4]; 2075 char buf[256]; 2076 2077 x86_cpuid(0x80000007, regs); 2078 2079 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2080 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2081 buf); 2082 } 2083 2084 int 2085 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2086 { 2087 struct cpu_info ci; 2088 int loader_version, res; 2089 struct cpu_ucode_version versreq; 2090 2091 cpu_probe_base_features(&ci, "unknown"); 2092 2093 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2094 loader_version = CPU_UCODE_LOADER_AMD; 2095 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2096 loader_version = CPU_UCODE_LOADER_INTEL1; 2097 else 2098 return -1; 2099 2100 /* check whether the kernel understands this loader version */ 2101 versreq.loader_version = loader_version; 2102 versreq.data = 0; 2103 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2104 if (res) 2105 return -1; 2106 2107 switch (loader_version) { 2108 case CPU_UCODE_LOADER_AMD: 2109 if (uc->cpu_nr != -1) { 2110 /* printf? */ 2111 return -1; 2112 } 2113 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2114 break; 2115 case CPU_UCODE_LOADER_INTEL1: 2116 if (uc->cpu_nr == -1) 2117 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2118 else 2119 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2120 break; 2121 default: /* can't happen */ 2122 return -1; 2123 } 2124 uc->loader_version = loader_version; 2125 return 0; 2126 } 2127
Indexes created Fri Sep 26 20:09:58 GMT 2025