i386.c revision 1.51
1 /* $NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.51 2013/12/23 10:13:59 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 155 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 156 * Architectures Software Developer's Manual, Volume 2A". 157 */ 158 static const char * const i386_intel_brand[] = { 159 "", /* Unsupported */ 160 "Celeron", /* Intel (R) Celeron (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 163 "Pentium III", /* Intel (R) Pentium (R) III processor */ 164 "", /* 0x05: Reserved */ 165 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Celeron", /* Intel (R) Celeron (TM) processor */ 170 "Xeon", /* Intel (R) Xeon (TM) processor */ 171 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 172 "", /* 0x0d: Reserved */ 173 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 174 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 175 "", /* 0x10: Reserved */ 176 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 177 "Celeron M", /* Intel (R) Celeron (R) M processor */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "Celeron", /* Intel (R) Celeron (R) processor */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Pentium M", /* Intel (R) Pentium (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 }; 184 185 /* 186 * AMD processors don't have Brand IDs, so we need these names for probe. 187 */ 188 static const char * const amd_brand[] = { 189 "", 190 "Duron", /* AMD Duron(tm) */ 191 "MP", /* AMD Athlon(tm) MP */ 192 "XP", /* AMD Athlon(tm) XP */ 193 "4" /* AMD Athlon(tm) 4 */ 194 }; 195 196 static int cpu_vendor; 197 static char cpu_brand_string[49]; 198 static char amd_brand_name[48]; 199 static int use_pae, largepagesize; 200 201 /* Setup functions */ 202 static void disable_tsc(struct cpu_info *); 203 static void amd_family5_setup(struct cpu_info *); 204 static void cyrix6x86_cpu_setup(struct cpu_info *); 205 static void winchip_cpu_setup(struct cpu_info *); 206 /* Brand/Model name functions */ 207 static const char *intel_family6_name(struct cpu_info *); 208 static const char *amd_amd64_name(struct cpu_info *); 209 /* Probe functions */ 210 static void amd_family6_probe(struct cpu_info *); 211 static void powernow_probe(struct cpu_info *); 212 static void intel_family_new_probe(struct cpu_info *); 213 static void via_cpu_probe(struct cpu_info *); 214 /* (Cache) Info functions */ 215 static void amd_cpu_cacheinfo(struct cpu_info *); 216 static void via_cpu_cacheinfo(struct cpu_info *); 217 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 218 static void transmeta_cpu_info(struct cpu_info *); 219 /* Common functions */ 220 static void cpu_probe_base_features(struct cpu_info *, const char *); 221 static void cpu_probe_features(struct cpu_info *); 222 static void print_bits(const char *, const char *, const char *, uint32_t); 223 static void identifycpu_cpuids(struct cpu_info *); 224 static const char *print_cache_config(struct cpu_info *, int, const char *, 225 const char *); 226 static const char *print_tlb_config(struct cpu_info *, int, const char *, 227 const char *); 228 static const struct x86_cache_info *cache_info_lookup( 229 const struct x86_cache_info *, uint8_t); 230 static void x86_print_cacheinfo(struct cpu_info *); 231 232 /* 233 * Note: these are just the ones that may not have a cpuid instruction. 234 * We deal with the rest in a different way. 235 */ 236 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 237 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 238 NULL, NULL, NULL }, /* CPU_386SX */ 239 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 240 NULL, NULL, NULL }, /* CPU_386 */ 241 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 242 NULL, NULL, NULL }, /* CPU_486SX */ 243 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 244 NULL, NULL, NULL }, /* CPU_486 */ 245 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 246 NULL, NULL, NULL }, /* CPU_486DLC */ 247 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_6x86 */ 249 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 250 NULL, NULL, NULL }, /* CPU_NX586 */ 251 }; 252 253 const char *classnames[] = { 254 "386", 255 "486", 256 "586", 257 "686" 258 }; 259 260 const char *modifiers[] = { 261 "", 262 "OverDrive", 263 "Dual", 264 "" 265 }; 266 267 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 268 { 269 /* 270 * For Intel processors, check Chapter 35Model-specific 271 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 272 * Software Developer's Manual, Volume 3C". 273 */ 274 "GenuineIntel", 275 CPUVENDOR_INTEL, 276 "Intel", 277 /* Family 4 */ 278 { { 279 CPUCLASS_486, 280 { 281 "486DX", "486DX", "486SX", "486DX2", "486SL", 282 "486SX2", 0, "486DX2 W/B Enhanced", 283 "486DX4", 0, 0, 0, 0, 0, 0, 0, 284 }, 285 "486", /* Default */ 286 NULL, 287 NULL, 288 NULL, 289 }, 290 /* Family 5 */ 291 { 292 CPUCLASS_586, 293 { 294 "Pentium (P5 A-step)", "Pentium (P5)", 295 "Pentium (P54C)", "Pentium (P24T)", 296 "Pentium/MMX", "Pentium", 0, 297 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 298 0, 0, 0, 0, 0, 0, 0, 299 }, 300 "Pentium", /* Default */ 301 NULL, 302 NULL, 303 NULL, 304 }, 305 /* Family 6 */ 306 { 307 CPUCLASS_686, 308 { 309 [0x00] = "Pentium Pro (A-step)", 310 [0x01] = "Pentium Pro", 311 [0x03] = "Pentium II (Klamath)", 312 [0x04] = "Pentium Pro", 313 [0x05] = "Pentium II/Celeron (Deschutes)", 314 [0x06] = "Celeron (Mendocino)", 315 [0x07] = "Pentium III (Katmai)", 316 [0x08] = "Pentium III (Coppermine)", 317 [0x09] = "Pentium M (Banias)", 318 [0x0a] = "Pentium III Xeon (Cascades)", 319 [0x0b] = "Pentium III (Tualatin)", 320 [0x0d] = "Pentium M (Dothan)", 321 [0x0e] = "Pentium Core Duo, Core solo", 322 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 323 "Core 2 Quad 6xxx, " 324 "Core 2 Extreme 6xxx, " 325 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 326 "and Pentium DC", 327 [0x15] = "EP80579 Integrated Processor", 328 [0x16] = "Celeron (45nm)", 329 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 330 "Core 2 Quad 8xxx and 9xxx", 331 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 332 "(Nehalem)", 333 [0x1c] = "Atom Family", 334 [0x1d] = "XeonMP 74xx (Nehalem)", 335 [0x1e] = "Core i7 and i5", 336 [0x1f] = "Core i7 and i5", 337 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 338 [0x26] = "Atom Family", 339 [0x27] = "Atom Family", 340 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 341 "i3 2xxx", 342 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x2d] = "Xeon E5 Sandy Bridge family, " 344 "Core i7-39xx Extreme", 345 [0x2e] = "Xeon 75xx & 65xx", 346 [0x2f] = "Xeon E7 family", 347 [0x35] = "Atom Family", 348 [0x36] = "Atom S1000", 349 [0x37] = "Atom C2000, E3000", 350 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 351 "Ivy Bridge", 352 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 353 "(Haswell)", 354 [0x3d] = "Next gen Core", 355 [0x3e] = "Xeon E5/E7, Ivy Bridge-EP", 356 [0x3f] = "Future gen Xeon", 357 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 360 "(Haswell)", 361 [0x4d] = "Atom C2000, E3000", 362 }, 363 "Pentium Pro, II or III", /* Default */ 364 NULL, 365 intel_family_new_probe, 366 NULL, 367 }, 368 /* Family > 6 */ 369 { 370 CPUCLASS_686, 371 { 372 0, 0, 0, 0, 0, 0, 0, 0, 373 0, 0, 0, 0, 0, 0, 0, 0, 374 }, 375 "Pentium 4", /* Default */ 376 NULL, 377 intel_family_new_probe, 378 NULL, 379 } } 380 }, 381 { 382 "AuthenticAMD", 383 CPUVENDOR_AMD, 384 "AMD", 385 /* Family 4 */ 386 { { 387 CPUCLASS_486, 388 { 389 0, 0, 0, "Am486DX2 W/T", 390 0, 0, 0, "Am486DX2 W/B", 391 "Am486DX4 W/T or Am5x86 W/T 150", 392 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 393 0, 0, "Am5x86 W/T 133/160", 394 "Am5x86 W/B 133/160", 395 }, 396 "Am486 or Am5x86", /* Default */ 397 NULL, 398 NULL, 399 NULL, 400 }, 401 /* Family 5 */ 402 { 403 CPUCLASS_586, 404 { 405 "K5", "K5", "K5", "K5", 0, 0, "K6", 406 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 407 "K6-2+/III+", 0, 0, 408 }, 409 "K5 or K6", /* Default */ 410 amd_family5_setup, 411 NULL, 412 amd_cpu_cacheinfo, 413 }, 414 /* Family 6 */ 415 { 416 CPUCLASS_686, 417 { 418 0, "Athlon Model 1", "Athlon Model 2", 419 "Duron", "Athlon Model 4 (Thunderbird)", 420 0, "Athlon", "Duron", "Athlon", 0, 421 "Athlon", 0, 0, 0, 0, 0, 422 }, 423 "K7 (Athlon)", /* Default */ 424 NULL, 425 amd_family6_probe, 426 amd_cpu_cacheinfo, 427 }, 428 /* Family > 6 */ 429 { 430 CPUCLASS_686, 431 { 432 0, 0, 0, 0, 0, 0, 0, 0, 433 0, 0, 0, 0, 0, 0, 0, 0, 434 }, 435 "Unknown K8 (Athlon)", /* Default */ 436 NULL, 437 amd_family6_probe, 438 amd_cpu_cacheinfo, 439 } } 440 }, 441 { 442 "CyrixInstead", 443 CPUVENDOR_CYRIX, 444 "Cyrix", 445 /* Family 4 */ 446 { { 447 CPUCLASS_486, 448 { 449 0, 0, 0, 450 "MediaGX", 451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 452 }, 453 "486", /* Default */ 454 cyrix6x86_cpu_setup, /* XXX ?? */ 455 NULL, 456 NULL, 457 }, 458 /* Family 5 */ 459 { 460 CPUCLASS_586, 461 { 462 0, 0, "6x86", 0, 463 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 465 }, 466 "6x86", /* Default */ 467 cyrix6x86_cpu_setup, 468 NULL, 469 NULL, 470 }, 471 /* Family 6 */ 472 { 473 CPUCLASS_686, 474 { 475 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 476 0, 0, 0, 0, 0, 0, 0, 0, 477 }, 478 "6x86MX", /* Default */ 479 cyrix6x86_cpu_setup, 480 NULL, 481 NULL, 482 }, 483 /* Family > 6 */ 484 { 485 CPUCLASS_686, 486 { 487 0, 0, 0, 0, 0, 0, 0, 0, 488 0, 0, 0, 0, 0, 0, 0, 0, 489 }, 490 "Unknown 6x86MX", /* Default */ 491 NULL, 492 NULL, 493 NULL, 494 } } 495 }, 496 { /* MediaGX is now owned by National Semiconductor */ 497 "Geode by NSC", 498 CPUVENDOR_CYRIX, /* XXX */ 499 "National Semiconductor", 500 /* Family 4, NSC never had any of these */ 501 { { 502 CPUCLASS_486, 503 { 504 0, 0, 0, 0, 0, 0, 0, 0, 505 0, 0, 0, 0, 0, 0, 0, 0, 506 }, 507 "486 compatible", /* Default */ 508 NULL, 509 NULL, 510 NULL, 511 }, 512 /* Family 5: Geode family, formerly MediaGX */ 513 { 514 CPUCLASS_586, 515 { 516 0, 0, 0, 0, 517 "Geode GX1", 518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 519 }, 520 "Geode", /* Default */ 521 cyrix6x86_cpu_setup, 522 NULL, 523 amd_cpu_cacheinfo, 524 }, 525 /* Family 6, not yet available from NSC */ 526 { 527 CPUCLASS_686, 528 { 529 0, 0, 0, 0, 0, 0, 0, 0, 530 0, 0, 0, 0, 0, 0, 0, 0, 531 }, 532 "Pentium Pro compatible", /* Default */ 533 NULL, 534 NULL, 535 NULL, 536 }, 537 /* Family > 6, not yet available from NSC */ 538 { 539 CPUCLASS_686, 540 { 541 0, 0, 0, 0, 0, 0, 0, 0, 542 0, 0, 0, 0, 0, 0, 0, 0, 543 }, 544 "Pentium Pro compatible", /* Default */ 545 NULL, 546 NULL, 547 NULL, 548 } } 549 }, 550 { 551 "CentaurHauls", 552 CPUVENDOR_IDT, 553 "IDT", 554 /* Family 4, IDT never had any of these */ 555 { { 556 CPUCLASS_486, 557 { 558 0, 0, 0, 0, 0, 0, 0, 0, 559 0, 0, 0, 0, 0, 0, 0, 0, 560 }, 561 "486 compatible", /* Default */ 562 NULL, 563 NULL, 564 NULL, 565 }, 566 /* Family 5 */ 567 { 568 CPUCLASS_586, 569 { 570 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 571 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 572 }, 573 "WinChip", /* Default */ 574 winchip_cpu_setup, 575 NULL, 576 NULL, 577 }, 578 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 579 { 580 CPUCLASS_686, 581 { 582 0, 0, 0, 0, 0, 0, "C3 Samuel", 583 "C3 Samuel 2/Ezra", "C3 Ezra-T", 584 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 585 0, "VIA Nano", 586 }, 587 "Unknown VIA/IDT", /* Default */ 588 NULL, 589 via_cpu_probe, 590 via_cpu_cacheinfo, 591 }, 592 /* Family > 6, not yet available from VIA */ 593 { 594 CPUCLASS_686, 595 { 596 0, 0, 0, 0, 0, 0, 0, 0, 597 0, 0, 0, 0, 0, 0, 0, 0, 598 }, 599 "Pentium Pro compatible", /* Default */ 600 NULL, 601 NULL, 602 NULL, 603 } } 604 }, 605 { 606 "GenuineTMx86", 607 CPUVENDOR_TRANSMETA, 608 "Transmeta", 609 /* Family 4, Transmeta never had any of these */ 610 { { 611 CPUCLASS_486, 612 { 613 0, 0, 0, 0, 0, 0, 0, 0, 614 0, 0, 0, 0, 0, 0, 0, 0, 615 }, 616 "486 compatible", /* Default */ 617 NULL, 618 NULL, 619 NULL, 620 }, 621 /* Family 5 */ 622 { 623 CPUCLASS_586, 624 { 625 0, 0, 0, 0, 0, 0, 0, 0, 626 0, 0, 0, 0, 0, 0, 0, 0, 627 }, 628 "Crusoe", /* Default */ 629 NULL, 630 NULL, 631 transmeta_cpu_info, 632 }, 633 /* Family 6, not yet available from Transmeta */ 634 { 635 CPUCLASS_686, 636 { 637 0, 0, 0, 0, 0, 0, 0, 0, 638 0, 0, 0, 0, 0, 0, 0, 0, 639 }, 640 "Pentium Pro compatible", /* Default */ 641 NULL, 642 NULL, 643 NULL, 644 }, 645 /* Family > 6, not yet available from Transmeta */ 646 { 647 CPUCLASS_686, 648 { 649 0, 0, 0, 0, 0, 0, 0, 0, 650 0, 0, 0, 0, 0, 0, 0, 0, 651 }, 652 "Pentium Pro compatible", /* Default */ 653 NULL, 654 NULL, 655 NULL, 656 } } 657 } 658 }; 659 660 /* 661 * disable the TSC such that we don't use the TSC in microtime(9) 662 * because some CPUs got the implementation wrong. 663 */ 664 static void 665 disable_tsc(struct cpu_info *ci) 666 { 667 if (ci->ci_feat_val[0] & CPUID_TSC) { 668 ci->ci_feat_val[0] &= ~CPUID_TSC; 669 aprint_error("WARNING: broken TSC disabled\n"); 670 } 671 } 672 673 static void 674 amd_family5_setup(struct cpu_info *ci) 675 { 676 677 switch (ci->ci_model) { 678 case 0: /* AMD-K5 Model 0 */ 679 /* 680 * According to the AMD Processor Recognition App Note, 681 * the AMD-K5 Model 0 uses the wrong bit to indicate 682 * support for global PTEs, instead using bit 9 (APIC) 683 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 684 */ 685 if (ci->ci_feat_val[0] & CPUID_APIC) 686 ci->ci_feat_val[0] = 687 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 688 /* 689 * XXX But pmap_pg_g is already initialized -- need to kick 690 * XXX the pmap somehow. How does the MP branch do this? 691 */ 692 break; 693 } 694 } 695 696 static void 697 cyrix6x86_cpu_setup(struct cpu_info *ci) 698 { 699 700 /* 701 * Do not disable the TSC on the Geode GX, it's reported to 702 * work fine. 703 */ 704 if (ci->ci_signature != 0x552) 705 disable_tsc(ci); 706 } 707 708 static void 709 winchip_cpu_setup(struct cpu_info *ci) 710 { 711 switch (ci->ci_model) { 712 case 4: /* WinChip C6 */ 713 disable_tsc(ci); 714 } 715 } 716 717 718 static const char * 719 intel_family6_name(struct cpu_info *ci) 720 { 721 const char *ret = NULL; 722 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 723 724 if (ci->ci_model == 5) { 725 switch (l2cache) { 726 case 0: 727 case 128 * 1024: 728 ret = "Celeron (Covington)"; 729 break; 730 case 256 * 1024: 731 ret = "Mobile Pentium II (Dixon)"; 732 break; 733 case 512 * 1024: 734 ret = "Pentium II"; 735 break; 736 case 1 * 1024 * 1024: 737 case 2 * 1024 * 1024: 738 ret = "Pentium II Xeon"; 739 break; 740 } 741 } else if (ci->ci_model == 6) { 742 switch (l2cache) { 743 case 256 * 1024: 744 case 512 * 1024: 745 ret = "Mobile Pentium II"; 746 break; 747 } 748 } else if (ci->ci_model == 7) { 749 switch (l2cache) { 750 case 512 * 1024: 751 ret = "Pentium III"; 752 break; 753 case 1 * 1024 * 1024: 754 case 2 * 1024 * 1024: 755 ret = "Pentium III Xeon"; 756 break; 757 } 758 } else if (ci->ci_model >= 8) { 759 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 760 switch (ci->ci_brand_id) { 761 case 0x3: 762 if (ci->ci_signature == 0x6B1) 763 ret = "Celeron"; 764 break; 765 case 0x8: 766 if (ci->ci_signature >= 0xF13) 767 ret = "genuine processor"; 768 break; 769 case 0xB: 770 if (ci->ci_signature >= 0xF13) 771 ret = "Xeon MP"; 772 break; 773 case 0xE: 774 if (ci->ci_signature < 0xF13) 775 ret = "Xeon"; 776 break; 777 } 778 if (ret == NULL) 779 ret = i386_intel_brand[ci->ci_brand_id]; 780 } 781 } 782 783 return ret; 784 } 785 786 /* 787 * Identify AMD64 CPU names from cpuid. 788 * 789 * Based on: 790 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 791 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 792 * "Revision Guide for AMD NPT Family 0Fh Processors" 793 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 794 * and other miscellaneous reports. 795 * 796 * This is all rather pointless, these are cross 'brand' since the raw 797 * silicon is shared. 798 */ 799 static const char * 800 amd_amd64_name(struct cpu_info *ci) 801 { 802 static char family_str[32]; 803 804 /* Only called if family >= 15 */ 805 806 switch (ci->ci_family) { 807 case 15: 808 switch (ci->ci_model) { 809 case 0x21: /* rev JH-E1/E6 */ 810 case 0x41: /* rev JH-F2 */ 811 return "Dual-Core Opteron"; 812 case 0x23: /* rev JH-E6 (Toledo) */ 813 return "Dual-Core Opteron or Athlon 64 X2"; 814 case 0x43: /* rev JH-F2 (Windsor) */ 815 return "Athlon 64 FX or Athlon 64 X2"; 816 case 0x24: /* rev SH-E5 (Lancaster?) */ 817 return "Mobile Athlon 64 or Turion 64"; 818 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 819 return "Opteron or Athlon 64 FX"; 820 case 0x15: /* rev SH-D0 */ 821 case 0x25: /* rev SH-E4 */ 822 return "Opteron"; 823 case 0x27: /* rev DH-E4, SH-E4 */ 824 return "Athlon 64 or Athlon 64 FX or Opteron"; 825 case 0x48: /* rev BH-F2 */ 826 return "Turion 64 X2"; 827 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 828 case 0x07: /* rev SH-CG (ClawHammer) */ 829 case 0x0b: /* rev CH-CG */ 830 case 0x14: /* rev SH-D0 */ 831 case 0x17: /* rev SH-D0 */ 832 case 0x1b: /* rev CH-D0 */ 833 return "Athlon 64"; 834 case 0x2b: /* rev BH-E4 (Manchester) */ 835 case 0x4b: /* rev BH-F2 (Windsor) */ 836 return "Athlon 64 X2"; 837 case 0x6b: /* rev BH-G1 (Brisbane) */ 838 return "Athlon X2 or Athlon 64 X2"; 839 case 0x08: /* rev CH-CG */ 840 case 0x0c: /* rev DH-CG (Newcastle) */ 841 case 0x0e: /* rev DH-CG (Newcastle?) */ 842 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 843 case 0x18: /* rev CH-D0 */ 844 case 0x1c: /* rev DH-D0 (Winchester) */ 845 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 846 case 0x2c: /* rev DH-E3/E6 */ 847 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 848 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 849 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 850 case 0x6f: /* rev DH-G1 */ 851 return "Athlon 64 or Sempron"; 852 default: 853 break; 854 } 855 return "Unknown AMD64 CPU"; 856 857 #if 0 858 case 16: 859 return "Family 10h"; 860 case 17: 861 return "Family 11h"; 862 case 18: 863 return "Family 12h"; 864 case 19: 865 return "Family 14h"; 866 case 20: 867 return "Family 15h"; 868 #endif 869 870 default: 871 break; 872 } 873 874 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 875 return family_str; 876 } 877 878 static void 879 intel_family_new_probe(struct cpu_info *ci) 880 { 881 uint32_t descs[4]; 882 883 x86_cpuid(0x80000000, descs); 884 885 /* 886 * Determine extended feature flags. 887 */ 888 if (descs[0] >= 0x80000001) { 889 x86_cpuid(0x80000001, descs); 890 ci->ci_feat_val[2] |= descs[3]; 891 ci->ci_feat_val[3] |= descs[2]; 892 } 893 } 894 895 static void 896 via_cpu_probe(struct cpu_info *ci) 897 { 898 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 899 u_int descs[4]; 900 u_int lfunc; 901 902 /* 903 * Determine the largest extended function value. 904 */ 905 x86_cpuid(0x80000000, descs); 906 lfunc = descs[0]; 907 908 /* 909 * Determine the extended feature flags. 910 */ 911 if (lfunc >= 0x80000001) { 912 x86_cpuid(0x80000001, descs); 913 ci->ci_feat_val[2] |= descs[3]; 914 } 915 916 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 917 return; 918 919 /* Nehemiah or Esther */ 920 x86_cpuid(0xc0000000, descs); 921 lfunc = descs[0]; 922 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 923 return; 924 925 x86_cpuid(0xc0000001, descs); 926 lfunc = descs[3]; 927 ci->ci_feat_val[4] = lfunc; 928 } 929 930 static void 931 amd_family6_probe(struct cpu_info *ci) 932 { 933 uint32_t descs[4]; 934 char *p; 935 size_t i; 936 937 x86_cpuid(0x80000000, descs); 938 939 /* 940 * Determine the extended feature flags. 941 */ 942 if (descs[0] >= 0x80000001) { 943 x86_cpuid(0x80000001, descs); 944 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 945 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 946 } 947 948 if (*cpu_brand_string == '\0') 949 return; 950 951 for (i = 1; i < __arraycount(amd_brand); i++) 952 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 953 ci->ci_brand_id = i; 954 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 955 break; 956 } 957 } 958 959 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 960 AMD_L2CACHE_INFO; 961 962 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 963 AMD_L3CACHE_INFO; 964 965 static void 966 amd_cpu_cacheinfo(struct cpu_info *ci) 967 { 968 const struct x86_cache_info *cp; 969 struct x86_cache_info *cai; 970 u_int descs[4]; 971 u_int lfunc; 972 973 /* 974 * K5 model 0 has none of this info. 975 */ 976 if (ci->ci_family == 5 && ci->ci_model == 0) 977 return; 978 979 /* 980 * Determine the largest extended function value. 981 */ 982 x86_cpuid(0x80000000, descs); 983 lfunc = descs[0]; 984 985 /* 986 * Determine L1 cache/TLB info. 987 */ 988 if (lfunc < 0x80000005) { 989 /* No L1 cache info available. */ 990 return; 991 } 992 993 x86_cpuid(0x80000005, descs); 994 995 /* 996 * K6-III and higher have large page TLBs. 997 */ 998 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 999 cai = &ci->ci_cinfo[CAI_ITLB2]; 1000 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1001 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1002 cai->cai_linesize = largepagesize; 1003 1004 cai = &ci->ci_cinfo[CAI_DTLB2]; 1005 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1006 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1007 cai->cai_linesize = largepagesize; 1008 } 1009 1010 cai = &ci->ci_cinfo[CAI_ITLB]; 1011 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1012 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1013 cai->cai_linesize = (4 * 1024); 1014 1015 cai = &ci->ci_cinfo[CAI_DTLB]; 1016 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1017 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1018 cai->cai_linesize = (4 * 1024); 1019 1020 cai = &ci->ci_cinfo[CAI_DCACHE]; 1021 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1022 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1023 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1024 1025 cai = &ci->ci_cinfo[CAI_ICACHE]; 1026 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1027 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1028 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1029 1030 /* 1031 * Determine L2 cache/TLB info. 1032 */ 1033 if (lfunc < 0x80000006) { 1034 /* No L2 cache info available. */ 1035 return; 1036 } 1037 1038 x86_cpuid(0x80000006, descs); 1039 1040 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1041 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1042 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1043 cai->cai_linesize = (4 * 1024); 1044 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1045 cai->cai_associativity); 1046 if (cp != NULL) 1047 cai->cai_associativity = cp->cai_associativity; 1048 else 1049 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1050 1051 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1052 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1053 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1054 cai->cai_linesize = largepagesize; 1055 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1056 cai->cai_associativity); 1057 if (cp != NULL) 1058 cai->cai_associativity = cp->cai_associativity; 1059 else 1060 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1061 1062 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1063 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1064 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1065 cai->cai_linesize = (4 * 1024); 1066 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1067 cai->cai_associativity); 1068 if (cp != NULL) 1069 cai->cai_associativity = cp->cai_associativity; 1070 else 1071 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1072 1073 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1074 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1075 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1076 cai->cai_linesize = largepagesize; 1077 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1078 cai->cai_associativity); 1079 if (cp != NULL) 1080 cai->cai_associativity = cp->cai_associativity; 1081 else 1082 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1083 1084 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1085 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1086 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1087 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1088 1089 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1090 cai->cai_associativity); 1091 if (cp != NULL) 1092 cai->cai_associativity = cp->cai_associativity; 1093 else 1094 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1095 1096 /* 1097 * Determine L3 cache info on AMD Family 10h and newer processors 1098 */ 1099 if (ci->ci_family >= 0x10) { 1100 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1101 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1102 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1103 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1104 1105 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1106 cai->cai_associativity); 1107 if (cp != NULL) 1108 cai->cai_associativity = cp->cai_associativity; 1109 else 1110 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1111 } 1112 1113 /* 1114 * Determine 1GB TLB info. 1115 */ 1116 if (lfunc < 0x80000019) { 1117 /* No 1GB TLB info available. */ 1118 return; 1119 } 1120 1121 x86_cpuid(0x80000019, descs); 1122 1123 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1124 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1125 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1126 cai->cai_linesize = (1024 * 1024 * 1024); 1127 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1128 cai->cai_associativity); 1129 if (cp != NULL) 1130 cai->cai_associativity = cp->cai_associativity; 1131 else 1132 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1133 1134 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1135 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1136 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1137 cai->cai_linesize = (1024 * 1024 * 1024); 1138 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1139 cai->cai_associativity); 1140 if (cp != NULL) 1141 cai->cai_associativity = cp->cai_associativity; 1142 else 1143 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1144 1145 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1146 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1147 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1148 cai->cai_linesize = (1024 * 1024 * 1024); 1149 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1150 cai->cai_associativity); 1151 if (cp != NULL) 1152 cai->cai_associativity = cp->cai_associativity; 1153 else 1154 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1155 1156 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1157 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1158 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1159 cai->cai_linesize = (1024 * 1024 * 1024); 1160 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1161 cai->cai_associativity); 1162 if (cp != NULL) 1163 cai->cai_associativity = cp->cai_associativity; 1164 else 1165 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1166 } 1167 1168 static void 1169 via_cpu_cacheinfo(struct cpu_info *ci) 1170 { 1171 struct x86_cache_info *cai; 1172 int stepping; 1173 u_int descs[4]; 1174 u_int lfunc; 1175 1176 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1177 1178 /* 1179 * Determine the largest extended function value. 1180 */ 1181 x86_cpuid(0x80000000, descs); 1182 lfunc = descs[0]; 1183 1184 /* 1185 * Determine L1 cache/TLB info. 1186 */ 1187 if (lfunc < 0x80000005) { 1188 /* No L1 cache info available. */ 1189 return; 1190 } 1191 1192 x86_cpuid(0x80000005, descs); 1193 1194 cai = &ci->ci_cinfo[CAI_ITLB]; 1195 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1196 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1197 cai->cai_linesize = (4 * 1024); 1198 1199 cai = &ci->ci_cinfo[CAI_DTLB]; 1200 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1201 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1202 cai->cai_linesize = (4 * 1024); 1203 1204 cai = &ci->ci_cinfo[CAI_DCACHE]; 1205 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1206 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1207 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1208 if (ci->ci_model == 9 && stepping == 8) { 1209 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1210 cai->cai_associativity = 2; 1211 } 1212 1213 cai = &ci->ci_cinfo[CAI_ICACHE]; 1214 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1215 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1216 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1217 if (ci->ci_model == 9 && stepping == 8) { 1218 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1219 cai->cai_associativity = 2; 1220 } 1221 1222 /* 1223 * Determine L2 cache/TLB info. 1224 */ 1225 if (lfunc < 0x80000006) { 1226 /* No L2 cache info available. */ 1227 return; 1228 } 1229 1230 x86_cpuid(0x80000006, descs); 1231 1232 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1233 if (ci->ci_model >= 9) { 1234 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1235 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1236 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1237 } else { 1238 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1239 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1240 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1241 } 1242 } 1243 1244 static void 1245 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1246 { 1247 u_int descs[4]; 1248 1249 x86_cpuid(0x80860007, descs); 1250 *frequency = descs[0]; 1251 *voltage = descs[1]; 1252 *percentage = descs[2]; 1253 } 1254 1255 static void 1256 transmeta_cpu_info(struct cpu_info *ci) 1257 { 1258 u_int descs[4], nreg; 1259 u_int frequency, voltage, percentage; 1260 1261 x86_cpuid(0x80860000, descs); 1262 nreg = descs[0]; 1263 if (nreg >= 0x80860001) { 1264 x86_cpuid(0x80860001, descs); 1265 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1266 (descs[1] >> 24) & 0xff, 1267 (descs[1] >> 16) & 0xff, 1268 (descs[1] >> 8) & 0xff, 1269 descs[1] & 0xff); 1270 } 1271 if (nreg >= 0x80860002) { 1272 x86_cpuid(0x80860002, descs); 1273 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1274 (descs[1] >> 24) & 0xff, 1275 (descs[1] >> 16) & 0xff, 1276 (descs[1] >> 8) & 0xff, 1277 descs[1] & 0xff, 1278 descs[2]); 1279 } 1280 if (nreg >= 0x80860006) { 1281 union { 1282 char text[65]; 1283 u_int descs[4][4]; 1284 } info; 1285 int i; 1286 1287 for (i=0; i<4; i++) { 1288 x86_cpuid(0x80860003 + i, info.descs[i]); 1289 } 1290 info.text[64] = '\0'; 1291 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1292 } 1293 1294 if (nreg >= 0x80860007) { 1295 tmx86_get_longrun_status(&frequency, 1296 &voltage, &percentage); 1297 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1298 frequency, voltage, percentage); 1299 } 1300 } 1301 1302 static void 1303 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1304 { 1305 const struct x86_cache_info *cai; 1306 u_int descs[4]; 1307 int iterations, i, j; 1308 int type, level; 1309 int ways, partitions, linesize, sets; 1310 int caitype = -1; 1311 int totalsize; 1312 uint8_t desc; 1313 uint32_t brand[12]; 1314 1315 memset(ci, 0, sizeof(*ci)); 1316 ci->ci_dev = cpuname; 1317 1318 ci->ci_cpu_type = x86_identify(); 1319 if (ci->ci_cpu_type >= 0) { 1320 /* Old pre-cpuid instruction cpu */ 1321 ci->ci_cpuid_level = -1; 1322 return; 1323 } 1324 1325 /* 1326 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1327 * function. 1328 */ 1329 1330 /* 1331 * Fn0000_0000: 1332 * - Save cpuid max level. 1333 * - Save vendor string. 1334 */ 1335 x86_cpuid(0, descs); 1336 ci->ci_cpuid_level = descs[0]; 1337 /* Save vendor string */ 1338 ci->ci_vendor[0] = descs[1]; 1339 ci->ci_vendor[2] = descs[2]; 1340 ci->ci_vendor[1] = descs[3]; 1341 ci->ci_vendor[3] = 0; 1342 1343 /* 1344 * Fn8000_000[2-4]: 1345 * - Save brand string. 1346 */ 1347 x86_cpuid(0x80000000, brand); 1348 if (brand[0] >= 0x80000004) { 1349 x86_cpuid(0x80000002, brand); 1350 x86_cpuid(0x80000003, brand + 4); 1351 x86_cpuid(0x80000004, brand + 8); 1352 for (i = 0; i < 48; i++) 1353 if (((char *) brand)[i] != ' ') 1354 break; 1355 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1356 } 1357 1358 if (ci->ci_cpuid_level < 1) 1359 return; 1360 1361 /* 1362 * Fn0000_0001: 1363 * - Get CPU family, model and stepping (from eax). 1364 * - Initial local APIC ID and brand ID (from ebx) 1365 */ 1366 x86_cpuid(1, descs); 1367 ci->ci_signature = descs[0]; 1368 1369 /* Extract full family/model values */ 1370 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1371 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1372 1373 /* Brand is low order 8 bits of ebx */ 1374 ci->ci_brand_id = descs[1] & 0xff; 1375 /* Initial local APIC ID */ 1376 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1377 1378 ci->ci_feat_val[1] = descs[2]; 1379 ci->ci_feat_val[0] = descs[3]; 1380 1381 if (ci->ci_cpuid_level < 2) 1382 return; 1383 1384 /* 1385 * Parse the cache info from `cpuid leaf 2', if we have it. 1386 * XXX This is kinda ugly, but hey, so is the architecture... 1387 */ 1388 1389 x86_cpuid(2, descs); 1390 1391 iterations = descs[0] & 0xff; 1392 while (iterations-- > 0) { 1393 for (i = 0; i < 4; i++) { 1394 if (descs[i] & 0x80000000) 1395 continue; 1396 for (j = 0; j < 4; j++) { 1397 if (i == 0 && j == 0) 1398 continue; 1399 desc = (descs[i] >> (j * 8)) & 0xff; 1400 if (desc == 0) 1401 continue; 1402 cai = cache_info_lookup(intel_cpuid_cache_info, 1403 desc); 1404 if (cai != NULL) 1405 ci->ci_cinfo[cai->cai_index] = *cai; 1406 } 1407 } 1408 x86_cpuid(2, descs); 1409 } 1410 1411 if (ci->ci_cpuid_level < 3) 1412 return; 1413 1414 /* 1415 * If the processor serial number misfeature is present and supported, 1416 * extract it here. 1417 */ 1418 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1419 ci->ci_cpu_serial[0] = ci->ci_signature; 1420 x86_cpuid(3, descs); 1421 ci->ci_cpu_serial[2] = descs[2]; 1422 ci->ci_cpu_serial[1] = descs[3]; 1423 } 1424 1425 if (ci->ci_cpuid_level < 4) 1426 return; 1427 1428 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1429 for (i = 0; ; i++) { 1430 x86_cpuid2(4, i, descs); 1431 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1432 if (type == CPUID_DCP_CACHETYPE_N) 1433 break; 1434 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1435 switch (level) { 1436 case 1: 1437 if (type == CPUID_DCP_CACHETYPE_I) 1438 caitype = CAI_ICACHE; 1439 else if (type == CPUID_DCP_CACHETYPE_D) 1440 caitype = CAI_DCACHE; 1441 else 1442 caitype = -1; 1443 break; 1444 case 2: 1445 if (type == CPUID_DCP_CACHETYPE_U) 1446 caitype = CAI_L2CACHE; 1447 else 1448 caitype = -1; 1449 break; 1450 case 3: 1451 if (type == CPUID_DCP_CACHETYPE_U) 1452 caitype = CAI_L3CACHE; 1453 else 1454 caitype = -1; 1455 break; 1456 default: 1457 caitype = -1; 1458 break; 1459 } 1460 if (caitype == -1) { 1461 printf("unknown cache level&type (%d & %d)\n", 1462 level, type); 1463 continue; 1464 } 1465 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1466 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1467 + 1; 1468 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1469 + 1; 1470 sets = descs[2] + 1; 1471 totalsize = ways * partitions * linesize * sets; 1472 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1473 ci->ci_cinfo[caitype].cai_associativity = ways; 1474 ci->ci_cinfo[caitype].cai_linesize = linesize; 1475 } 1476 1477 if (ci->ci_cpuid_level < 0xd) 1478 return; 1479 1480 /* Get support XCR0 bits */ 1481 x86_cpuid2(0xd, 0, descs); 1482 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1483 ci->ci_cur_xsave = descs[1]; 1484 ci->ci_max_xsave = descs[2]; 1485 1486 /* Additional flags (eg xsaveopt support) */ 1487 x86_cpuid2(0xd, 1, descs); 1488 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1489 } 1490 1491 static void 1492 cpu_probe_features(struct cpu_info *ci) 1493 { 1494 const struct cpu_cpuid_nameclass *cpup = NULL; 1495 unsigned int i; 1496 1497 if (ci->ci_cpuid_level < 1) 1498 return; 1499 1500 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1501 if (!strncmp((char *)ci->ci_vendor, 1502 i386_cpuid_cpus[i].cpu_id, 12)) { 1503 cpup = &i386_cpuid_cpus[i]; 1504 break; 1505 } 1506 } 1507 1508 if (cpup == NULL) 1509 return; 1510 1511 i = ci->ci_family - CPU_MINFAMILY; 1512 1513 if (i >= __arraycount(cpup->cpu_family)) 1514 i = __arraycount(cpup->cpu_family) - 1; 1515 1516 if (cpup->cpu_family[i].cpu_probe == NULL) 1517 return; 1518 1519 (*cpup->cpu_family[i].cpu_probe)(ci); 1520 } 1521 1522 static void 1523 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1524 { 1525 char buf[32 * 16]; 1526 char *bp; 1527 1528 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1529 1530 if (val == 0 || fmt == NULL) 1531 return; 1532 1533 snprintb_m(buf, sizeof(buf), fmt, val, 1534 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1535 bp = buf; 1536 while (*bp != '\0') { 1537 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1538 bp += strlen(bp) + 1; 1539 } 1540 } 1541 1542 static void 1543 identifycpu_cpuids(struct cpu_info *ci) 1544 { 1545 const char *cpuname = ci->ci_dev; 1546 u_int lp_max = 1; /* logical processors per package */ 1547 u_int smt_max; /* smt per core */ 1548 u_int core_max = 1; /* core per package */ 1549 u_int smt_bits, core_bits; 1550 uint32_t descs[4]; 1551 uint32_t highest_basic_info; 1552 1553 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1554 ci->ci_packageid = ci->ci_initapicid; 1555 ci->ci_coreid = 0; 1556 ci->ci_smtid = 0; 1557 if (cpu_vendor != CPUVENDOR_INTEL) { 1558 return; 1559 } 1560 1561 /* 1562 * 253668.pdf 7.10.2 1563 */ 1564 1565 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1566 x86_cpuid(1, descs); 1567 lp_max = (descs[1] >> 16) & 0xff; 1568 } 1569 x86_cpuid(0, descs); 1570 highest_basic_info = descs[0]; 1571 if (highest_basic_info >= 4) { 1572 x86_cpuid2(4, 0, descs); 1573 core_max = (descs[0] >> 26) + 1; 1574 } 1575 assert(lp_max >= core_max); 1576 smt_max = lp_max / core_max; 1577 smt_bits = ilog2(smt_max - 1) + 1; 1578 core_bits = ilog2(core_max - 1) + 1; 1579 if (smt_bits + core_bits) { 1580 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1581 } 1582 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1583 ci->ci_packageid); 1584 if (core_bits) { 1585 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1586 1587 ci->ci_coreid = 1588 __SHIFTOUT(ci->ci_initapicid, core_mask); 1589 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1590 } 1591 if (smt_bits) { 1592 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1593 1594 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1595 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1596 } 1597 } 1598 1599 void 1600 identifycpu(int fd, const char *cpuname) 1601 { 1602 const char *name = "", *modifier, *vendorname, *brand = ""; 1603 int class = CPUCLASS_386; 1604 unsigned int i; 1605 int modif, family; 1606 const struct cpu_cpuid_nameclass *cpup = NULL; 1607 const struct cpu_cpuid_family *cpufam; 1608 struct cpu_info *ci, cistore; 1609 size_t sz; 1610 struct cpu_ucode_version ucode; 1611 union { 1612 struct cpu_ucode_version_amd amd; 1613 struct cpu_ucode_version_intel1 intel1; 1614 } ucvers; 1615 1616 ci = &cistore; 1617 cpu_probe_base_features(ci, cpuname); 1618 cpu_probe_features(ci); 1619 1620 if (ci->ci_cpu_type >= 0) { 1621 /* Old pre-cpuid instruction cpu */ 1622 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1623 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1624 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1625 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1626 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1627 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1628 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1629 modifier = ""; 1630 } else { 1631 /* CPU which support cpuid instruction */ 1632 modif = (ci->ci_signature >> 12) & 0x3; 1633 family = ci->ci_family; 1634 if (family < CPU_MINFAMILY) 1635 errx(1, "identifycpu: strange family value"); 1636 if (family > CPU_MAXFAMILY) 1637 family = CPU_MAXFAMILY; 1638 1639 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1640 if (!strncmp((char *)ci->ci_vendor, 1641 i386_cpuid_cpus[i].cpu_id, 12)) { 1642 cpup = &i386_cpuid_cpus[i]; 1643 break; 1644 } 1645 } 1646 1647 if (cpup == NULL) { 1648 cpu_vendor = CPUVENDOR_UNKNOWN; 1649 if (ci->ci_vendor[0] != '\0') 1650 vendorname = (char *)&ci->ci_vendor[0]; 1651 else 1652 vendorname = "Unknown"; 1653 class = family - 3; 1654 modifier = ""; 1655 name = ""; 1656 ci->ci_info = NULL; 1657 } else { 1658 cpu_vendor = cpup->cpu_vendor; 1659 vendorname = cpup->cpu_vendorname; 1660 modifier = modifiers[modif]; 1661 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1662 name = cpufam->cpu_models[ci->ci_model]; 1663 if (name == NULL || *name == '\0') 1664 name = cpufam->cpu_model_default; 1665 class = cpufam->cpu_class; 1666 ci->ci_info = cpufam->cpu_info; 1667 1668 if (cpu_vendor == CPUVENDOR_INTEL) { 1669 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1670 const char *tmp; 1671 tmp = intel_family6_name(ci); 1672 if (tmp != NULL) 1673 name = tmp; 1674 } 1675 if (ci->ci_family == 15 && 1676 ci->ci_brand_id < 1677 __arraycount(i386_intel_brand) && 1678 i386_intel_brand[ci->ci_brand_id]) 1679 name = 1680 i386_intel_brand[ci->ci_brand_id]; 1681 } 1682 1683 if (cpu_vendor == CPUVENDOR_AMD) { 1684 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1685 if (ci->ci_brand_id == 1) 1686 /* 1687 * It's Duron. We override the 1688 * name, since it might have 1689 * been misidentified as Athlon. 1690 */ 1691 name = 1692 amd_brand[ci->ci_brand_id]; 1693 else 1694 brand = amd_brand_name; 1695 } 1696 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1697 == 0xf) { 1698 /* Identify AMD64 CPU names. */ 1699 const char *tmp; 1700 tmp = amd_amd64_name(ci); 1701 if (tmp != NULL) 1702 name = tmp; 1703 } 1704 } 1705 1706 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1707 vendorname = "VIA"; 1708 } 1709 } 1710 1711 ci->ci_cpu_class = class; 1712 1713 sz = sizeof(ci->ci_tsc_freq); 1714 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1715 sz = sizeof(use_pae); 1716 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1717 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1718 1719 /* 1720 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1721 * we try to determine from the family/model values. 1722 */ 1723 if (*cpu_brand_string != '\0') 1724 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1725 1726 aprint_normal("%s: %s", cpuname, vendorname); 1727 if (*modifier) 1728 aprint_normal(" %s", modifier); 1729 if (*name) 1730 aprint_normal(" %s", name); 1731 if (*brand) 1732 aprint_normal(" %s", brand); 1733 aprint_normal(" (%s-class)", classnames[class]); 1734 1735 if (ci->ci_tsc_freq != 0) 1736 aprint_normal(", %ju.%02ju MHz\n", 1737 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1738 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1739 1740 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1741 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1742 if (ci->ci_signature != 0) 1743 aprint_normal(" (id %#x)", ci->ci_signature); 1744 aprint_normal("\n"); 1745 1746 if (ci->ci_info) 1747 (*ci->ci_info)(ci); 1748 1749 /* 1750 * display CPU feature flags 1751 */ 1752 1753 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1754 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1755 1756 /* These next two are actually common definitions! */ 1757 print_bits(cpuname, "features2", 1758 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1759 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1760 print_bits(cpuname, "features3", 1761 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1762 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1763 1764 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1765 ci->ci_feat_val[4]); 1766 1767 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1768 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1769 ci->ci_feat_val[6]); 1770 1771 if (ci->ci_max_xsave != 0) { 1772 aprint_normal("%s: xsave area size: current %d, maximum %d", 1773 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1774 aprint_normal(", xgetbv %sabled\n", 1775 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1776 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1777 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1778 x86_xgetbv()); 1779 } 1780 1781 x86_print_cacheinfo(ci); 1782 1783 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1784 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1785 cpuname, 1786 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1787 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1788 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1789 } 1790 1791 if (ci->ci_cpu_class == CPUCLASS_386) { 1792 errx(1, "NetBSD requires an 80486 or later processor"); 1793 } 1794 1795 if (ci->ci_cpu_type == CPU_486DLC) { 1796 #ifndef CYRIX_CACHE_WORKS 1797 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1798 #else 1799 #ifndef CYRIX_CACHE_REALLY_WORKS 1800 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1801 #else 1802 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1803 #endif 1804 #endif 1805 } 1806 1807 /* 1808 * Everything past this point requires a Pentium or later. 1809 */ 1810 if (ci->ci_cpuid_level < 0) 1811 return; 1812 1813 identifycpu_cpuids(ci); 1814 1815 #ifdef INTEL_CORETEMP 1816 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1817 coretemp_register(ci); 1818 #endif 1819 1820 if (cpu_vendor == CPUVENDOR_AMD) { 1821 uint32_t data[4]; 1822 1823 x86_cpuid(0x80000000, data); 1824 if (data[0] >= 0x80000007) 1825 powernow_probe(ci); 1826 1827 if ((data[0] >= 0x8000000a) 1828 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1829 x86_cpuid(0x8000000a, data); 1830 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1831 data[0] & 0xf); 1832 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1833 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1834 data[3]); 1835 } 1836 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1837 uint32_t data[4]; 1838 uint32_t highest_basic_info; 1839 uint32_t bi_index; 1840 1841 x86_cpuid(0x00000000, data); 1842 highest_basic_info = data[0]; 1843 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1844 highest_basic_info); 1845 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1846 x86_cpuid(bi_index, data); 1847 switch (bi_index) { 1848 case 6: 1849 print_bits(cpuname, "DSPM-eax", 1850 CPUID_DSPM_FLAGS, data[0]); 1851 print_bits(cpuname, "DSPM-ecx", 1852 CPUID_DSPM_FLAGS1, data[2]); 1853 break; 1854 case 7: 1855 aprint_verbose("%s: SEF highest subleaf %08x\n", 1856 cpuname, data[0]); 1857 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1858 data[1]); 1859 break; 1860 #if 0 1861 default: 1862 aprint_verbose("%s: basic %08x-eax %08x\n", 1863 cpuname, bi_index, data[0]); 1864 aprint_verbose("%s: basic %08x-ebx %08x\n", 1865 cpuname, bi_index, data[1]); 1866 aprint_verbose("%s: basic %08x-ecx %08x\n", 1867 cpuname, bi_index, data[2]); 1868 aprint_verbose("%s: basic %08x-edx %08x\n", 1869 cpuname, bi_index, data[3]); 1870 break; 1871 #endif 1872 } 1873 } 1874 } 1875 1876 #ifdef INTEL_ONDEMAND_CLOCKMOD 1877 clockmod_init(); 1878 #endif 1879 1880 if (cpu_vendor == CPUVENDOR_AMD) 1881 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1882 else if (cpu_vendor == CPUVENDOR_INTEL) 1883 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1884 else 1885 return; 1886 1887 ucode.data = &ucvers; 1888 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1889 #ifdef __i386__ 1890 struct cpu_ucode_version_64 ucode_64; 1891 if (errno != ENOTTY) 1892 return; 1893 /* Try the 64 bit ioctl */ 1894 memset(&ucode_64, 0, sizeof ucode_64); 1895 ucode_64.data = &ucvers; 1896 ucode_64.loader_version = ucode.loader_version; 1897 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1898 return; 1899 #endif 1900 } 1901 1902 if (cpu_vendor == CPUVENDOR_AMD) 1903 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1904 else if (cpu_vendor == CPUVENDOR_INTEL) 1905 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1906 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1907 } 1908 1909 static const char * 1910 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1911 const char *sep) 1912 { 1913 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1914 char human_num[HUMAN_BUFSIZE]; 1915 1916 if (cai->cai_totalsize == 0) 1917 return sep; 1918 1919 if (sep == NULL) 1920 aprint_verbose_dev(ci->ci_dev, ""); 1921 else 1922 aprint_verbose("%s", sep); 1923 if (name != NULL) 1924 aprint_verbose("%s ", name); 1925 1926 if (cai->cai_string != NULL) { 1927 aprint_verbose("%s ", cai->cai_string); 1928 } else { 1929 (void)humanize_number(human_num, sizeof(human_num), 1930 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1931 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1932 } 1933 switch (cai->cai_associativity) { 1934 case 0: 1935 aprint_verbose("disabled"); 1936 break; 1937 case 1: 1938 aprint_verbose("direct-mapped"); 1939 break; 1940 case 0xff: 1941 aprint_verbose("fully associative"); 1942 break; 1943 default: 1944 aprint_verbose("%d-way", cai->cai_associativity); 1945 break; 1946 } 1947 return ", "; 1948 } 1949 1950 static const char * 1951 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1952 const char *sep) 1953 { 1954 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1955 char human_num[HUMAN_BUFSIZE]; 1956 1957 if (cai->cai_totalsize == 0) 1958 return sep; 1959 1960 if (sep == NULL) 1961 aprint_verbose_dev(ci->ci_dev, ""); 1962 else 1963 aprint_verbose("%s", sep); 1964 if (name != NULL) 1965 aprint_verbose("%s ", name); 1966 1967 if (cai->cai_string != NULL) { 1968 aprint_verbose("%s", cai->cai_string); 1969 } else { 1970 (void)humanize_number(human_num, sizeof(human_num), 1971 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1972 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1973 human_num); 1974 switch (cai->cai_associativity) { 1975 case 0: 1976 aprint_verbose("disabled"); 1977 break; 1978 case 1: 1979 aprint_verbose("direct-mapped"); 1980 break; 1981 case 0xff: 1982 aprint_verbose("fully associative"); 1983 break; 1984 default: 1985 aprint_verbose("%d-way", cai->cai_associativity); 1986 break; 1987 } 1988 } 1989 return ", "; 1990 } 1991 1992 static const struct x86_cache_info * 1993 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1994 { 1995 int i; 1996 1997 for (i = 0; cai[i].cai_desc != 0; i++) { 1998 if (cai[i].cai_desc == desc) 1999 return (&cai[i]); 2000 } 2001 2002 return (NULL); 2003 } 2004 2005 static void 2006 x86_print_cacheinfo(struct cpu_info *ci) 2007 { 2008 const char *sep = NULL; 2009 2010 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2011 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2012 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2013 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2014 if (sep != NULL) 2015 aprint_verbose("\n"); 2016 } 2017 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2018 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2019 if (sep != NULL) 2020 aprint_verbose("\n"); 2021 } 2022 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2023 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2024 if (sep != NULL) 2025 aprint_verbose("\n"); 2026 } 2027 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2028 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2029 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2030 if (sep != NULL) 2031 aprint_verbose("\n"); 2032 } 2033 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2034 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2035 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2036 if (sep != NULL) 2037 aprint_verbose("\n"); 2038 } 2039 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2040 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2041 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2042 if (sep != NULL) 2043 aprint_verbose("\n"); 2044 } 2045 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2046 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2047 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2048 if (sep != NULL) 2049 aprint_verbose("\n"); 2050 } 2051 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2052 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2053 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2054 if (sep != NULL) 2055 aprint_verbose("\n"); 2056 } 2057 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2058 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2059 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2060 if (sep != NULL) 2061 aprint_verbose("\n"); 2062 } 2063 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2064 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2065 NULL); 2066 if (sep != NULL) 2067 aprint_verbose("\n"); 2068 } 2069 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2070 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2071 NULL); 2072 if (sep != NULL) 2073 aprint_verbose("\n"); 2074 } 2075 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2076 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2077 NULL); 2078 if (sep != NULL) 2079 aprint_verbose("\n"); 2080 } 2081 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2082 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2083 NULL); 2084 if (sep != NULL) 2085 aprint_verbose("\n"); 2086 } 2087 } 2088 2089 static void 2090 powernow_probe(struct cpu_info *ci) 2091 { 2092 uint32_t regs[4]; 2093 char buf[256]; 2094 2095 x86_cpuid(0x80000007, regs); 2096 2097 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2098 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2099 buf); 2100 } 2101 2102 int 2103 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2104 { 2105 struct cpu_info ci; 2106 int loader_version, res; 2107 struct cpu_ucode_version versreq; 2108 2109 cpu_probe_base_features(&ci, "unknown"); 2110 2111 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2112 loader_version = CPU_UCODE_LOADER_AMD; 2113 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2114 loader_version = CPU_UCODE_LOADER_INTEL1; 2115 else 2116 return -1; 2117 2118 /* check whether the kernel understands this loader version */ 2119 versreq.loader_version = loader_version; 2120 versreq.data = 0; 2121 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2122 if (res) 2123 return -1; 2124 2125 switch (loader_version) { 2126 case CPU_UCODE_LOADER_AMD: 2127 if (uc->cpu_nr != -1) { 2128 /* printf? */ 2129 return -1; 2130 } 2131 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2132 break; 2133 case CPU_UCODE_LOADER_INTEL1: 2134 if (uc->cpu_nr == -1) 2135 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2136 else 2137 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2138 break; 2139 default: /* can't happen */ 2140 return -1; 2141 } 2142 uc->loader_version = loader_version; 2143 return 0; 2144 } 2145
Indexes created Thu Sep 25 16:09:42 GMT 2025