i386.c revision 1.58.2.3
1 /* $NetBSD: i386.c,v 1.58.2.3 2015/04/19 16:42:19 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.58.2.3 2015/04/19 16:42:19 riz Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] XCR0 bits (d:0 %eax) 108 * [6] xsave flags (d:1 %eax) 109 */ 110 uint32_t ci_cpu_class; /* CPU class */ 111 uint32_t ci_brand_id; /* Intel brand id */ 112 uint32_t ci_vendor[4]; /* vendor string */ 113 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 114 uint64_t ci_tsc_freq; /* cpu cycles/second */ 115 uint8_t ci_packageid; 116 uint8_t ci_coreid; 117 uint8_t ci_smtid; 118 uint32_t ci_initapicid; 119 120 uint32_t ci_cur_xsave; 121 uint32_t ci_max_xsave; 122 123 struct x86_cache_info ci_cinfo[CAI_COUNT]; 124 void (*ci_info)(struct cpu_info *); 125 }; 126 127 struct cpu_nocpuid_nameclass { 128 int cpu_vendor; 129 const char *cpu_vendorname; 130 const char *cpu_name; 131 int cpu_class; 132 void (*cpu_setup)(struct cpu_info *); 133 void (*cpu_cacheinfo)(struct cpu_info *); 134 void (*cpu_info)(struct cpu_info *); 135 }; 136 137 struct cpu_cpuid_nameclass { 138 const char *cpu_id; 139 int cpu_vendor; 140 const char *cpu_vendorname; 141 struct cpu_cpuid_family { 142 int cpu_class; 143 const char *cpu_models[256]; 144 const char *cpu_model_default; 145 void (*cpu_setup)(struct cpu_info *); 146 void (*cpu_probe)(struct cpu_info *); 147 void (*cpu_info)(struct cpu_info *); 148 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 149 }; 150 151 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 152 153 /* 154 * Map Brand ID from cpuid instruction to brand name. 155 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 156 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 157 * Architectures Software Developer's Manual, Volume 2A". 158 */ 159 static const char * const i386_intel_brand[] = { 160 "", /* Unsupported */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Pentium III", /* Intel (R) Pentium (R) III processor */ 163 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "", /* 0x05: Reserved */ 166 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 167 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 170 "Celeron", /* Intel (R) Celeron (TM) processor */ 171 "Xeon", /* Intel (R) Xeon (TM) processor */ 172 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 173 "", /* 0x0d: Reserved */ 174 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 175 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 176 "", /* 0x10: Reserved */ 177 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 178 "Celeron M", /* Intel (R) Celeron (R) M processor */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "Celeron", /* Intel (R) Celeron (R) processor */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Pentium M", /* Intel (R) Pentium (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 }; 185 186 /* 187 * AMD processors don't have Brand IDs, so we need these names for probe. 188 */ 189 static const char * const amd_brand[] = { 190 "", 191 "Duron", /* AMD Duron(tm) */ 192 "MP", /* AMD Athlon(tm) MP */ 193 "XP", /* AMD Athlon(tm) XP */ 194 "4" /* AMD Athlon(tm) 4 */ 195 }; 196 197 static int cpu_vendor; 198 static char cpu_brand_string[49]; 199 static char amd_brand_name[48]; 200 static int use_pae, largepagesize; 201 202 /* Setup functions */ 203 static void disable_tsc(struct cpu_info *); 204 static void amd_family5_setup(struct cpu_info *); 205 static void cyrix6x86_cpu_setup(struct cpu_info *); 206 static void winchip_cpu_setup(struct cpu_info *); 207 /* Brand/Model name functions */ 208 static const char *intel_family6_name(struct cpu_info *); 209 static const char *amd_amd64_name(struct cpu_info *); 210 /* Probe functions */ 211 static void amd_family6_probe(struct cpu_info *); 212 static void powernow_probe(struct cpu_info *); 213 static void intel_family_new_probe(struct cpu_info *); 214 static void via_cpu_probe(struct cpu_info *); 215 /* (Cache) Info functions */ 216 static void intel_cpu_cacheinfo(struct cpu_info *); 217 static void amd_cpu_cacheinfo(struct cpu_info *); 218 static void via_cpu_cacheinfo(struct cpu_info *); 219 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 220 static void transmeta_cpu_info(struct cpu_info *); 221 /* Common functions */ 222 static void cpu_probe_base_features(struct cpu_info *, const char *); 223 static void cpu_probe_hv_features(struct cpu_info *, const char *); 224 static void cpu_probe_features(struct cpu_info *); 225 static void print_bits(const char *, const char *, const char *, uint32_t); 226 static void identifycpu_cpuids(struct cpu_info *); 227 static const struct x86_cache_info *cache_info_lookup( 228 const struct x86_cache_info *, uint8_t); 229 static const char *print_cache_config(struct cpu_info *, int, const char *, 230 const char *); 231 static const char *print_tlb_config(struct cpu_info *, int, const char *, 232 const char *); 233 static void x86_print_cache_and_tlb_info(struct cpu_info *); 234 235 /* 236 * Note: these are just the ones that may not have a cpuid instruction. 237 * We deal with the rest in a different way. 238 */ 239 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 240 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 241 NULL, NULL, NULL }, /* CPU_386SX */ 242 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386 */ 244 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 245 NULL, NULL, NULL }, /* CPU_486SX */ 246 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486 */ 248 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486DLC */ 250 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_6x86 */ 252 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 253 NULL, NULL, NULL }, /* CPU_NX586 */ 254 }; 255 256 const char *classnames[] = { 257 "386", 258 "486", 259 "586", 260 "686" 261 }; 262 263 const char *modifiers[] = { 264 "", 265 "OverDrive", 266 "Dual", 267 "" 268 }; 269 270 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 271 { 272 /* 273 * For Intel processors, check Chapter 35Model-specific 274 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 275 * Software Developer's Manual, Volume 3C". 276 */ 277 "GenuineIntel", 278 CPUVENDOR_INTEL, 279 "Intel", 280 /* Family 4 */ 281 { { 282 CPUCLASS_486, 283 { 284 "486DX", "486DX", "486SX", "486DX2", "486SL", 285 "486SX2", 0, "486DX2 W/B Enhanced", 286 "486DX4", 0, 0, 0, 0, 0, 0, 0, 287 }, 288 "486", /* Default */ 289 NULL, 290 NULL, 291 intel_cpu_cacheinfo, 292 }, 293 /* Family 5 */ 294 { 295 CPUCLASS_586, 296 { 297 "Pentium (P5 A-step)", "Pentium (P5)", 298 "Pentium (P54C)", "Pentium (P24T)", 299 "Pentium/MMX", "Pentium", 0, 300 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 301 0, 0, 0, 0, 0, 0, 0, 302 }, 303 "Pentium", /* Default */ 304 NULL, 305 NULL, 306 intel_cpu_cacheinfo, 307 }, 308 /* Family 6 */ 309 { 310 CPUCLASS_686, 311 { 312 [0x00] = "Pentium Pro (A-step)", 313 [0x01] = "Pentium Pro", 314 [0x03] = "Pentium II (Klamath)", 315 [0x04] = "Pentium Pro", 316 [0x05] = "Pentium II/Celeron (Deschutes)", 317 [0x06] = "Celeron (Mendocino)", 318 [0x07] = "Pentium III (Katmai)", 319 [0x08] = "Pentium III (Coppermine)", 320 [0x09] = "Pentium M (Banias)", 321 [0x0a] = "Pentium III Xeon (Cascades)", 322 [0x0b] = "Pentium III (Tualatin)", 323 [0x0d] = "Pentium M (Dothan)", 324 [0x0e] = "Pentium Core Duo, Core solo", 325 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 326 "Core 2 Quad 6xxx, " 327 "Core 2 Extreme 6xxx, " 328 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 329 "and Pentium DC", 330 [0x15] = "EP80579 Integrated Processor", 331 [0x16] = "Celeron (45nm)", 332 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 333 "Core 2 Quad 8xxx and 9xxx", 334 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 335 "(Nehalem)", 336 [0x1c] = "Atom Family", 337 [0x1d] = "XeonMP 74xx (Nehalem)", 338 [0x1e] = "Core i7 and i5", 339 [0x1f] = "Core i7 and i5", 340 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 341 [0x26] = "Atom Family", 342 [0x27] = "Atom Family", 343 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 344 "i3 2xxx", 345 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 346 [0x2d] = "Xeon E5 Sandy Bridge family, " 347 "Core i7-39xx Extreme", 348 [0x2e] = "Xeon 75xx & 65xx", 349 [0x2f] = "Xeon E7 family", 350 [0x35] = "Atom Family", 351 [0x36] = "Atom S1000", 352 [0x37] = "Atom E3000, Z3[67]00", 353 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 354 "Ivy Bridge", 355 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 356 "(Haswell)", 357 [0x3d] = "Core M-5xxx, Future 5th gen Core (Broadwell)", 358 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 359 "Core i7-49xx Extreme", 360 [0x3f] = "Xeon E5-2600/1600 v3 (Haswell-E), " 361 "Core i7-59xx Extreme", 362 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 363 "(Haswell)", 364 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x4a] = "Atom Z3400", 367 [0x4c] = "Atom Z8000", 368 [0x4d] = "Atom C2000", 369 [0x4e] = "Future gen Core", 370 [0x4f] = "Future gen Xeon (Broadwell)", 371 [0x56] = "Next gen Xeon D (Broadwell)", 372 [0x57] = "Next gen Xeon Phi", 373 [0x5a] = "Atom E3500", 374 [0x5d] = "Future Atom (Silvermont)", 375 }, 376 "Pentium Pro, II or III", /* Default */ 377 NULL, 378 intel_family_new_probe, 379 intel_cpu_cacheinfo, 380 }, 381 /* Family > 6 */ 382 { 383 CPUCLASS_686, 384 { 385 0, 0, 0, 0, 0, 0, 0, 0, 386 0, 0, 0, 0, 0, 0, 0, 0, 387 }, 388 "Pentium 4", /* Default */ 389 NULL, 390 intel_family_new_probe, 391 intel_cpu_cacheinfo, 392 } } 393 }, 394 { 395 "AuthenticAMD", 396 CPUVENDOR_AMD, 397 "AMD", 398 /* Family 4 */ 399 { { 400 CPUCLASS_486, 401 { 402 0, 0, 0, "Am486DX2 W/T", 403 0, 0, 0, "Am486DX2 W/B", 404 "Am486DX4 W/T or Am5x86 W/T 150", 405 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 406 0, 0, "Am5x86 W/T 133/160", 407 "Am5x86 W/B 133/160", 408 }, 409 "Am486 or Am5x86", /* Default */ 410 NULL, 411 NULL, 412 NULL, 413 }, 414 /* Family 5 */ 415 { 416 CPUCLASS_586, 417 { 418 "K5", "K5", "K5", "K5", 0, 0, "K6", 419 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 420 "K6-2+/III+", 0, 0, 421 }, 422 "K5 or K6", /* Default */ 423 amd_family5_setup, 424 NULL, 425 amd_cpu_cacheinfo, 426 }, 427 /* Family 6 */ 428 { 429 CPUCLASS_686, 430 { 431 0, "Athlon Model 1", "Athlon Model 2", 432 "Duron", "Athlon Model 4 (Thunderbird)", 433 0, "Athlon", "Duron", "Athlon", 0, 434 "Athlon", 0, 0, 0, 0, 0, 435 }, 436 "K7 (Athlon)", /* Default */ 437 NULL, 438 amd_family6_probe, 439 amd_cpu_cacheinfo, 440 }, 441 /* Family > 6 */ 442 { 443 CPUCLASS_686, 444 { 445 0, 0, 0, 0, 0, 0, 0, 0, 446 0, 0, 0, 0, 0, 0, 0, 0, 447 }, 448 "Unknown K8 (Athlon)", /* Default */ 449 NULL, 450 amd_family6_probe, 451 amd_cpu_cacheinfo, 452 } } 453 }, 454 { 455 "CyrixInstead", 456 CPUVENDOR_CYRIX, 457 "Cyrix", 458 /* Family 4 */ 459 { { 460 CPUCLASS_486, 461 { 462 0, 0, 0, 463 "MediaGX", 464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 465 }, 466 "486", /* Default */ 467 cyrix6x86_cpu_setup, /* XXX ?? */ 468 NULL, 469 NULL, 470 }, 471 /* Family 5 */ 472 { 473 CPUCLASS_586, 474 { 475 0, 0, "6x86", 0, 476 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 478 }, 479 "6x86", /* Default */ 480 cyrix6x86_cpu_setup, 481 NULL, 482 NULL, 483 }, 484 /* Family 6 */ 485 { 486 CPUCLASS_686, 487 { 488 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 489 0, 0, 0, 0, 0, 0, 0, 0, 490 }, 491 "6x86MX", /* Default */ 492 cyrix6x86_cpu_setup, 493 NULL, 494 NULL, 495 }, 496 /* Family > 6 */ 497 { 498 CPUCLASS_686, 499 { 500 0, 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 502 }, 503 "Unknown 6x86MX", /* Default */ 504 NULL, 505 NULL, 506 NULL, 507 } } 508 }, 509 { /* MediaGX is now owned by National Semiconductor */ 510 "Geode by NSC", 511 CPUVENDOR_CYRIX, /* XXX */ 512 "National Semiconductor", 513 /* Family 4, NSC never had any of these */ 514 { { 515 CPUCLASS_486, 516 { 517 0, 0, 0, 0, 0, 0, 0, 0, 518 0, 0, 0, 0, 0, 0, 0, 0, 519 }, 520 "486 compatible", /* Default */ 521 NULL, 522 NULL, 523 NULL, 524 }, 525 /* Family 5: Geode family, formerly MediaGX */ 526 { 527 CPUCLASS_586, 528 { 529 0, 0, 0, 0, 530 "Geode GX1", 531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 532 }, 533 "Geode", /* Default */ 534 cyrix6x86_cpu_setup, 535 NULL, 536 amd_cpu_cacheinfo, 537 }, 538 /* Family 6, not yet available from NSC */ 539 { 540 CPUCLASS_686, 541 { 542 0, 0, 0, 0, 0, 0, 0, 0, 543 0, 0, 0, 0, 0, 0, 0, 0, 544 }, 545 "Pentium Pro compatible", /* Default */ 546 NULL, 547 NULL, 548 NULL, 549 }, 550 /* Family > 6, not yet available from NSC */ 551 { 552 CPUCLASS_686, 553 { 554 0, 0, 0, 0, 0, 0, 0, 0, 555 0, 0, 0, 0, 0, 0, 0, 0, 556 }, 557 "Pentium Pro compatible", /* Default */ 558 NULL, 559 NULL, 560 NULL, 561 } } 562 }, 563 { 564 "CentaurHauls", 565 CPUVENDOR_IDT, 566 "IDT", 567 /* Family 4, IDT never had any of these */ 568 { { 569 CPUCLASS_486, 570 { 571 0, 0, 0, 0, 0, 0, 0, 0, 572 0, 0, 0, 0, 0, 0, 0, 0, 573 }, 574 "486 compatible", /* Default */ 575 NULL, 576 NULL, 577 NULL, 578 }, 579 /* Family 5 */ 580 { 581 CPUCLASS_586, 582 { 583 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 584 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 585 }, 586 "WinChip", /* Default */ 587 winchip_cpu_setup, 588 NULL, 589 NULL, 590 }, 591 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 592 { 593 CPUCLASS_686, 594 { 595 0, 0, 0, 0, 0, 0, "C3 Samuel", 596 "C3 Samuel 2/Ezra", "C3 Ezra-T", 597 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 598 0, "VIA Nano", 599 }, 600 "Unknown VIA/IDT", /* Default */ 601 NULL, 602 via_cpu_probe, 603 via_cpu_cacheinfo, 604 }, 605 /* Family > 6, not yet available from VIA */ 606 { 607 CPUCLASS_686, 608 { 609 0, 0, 0, 0, 0, 0, 0, 0, 610 0, 0, 0, 0, 0, 0, 0, 0, 611 }, 612 "Pentium Pro compatible", /* Default */ 613 NULL, 614 NULL, 615 NULL, 616 } } 617 }, 618 { 619 "GenuineTMx86", 620 CPUVENDOR_TRANSMETA, 621 "Transmeta", 622 /* Family 4, Transmeta never had any of these */ 623 { { 624 CPUCLASS_486, 625 { 626 0, 0, 0, 0, 0, 0, 0, 0, 627 0, 0, 0, 0, 0, 0, 0, 0, 628 }, 629 "486 compatible", /* Default */ 630 NULL, 631 NULL, 632 NULL, 633 }, 634 /* Family 5 */ 635 { 636 CPUCLASS_586, 637 { 638 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 640 }, 641 "Crusoe", /* Default */ 642 NULL, 643 NULL, 644 transmeta_cpu_info, 645 }, 646 /* Family 6, not yet available from Transmeta */ 647 { 648 CPUCLASS_686, 649 { 650 0, 0, 0, 0, 0, 0, 0, 0, 651 0, 0, 0, 0, 0, 0, 0, 0, 652 }, 653 "Pentium Pro compatible", /* Default */ 654 NULL, 655 NULL, 656 NULL, 657 }, 658 /* Family > 6, not yet available from Transmeta */ 659 { 660 CPUCLASS_686, 661 { 662 0, 0, 0, 0, 0, 0, 0, 0, 663 0, 0, 0, 0, 0, 0, 0, 0, 664 }, 665 "Pentium Pro compatible", /* Default */ 666 NULL, 667 NULL, 668 NULL, 669 } } 670 } 671 }; 672 673 /* 674 * disable the TSC such that we don't use the TSC in microtime(9) 675 * because some CPUs got the implementation wrong. 676 */ 677 static void 678 disable_tsc(struct cpu_info *ci) 679 { 680 if (ci->ci_feat_val[0] & CPUID_TSC) { 681 ci->ci_feat_val[0] &= ~CPUID_TSC; 682 aprint_error("WARNING: broken TSC disabled\n"); 683 } 684 } 685 686 static void 687 amd_family5_setup(struct cpu_info *ci) 688 { 689 690 switch (ci->ci_model) { 691 case 0: /* AMD-K5 Model 0 */ 692 /* 693 * According to the AMD Processor Recognition App Note, 694 * the AMD-K5 Model 0 uses the wrong bit to indicate 695 * support for global PTEs, instead using bit 9 (APIC) 696 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 697 */ 698 if (ci->ci_feat_val[0] & CPUID_APIC) 699 ci->ci_feat_val[0] = 700 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 701 /* 702 * XXX But pmap_pg_g is already initialized -- need to kick 703 * XXX the pmap somehow. How does the MP branch do this? 704 */ 705 break; 706 } 707 } 708 709 static void 710 cyrix6x86_cpu_setup(struct cpu_info *ci) 711 { 712 713 /* 714 * Do not disable the TSC on the Geode GX, it's reported to 715 * work fine. 716 */ 717 if (ci->ci_signature != 0x552) 718 disable_tsc(ci); 719 } 720 721 static void 722 winchip_cpu_setup(struct cpu_info *ci) 723 { 724 switch (ci->ci_model) { 725 case 4: /* WinChip C6 */ 726 disable_tsc(ci); 727 } 728 } 729 730 731 static const char * 732 intel_family6_name(struct cpu_info *ci) 733 { 734 const char *ret = NULL; 735 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 736 737 if (ci->ci_model == 5) { 738 switch (l2cache) { 739 case 0: 740 case 128 * 1024: 741 ret = "Celeron (Covington)"; 742 break; 743 case 256 * 1024: 744 ret = "Mobile Pentium II (Dixon)"; 745 break; 746 case 512 * 1024: 747 ret = "Pentium II"; 748 break; 749 case 1 * 1024 * 1024: 750 case 2 * 1024 * 1024: 751 ret = "Pentium II Xeon"; 752 break; 753 } 754 } else if (ci->ci_model == 6) { 755 switch (l2cache) { 756 case 256 * 1024: 757 case 512 * 1024: 758 ret = "Mobile Pentium II"; 759 break; 760 } 761 } else if (ci->ci_model == 7) { 762 switch (l2cache) { 763 case 512 * 1024: 764 ret = "Pentium III"; 765 break; 766 case 1 * 1024 * 1024: 767 case 2 * 1024 * 1024: 768 ret = "Pentium III Xeon"; 769 break; 770 } 771 } else if (ci->ci_model >= 8) { 772 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 773 switch (ci->ci_brand_id) { 774 case 0x3: 775 if (ci->ci_signature == 0x6B1) 776 ret = "Celeron"; 777 break; 778 case 0x8: 779 if (ci->ci_signature >= 0xF13) 780 ret = "genuine processor"; 781 break; 782 case 0xB: 783 if (ci->ci_signature >= 0xF13) 784 ret = "Xeon MP"; 785 break; 786 case 0xE: 787 if (ci->ci_signature < 0xF13) 788 ret = "Xeon"; 789 break; 790 } 791 if (ret == NULL) 792 ret = i386_intel_brand[ci->ci_brand_id]; 793 } 794 } 795 796 return ret; 797 } 798 799 /* 800 * Identify AMD64 CPU names from cpuid. 801 * 802 * Based on: 803 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 804 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 805 * "Revision Guide for AMD NPT Family 0Fh Processors" 806 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 807 * and other miscellaneous reports. 808 * 809 * This is all rather pointless, these are cross 'brand' since the raw 810 * silicon is shared. 811 */ 812 static const char * 813 amd_amd64_name(struct cpu_info *ci) 814 { 815 static char family_str[32]; 816 817 /* Only called if family >= 15 */ 818 819 switch (ci->ci_family) { 820 case 15: 821 switch (ci->ci_model) { 822 case 0x21: /* rev JH-E1/E6 */ 823 case 0x41: /* rev JH-F2 */ 824 return "Dual-Core Opteron"; 825 case 0x23: /* rev JH-E6 (Toledo) */ 826 return "Dual-Core Opteron or Athlon 64 X2"; 827 case 0x43: /* rev JH-F2 (Windsor) */ 828 return "Athlon 64 FX or Athlon 64 X2"; 829 case 0x24: /* rev SH-E5 (Lancaster?) */ 830 return "Mobile Athlon 64 or Turion 64"; 831 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 832 return "Opteron or Athlon 64 FX"; 833 case 0x15: /* rev SH-D0 */ 834 case 0x25: /* rev SH-E4 */ 835 return "Opteron"; 836 case 0x27: /* rev DH-E4, SH-E4 */ 837 return "Athlon 64 or Athlon 64 FX or Opteron"; 838 case 0x48: /* rev BH-F2 */ 839 return "Turion 64 X2"; 840 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 841 case 0x07: /* rev SH-CG (ClawHammer) */ 842 case 0x0b: /* rev CH-CG */ 843 case 0x14: /* rev SH-D0 */ 844 case 0x17: /* rev SH-D0 */ 845 case 0x1b: /* rev CH-D0 */ 846 return "Athlon 64"; 847 case 0x2b: /* rev BH-E4 (Manchester) */ 848 case 0x4b: /* rev BH-F2 (Windsor) */ 849 return "Athlon 64 X2"; 850 case 0x6b: /* rev BH-G1 (Brisbane) */ 851 return "Athlon X2 or Athlon 64 X2"; 852 case 0x08: /* rev CH-CG */ 853 case 0x0c: /* rev DH-CG (Newcastle) */ 854 case 0x0e: /* rev DH-CG (Newcastle?) */ 855 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 856 case 0x18: /* rev CH-D0 */ 857 case 0x1c: /* rev DH-D0 (Winchester) */ 858 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 859 case 0x2c: /* rev DH-E3/E6 */ 860 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 861 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 862 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 863 case 0x6f: /* rev DH-G1 */ 864 return "Athlon 64 or Sempron"; 865 default: 866 break; 867 } 868 return "Unknown AMD64 CPU"; 869 870 #if 0 871 case 16: 872 return "Family 10h"; 873 case 17: 874 return "Family 11h"; 875 case 18: 876 return "Family 12h"; 877 case 19: 878 return "Family 14h"; 879 case 20: 880 return "Family 15h"; 881 #endif 882 883 default: 884 break; 885 } 886 887 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 888 return family_str; 889 } 890 891 static void 892 intel_family_new_probe(struct cpu_info *ci) 893 { 894 uint32_t descs[4]; 895 896 x86_cpuid(0x80000000, descs); 897 898 /* 899 * Determine extended feature flags. 900 */ 901 if (descs[0] >= 0x80000001) { 902 x86_cpuid(0x80000001, descs); 903 ci->ci_feat_val[2] |= descs[3]; 904 ci->ci_feat_val[3] |= descs[2]; 905 } 906 } 907 908 static void 909 via_cpu_probe(struct cpu_info *ci) 910 { 911 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 912 u_int descs[4]; 913 u_int lfunc; 914 915 /* 916 * Determine the largest extended function value. 917 */ 918 x86_cpuid(0x80000000, descs); 919 lfunc = descs[0]; 920 921 /* 922 * Determine the extended feature flags. 923 */ 924 if (lfunc >= 0x80000001) { 925 x86_cpuid(0x80000001, descs); 926 ci->ci_feat_val[2] |= descs[3]; 927 } 928 929 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 930 return; 931 932 /* Nehemiah or Esther */ 933 x86_cpuid(0xc0000000, descs); 934 lfunc = descs[0]; 935 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 936 return; 937 938 x86_cpuid(0xc0000001, descs); 939 lfunc = descs[3]; 940 ci->ci_feat_val[4] = lfunc; 941 } 942 943 static void 944 amd_family6_probe(struct cpu_info *ci) 945 { 946 uint32_t descs[4]; 947 char *p; 948 size_t i; 949 950 x86_cpuid(0x80000000, descs); 951 952 /* 953 * Determine the extended feature flags. 954 */ 955 if (descs[0] >= 0x80000001) { 956 x86_cpuid(0x80000001, descs); 957 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 958 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 959 } 960 961 if (*cpu_brand_string == '\0') 962 return; 963 964 for (i = 1; i < __arraycount(amd_brand); i++) 965 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 966 ci->ci_brand_id = i; 967 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 968 break; 969 } 970 } 971 972 static void 973 intel_cpu_cacheinfo(struct cpu_info *ci) 974 { 975 const struct x86_cache_info *cai; 976 u_int descs[4]; 977 int iterations, i, j; 978 int type, level; 979 int ways, partitions, linesize, sets; 980 int caitype = -1; 981 int totalsize; 982 uint8_t desc; 983 984 /* Return if the cpu is old pre-cpuid instruction cpu */ 985 if (ci->ci_cpu_type >= 0) 986 return; 987 988 if (ci->ci_cpuid_level < 2) 989 return; 990 991 /* 992 * Parse the cache info from `cpuid leaf 2', if we have it. 993 * XXX This is kinda ugly, but hey, so is the architecture... 994 */ 995 x86_cpuid(2, descs); 996 iterations = descs[0] & 0xff; 997 while (iterations-- > 0) { 998 for (i = 0; i < 4; i++) { 999 if (descs[i] & 0x80000000) 1000 continue; 1001 for (j = 0; j < 4; j++) { 1002 /* 1003 * The least significant byte in EAX 1004 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1005 * it should be ignored. 1006 */ 1007 if (i == 0 && j == 0) 1008 continue; 1009 desc = (descs[i] >> (j * 8)) & 0xff; 1010 if (desc == 0) 1011 continue; 1012 cai = cache_info_lookup(intel_cpuid_cache_info, 1013 desc); 1014 if (cai != NULL) 1015 ci->ci_cinfo[cai->cai_index] = *cai; 1016 else if ((verbose != 0) && (desc != 0xff)) 1017 printf("Unknown cacheinfo desc %02x\n", 1018 desc); 1019 } 1020 } 1021 x86_cpuid(2, descs); 1022 } 1023 1024 if (ci->ci_cpuid_level < 4) 1025 return; 1026 1027 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1028 for (i = 0; ; i++) { 1029 x86_cpuid2(4, i, descs); 1030 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1031 if (type == CPUID_DCP_CACHETYPE_N) 1032 break; 1033 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1034 switch (level) { 1035 case 1: 1036 if (type == CPUID_DCP_CACHETYPE_I) 1037 caitype = CAI_ICACHE; 1038 else if (type == CPUID_DCP_CACHETYPE_D) 1039 caitype = CAI_DCACHE; 1040 else 1041 caitype = -1; 1042 break; 1043 case 2: 1044 if (type == CPUID_DCP_CACHETYPE_U) 1045 caitype = CAI_L2CACHE; 1046 else 1047 caitype = -1; 1048 break; 1049 case 3: 1050 if (type == CPUID_DCP_CACHETYPE_U) 1051 caitype = CAI_L3CACHE; 1052 else 1053 caitype = -1; 1054 break; 1055 default: 1056 caitype = -1; 1057 break; 1058 } 1059 if (caitype == -1) { 1060 printf("unknown cache level&type (%d & %d)\n", 1061 level, type); 1062 continue; 1063 } 1064 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1065 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1066 + 1; 1067 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1068 + 1; 1069 sets = descs[2] + 1; 1070 totalsize = ways * partitions * linesize * sets; 1071 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1072 ci->ci_cinfo[caitype].cai_associativity = ways; 1073 ci->ci_cinfo[caitype].cai_linesize = linesize; 1074 } 1075 } 1076 1077 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1078 AMD_L2CACHE_INFO; 1079 1080 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1081 AMD_L3CACHE_INFO; 1082 1083 static void 1084 amd_cpu_cacheinfo(struct cpu_info *ci) 1085 { 1086 const struct x86_cache_info *cp; 1087 struct x86_cache_info *cai; 1088 u_int descs[4]; 1089 u_int lfunc; 1090 1091 /* 1092 * K5 model 0 has none of this info. 1093 */ 1094 if (ci->ci_family == 5 && ci->ci_model == 0) 1095 return; 1096 1097 /* 1098 * Determine the largest extended function value. 1099 */ 1100 x86_cpuid(0x80000000, descs); 1101 lfunc = descs[0]; 1102 1103 /* 1104 * Determine L1 cache/TLB info. 1105 */ 1106 if (lfunc < 0x80000005) { 1107 /* No L1 cache info available. */ 1108 return; 1109 } 1110 1111 x86_cpuid(0x80000005, descs); 1112 1113 /* 1114 * K6-III and higher have large page TLBs. 1115 */ 1116 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1117 cai = &ci->ci_cinfo[CAI_ITLB2]; 1118 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1119 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1120 cai->cai_linesize = largepagesize; 1121 1122 cai = &ci->ci_cinfo[CAI_DTLB2]; 1123 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1124 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1125 cai->cai_linesize = largepagesize; 1126 } 1127 1128 cai = &ci->ci_cinfo[CAI_ITLB]; 1129 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1130 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1131 cai->cai_linesize = (4 * 1024); 1132 1133 cai = &ci->ci_cinfo[CAI_DTLB]; 1134 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1135 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1136 cai->cai_linesize = (4 * 1024); 1137 1138 cai = &ci->ci_cinfo[CAI_DCACHE]; 1139 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1140 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1141 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1142 1143 cai = &ci->ci_cinfo[CAI_ICACHE]; 1144 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1145 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1146 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1147 1148 /* 1149 * Determine L2 cache/TLB info. 1150 */ 1151 if (lfunc < 0x80000006) { 1152 /* No L2 cache info available. */ 1153 return; 1154 } 1155 1156 x86_cpuid(0x80000006, descs); 1157 1158 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1159 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1160 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1161 cai->cai_linesize = (4 * 1024); 1162 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1163 cai->cai_associativity); 1164 if (cp != NULL) 1165 cai->cai_associativity = cp->cai_associativity; 1166 else 1167 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1168 1169 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1170 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1171 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1172 cai->cai_linesize = largepagesize; 1173 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1174 cai->cai_associativity); 1175 if (cp != NULL) 1176 cai->cai_associativity = cp->cai_associativity; 1177 else 1178 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1179 1180 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1181 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1182 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1183 cai->cai_linesize = (4 * 1024); 1184 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1185 cai->cai_associativity); 1186 if (cp != NULL) 1187 cai->cai_associativity = cp->cai_associativity; 1188 else 1189 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1190 1191 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1192 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1193 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1194 cai->cai_linesize = largepagesize; 1195 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1196 cai->cai_associativity); 1197 if (cp != NULL) 1198 cai->cai_associativity = cp->cai_associativity; 1199 else 1200 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1201 1202 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1203 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1204 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1205 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1206 1207 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1208 cai->cai_associativity); 1209 if (cp != NULL) 1210 cai->cai_associativity = cp->cai_associativity; 1211 else 1212 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1213 1214 /* 1215 * Determine L3 cache info on AMD Family 10h and newer processors 1216 */ 1217 if (ci->ci_family >= 0x10) { 1218 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1219 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1220 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1221 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1222 1223 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1224 cai->cai_associativity); 1225 if (cp != NULL) 1226 cai->cai_associativity = cp->cai_associativity; 1227 else 1228 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1229 } 1230 1231 /* 1232 * Determine 1GB TLB info. 1233 */ 1234 if (lfunc < 0x80000019) { 1235 /* No 1GB TLB info available. */ 1236 return; 1237 } 1238 1239 x86_cpuid(0x80000019, descs); 1240 1241 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1242 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1243 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1244 cai->cai_linesize = (1024 * 1024 * 1024); 1245 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1246 cai->cai_associativity); 1247 if (cp != NULL) 1248 cai->cai_associativity = cp->cai_associativity; 1249 else 1250 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1251 1252 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1253 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1254 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1255 cai->cai_linesize = (1024 * 1024 * 1024); 1256 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1257 cai->cai_associativity); 1258 if (cp != NULL) 1259 cai->cai_associativity = cp->cai_associativity; 1260 else 1261 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1262 1263 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1264 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1265 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1266 cai->cai_linesize = (1024 * 1024 * 1024); 1267 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1268 cai->cai_associativity); 1269 if (cp != NULL) 1270 cai->cai_associativity = cp->cai_associativity; 1271 else 1272 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1273 1274 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1275 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1276 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1277 cai->cai_linesize = (1024 * 1024 * 1024); 1278 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1279 cai->cai_associativity); 1280 if (cp != NULL) 1281 cai->cai_associativity = cp->cai_associativity; 1282 else 1283 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1284 } 1285 1286 static void 1287 via_cpu_cacheinfo(struct cpu_info *ci) 1288 { 1289 struct x86_cache_info *cai; 1290 int stepping; 1291 u_int descs[4]; 1292 u_int lfunc; 1293 1294 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1295 1296 /* 1297 * Determine the largest extended function value. 1298 */ 1299 x86_cpuid(0x80000000, descs); 1300 lfunc = descs[0]; 1301 1302 /* 1303 * Determine L1 cache/TLB info. 1304 */ 1305 if (lfunc < 0x80000005) { 1306 /* No L1 cache info available. */ 1307 return; 1308 } 1309 1310 x86_cpuid(0x80000005, descs); 1311 1312 cai = &ci->ci_cinfo[CAI_ITLB]; 1313 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1314 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1315 cai->cai_linesize = (4 * 1024); 1316 1317 cai = &ci->ci_cinfo[CAI_DTLB]; 1318 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1319 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1320 cai->cai_linesize = (4 * 1024); 1321 1322 cai = &ci->ci_cinfo[CAI_DCACHE]; 1323 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1324 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1325 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1326 if (ci->ci_model == 9 && stepping == 8) { 1327 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1328 cai->cai_associativity = 2; 1329 } 1330 1331 cai = &ci->ci_cinfo[CAI_ICACHE]; 1332 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1333 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1334 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1335 if (ci->ci_model == 9 && stepping == 8) { 1336 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1337 cai->cai_associativity = 2; 1338 } 1339 1340 /* 1341 * Determine L2 cache/TLB info. 1342 */ 1343 if (lfunc < 0x80000006) { 1344 /* No L2 cache info available. */ 1345 return; 1346 } 1347 1348 x86_cpuid(0x80000006, descs); 1349 1350 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1351 if (ci->ci_model >= 9) { 1352 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1353 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1354 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1355 } else { 1356 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1357 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1358 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1359 } 1360 } 1361 1362 static void 1363 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1364 { 1365 u_int descs[4]; 1366 1367 x86_cpuid(0x80860007, descs); 1368 *frequency = descs[0]; 1369 *voltage = descs[1]; 1370 *percentage = descs[2]; 1371 } 1372 1373 static void 1374 transmeta_cpu_info(struct cpu_info *ci) 1375 { 1376 u_int descs[4], nreg; 1377 u_int frequency, voltage, percentage; 1378 1379 x86_cpuid(0x80860000, descs); 1380 nreg = descs[0]; 1381 if (nreg >= 0x80860001) { 1382 x86_cpuid(0x80860001, descs); 1383 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1384 (descs[1] >> 24) & 0xff, 1385 (descs[1] >> 16) & 0xff, 1386 (descs[1] >> 8) & 0xff, 1387 descs[1] & 0xff); 1388 } 1389 if (nreg >= 0x80860002) { 1390 x86_cpuid(0x80860002, descs); 1391 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1392 (descs[1] >> 24) & 0xff, 1393 (descs[1] >> 16) & 0xff, 1394 (descs[1] >> 8) & 0xff, 1395 descs[1] & 0xff, 1396 descs[2]); 1397 } 1398 if (nreg >= 0x80860006) { 1399 union { 1400 char text[65]; 1401 u_int descs[4][4]; 1402 } info; 1403 int i; 1404 1405 for (i=0; i<4; i++) { 1406 x86_cpuid(0x80860003 + i, info.descs[i]); 1407 } 1408 info.text[64] = '\0'; 1409 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1410 } 1411 1412 if (nreg >= 0x80860007) { 1413 tmx86_get_longrun_status(&frequency, 1414 &voltage, &percentage); 1415 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1416 frequency, voltage, percentage); 1417 } 1418 } 1419 1420 static void 1421 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1422 { 1423 u_int descs[4]; 1424 int i; 1425 uint32_t brand[12]; 1426 1427 memset(ci, 0, sizeof(*ci)); 1428 ci->ci_dev = cpuname; 1429 1430 ci->ci_cpu_type = x86_identify(); 1431 if (ci->ci_cpu_type >= 0) { 1432 /* Old pre-cpuid instruction cpu */ 1433 ci->ci_cpuid_level = -1; 1434 return; 1435 } 1436 1437 /* 1438 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1439 * function. 1440 */ 1441 1442 /* 1443 * Fn0000_0000: 1444 * - Save cpuid max level. 1445 * - Save vendor string. 1446 */ 1447 x86_cpuid(0, descs); 1448 ci->ci_cpuid_level = descs[0]; 1449 /* Save vendor string */ 1450 ci->ci_vendor[0] = descs[1]; 1451 ci->ci_vendor[2] = descs[2]; 1452 ci->ci_vendor[1] = descs[3]; 1453 ci->ci_vendor[3] = 0; 1454 1455 /* 1456 * Fn8000_0000: 1457 * - Get cpuid extended function's max level. 1458 */ 1459 x86_cpuid(0x80000000, descs); 1460 if (descs[0] >= 0x80000000) 1461 ci->ci_cpuid_extlevel = descs[0]; 1462 else { 1463 /* Set lower value than 0x80000000 */ 1464 ci->ci_cpuid_extlevel = 0; 1465 } 1466 1467 /* 1468 * Fn8000_000[2-4]: 1469 * - Save brand string. 1470 */ 1471 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1472 x86_cpuid(0x80000002, brand); 1473 x86_cpuid(0x80000003, brand + 4); 1474 x86_cpuid(0x80000004, brand + 8); 1475 for (i = 0; i < 48; i++) 1476 if (((char *) brand)[i] != ' ') 1477 break; 1478 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1479 } 1480 1481 if (ci->ci_cpuid_level < 1) 1482 return; 1483 1484 /* 1485 * Fn0000_0001: 1486 * - Get CPU family, model and stepping (from eax). 1487 * - Initial local APIC ID and brand ID (from ebx) 1488 * - CPUID2 (from ecx) 1489 * - CPUID (from edx) 1490 */ 1491 x86_cpuid(1, descs); 1492 ci->ci_signature = descs[0]; 1493 1494 /* Extract full family/model values */ 1495 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1496 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1497 1498 /* Brand is low order 8 bits of ebx */ 1499 ci->ci_brand_id = descs[1] & 0xff; 1500 /* Initial local APIC ID */ 1501 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1502 1503 ci->ci_feat_val[1] = descs[2]; 1504 ci->ci_feat_val[0] = descs[3]; 1505 1506 if (ci->ci_cpuid_level < 3) 1507 return; 1508 1509 /* 1510 * If the processor serial number misfeature is present and supported, 1511 * extract it here. 1512 */ 1513 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1514 ci->ci_cpu_serial[0] = ci->ci_signature; 1515 x86_cpuid(3, descs); 1516 ci->ci_cpu_serial[2] = descs[2]; 1517 ci->ci_cpu_serial[1] = descs[3]; 1518 } 1519 1520 if (ci->ci_cpuid_level < 0xd) 1521 return; 1522 1523 /* Get support XCR0 bits */ 1524 x86_cpuid2(0xd, 0, descs); 1525 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1526 ci->ci_cur_xsave = descs[1]; 1527 ci->ci_max_xsave = descs[2]; 1528 1529 /* Additional flags (eg xsaveopt support) */ 1530 x86_cpuid2(0xd, 1, descs); 1531 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1532 } 1533 1534 static void 1535 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1536 { 1537 uint32_t descs[4]; 1538 char hv_sig[13]; 1539 char *p; 1540 const char *hv_name; 1541 int i; 1542 1543 /* 1544 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1545 * http://lkml.org/lkml/2008/10/1/246 1546 * 1547 * KB1009458: Mechanisms to determine if software is running in 1548 * a VMware virtual machine 1549 * http://kb.vmware.com/kb/1009458 1550 */ 1551 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1552 x86_cpuid(0x40000000, descs); 1553 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1554 memcpy(p, &descs[i], sizeof(descs[i])); 1555 *p = '\0'; 1556 /* 1557 * HV vendor ID string 1558 * ------------+-------------- 1559 * KVM "KVMKVMKVM" 1560 * Microsoft "Microsoft Hv" 1561 * VMware "VMwareVMware" 1562 * Xen "XenVMMXenVMM" 1563 */ 1564 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1565 hv_name = "KVM"; 1566 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1567 hv_name = "Hyper-V"; 1568 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1569 hv_name = "VMware"; 1570 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1571 hv_name = "Xen"; 1572 else 1573 hv_name = "unknown"; 1574 1575 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1576 } 1577 } 1578 1579 static void 1580 cpu_probe_features(struct cpu_info *ci) 1581 { 1582 const struct cpu_cpuid_nameclass *cpup = NULL; 1583 unsigned int i; 1584 1585 if (ci->ci_cpuid_level < 1) 1586 return; 1587 1588 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1589 if (!strncmp((char *)ci->ci_vendor, 1590 i386_cpuid_cpus[i].cpu_id, 12)) { 1591 cpup = &i386_cpuid_cpus[i]; 1592 break; 1593 } 1594 } 1595 1596 if (cpup == NULL) 1597 return; 1598 1599 i = ci->ci_family - CPU_MINFAMILY; 1600 1601 if (i >= __arraycount(cpup->cpu_family)) 1602 i = __arraycount(cpup->cpu_family) - 1; 1603 1604 if (cpup->cpu_family[i].cpu_probe == NULL) 1605 return; 1606 1607 (*cpup->cpu_family[i].cpu_probe)(ci); 1608 } 1609 1610 static void 1611 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1612 { 1613 char buf[32 * 16]; 1614 char *bp; 1615 1616 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1617 1618 if (val == 0 || fmt == NULL) 1619 return; 1620 1621 snprintb_m(buf, sizeof(buf), fmt, val, 1622 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1623 bp = buf; 1624 while (*bp != '\0') { 1625 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1626 bp += strlen(bp) + 1; 1627 } 1628 } 1629 1630 static void 1631 identifycpu_cpuids(struct cpu_info *ci) 1632 { 1633 const char *cpuname = ci->ci_dev; 1634 u_int lp_max = 1; /* logical processors per package */ 1635 u_int smt_max; /* smt per core */ 1636 u_int core_max = 1; /* core per package */ 1637 u_int smt_bits, core_bits; 1638 uint32_t descs[4]; 1639 1640 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1641 ci->ci_packageid = ci->ci_initapicid; 1642 ci->ci_coreid = 0; 1643 ci->ci_smtid = 0; 1644 if (cpu_vendor != CPUVENDOR_INTEL) { 1645 return; 1646 } 1647 1648 /* 1649 * 253668.pdf 7.10.2 1650 */ 1651 1652 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1653 x86_cpuid(1, descs); 1654 lp_max = (descs[1] >> 16) & 0xff; 1655 } 1656 if (ci->ci_cpuid_level >= 4) { 1657 x86_cpuid2(4, 0, descs); 1658 core_max = (descs[0] >> 26) + 1; 1659 } 1660 assert(lp_max >= core_max); 1661 smt_max = lp_max / core_max; 1662 smt_bits = ilog2(smt_max - 1) + 1; 1663 core_bits = ilog2(core_max - 1) + 1; 1664 if (smt_bits + core_bits) { 1665 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1666 } 1667 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1668 ci->ci_packageid); 1669 if (core_bits) { 1670 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1671 1672 ci->ci_coreid = 1673 __SHIFTOUT(ci->ci_initapicid, core_mask); 1674 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1675 } 1676 if (smt_bits) { 1677 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1678 1679 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1680 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1681 } 1682 } 1683 1684 void 1685 identifycpu(int fd, const char *cpuname) 1686 { 1687 const char *name = "", *modifier, *vendorname, *brand = ""; 1688 int class = CPUCLASS_386; 1689 unsigned int i; 1690 int modif, family; 1691 const struct cpu_cpuid_nameclass *cpup = NULL; 1692 const struct cpu_cpuid_family *cpufam; 1693 struct cpu_info *ci, cistore; 1694 u_int descs[4]; 1695 size_t sz; 1696 struct cpu_ucode_version ucode; 1697 union { 1698 struct cpu_ucode_version_amd amd; 1699 struct cpu_ucode_version_intel1 intel1; 1700 } ucvers; 1701 1702 ci = &cistore; 1703 cpu_probe_base_features(ci, cpuname); 1704 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1705 ci->ci_cpuid_level); 1706 if (verbose) { 1707 int bf; 1708 1709 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1710 x86_cpuid(bf, descs); 1711 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1712 bf, descs[0], descs[1], descs[2], descs[3]); 1713 } 1714 } 1715 if (ci->ci_cpuid_extlevel >= 0x80000000) 1716 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1717 ci->ci_cpuid_extlevel); 1718 if (verbose) { 1719 unsigned int ef; 1720 1721 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1722 x86_cpuid(ef, descs); 1723 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1724 ef, descs[0], descs[1], descs[2], descs[3]); 1725 } 1726 } 1727 1728 cpu_probe_hv_features(ci, cpuname); 1729 cpu_probe_features(ci); 1730 1731 if (ci->ci_cpu_type >= 0) { 1732 /* Old pre-cpuid instruction cpu */ 1733 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1734 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1735 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1736 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1737 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1738 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1739 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1740 modifier = ""; 1741 } else { 1742 /* CPU which support cpuid instruction */ 1743 modif = (ci->ci_signature >> 12) & 0x3; 1744 family = ci->ci_family; 1745 if (family < CPU_MINFAMILY) 1746 errx(1, "identifycpu: strange family value"); 1747 if (family > CPU_MAXFAMILY) 1748 family = CPU_MAXFAMILY; 1749 1750 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1751 if (!strncmp((char *)ci->ci_vendor, 1752 i386_cpuid_cpus[i].cpu_id, 12)) { 1753 cpup = &i386_cpuid_cpus[i]; 1754 break; 1755 } 1756 } 1757 1758 if (cpup == NULL) { 1759 cpu_vendor = CPUVENDOR_UNKNOWN; 1760 if (ci->ci_vendor[0] != '\0') 1761 vendorname = (char *)&ci->ci_vendor[0]; 1762 else 1763 vendorname = "Unknown"; 1764 class = family - 3; 1765 modifier = ""; 1766 name = ""; 1767 ci->ci_info = NULL; 1768 } else { 1769 cpu_vendor = cpup->cpu_vendor; 1770 vendorname = cpup->cpu_vendorname; 1771 modifier = modifiers[modif]; 1772 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1773 name = cpufam->cpu_models[ci->ci_model]; 1774 if (name == NULL || *name == '\0') 1775 name = cpufam->cpu_model_default; 1776 class = cpufam->cpu_class; 1777 ci->ci_info = cpufam->cpu_info; 1778 1779 if (cpu_vendor == CPUVENDOR_INTEL) { 1780 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1781 const char *tmp; 1782 tmp = intel_family6_name(ci); 1783 if (tmp != NULL) 1784 name = tmp; 1785 } 1786 if (ci->ci_family == 15 && 1787 ci->ci_brand_id < 1788 __arraycount(i386_intel_brand) && 1789 i386_intel_brand[ci->ci_brand_id]) 1790 name = 1791 i386_intel_brand[ci->ci_brand_id]; 1792 } 1793 1794 if (cpu_vendor == CPUVENDOR_AMD) { 1795 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1796 if (ci->ci_brand_id == 1) 1797 /* 1798 * It's Duron. We override the 1799 * name, since it might have 1800 * been misidentified as Athlon. 1801 */ 1802 name = 1803 amd_brand[ci->ci_brand_id]; 1804 else 1805 brand = amd_brand_name; 1806 } 1807 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1808 == 0xf) { 1809 /* Identify AMD64 CPU names. */ 1810 const char *tmp; 1811 tmp = amd_amd64_name(ci); 1812 if (tmp != NULL) 1813 name = tmp; 1814 } 1815 } 1816 1817 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1818 vendorname = "VIA"; 1819 } 1820 } 1821 1822 ci->ci_cpu_class = class; 1823 1824 sz = sizeof(ci->ci_tsc_freq); 1825 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1826 sz = sizeof(use_pae); 1827 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1828 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1829 1830 /* 1831 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1832 * we try to determine from the family/model values. 1833 */ 1834 if (*cpu_brand_string != '\0') 1835 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1836 1837 aprint_normal("%s: %s", cpuname, vendorname); 1838 if (*modifier) 1839 aprint_normal(" %s", modifier); 1840 if (*name) 1841 aprint_normal(" %s", name); 1842 if (*brand) 1843 aprint_normal(" %s", brand); 1844 aprint_normal(" (%s-class)", classnames[class]); 1845 1846 if (ci->ci_tsc_freq != 0) 1847 aprint_normal(", %ju.%02ju MHz", 1848 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1849 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1850 aprint_normal("\n"); 1851 1852 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1853 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1854 if (ci->ci_signature != 0) 1855 aprint_normal(" (id %#x)", ci->ci_signature); 1856 aprint_normal("\n"); 1857 1858 if (ci->ci_info) 1859 (*ci->ci_info)(ci); 1860 1861 /* 1862 * display CPU feature flags 1863 */ 1864 1865 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1866 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1867 1868 /* These next two are actually common definitions! */ 1869 print_bits(cpuname, "features2", 1870 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1871 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1872 print_bits(cpuname, "features3", 1873 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1874 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1875 1876 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1877 ci->ci_feat_val[4]); 1878 1879 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1880 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1881 ci->ci_feat_val[6]); 1882 1883 if (ci->ci_max_xsave != 0) { 1884 aprint_normal("%s: xsave area size: current %d, maximum %d", 1885 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1886 aprint_normal(", xgetbv %sabled\n", 1887 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1888 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1889 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1890 x86_xgetbv()); 1891 } 1892 1893 x86_print_cache_and_tlb_info(ci); 1894 1895 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1896 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1897 cpuname, 1898 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1899 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1900 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1901 } 1902 1903 if (ci->ci_cpu_class == CPUCLASS_386) { 1904 errx(1, "NetBSD requires an 80486 or later processor"); 1905 } 1906 1907 if (ci->ci_cpu_type == CPU_486DLC) { 1908 #ifndef CYRIX_CACHE_WORKS 1909 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1910 #else 1911 #ifndef CYRIX_CACHE_REALLY_WORKS 1912 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1913 #else 1914 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1915 #endif 1916 #endif 1917 } 1918 1919 /* 1920 * Everything past this point requires a Pentium or later. 1921 */ 1922 if (ci->ci_cpuid_level < 0) 1923 return; 1924 1925 identifycpu_cpuids(ci); 1926 1927 #ifdef INTEL_CORETEMP 1928 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1929 coretemp_register(ci); 1930 #endif 1931 1932 if (cpu_vendor == CPUVENDOR_AMD) { 1933 uint32_t data[4]; 1934 1935 x86_cpuid(0x80000000, data); 1936 if (data[0] >= 0x80000007) 1937 powernow_probe(ci); 1938 1939 if ((data[0] >= 0x8000000a) 1940 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1941 x86_cpuid(0x8000000a, data); 1942 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1943 data[0] & 0xf); 1944 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1945 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1946 data[3]); 1947 } 1948 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1949 uint32_t data[4]; 1950 int32_t bi_index; 1951 1952 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1953 x86_cpuid(bi_index, data); 1954 switch (bi_index) { 1955 case 6: 1956 print_bits(cpuname, "DSPM-eax", 1957 CPUID_DSPM_FLAGS, data[0]); 1958 print_bits(cpuname, "DSPM-ecx", 1959 CPUID_DSPM_FLAGS1, data[2]); 1960 break; 1961 case 7: 1962 aprint_verbose("%s: SEF highest subleaf %08x\n", 1963 cpuname, data[0]); 1964 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1965 data[1]); 1966 break; 1967 #if 0 1968 default: 1969 aprint_verbose("%s: basic %08x-eax %08x\n", 1970 cpuname, bi_index, data[0]); 1971 aprint_verbose("%s: basic %08x-ebx %08x\n", 1972 cpuname, bi_index, data[1]); 1973 aprint_verbose("%s: basic %08x-ecx %08x\n", 1974 cpuname, bi_index, data[2]); 1975 aprint_verbose("%s: basic %08x-edx %08x\n", 1976 cpuname, bi_index, data[3]); 1977 break; 1978 #endif 1979 } 1980 } 1981 } 1982 1983 #ifdef INTEL_ONDEMAND_CLOCKMOD 1984 clockmod_init(); 1985 #endif 1986 1987 if (cpu_vendor == CPUVENDOR_AMD) 1988 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1989 else if (cpu_vendor == CPUVENDOR_INTEL) 1990 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1991 else 1992 return; 1993 1994 ucode.data = &ucvers; 1995 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1996 #ifdef __i386__ 1997 struct cpu_ucode_version_64 ucode_64; 1998 if (errno != ENOTTY) 1999 return; 2000 /* Try the 64 bit ioctl */ 2001 memset(&ucode_64, 0, sizeof ucode_64); 2002 ucode_64.data = &ucvers; 2003 ucode_64.loader_version = ucode.loader_version; 2004 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2005 return; 2006 #else 2007 return; 2008 #endif 2009 } 2010 2011 if (cpu_vendor == CPUVENDOR_AMD) 2012 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2013 else if (cpu_vendor == CPUVENDOR_INTEL) 2014 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2015 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2016 } 2017 2018 static const struct x86_cache_info * 2019 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2020 { 2021 int i; 2022 2023 for (i = 0; cai[i].cai_desc != 0; i++) { 2024 if (cai[i].cai_desc == desc) 2025 return (&cai[i]); 2026 } 2027 2028 return (NULL); 2029 } 2030 2031 static const char * 2032 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2033 const char *sep) 2034 { 2035 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2036 char human_num[HUMAN_BUFSIZE]; 2037 2038 if (cai->cai_totalsize == 0) 2039 return sep; 2040 2041 if (sep == NULL) 2042 aprint_verbose_dev(ci->ci_dev, ""); 2043 else 2044 aprint_verbose("%s", sep); 2045 if (name != NULL) 2046 aprint_verbose("%s ", name); 2047 2048 if (cai->cai_string != NULL) { 2049 aprint_verbose("%s ", cai->cai_string); 2050 } else { 2051 (void)humanize_number(human_num, sizeof(human_num), 2052 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2053 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2054 } 2055 switch (cai->cai_associativity) { 2056 case 0: 2057 aprint_verbose("disabled"); 2058 break; 2059 case 1: 2060 aprint_verbose("direct-mapped"); 2061 break; 2062 case 0xff: 2063 aprint_verbose("fully associative"); 2064 break; 2065 default: 2066 aprint_verbose("%d-way", cai->cai_associativity); 2067 break; 2068 } 2069 return ", "; 2070 } 2071 2072 static const char * 2073 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2074 const char *sep) 2075 { 2076 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2077 char human_num[HUMAN_BUFSIZE]; 2078 2079 if (cai->cai_totalsize == 0) 2080 return sep; 2081 2082 if (sep == NULL) 2083 aprint_verbose_dev(ci->ci_dev, ""); 2084 else 2085 aprint_verbose("%s", sep); 2086 if (name != NULL) 2087 aprint_verbose("%s ", name); 2088 2089 if (cai->cai_string != NULL) { 2090 aprint_verbose("%s", cai->cai_string); 2091 } else { 2092 (void)humanize_number(human_num, sizeof(human_num), 2093 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2094 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2095 human_num); 2096 switch (cai->cai_associativity) { 2097 case 0: 2098 aprint_verbose("disabled"); 2099 break; 2100 case 1: 2101 aprint_verbose("direct-mapped"); 2102 break; 2103 case 0xff: 2104 aprint_verbose("fully associative"); 2105 break; 2106 default: 2107 aprint_verbose("%d-way", cai->cai_associativity); 2108 break; 2109 } 2110 } 2111 return ", "; 2112 } 2113 2114 static void 2115 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2116 { 2117 const char *sep = NULL; 2118 2119 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2120 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2121 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2122 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2123 if (sep != NULL) 2124 aprint_verbose("\n"); 2125 } 2126 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2127 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2128 if (sep != NULL) 2129 aprint_verbose("\n"); 2130 } 2131 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2132 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2133 if (sep != NULL) 2134 aprint_verbose("\n"); 2135 } 2136 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2137 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2138 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2139 if (sep != NULL) 2140 aprint_verbose("\n"); 2141 } 2142 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2143 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2144 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2145 if (sep != NULL) 2146 aprint_verbose("\n"); 2147 } 2148 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2149 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2150 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2151 if (sep != NULL) 2152 aprint_verbose("\n"); 2153 } 2154 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2155 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2156 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2157 if (sep != NULL) 2158 aprint_verbose("\n"); 2159 } 2160 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2161 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2162 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2163 if (sep != NULL) 2164 aprint_verbose("\n"); 2165 } 2166 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2167 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2168 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2169 if (sep != NULL) 2170 aprint_verbose("\n"); 2171 } 2172 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2173 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2174 NULL); 2175 if (sep != NULL) 2176 aprint_verbose("\n"); 2177 } 2178 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2179 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2180 NULL); 2181 if (sep != NULL) 2182 aprint_verbose("\n"); 2183 } 2184 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2185 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2186 NULL); 2187 if (sep != NULL) 2188 aprint_verbose("\n"); 2189 } 2190 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2191 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2192 NULL); 2193 if (sep != NULL) 2194 aprint_verbose("\n"); 2195 } 2196 } 2197 2198 static void 2199 powernow_probe(struct cpu_info *ci) 2200 { 2201 uint32_t regs[4]; 2202 char buf[256]; 2203 2204 x86_cpuid(0x80000007, regs); 2205 2206 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2207 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2208 buf); 2209 } 2210 2211 int 2212 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2213 { 2214 struct cpu_info ci; 2215 int loader_version, res; 2216 struct cpu_ucode_version versreq; 2217 2218 cpu_probe_base_features(&ci, "unknown"); 2219 2220 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2221 loader_version = CPU_UCODE_LOADER_AMD; 2222 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2223 loader_version = CPU_UCODE_LOADER_INTEL1; 2224 else 2225 return -1; 2226 2227 /* check whether the kernel understands this loader version */ 2228 versreq.loader_version = loader_version; 2229 versreq.data = 0; 2230 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2231 if (res) 2232 return -1; 2233 2234 switch (loader_version) { 2235 case CPU_UCODE_LOADER_AMD: 2236 if (uc->cpu_nr != -1) { 2237 /* printf? */ 2238 return -1; 2239 } 2240 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2241 break; 2242 case CPU_UCODE_LOADER_INTEL1: 2243 if (uc->cpu_nr == -1) 2244 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2245 else 2246 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2247 break; 2248 default: /* can't happen */ 2249 return -1; 2250 } 2251 uc->loader_version = loader_version; 2252 return 0; 2253 } 2254
Indexes created Sat Oct 25 00:10:07 GMT 2025