i386.c revision 1.58.2.5.2.1
1 /* $NetBSD: i386.c,v 1.58.2.5.2.1 2017/01/18 08:46:47 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.58.2.5.2.1 2017/01/18 08:46:47 skrll Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] XCR0 bits (d:0 %eax) 108 * [6] xsave flags (d:1 %eax) 109 */ 110 uint32_t ci_cpu_class; /* CPU class */ 111 uint32_t ci_brand_id; /* Intel brand id */ 112 uint32_t ci_vendor[4]; /* vendor string */ 113 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 114 uint64_t ci_tsc_freq; /* cpu cycles/second */ 115 uint8_t ci_packageid; 116 uint8_t ci_coreid; 117 uint8_t ci_smtid; 118 uint32_t ci_initapicid; 119 120 uint32_t ci_cur_xsave; 121 uint32_t ci_max_xsave; 122 123 struct x86_cache_info ci_cinfo[CAI_COUNT]; 124 void (*ci_info)(struct cpu_info *); 125 }; 126 127 struct cpu_nocpuid_nameclass { 128 int cpu_vendor; 129 const char *cpu_vendorname; 130 const char *cpu_name; 131 int cpu_class; 132 void (*cpu_setup)(struct cpu_info *); 133 void (*cpu_cacheinfo)(struct cpu_info *); 134 void (*cpu_info)(struct cpu_info *); 135 }; 136 137 struct cpu_cpuid_nameclass { 138 const char *cpu_id; 139 int cpu_vendor; 140 const char *cpu_vendorname; 141 struct cpu_cpuid_family { 142 int cpu_class; 143 const char *cpu_models[256]; 144 const char *cpu_model_default; 145 void (*cpu_setup)(struct cpu_info *); 146 void (*cpu_probe)(struct cpu_info *); 147 void (*cpu_info)(struct cpu_info *); 148 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 149 }; 150 151 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 152 153 /* 154 * Map Brand ID from cpuid instruction to brand name. 155 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 156 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 157 * Architectures Software Developer's Manual, Volume 2A". 158 */ 159 static const char * const i386_intel_brand[] = { 160 "", /* Unsupported */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Pentium III", /* Intel (R) Pentium (R) III processor */ 163 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "", /* 0x05: Reserved */ 166 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 167 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 170 "Celeron", /* Intel (R) Celeron (TM) processor */ 171 "Xeon", /* Intel (R) Xeon (TM) processor */ 172 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 173 "", /* 0x0d: Reserved */ 174 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 175 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 176 "", /* 0x10: Reserved */ 177 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 178 "Celeron M", /* Intel (R) Celeron (R) M processor */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "Celeron", /* Intel (R) Celeron (R) processor */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Pentium M", /* Intel (R) Pentium (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 }; 185 186 /* 187 * AMD processors don't have Brand IDs, so we need these names for probe. 188 */ 189 static const char * const amd_brand[] = { 190 "", 191 "Duron", /* AMD Duron(tm) */ 192 "MP", /* AMD Athlon(tm) MP */ 193 "XP", /* AMD Athlon(tm) XP */ 194 "4" /* AMD Athlon(tm) 4 */ 195 }; 196 197 static int cpu_vendor; 198 static char cpu_brand_string[49]; 199 static char amd_brand_name[48]; 200 static int use_pae, largepagesize; 201 202 /* Setup functions */ 203 static void disable_tsc(struct cpu_info *); 204 static void amd_family5_setup(struct cpu_info *); 205 static void cyrix6x86_cpu_setup(struct cpu_info *); 206 static void winchip_cpu_setup(struct cpu_info *); 207 /* Brand/Model name functions */ 208 static const char *intel_family6_name(struct cpu_info *); 209 static const char *amd_amd64_name(struct cpu_info *); 210 /* Probe functions */ 211 static void amd_family6_probe(struct cpu_info *); 212 static void powernow_probe(struct cpu_info *); 213 static void intel_family_new_probe(struct cpu_info *); 214 static void via_cpu_probe(struct cpu_info *); 215 /* (Cache) Info functions */ 216 static void intel_cpu_cacheinfo(struct cpu_info *); 217 static void amd_cpu_cacheinfo(struct cpu_info *); 218 static void via_cpu_cacheinfo(struct cpu_info *); 219 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 220 static void transmeta_cpu_info(struct cpu_info *); 221 /* Common functions */ 222 static void cpu_probe_base_features(struct cpu_info *, const char *); 223 static void cpu_probe_hv_features(struct cpu_info *, const char *); 224 static void cpu_probe_features(struct cpu_info *); 225 static void print_bits(const char *, const char *, const char *, uint32_t); 226 static void identifycpu_cpuids(struct cpu_info *); 227 static const struct x86_cache_info *cache_info_lookup( 228 const struct x86_cache_info *, uint8_t); 229 static const char *print_cache_config(struct cpu_info *, int, const char *, 230 const char *); 231 static const char *print_tlb_config(struct cpu_info *, int, const char *, 232 const char *); 233 static void x86_print_cache_and_tlb_info(struct cpu_info *); 234 235 /* 236 * Note: these are just the ones that may not have a cpuid instruction. 237 * We deal with the rest in a different way. 238 */ 239 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 240 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 241 NULL, NULL, NULL }, /* CPU_386SX */ 242 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386 */ 244 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 245 NULL, NULL, NULL }, /* CPU_486SX */ 246 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486 */ 248 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486DLC */ 250 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_6x86 */ 252 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 253 NULL, NULL, NULL }, /* CPU_NX586 */ 254 }; 255 256 const char *classnames[] = { 257 "386", 258 "486", 259 "586", 260 "686" 261 }; 262 263 const char *modifiers[] = { 264 "", 265 "OverDrive", 266 "Dual", 267 "" 268 }; 269 270 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 271 { 272 /* 273 * For Intel processors, check Chapter 35Model-specific 274 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 275 * Software Developer's Manual, Volume 3C". 276 */ 277 "GenuineIntel", 278 CPUVENDOR_INTEL, 279 "Intel", 280 /* Family 4 */ 281 { { 282 CPUCLASS_486, 283 { 284 "486DX", "486DX", "486SX", "486DX2", "486SL", 285 "486SX2", 0, "486DX2 W/B Enhanced", 286 "486DX4", 0, 0, 0, 0, 0, 0, 0, 287 }, 288 "486", /* Default */ 289 NULL, 290 NULL, 291 intel_cpu_cacheinfo, 292 }, 293 /* Family 5 */ 294 { 295 CPUCLASS_586, 296 { 297 "Pentium (P5 A-step)", "Pentium (P5)", 298 "Pentium (P54C)", "Pentium (P24T)", 299 "Pentium/MMX", "Pentium", 0, 300 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 301 "Quark X1000", 0, 0, 0, 0, 0, 0, 302 }, 303 "Pentium", /* Default */ 304 NULL, 305 NULL, 306 intel_cpu_cacheinfo, 307 }, 308 /* Family 6 */ 309 { 310 CPUCLASS_686, 311 { 312 [0x00] = "Pentium Pro (A-step)", 313 [0x01] = "Pentium Pro", 314 [0x03] = "Pentium II (Klamath)", 315 [0x04] = "Pentium Pro", 316 [0x05] = "Pentium II/Celeron (Deschutes)", 317 [0x06] = "Celeron (Mendocino)", 318 [0x07] = "Pentium III (Katmai)", 319 [0x08] = "Pentium III (Coppermine)", 320 [0x09] = "Pentium M (Banias)", 321 [0x0a] = "Pentium III Xeon (Cascades)", 322 [0x0b] = "Pentium III (Tualatin)", 323 [0x0d] = "Pentium M (Dothan)", 324 [0x0e] = "Pentium Core Duo, Core solo", 325 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 326 "Core 2 Quad 6xxx, " 327 "Core 2 Extreme 6xxx, " 328 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 329 "and Pentium DC", 330 [0x15] = "EP80579 Integrated Processor", 331 [0x16] = "Celeron (45nm)", 332 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 333 "Core 2 Quad 8xxx and 9xxx", 334 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 335 "(Nehalem)", 336 [0x1c] = "45nm Atom Family", 337 [0x1d] = "XeonMP 74xx (Nehalem)", 338 [0x1e] = "Core i7 and i5", 339 [0x1f] = "Core i7 and i5", 340 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 341 [0x26] = "Atom Family", 342 [0x27] = "Atom Family", 343 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 344 "i3 2xxx", 345 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 346 [0x2d] = "Xeon E5 Sandy Bridge family, " 347 "Core i7-39xx Extreme", 348 [0x2e] = "Xeon 75xx & 65xx", 349 [0x2f] = "Xeon E7 family", 350 [0x35] = "Atom Family", 351 [0x36] = "Atom S1000", 352 [0x37] = "Atom E3000, Z3[67]00", 353 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 354 "Ivy Bridge", 355 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 356 "(Haswell)", 357 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 358 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 359 "Core i7-49xx Extreme", 360 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 361 "Core i7-59xx Extreme", 362 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 363 "(Haswell)", 364 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 367 [0x4a] = "Atom Z3400", 368 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 369 [0x4d] = "Atom C2000", 370 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 371 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 372 [0x55] = "Future Xeon", 373 [0x56] = "Xeon D-1500 (Broadwell)", 374 [0x57] = "Xeon Phi [357]200", 375 [0x5a] = "Atom E3500", 376 [0x5c] = "Next Atom (Goldmont)", 377 [0x5d] = "Atom X3-C3000 (Silvermont)", 378 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 379 [0x5f] = "Future Atom (Denverton)", 380 [0x85] = "Future Xeon Phi", 381 [0x8e] = "7th gen Core (Kaby Lake)", 382 [0x9e] = "7th gen Core (Kaby Lake)", 383 }, 384 "Pentium Pro, II or III", /* Default */ 385 NULL, 386 intel_family_new_probe, 387 intel_cpu_cacheinfo, 388 }, 389 /* Family > 6 */ 390 { 391 CPUCLASS_686, 392 { 393 0, 0, 0, 0, 0, 0, 0, 0, 394 0, 0, 0, 0, 0, 0, 0, 0, 395 }, 396 "Pentium 4", /* Default */ 397 NULL, 398 intel_family_new_probe, 399 intel_cpu_cacheinfo, 400 } } 401 }, 402 { 403 "AuthenticAMD", 404 CPUVENDOR_AMD, 405 "AMD", 406 /* Family 4 */ 407 { { 408 CPUCLASS_486, 409 { 410 0, 0, 0, "Am486DX2 W/T", 411 0, 0, 0, "Am486DX2 W/B", 412 "Am486DX4 W/T or Am5x86 W/T 150", 413 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 414 0, 0, "Am5x86 W/T 133/160", 415 "Am5x86 W/B 133/160", 416 }, 417 "Am486 or Am5x86", /* Default */ 418 NULL, 419 NULL, 420 NULL, 421 }, 422 /* Family 5 */ 423 { 424 CPUCLASS_586, 425 { 426 "K5", "K5", "K5", "K5", 0, 0, "K6", 427 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 428 "K6-2+/III+", 0, 0, 429 }, 430 "K5 or K6", /* Default */ 431 amd_family5_setup, 432 NULL, 433 amd_cpu_cacheinfo, 434 }, 435 /* Family 6 */ 436 { 437 CPUCLASS_686, 438 { 439 0, "Athlon Model 1", "Athlon Model 2", 440 "Duron", "Athlon Model 4 (Thunderbird)", 441 0, "Athlon", "Duron", "Athlon", 0, 442 "Athlon", 0, 0, 0, 0, 0, 443 }, 444 "K7 (Athlon)", /* Default */ 445 NULL, 446 amd_family6_probe, 447 amd_cpu_cacheinfo, 448 }, 449 /* Family > 6 */ 450 { 451 CPUCLASS_686, 452 { 453 0, 0, 0, 0, 0, 0, 0, 0, 454 0, 0, 0, 0, 0, 0, 0, 0, 455 }, 456 "Unknown K8 (Athlon)", /* Default */ 457 NULL, 458 amd_family6_probe, 459 amd_cpu_cacheinfo, 460 } } 461 }, 462 { 463 "CyrixInstead", 464 CPUVENDOR_CYRIX, 465 "Cyrix", 466 /* Family 4 */ 467 { { 468 CPUCLASS_486, 469 { 470 0, 0, 0, 471 "MediaGX", 472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 473 }, 474 "486", /* Default */ 475 cyrix6x86_cpu_setup, /* XXX ?? */ 476 NULL, 477 NULL, 478 }, 479 /* Family 5 */ 480 { 481 CPUCLASS_586, 482 { 483 0, 0, "6x86", 0, 484 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 486 }, 487 "6x86", /* Default */ 488 cyrix6x86_cpu_setup, 489 NULL, 490 NULL, 491 }, 492 /* Family 6 */ 493 { 494 CPUCLASS_686, 495 { 496 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 497 0, 0, 0, 0, 0, 0, 0, 0, 498 }, 499 "6x86MX", /* Default */ 500 cyrix6x86_cpu_setup, 501 NULL, 502 NULL, 503 }, 504 /* Family > 6 */ 505 { 506 CPUCLASS_686, 507 { 508 0, 0, 0, 0, 0, 0, 0, 0, 509 0, 0, 0, 0, 0, 0, 0, 0, 510 }, 511 "Unknown 6x86MX", /* Default */ 512 NULL, 513 NULL, 514 NULL, 515 } } 516 }, 517 { /* MediaGX is now owned by National Semiconductor */ 518 "Geode by NSC", 519 CPUVENDOR_CYRIX, /* XXX */ 520 "National Semiconductor", 521 /* Family 4, NSC never had any of these */ 522 { { 523 CPUCLASS_486, 524 { 525 0, 0, 0, 0, 0, 0, 0, 0, 526 0, 0, 0, 0, 0, 0, 0, 0, 527 }, 528 "486 compatible", /* Default */ 529 NULL, 530 NULL, 531 NULL, 532 }, 533 /* Family 5: Geode family, formerly MediaGX */ 534 { 535 CPUCLASS_586, 536 { 537 0, 0, 0, 0, 538 "Geode GX1", 539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 540 }, 541 "Geode", /* Default */ 542 cyrix6x86_cpu_setup, 543 NULL, 544 amd_cpu_cacheinfo, 545 }, 546 /* Family 6, not yet available from NSC */ 547 { 548 CPUCLASS_686, 549 { 550 0, 0, 0, 0, 0, 0, 0, 0, 551 0, 0, 0, 0, 0, 0, 0, 0, 552 }, 553 "Pentium Pro compatible", /* Default */ 554 NULL, 555 NULL, 556 NULL, 557 }, 558 /* Family > 6, not yet available from NSC */ 559 { 560 CPUCLASS_686, 561 { 562 0, 0, 0, 0, 0, 0, 0, 0, 563 0, 0, 0, 0, 0, 0, 0, 0, 564 }, 565 "Pentium Pro compatible", /* Default */ 566 NULL, 567 NULL, 568 NULL, 569 } } 570 }, 571 { 572 "CentaurHauls", 573 CPUVENDOR_IDT, 574 "IDT", 575 /* Family 4, IDT never had any of these */ 576 { { 577 CPUCLASS_486, 578 { 579 0, 0, 0, 0, 0, 0, 0, 0, 580 0, 0, 0, 0, 0, 0, 0, 0, 581 }, 582 "486 compatible", /* Default */ 583 NULL, 584 NULL, 585 NULL, 586 }, 587 /* Family 5 */ 588 { 589 CPUCLASS_586, 590 { 591 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 592 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 593 }, 594 "WinChip", /* Default */ 595 winchip_cpu_setup, 596 NULL, 597 NULL, 598 }, 599 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 600 { 601 CPUCLASS_686, 602 { 603 0, 0, 0, 0, 0, 0, "C3 Samuel", 604 "C3 Samuel 2/Ezra", "C3 Ezra-T", 605 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 606 0, "VIA Nano", 607 }, 608 "Unknown VIA/IDT", /* Default */ 609 NULL, 610 via_cpu_probe, 611 via_cpu_cacheinfo, 612 }, 613 /* Family > 6, not yet available from VIA */ 614 { 615 CPUCLASS_686, 616 { 617 0, 0, 0, 0, 0, 0, 0, 0, 618 0, 0, 0, 0, 0, 0, 0, 0, 619 }, 620 "Pentium Pro compatible", /* Default */ 621 NULL, 622 NULL, 623 NULL, 624 } } 625 }, 626 { 627 "GenuineTMx86", 628 CPUVENDOR_TRANSMETA, 629 "Transmeta", 630 /* Family 4, Transmeta never had any of these */ 631 { { 632 CPUCLASS_486, 633 { 634 0, 0, 0, 0, 0, 0, 0, 0, 635 0, 0, 0, 0, 0, 0, 0, 0, 636 }, 637 "486 compatible", /* Default */ 638 NULL, 639 NULL, 640 NULL, 641 }, 642 /* Family 5 */ 643 { 644 CPUCLASS_586, 645 { 646 0, 0, 0, 0, 0, 0, 0, 0, 647 0, 0, 0, 0, 0, 0, 0, 0, 648 }, 649 "Crusoe", /* Default */ 650 NULL, 651 NULL, 652 transmeta_cpu_info, 653 }, 654 /* Family 6, not yet available from Transmeta */ 655 { 656 CPUCLASS_686, 657 { 658 0, 0, 0, 0, 0, 0, 0, 0, 659 0, 0, 0, 0, 0, 0, 0, 0, 660 }, 661 "Pentium Pro compatible", /* Default */ 662 NULL, 663 NULL, 664 NULL, 665 }, 666 /* Family > 6, not yet available from Transmeta */ 667 { 668 CPUCLASS_686, 669 { 670 0, 0, 0, 0, 0, 0, 0, 0, 671 0, 0, 0, 0, 0, 0, 0, 0, 672 }, 673 "Pentium Pro compatible", /* Default */ 674 NULL, 675 NULL, 676 NULL, 677 } } 678 } 679 }; 680 681 /* 682 * disable the TSC such that we don't use the TSC in microtime(9) 683 * because some CPUs got the implementation wrong. 684 */ 685 static void 686 disable_tsc(struct cpu_info *ci) 687 { 688 if (ci->ci_feat_val[0] & CPUID_TSC) { 689 ci->ci_feat_val[0] &= ~CPUID_TSC; 690 aprint_error("WARNING: broken TSC disabled\n"); 691 } 692 } 693 694 static void 695 amd_family5_setup(struct cpu_info *ci) 696 { 697 698 switch (ci->ci_model) { 699 case 0: /* AMD-K5 Model 0 */ 700 /* 701 * According to the AMD Processor Recognition App Note, 702 * the AMD-K5 Model 0 uses the wrong bit to indicate 703 * support for global PTEs, instead using bit 9 (APIC) 704 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 705 */ 706 if (ci->ci_feat_val[0] & CPUID_APIC) 707 ci->ci_feat_val[0] = 708 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 709 /* 710 * XXX But pmap_pg_g is already initialized -- need to kick 711 * XXX the pmap somehow. How does the MP branch do this? 712 */ 713 break; 714 } 715 } 716 717 static void 718 cyrix6x86_cpu_setup(struct cpu_info *ci) 719 { 720 721 /* 722 * Do not disable the TSC on the Geode GX, it's reported to 723 * work fine. 724 */ 725 if (ci->ci_signature != 0x552) 726 disable_tsc(ci); 727 } 728 729 static void 730 winchip_cpu_setup(struct cpu_info *ci) 731 { 732 switch (ci->ci_model) { 733 case 4: /* WinChip C6 */ 734 disable_tsc(ci); 735 } 736 } 737 738 739 static const char * 740 intel_family6_name(struct cpu_info *ci) 741 { 742 const char *ret = NULL; 743 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 744 745 if (ci->ci_model == 5) { 746 switch (l2cache) { 747 case 0: 748 case 128 * 1024: 749 ret = "Celeron (Covington)"; 750 break; 751 case 256 * 1024: 752 ret = "Mobile Pentium II (Dixon)"; 753 break; 754 case 512 * 1024: 755 ret = "Pentium II"; 756 break; 757 case 1 * 1024 * 1024: 758 case 2 * 1024 * 1024: 759 ret = "Pentium II Xeon"; 760 break; 761 } 762 } else if (ci->ci_model == 6) { 763 switch (l2cache) { 764 case 256 * 1024: 765 case 512 * 1024: 766 ret = "Mobile Pentium II"; 767 break; 768 } 769 } else if (ci->ci_model == 7) { 770 switch (l2cache) { 771 case 512 * 1024: 772 ret = "Pentium III"; 773 break; 774 case 1 * 1024 * 1024: 775 case 2 * 1024 * 1024: 776 ret = "Pentium III Xeon"; 777 break; 778 } 779 } else if (ci->ci_model >= 8) { 780 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 781 switch (ci->ci_brand_id) { 782 case 0x3: 783 if (ci->ci_signature == 0x6B1) 784 ret = "Celeron"; 785 break; 786 case 0x8: 787 if (ci->ci_signature >= 0xF13) 788 ret = "genuine processor"; 789 break; 790 case 0xB: 791 if (ci->ci_signature >= 0xF13) 792 ret = "Xeon MP"; 793 break; 794 case 0xE: 795 if (ci->ci_signature < 0xF13) 796 ret = "Xeon"; 797 break; 798 } 799 if (ret == NULL) 800 ret = i386_intel_brand[ci->ci_brand_id]; 801 } 802 } 803 804 return ret; 805 } 806 807 /* 808 * Identify AMD64 CPU names from cpuid. 809 * 810 * Based on: 811 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 812 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 813 * "Revision Guide for AMD NPT Family 0Fh Processors" 814 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 815 * and other miscellaneous reports. 816 * 817 * This is all rather pointless, these are cross 'brand' since the raw 818 * silicon is shared. 819 */ 820 static const char * 821 amd_amd64_name(struct cpu_info *ci) 822 { 823 static char family_str[32]; 824 825 /* Only called if family >= 15 */ 826 827 switch (ci->ci_family) { 828 case 15: 829 switch (ci->ci_model) { 830 case 0x21: /* rev JH-E1/E6 */ 831 case 0x41: /* rev JH-F2 */ 832 return "Dual-Core Opteron"; 833 case 0x23: /* rev JH-E6 (Toledo) */ 834 return "Dual-Core Opteron or Athlon 64 X2"; 835 case 0x43: /* rev JH-F2 (Windsor) */ 836 return "Athlon 64 FX or Athlon 64 X2"; 837 case 0x24: /* rev SH-E5 (Lancaster?) */ 838 return "Mobile Athlon 64 or Turion 64"; 839 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 840 return "Opteron or Athlon 64 FX"; 841 case 0x15: /* rev SH-D0 */ 842 case 0x25: /* rev SH-E4 */ 843 return "Opteron"; 844 case 0x27: /* rev DH-E4, SH-E4 */ 845 return "Athlon 64 or Athlon 64 FX or Opteron"; 846 case 0x48: /* rev BH-F2 */ 847 return "Turion 64 X2"; 848 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 849 case 0x07: /* rev SH-CG (ClawHammer) */ 850 case 0x0b: /* rev CH-CG */ 851 case 0x14: /* rev SH-D0 */ 852 case 0x17: /* rev SH-D0 */ 853 case 0x1b: /* rev CH-D0 */ 854 return "Athlon 64"; 855 case 0x2b: /* rev BH-E4 (Manchester) */ 856 case 0x4b: /* rev BH-F2 (Windsor) */ 857 return "Athlon 64 X2"; 858 case 0x6b: /* rev BH-G1 (Brisbane) */ 859 return "Athlon X2 or Athlon 64 X2"; 860 case 0x08: /* rev CH-CG */ 861 case 0x0c: /* rev DH-CG (Newcastle) */ 862 case 0x0e: /* rev DH-CG (Newcastle?) */ 863 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 864 case 0x18: /* rev CH-D0 */ 865 case 0x1c: /* rev DH-D0 (Winchester) */ 866 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 867 case 0x2c: /* rev DH-E3/E6 */ 868 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 869 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 870 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 871 case 0x6f: /* rev DH-G1 */ 872 return "Athlon 64 or Sempron"; 873 default: 874 break; 875 } 876 return "Unknown AMD64 CPU"; 877 878 #if 0 879 case 16: 880 return "Family 10h"; 881 case 17: 882 return "Family 11h"; 883 case 18: 884 return "Family 12h"; 885 case 19: 886 return "Family 14h"; 887 case 20: 888 return "Family 15h"; 889 #endif 890 891 default: 892 break; 893 } 894 895 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 896 return family_str; 897 } 898 899 static void 900 intel_family_new_probe(struct cpu_info *ci) 901 { 902 uint32_t descs[4]; 903 904 x86_cpuid(0x80000000, descs); 905 906 /* 907 * Determine extended feature flags. 908 */ 909 if (descs[0] >= 0x80000001) { 910 x86_cpuid(0x80000001, descs); 911 ci->ci_feat_val[2] |= descs[3]; 912 ci->ci_feat_val[3] |= descs[2]; 913 } 914 } 915 916 static void 917 via_cpu_probe(struct cpu_info *ci) 918 { 919 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 920 u_int descs[4]; 921 u_int lfunc; 922 923 /* 924 * Determine the largest extended function value. 925 */ 926 x86_cpuid(0x80000000, descs); 927 lfunc = descs[0]; 928 929 /* 930 * Determine the extended feature flags. 931 */ 932 if (lfunc >= 0x80000001) { 933 x86_cpuid(0x80000001, descs); 934 ci->ci_feat_val[2] |= descs[3]; 935 } 936 937 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 938 return; 939 940 /* Nehemiah or Esther */ 941 x86_cpuid(0xc0000000, descs); 942 lfunc = descs[0]; 943 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 944 return; 945 946 x86_cpuid(0xc0000001, descs); 947 lfunc = descs[3]; 948 ci->ci_feat_val[4] = lfunc; 949 } 950 951 static void 952 amd_family6_probe(struct cpu_info *ci) 953 { 954 uint32_t descs[4]; 955 char *p; 956 size_t i; 957 958 x86_cpuid(0x80000000, descs); 959 960 /* 961 * Determine the extended feature flags. 962 */ 963 if (descs[0] >= 0x80000001) { 964 x86_cpuid(0x80000001, descs); 965 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 966 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 967 } 968 969 if (*cpu_brand_string == '\0') 970 return; 971 972 for (i = 1; i < __arraycount(amd_brand); i++) 973 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 974 ci->ci_brand_id = i; 975 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 976 break; 977 } 978 } 979 980 static void 981 intel_cpu_cacheinfo(struct cpu_info *ci) 982 { 983 const struct x86_cache_info *cai; 984 u_int descs[4]; 985 int iterations, i, j; 986 int type, level; 987 int ways, partitions, linesize, sets; 988 int caitype = -1; 989 int totalsize; 990 uint8_t desc; 991 992 /* Return if the cpu is old pre-cpuid instruction cpu */ 993 if (ci->ci_cpu_type >= 0) 994 return; 995 996 if (ci->ci_cpuid_level < 2) 997 return; 998 999 /* 1000 * Parse the cache info from `cpuid leaf 2', if we have it. 1001 * XXX This is kinda ugly, but hey, so is the architecture... 1002 */ 1003 x86_cpuid(2, descs); 1004 iterations = descs[0] & 0xff; 1005 while (iterations-- > 0) { 1006 for (i = 0; i < 4; i++) { 1007 if (descs[i] & 0x80000000) 1008 continue; 1009 for (j = 0; j < 4; j++) { 1010 /* 1011 * The least significant byte in EAX 1012 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1013 * it should be ignored. 1014 */ 1015 if (i == 0 && j == 0) 1016 continue; 1017 desc = (descs[i] >> (j * 8)) & 0xff; 1018 if (desc == 0) 1019 continue; 1020 cai = cache_info_lookup(intel_cpuid_cache_info, 1021 desc); 1022 if (cai != NULL) 1023 ci->ci_cinfo[cai->cai_index] = *cai; 1024 else if ((verbose != 0) && (desc != 0xff)) 1025 printf("Unknown cacheinfo desc %02x\n", 1026 desc); 1027 } 1028 } 1029 x86_cpuid(2, descs); 1030 } 1031 1032 if (ci->ci_cpuid_level < 4) 1033 return; 1034 1035 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1036 for (i = 0; ; i++) { 1037 x86_cpuid2(4, i, descs); 1038 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1039 if (type == CPUID_DCP_CACHETYPE_N) 1040 break; 1041 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1042 switch (level) { 1043 case 1: 1044 if (type == CPUID_DCP_CACHETYPE_I) 1045 caitype = CAI_ICACHE; 1046 else if (type == CPUID_DCP_CACHETYPE_D) 1047 caitype = CAI_DCACHE; 1048 else 1049 caitype = -1; 1050 break; 1051 case 2: 1052 if (type == CPUID_DCP_CACHETYPE_U) 1053 caitype = CAI_L2CACHE; 1054 else 1055 caitype = -1; 1056 break; 1057 case 3: 1058 if (type == CPUID_DCP_CACHETYPE_U) 1059 caitype = CAI_L3CACHE; 1060 else 1061 caitype = -1; 1062 break; 1063 default: 1064 caitype = -1; 1065 break; 1066 } 1067 if (caitype == -1) { 1068 printf("unknown cache level&type (%d & %d)\n", 1069 level, type); 1070 continue; 1071 } 1072 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1073 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1074 + 1; 1075 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1076 + 1; 1077 sets = descs[2] + 1; 1078 totalsize = ways * partitions * linesize * sets; 1079 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1080 ci->ci_cinfo[caitype].cai_associativity = ways; 1081 ci->ci_cinfo[caitype].cai_linesize = linesize; 1082 } 1083 } 1084 1085 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1086 AMD_L2CACHE_INFO; 1087 1088 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1089 AMD_L3CACHE_INFO; 1090 1091 static void 1092 amd_cpu_cacheinfo(struct cpu_info *ci) 1093 { 1094 const struct x86_cache_info *cp; 1095 struct x86_cache_info *cai; 1096 u_int descs[4]; 1097 u_int lfunc; 1098 1099 /* 1100 * K5 model 0 has none of this info. 1101 */ 1102 if (ci->ci_family == 5 && ci->ci_model == 0) 1103 return; 1104 1105 /* 1106 * Determine the largest extended function value. 1107 */ 1108 x86_cpuid(0x80000000, descs); 1109 lfunc = descs[0]; 1110 1111 /* 1112 * Determine L1 cache/TLB info. 1113 */ 1114 if (lfunc < 0x80000005) { 1115 /* No L1 cache info available. */ 1116 return; 1117 } 1118 1119 x86_cpuid(0x80000005, descs); 1120 1121 /* 1122 * K6-III and higher have large page TLBs. 1123 */ 1124 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1125 cai = &ci->ci_cinfo[CAI_ITLB2]; 1126 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1127 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1128 cai->cai_linesize = largepagesize; 1129 1130 cai = &ci->ci_cinfo[CAI_DTLB2]; 1131 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1132 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1133 cai->cai_linesize = largepagesize; 1134 } 1135 1136 cai = &ci->ci_cinfo[CAI_ITLB]; 1137 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1138 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1139 cai->cai_linesize = (4 * 1024); 1140 1141 cai = &ci->ci_cinfo[CAI_DTLB]; 1142 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1143 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1144 cai->cai_linesize = (4 * 1024); 1145 1146 cai = &ci->ci_cinfo[CAI_DCACHE]; 1147 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1148 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1149 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1150 1151 cai = &ci->ci_cinfo[CAI_ICACHE]; 1152 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1153 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1154 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1155 1156 /* 1157 * Determine L2 cache/TLB info. 1158 */ 1159 if (lfunc < 0x80000006) { 1160 /* No L2 cache info available. */ 1161 return; 1162 } 1163 1164 x86_cpuid(0x80000006, descs); 1165 1166 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1167 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1168 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1169 cai->cai_linesize = (4 * 1024); 1170 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1171 cai->cai_associativity); 1172 if (cp != NULL) 1173 cai->cai_associativity = cp->cai_associativity; 1174 else 1175 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1176 1177 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1178 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1179 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1180 cai->cai_linesize = largepagesize; 1181 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1182 cai->cai_associativity); 1183 if (cp != NULL) 1184 cai->cai_associativity = cp->cai_associativity; 1185 else 1186 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1187 1188 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1189 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1190 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1191 cai->cai_linesize = (4 * 1024); 1192 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1193 cai->cai_associativity); 1194 if (cp != NULL) 1195 cai->cai_associativity = cp->cai_associativity; 1196 else 1197 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1198 1199 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1200 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1201 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1202 cai->cai_linesize = largepagesize; 1203 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1204 cai->cai_associativity); 1205 if (cp != NULL) 1206 cai->cai_associativity = cp->cai_associativity; 1207 else 1208 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1209 1210 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1211 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1212 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1213 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1214 1215 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1216 cai->cai_associativity); 1217 if (cp != NULL) 1218 cai->cai_associativity = cp->cai_associativity; 1219 else 1220 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1221 1222 /* 1223 * Determine L3 cache info on AMD Family 10h and newer processors 1224 */ 1225 if (ci->ci_family >= 0x10) { 1226 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1227 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1228 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1229 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1230 1231 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1232 cai->cai_associativity); 1233 if (cp != NULL) 1234 cai->cai_associativity = cp->cai_associativity; 1235 else 1236 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1237 } 1238 1239 /* 1240 * Determine 1GB TLB info. 1241 */ 1242 if (lfunc < 0x80000019) { 1243 /* No 1GB TLB info available. */ 1244 return; 1245 } 1246 1247 x86_cpuid(0x80000019, descs); 1248 1249 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1250 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1251 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1252 cai->cai_linesize = (1024 * 1024 * 1024); 1253 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1254 cai->cai_associativity); 1255 if (cp != NULL) 1256 cai->cai_associativity = cp->cai_associativity; 1257 else 1258 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1259 1260 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1261 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1262 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1263 cai->cai_linesize = (1024 * 1024 * 1024); 1264 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1265 cai->cai_associativity); 1266 if (cp != NULL) 1267 cai->cai_associativity = cp->cai_associativity; 1268 else 1269 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1270 1271 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1272 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1273 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1274 cai->cai_linesize = (1024 * 1024 * 1024); 1275 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1276 cai->cai_associativity); 1277 if (cp != NULL) 1278 cai->cai_associativity = cp->cai_associativity; 1279 else 1280 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1281 1282 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1283 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1284 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1285 cai->cai_linesize = (1024 * 1024 * 1024); 1286 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1287 cai->cai_associativity); 1288 if (cp != NULL) 1289 cai->cai_associativity = cp->cai_associativity; 1290 else 1291 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1292 } 1293 1294 static void 1295 via_cpu_cacheinfo(struct cpu_info *ci) 1296 { 1297 struct x86_cache_info *cai; 1298 int stepping; 1299 u_int descs[4]; 1300 u_int lfunc; 1301 1302 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1303 1304 /* 1305 * Determine the largest extended function value. 1306 */ 1307 x86_cpuid(0x80000000, descs); 1308 lfunc = descs[0]; 1309 1310 /* 1311 * Determine L1 cache/TLB info. 1312 */ 1313 if (lfunc < 0x80000005) { 1314 /* No L1 cache info available. */ 1315 return; 1316 } 1317 1318 x86_cpuid(0x80000005, descs); 1319 1320 cai = &ci->ci_cinfo[CAI_ITLB]; 1321 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1322 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1323 cai->cai_linesize = (4 * 1024); 1324 1325 cai = &ci->ci_cinfo[CAI_DTLB]; 1326 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1327 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1328 cai->cai_linesize = (4 * 1024); 1329 1330 cai = &ci->ci_cinfo[CAI_DCACHE]; 1331 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1332 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1333 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1334 if (ci->ci_model == 9 && stepping == 8) { 1335 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1336 cai->cai_associativity = 2; 1337 } 1338 1339 cai = &ci->ci_cinfo[CAI_ICACHE]; 1340 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1341 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1342 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1343 if (ci->ci_model == 9 && stepping == 8) { 1344 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1345 cai->cai_associativity = 2; 1346 } 1347 1348 /* 1349 * Determine L2 cache/TLB info. 1350 */ 1351 if (lfunc < 0x80000006) { 1352 /* No L2 cache info available. */ 1353 return; 1354 } 1355 1356 x86_cpuid(0x80000006, descs); 1357 1358 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1359 if (ci->ci_model >= 9) { 1360 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1361 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1362 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1363 } else { 1364 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1365 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1366 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1367 } 1368 } 1369 1370 static void 1371 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1372 { 1373 u_int descs[4]; 1374 1375 x86_cpuid(0x80860007, descs); 1376 *frequency = descs[0]; 1377 *voltage = descs[1]; 1378 *percentage = descs[2]; 1379 } 1380 1381 static void 1382 transmeta_cpu_info(struct cpu_info *ci) 1383 { 1384 u_int descs[4], nreg; 1385 u_int frequency, voltage, percentage; 1386 1387 x86_cpuid(0x80860000, descs); 1388 nreg = descs[0]; 1389 if (nreg >= 0x80860001) { 1390 x86_cpuid(0x80860001, descs); 1391 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1392 (descs[1] >> 24) & 0xff, 1393 (descs[1] >> 16) & 0xff, 1394 (descs[1] >> 8) & 0xff, 1395 descs[1] & 0xff); 1396 } 1397 if (nreg >= 0x80860002) { 1398 x86_cpuid(0x80860002, descs); 1399 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1400 (descs[1] >> 24) & 0xff, 1401 (descs[1] >> 16) & 0xff, 1402 (descs[1] >> 8) & 0xff, 1403 descs[1] & 0xff, 1404 descs[2]); 1405 } 1406 if (nreg >= 0x80860006) { 1407 union { 1408 char text[65]; 1409 u_int descs[4][4]; 1410 } info; 1411 int i; 1412 1413 for (i=0; i<4; i++) { 1414 x86_cpuid(0x80860003 + i, info.descs[i]); 1415 } 1416 info.text[64] = '\0'; 1417 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1418 } 1419 1420 if (nreg >= 0x80860007) { 1421 tmx86_get_longrun_status(&frequency, 1422 &voltage, &percentage); 1423 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1424 frequency, voltage, percentage); 1425 } 1426 } 1427 1428 static void 1429 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1430 { 1431 u_int descs[4]; 1432 int i; 1433 uint32_t brand[12]; 1434 1435 memset(ci, 0, sizeof(*ci)); 1436 ci->ci_dev = cpuname; 1437 1438 ci->ci_cpu_type = x86_identify(); 1439 if (ci->ci_cpu_type >= 0) { 1440 /* Old pre-cpuid instruction cpu */ 1441 ci->ci_cpuid_level = -1; 1442 return; 1443 } 1444 1445 /* 1446 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1447 * function. 1448 */ 1449 1450 /* 1451 * Fn0000_0000: 1452 * - Save cpuid max level. 1453 * - Save vendor string. 1454 */ 1455 x86_cpuid(0, descs); 1456 ci->ci_cpuid_level = descs[0]; 1457 /* Save vendor string */ 1458 ci->ci_vendor[0] = descs[1]; 1459 ci->ci_vendor[2] = descs[2]; 1460 ci->ci_vendor[1] = descs[3]; 1461 ci->ci_vendor[3] = 0; 1462 1463 /* 1464 * Fn8000_0000: 1465 * - Get cpuid extended function's max level. 1466 */ 1467 x86_cpuid(0x80000000, descs); 1468 if (descs[0] >= 0x80000000) 1469 ci->ci_cpuid_extlevel = descs[0]; 1470 else { 1471 /* Set lower value than 0x80000000 */ 1472 ci->ci_cpuid_extlevel = 0; 1473 } 1474 1475 /* 1476 * Fn8000_000[2-4]: 1477 * - Save brand string. 1478 */ 1479 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1480 x86_cpuid(0x80000002, brand); 1481 x86_cpuid(0x80000003, brand + 4); 1482 x86_cpuid(0x80000004, brand + 8); 1483 for (i = 0; i < 48; i++) 1484 if (((char *) brand)[i] != ' ') 1485 break; 1486 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1487 } 1488 1489 if (ci->ci_cpuid_level < 1) 1490 return; 1491 1492 /* 1493 * Fn0000_0001: 1494 * - Get CPU family, model and stepping (from eax). 1495 * - Initial local APIC ID and brand ID (from ebx) 1496 * - CPUID2 (from ecx) 1497 * - CPUID (from edx) 1498 */ 1499 x86_cpuid(1, descs); 1500 ci->ci_signature = descs[0]; 1501 1502 /* Extract full family/model values */ 1503 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1504 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1505 1506 /* Brand is low order 8 bits of ebx */ 1507 ci->ci_brand_id = descs[1] & 0xff; 1508 /* Initial local APIC ID */ 1509 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1510 1511 ci->ci_feat_val[1] = descs[2]; 1512 ci->ci_feat_val[0] = descs[3]; 1513 1514 if (ci->ci_cpuid_level < 3) 1515 return; 1516 1517 /* 1518 * If the processor serial number misfeature is present and supported, 1519 * extract it here. 1520 */ 1521 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1522 ci->ci_cpu_serial[0] = ci->ci_signature; 1523 x86_cpuid(3, descs); 1524 ci->ci_cpu_serial[2] = descs[2]; 1525 ci->ci_cpu_serial[1] = descs[3]; 1526 } 1527 1528 if (ci->ci_cpuid_level < 0xd) 1529 return; 1530 1531 /* Get support XCR0 bits */ 1532 x86_cpuid2(0xd, 0, descs); 1533 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1534 ci->ci_cur_xsave = descs[1]; 1535 ci->ci_max_xsave = descs[2]; 1536 1537 /* Additional flags (eg xsaveopt support) */ 1538 x86_cpuid2(0xd, 1, descs); 1539 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1540 } 1541 1542 static void 1543 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1544 { 1545 uint32_t descs[4]; 1546 char hv_sig[13]; 1547 char *p; 1548 const char *hv_name; 1549 int i; 1550 1551 /* 1552 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1553 * http://lkml.org/lkml/2008/10/1/246 1554 * 1555 * KB1009458: Mechanisms to determine if software is running in 1556 * a VMware virtual machine 1557 * http://kb.vmware.com/kb/1009458 1558 */ 1559 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1560 x86_cpuid(0x40000000, descs); 1561 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1562 memcpy(p, &descs[i], sizeof(descs[i])); 1563 *p = '\0'; 1564 /* 1565 * HV vendor ID string 1566 * ------------+-------------- 1567 * KVM "KVMKVMKVM" 1568 * Microsoft "Microsoft Hv" 1569 * VMware "VMwareVMware" 1570 * Xen "XenVMMXenVMM" 1571 */ 1572 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1573 hv_name = "KVM"; 1574 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1575 hv_name = "Hyper-V"; 1576 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1577 hv_name = "VMware"; 1578 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1579 hv_name = "Xen"; 1580 else 1581 hv_name = "unknown"; 1582 1583 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1584 } 1585 } 1586 1587 static void 1588 cpu_probe_features(struct cpu_info *ci) 1589 { 1590 const struct cpu_cpuid_nameclass *cpup = NULL; 1591 unsigned int i; 1592 1593 if (ci->ci_cpuid_level < 1) 1594 return; 1595 1596 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1597 if (!strncmp((char *)ci->ci_vendor, 1598 i386_cpuid_cpus[i].cpu_id, 12)) { 1599 cpup = &i386_cpuid_cpus[i]; 1600 break; 1601 } 1602 } 1603 1604 if (cpup == NULL) 1605 return; 1606 1607 i = ci->ci_family - CPU_MINFAMILY; 1608 1609 if (i >= __arraycount(cpup->cpu_family)) 1610 i = __arraycount(cpup->cpu_family) - 1; 1611 1612 if (cpup->cpu_family[i].cpu_probe == NULL) 1613 return; 1614 1615 (*cpup->cpu_family[i].cpu_probe)(ci); 1616 } 1617 1618 static void 1619 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1620 { 1621 char buf[32 * 16]; 1622 char *bp; 1623 1624 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1625 1626 if (val == 0 || fmt == NULL) 1627 return; 1628 1629 snprintb_m(buf, sizeof(buf), fmt, val, 1630 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1631 bp = buf; 1632 while (*bp != '\0') { 1633 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1634 bp += strlen(bp) + 1; 1635 } 1636 } 1637 1638 static void 1639 identifycpu_cpuids(struct cpu_info *ci) 1640 { 1641 const char *cpuname = ci->ci_dev; 1642 u_int lp_max = 1; /* logical processors per package */ 1643 u_int smt_max; /* smt per core */ 1644 u_int core_max = 1; /* core per package */ 1645 u_int smt_bits, core_bits; 1646 uint32_t descs[4]; 1647 1648 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1649 ci->ci_packageid = ci->ci_initapicid; 1650 ci->ci_coreid = 0; 1651 ci->ci_smtid = 0; 1652 if (cpu_vendor != CPUVENDOR_INTEL) { 1653 return; 1654 } 1655 1656 /* 1657 * 253668.pdf 7.10.2 1658 */ 1659 1660 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1661 x86_cpuid(1, descs); 1662 lp_max = (descs[1] >> 16) & 0xff; 1663 } 1664 if (ci->ci_cpuid_level >= 4) { 1665 x86_cpuid2(4, 0, descs); 1666 core_max = (descs[0] >> 26) + 1; 1667 } 1668 assert(lp_max >= core_max); 1669 smt_max = lp_max / core_max; 1670 smt_bits = ilog2(smt_max - 1) + 1; 1671 core_bits = ilog2(core_max - 1) + 1; 1672 if (smt_bits + core_bits) { 1673 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1674 } 1675 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1676 ci->ci_packageid); 1677 if (core_bits) { 1678 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1679 1680 ci->ci_coreid = 1681 __SHIFTOUT(ci->ci_initapicid, core_mask); 1682 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1683 } 1684 if (smt_bits) { 1685 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1686 1687 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1688 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1689 } 1690 } 1691 1692 void 1693 identifycpu(int fd, const char *cpuname) 1694 { 1695 const char *name = "", *modifier, *vendorname, *brand = ""; 1696 int class = CPUCLASS_386; 1697 unsigned int i; 1698 int modif, family; 1699 const struct cpu_cpuid_nameclass *cpup = NULL; 1700 const struct cpu_cpuid_family *cpufam; 1701 struct cpu_info *ci, cistore; 1702 u_int descs[4]; 1703 size_t sz; 1704 struct cpu_ucode_version ucode; 1705 union { 1706 struct cpu_ucode_version_amd amd; 1707 struct cpu_ucode_version_intel1 intel1; 1708 } ucvers; 1709 1710 ci = &cistore; 1711 cpu_probe_base_features(ci, cpuname); 1712 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1713 ci->ci_cpuid_level); 1714 if (verbose) { 1715 int bf; 1716 1717 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1718 x86_cpuid(bf, descs); 1719 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1720 bf, descs[0], descs[1], descs[2], descs[3]); 1721 } 1722 } 1723 if (ci->ci_cpuid_extlevel >= 0x80000000) 1724 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1725 ci->ci_cpuid_extlevel); 1726 if (verbose) { 1727 unsigned int ef; 1728 1729 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1730 x86_cpuid(ef, descs); 1731 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1732 ef, descs[0], descs[1], descs[2], descs[3]); 1733 } 1734 } 1735 1736 cpu_probe_hv_features(ci, cpuname); 1737 cpu_probe_features(ci); 1738 1739 if (ci->ci_cpu_type >= 0) { 1740 /* Old pre-cpuid instruction cpu */ 1741 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1742 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1743 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1744 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1745 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1746 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1747 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1748 modifier = ""; 1749 } else { 1750 /* CPU which support cpuid instruction */ 1751 modif = (ci->ci_signature >> 12) & 0x3; 1752 family = ci->ci_family; 1753 if (family < CPU_MINFAMILY) 1754 errx(1, "identifycpu: strange family value"); 1755 if (family > CPU_MAXFAMILY) 1756 family = CPU_MAXFAMILY; 1757 1758 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1759 if (!strncmp((char *)ci->ci_vendor, 1760 i386_cpuid_cpus[i].cpu_id, 12)) { 1761 cpup = &i386_cpuid_cpus[i]; 1762 break; 1763 } 1764 } 1765 1766 if (cpup == NULL) { 1767 cpu_vendor = CPUVENDOR_UNKNOWN; 1768 if (ci->ci_vendor[0] != '\0') 1769 vendorname = (char *)&ci->ci_vendor[0]; 1770 else 1771 vendorname = "Unknown"; 1772 class = family - 3; 1773 modifier = ""; 1774 name = ""; 1775 ci->ci_info = NULL; 1776 } else { 1777 cpu_vendor = cpup->cpu_vendor; 1778 vendorname = cpup->cpu_vendorname; 1779 modifier = modifiers[modif]; 1780 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1781 name = cpufam->cpu_models[ci->ci_model]; 1782 if (name == NULL || *name == '\0') 1783 name = cpufam->cpu_model_default; 1784 class = cpufam->cpu_class; 1785 ci->ci_info = cpufam->cpu_info; 1786 1787 if (cpu_vendor == CPUVENDOR_INTEL) { 1788 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1789 const char *tmp; 1790 tmp = intel_family6_name(ci); 1791 if (tmp != NULL) 1792 name = tmp; 1793 } 1794 if (ci->ci_family == 15 && 1795 ci->ci_brand_id < 1796 __arraycount(i386_intel_brand) && 1797 i386_intel_brand[ci->ci_brand_id]) 1798 name = 1799 i386_intel_brand[ci->ci_brand_id]; 1800 } 1801 1802 if (cpu_vendor == CPUVENDOR_AMD) { 1803 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1804 if (ci->ci_brand_id == 1) 1805 /* 1806 * It's Duron. We override the 1807 * name, since it might have 1808 * been misidentified as Athlon. 1809 */ 1810 name = 1811 amd_brand[ci->ci_brand_id]; 1812 else 1813 brand = amd_brand_name; 1814 } 1815 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1816 == 0xf) { 1817 /* Identify AMD64 CPU names. */ 1818 const char *tmp; 1819 tmp = amd_amd64_name(ci); 1820 if (tmp != NULL) 1821 name = tmp; 1822 } 1823 } 1824 1825 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1826 vendorname = "VIA"; 1827 } 1828 } 1829 1830 ci->ci_cpu_class = class; 1831 1832 sz = sizeof(ci->ci_tsc_freq); 1833 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1834 sz = sizeof(use_pae); 1835 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1836 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1837 1838 /* 1839 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1840 * we try to determine from the family/model values. 1841 */ 1842 if (*cpu_brand_string != '\0') 1843 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1844 1845 aprint_normal("%s: %s", cpuname, vendorname); 1846 if (*modifier) 1847 aprint_normal(" %s", modifier); 1848 if (*name) 1849 aprint_normal(" %s", name); 1850 if (*brand) 1851 aprint_normal(" %s", brand); 1852 aprint_normal(" (%s-class)", classnames[class]); 1853 1854 if (ci->ci_tsc_freq != 0) 1855 aprint_normal(", %ju.%02ju MHz", 1856 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1857 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1858 aprint_normal("\n"); 1859 1860 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1861 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1862 if (ci->ci_signature != 0) 1863 aprint_normal(" (id %#x)", ci->ci_signature); 1864 aprint_normal("\n"); 1865 1866 if (ci->ci_info) 1867 (*ci->ci_info)(ci); 1868 1869 /* 1870 * display CPU feature flags 1871 */ 1872 1873 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1874 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1875 1876 /* These next two are actually common definitions! */ 1877 print_bits(cpuname, "features2", 1878 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1879 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1880 print_bits(cpuname, "features3", 1881 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1882 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1883 1884 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1885 ci->ci_feat_val[4]); 1886 1887 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1888 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1889 ci->ci_feat_val[6]); 1890 1891 if (ci->ci_max_xsave != 0) { 1892 aprint_normal("%s: xsave area size: current %d, maximum %d", 1893 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1894 aprint_normal(", xgetbv %sabled\n", 1895 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1896 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1897 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1898 x86_xgetbv()); 1899 } 1900 1901 x86_print_cache_and_tlb_info(ci); 1902 1903 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1904 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1905 cpuname, 1906 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1907 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1908 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1909 } 1910 1911 if (ci->ci_cpu_class == CPUCLASS_386) { 1912 errx(1, "NetBSD requires an 80486 or later processor"); 1913 } 1914 1915 if (ci->ci_cpu_type == CPU_486DLC) { 1916 #ifndef CYRIX_CACHE_WORKS 1917 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1918 #else 1919 #ifndef CYRIX_CACHE_REALLY_WORKS 1920 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1921 #else 1922 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1923 #endif 1924 #endif 1925 } 1926 1927 /* 1928 * Everything past this point requires a Pentium or later. 1929 */ 1930 if (ci->ci_cpuid_level < 0) 1931 return; 1932 1933 identifycpu_cpuids(ci); 1934 1935 #ifdef INTEL_CORETEMP 1936 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1937 coretemp_register(ci); 1938 #endif 1939 1940 if (cpu_vendor == CPUVENDOR_AMD) { 1941 uint32_t data[4]; 1942 1943 x86_cpuid(0x80000000, data); 1944 if (data[0] >= 0x80000007) 1945 powernow_probe(ci); 1946 1947 if ((data[0] >= 0x8000000a) 1948 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1949 x86_cpuid(0x8000000a, data); 1950 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1951 data[0] & 0xf); 1952 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1953 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1954 data[3]); 1955 } 1956 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1957 uint32_t data[4]; 1958 int32_t bi_index; 1959 1960 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1961 x86_cpuid(bi_index, data); 1962 switch (bi_index) { 1963 case 6: 1964 print_bits(cpuname, "DSPM-eax", 1965 CPUID_DSPM_FLAGS, data[0]); 1966 print_bits(cpuname, "DSPM-ecx", 1967 CPUID_DSPM_FLAGS1, data[2]); 1968 break; 1969 case 7: 1970 aprint_verbose("%s: SEF highest subleaf %08x\n", 1971 cpuname, data[0]); 1972 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1973 data[1]); 1974 break; 1975 #if 0 1976 default: 1977 aprint_verbose("%s: basic %08x-eax %08x\n", 1978 cpuname, bi_index, data[0]); 1979 aprint_verbose("%s: basic %08x-ebx %08x\n", 1980 cpuname, bi_index, data[1]); 1981 aprint_verbose("%s: basic %08x-ecx %08x\n", 1982 cpuname, bi_index, data[2]); 1983 aprint_verbose("%s: basic %08x-edx %08x\n", 1984 cpuname, bi_index, data[3]); 1985 break; 1986 #endif 1987 } 1988 } 1989 } 1990 1991 #ifdef INTEL_ONDEMAND_CLOCKMOD 1992 clockmod_init(); 1993 #endif 1994 1995 if (cpu_vendor == CPUVENDOR_AMD) 1996 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1997 else if (cpu_vendor == CPUVENDOR_INTEL) 1998 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1999 else 2000 return; 2001 2002 ucode.data = &ucvers; 2003 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2004 #ifdef __i386__ 2005 struct cpu_ucode_version_64 ucode_64; 2006 if (errno != ENOTTY) 2007 return; 2008 /* Try the 64 bit ioctl */ 2009 memset(&ucode_64, 0, sizeof ucode_64); 2010 ucode_64.data = &ucvers; 2011 ucode_64.loader_version = ucode.loader_version; 2012 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2013 return; 2014 #else 2015 return; 2016 #endif 2017 } 2018 2019 if (cpu_vendor == CPUVENDOR_AMD) 2020 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2021 else if (cpu_vendor == CPUVENDOR_INTEL) 2022 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2023 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2024 } 2025 2026 static const struct x86_cache_info * 2027 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2028 { 2029 int i; 2030 2031 for (i = 0; cai[i].cai_desc != 0; i++) { 2032 if (cai[i].cai_desc == desc) 2033 return (&cai[i]); 2034 } 2035 2036 return (NULL); 2037 } 2038 2039 static const char * 2040 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2041 const char *sep) 2042 { 2043 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2044 char human_num[HUMAN_BUFSIZE]; 2045 2046 if (cai->cai_totalsize == 0) 2047 return sep; 2048 2049 if (sep == NULL) 2050 aprint_verbose_dev(ci->ci_dev, ""); 2051 else 2052 aprint_verbose("%s", sep); 2053 if (name != NULL) 2054 aprint_verbose("%s ", name); 2055 2056 if (cai->cai_string != NULL) { 2057 aprint_verbose("%s ", cai->cai_string); 2058 } else { 2059 (void)humanize_number(human_num, sizeof(human_num), 2060 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2061 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2062 } 2063 switch (cai->cai_associativity) { 2064 case 0: 2065 aprint_verbose("disabled"); 2066 break; 2067 case 1: 2068 aprint_verbose("direct-mapped"); 2069 break; 2070 case 0xff: 2071 aprint_verbose("fully associative"); 2072 break; 2073 default: 2074 aprint_verbose("%d-way", cai->cai_associativity); 2075 break; 2076 } 2077 return ", "; 2078 } 2079 2080 static const char * 2081 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2082 const char *sep) 2083 { 2084 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2085 char human_num[HUMAN_BUFSIZE]; 2086 2087 if (cai->cai_totalsize == 0) 2088 return sep; 2089 2090 if (sep == NULL) 2091 aprint_verbose_dev(ci->ci_dev, ""); 2092 else 2093 aprint_verbose("%s", sep); 2094 if (name != NULL) 2095 aprint_verbose("%s ", name); 2096 2097 if (cai->cai_string != NULL) { 2098 aprint_verbose("%s", cai->cai_string); 2099 } else { 2100 (void)humanize_number(human_num, sizeof(human_num), 2101 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2102 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2103 human_num); 2104 switch (cai->cai_associativity) { 2105 case 0: 2106 aprint_verbose("disabled"); 2107 break; 2108 case 1: 2109 aprint_verbose("direct-mapped"); 2110 break; 2111 case 0xff: 2112 aprint_verbose("fully associative"); 2113 break; 2114 default: 2115 aprint_verbose("%d-way", cai->cai_associativity); 2116 break; 2117 } 2118 } 2119 return ", "; 2120 } 2121 2122 static void 2123 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2124 { 2125 const char *sep = NULL; 2126 2127 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2128 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2129 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2130 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2131 if (sep != NULL) 2132 aprint_verbose("\n"); 2133 } 2134 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2135 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2136 if (sep != NULL) 2137 aprint_verbose("\n"); 2138 } 2139 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2140 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2141 if (sep != NULL) 2142 aprint_verbose("\n"); 2143 } 2144 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2145 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2146 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2147 if (sep != NULL) 2148 aprint_verbose("\n"); 2149 } 2150 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2151 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2152 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2153 if (sep != NULL) 2154 aprint_verbose("\n"); 2155 } 2156 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2157 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2158 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2159 if (sep != NULL) 2160 aprint_verbose("\n"); 2161 } 2162 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2163 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2164 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2165 if (sep != NULL) 2166 aprint_verbose("\n"); 2167 } 2168 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2169 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2170 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2171 if (sep != NULL) 2172 aprint_verbose("\n"); 2173 } 2174 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2175 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2176 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2177 if (sep != NULL) 2178 aprint_verbose("\n"); 2179 } 2180 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2181 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2182 NULL); 2183 if (sep != NULL) 2184 aprint_verbose("\n"); 2185 } 2186 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2187 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2188 NULL); 2189 if (sep != NULL) 2190 aprint_verbose("\n"); 2191 } 2192 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2193 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2194 NULL); 2195 if (sep != NULL) 2196 aprint_verbose("\n"); 2197 } 2198 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2199 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2200 NULL); 2201 if (sep != NULL) 2202 aprint_verbose("\n"); 2203 } 2204 } 2205 2206 static void 2207 powernow_probe(struct cpu_info *ci) 2208 { 2209 uint32_t regs[4]; 2210 char buf[256]; 2211 2212 x86_cpuid(0x80000007, regs); 2213 2214 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2215 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2216 buf); 2217 } 2218 2219 int 2220 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2221 { 2222 struct cpu_info ci; 2223 int loader_version, res; 2224 struct cpu_ucode_version versreq; 2225 2226 cpu_probe_base_features(&ci, "unknown"); 2227 2228 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2229 loader_version = CPU_UCODE_LOADER_AMD; 2230 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2231 loader_version = CPU_UCODE_LOADER_INTEL1; 2232 else 2233 return -1; 2234 2235 /* check whether the kernel understands this loader version */ 2236 versreq.loader_version = loader_version; 2237 versreq.data = 0; 2238 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2239 if (res) 2240 return -1; 2241 2242 switch (loader_version) { 2243 case CPU_UCODE_LOADER_AMD: 2244 if (uc->cpu_nr != -1) { 2245 /* printf? */ 2246 return -1; 2247 } 2248 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2249 break; 2250 case CPU_UCODE_LOADER_INTEL1: 2251 if (uc->cpu_nr == -1) 2252 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2253 else 2254 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2255 break; 2256 default: /* can't happen */ 2257 return -1; 2258 } 2259 uc->loader_version = loader_version; 2260 return 0; 2261 } 2262
Indexes created Sat Oct 25 10:09:55 GMT 2025