i386.c revision 1.59
1 /* $NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.59 2014/09/09 15:14:39 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] XCR0 bits (d:0 %eax) 108 * [6] xsave flags (d:1 %eax) 109 */ 110 uint32_t ci_cpu_class; /* CPU class */ 111 uint32_t ci_brand_id; /* Intel brand id */ 112 uint32_t ci_vendor[4]; /* vendor string */ 113 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 114 uint64_t ci_tsc_freq; /* cpu cycles/second */ 115 uint8_t ci_packageid; 116 uint8_t ci_coreid; 117 uint8_t ci_smtid; 118 uint32_t ci_initapicid; 119 120 uint32_t ci_cur_xsave; 121 uint32_t ci_max_xsave; 122 123 struct x86_cache_info ci_cinfo[CAI_COUNT]; 124 void (*ci_info)(struct cpu_info *); 125 }; 126 127 struct cpu_nocpuid_nameclass { 128 int cpu_vendor; 129 const char *cpu_vendorname; 130 const char *cpu_name; 131 int cpu_class; 132 void (*cpu_setup)(struct cpu_info *); 133 void (*cpu_cacheinfo)(struct cpu_info *); 134 void (*cpu_info)(struct cpu_info *); 135 }; 136 137 struct cpu_cpuid_nameclass { 138 const char *cpu_id; 139 int cpu_vendor; 140 const char *cpu_vendorname; 141 struct cpu_cpuid_family { 142 int cpu_class; 143 const char *cpu_models[256]; 144 const char *cpu_model_default; 145 void (*cpu_setup)(struct cpu_info *); 146 void (*cpu_probe)(struct cpu_info *); 147 void (*cpu_info)(struct cpu_info *); 148 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 149 }; 150 151 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 152 153 /* 154 * Map Brand ID from cpuid instruction to brand name. 155 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 156 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 157 * Architectures Software Developer's Manual, Volume 2A". 158 */ 159 static const char * const i386_intel_brand[] = { 160 "", /* Unsupported */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Pentium III", /* Intel (R) Pentium (R) III processor */ 163 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "", /* 0x05: Reserved */ 166 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 167 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 170 "Celeron", /* Intel (R) Celeron (TM) processor */ 171 "Xeon", /* Intel (R) Xeon (TM) processor */ 172 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 173 "", /* 0x0d: Reserved */ 174 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 175 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 176 "", /* 0x10: Reserved */ 177 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 178 "Celeron M", /* Intel (R) Celeron (R) M processor */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "Celeron", /* Intel (R) Celeron (R) processor */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Pentium M", /* Intel (R) Pentium (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 }; 185 186 /* 187 * AMD processors don't have Brand IDs, so we need these names for probe. 188 */ 189 static const char * const amd_brand[] = { 190 "", 191 "Duron", /* AMD Duron(tm) */ 192 "MP", /* AMD Athlon(tm) MP */ 193 "XP", /* AMD Athlon(tm) XP */ 194 "4" /* AMD Athlon(tm) 4 */ 195 }; 196 197 static int cpu_vendor; 198 static char cpu_brand_string[49]; 199 static char amd_brand_name[48]; 200 static int use_pae, largepagesize; 201 202 /* Setup functions */ 203 static void disable_tsc(struct cpu_info *); 204 static void amd_family5_setup(struct cpu_info *); 205 static void cyrix6x86_cpu_setup(struct cpu_info *); 206 static void winchip_cpu_setup(struct cpu_info *); 207 /* Brand/Model name functions */ 208 static const char *intel_family6_name(struct cpu_info *); 209 static const char *amd_amd64_name(struct cpu_info *); 210 /* Probe functions */ 211 static void amd_family6_probe(struct cpu_info *); 212 static void powernow_probe(struct cpu_info *); 213 static void intel_family_new_probe(struct cpu_info *); 214 static void via_cpu_probe(struct cpu_info *); 215 /* (Cache) Info functions */ 216 static void intel_cpu_cacheinfo(struct cpu_info *); 217 static void amd_cpu_cacheinfo(struct cpu_info *); 218 static void via_cpu_cacheinfo(struct cpu_info *); 219 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 220 static void transmeta_cpu_info(struct cpu_info *); 221 /* Common functions */ 222 static void cpu_probe_base_features(struct cpu_info *, const char *); 223 static void cpu_probe_features(struct cpu_info *); 224 static void print_bits(const char *, const char *, const char *, uint32_t); 225 static void identifycpu_cpuids(struct cpu_info *); 226 static const struct x86_cache_info *cache_info_lookup( 227 const struct x86_cache_info *, uint8_t); 228 static const char *print_cache_config(struct cpu_info *, int, const char *, 229 const char *); 230 static const char *print_tlb_config(struct cpu_info *, int, const char *, 231 const char *); 232 static void x86_print_cache_and_tlb_info(struct cpu_info *); 233 234 /* 235 * Note: these are just the ones that may not have a cpuid instruction. 236 * We deal with the rest in a different way. 237 */ 238 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 239 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 240 NULL, NULL, NULL }, /* CPU_386SX */ 241 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 242 NULL, NULL, NULL }, /* CPU_386 */ 243 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 244 NULL, NULL, NULL }, /* CPU_486SX */ 245 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 246 NULL, NULL, NULL }, /* CPU_486 */ 247 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486DLC */ 249 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_6x86 */ 251 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 252 NULL, NULL, NULL }, /* CPU_NX586 */ 253 }; 254 255 const char *classnames[] = { 256 "386", 257 "486", 258 "586", 259 "686" 260 }; 261 262 const char *modifiers[] = { 263 "", 264 "OverDrive", 265 "Dual", 266 "" 267 }; 268 269 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 270 { 271 /* 272 * For Intel processors, check Chapter 35Model-specific 273 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 274 * Software Developer's Manual, Volume 3C". 275 */ 276 "GenuineIntel", 277 CPUVENDOR_INTEL, 278 "Intel", 279 /* Family 4 */ 280 { { 281 CPUCLASS_486, 282 { 283 "486DX", "486DX", "486SX", "486DX2", "486SL", 284 "486SX2", 0, "486DX2 W/B Enhanced", 285 "486DX4", 0, 0, 0, 0, 0, 0, 0, 286 }, 287 "486", /* Default */ 288 NULL, 289 NULL, 290 intel_cpu_cacheinfo, 291 }, 292 /* Family 5 */ 293 { 294 CPUCLASS_586, 295 { 296 "Pentium (P5 A-step)", "Pentium (P5)", 297 "Pentium (P54C)", "Pentium (P24T)", 298 "Pentium/MMX", "Pentium", 0, 299 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 300 0, 0, 0, 0, 0, 0, 0, 301 }, 302 "Pentium", /* Default */ 303 NULL, 304 NULL, 305 intel_cpu_cacheinfo, 306 }, 307 /* Family 6 */ 308 { 309 CPUCLASS_686, 310 { 311 [0x00] = "Pentium Pro (A-step)", 312 [0x01] = "Pentium Pro", 313 [0x03] = "Pentium II (Klamath)", 314 [0x04] = "Pentium Pro", 315 [0x05] = "Pentium II/Celeron (Deschutes)", 316 [0x06] = "Celeron (Mendocino)", 317 [0x07] = "Pentium III (Katmai)", 318 [0x08] = "Pentium III (Coppermine)", 319 [0x09] = "Pentium M (Banias)", 320 [0x0a] = "Pentium III Xeon (Cascades)", 321 [0x0b] = "Pentium III (Tualatin)", 322 [0x0d] = "Pentium M (Dothan)", 323 [0x0e] = "Pentium Core Duo, Core solo", 324 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 325 "Core 2 Quad 6xxx, " 326 "Core 2 Extreme 6xxx, " 327 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 328 "and Pentium DC", 329 [0x15] = "EP80579 Integrated Processor", 330 [0x16] = "Celeron (45nm)", 331 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 332 "Core 2 Quad 8xxx and 9xxx", 333 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 334 "(Nehalem)", 335 [0x1c] = "Atom Family", 336 [0x1d] = "XeonMP 74xx (Nehalem)", 337 [0x1e] = "Core i7 and i5", 338 [0x1f] = "Core i7 and i5", 339 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 340 [0x26] = "Atom Family", 341 [0x27] = "Atom Family", 342 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 343 "i3 2xxx", 344 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 345 [0x2d] = "Xeon E5 Sandy Bridge family, " 346 "Core i7-39xx Extreme", 347 [0x2e] = "Xeon 75xx & 65xx", 348 [0x2f] = "Xeon E7 family", 349 [0x35] = "Atom Family", 350 [0x36] = "Atom S1000", 351 [0x37] = "Atom E3000, Z3000", 352 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 353 "Ivy Bridge", 354 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 355 "(Haswell)", 356 [0x3d] = "Core M-5xxx (Broadwell)", 357 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 358 "Core i7-49xx Extreme", 359 [0x3f] = "Xeon E5-2600/1600 v3 (Haswell-E), " 360 "Core i7-59xx Extreme", 361 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 362 "(Haswell)", 363 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 364 "(Haswell)", 365 [0x4a] = "Future Atom E3000, Z3000", 366 [0x4d] = "Atom C2000", 367 [0x4e] = "Future Core", 368 [0x56] = "Future Xeon", 369 [0x5a] = "Future Atom E3000, Z3000", 370 [0x5d] = "Future Atom E3000, Z3000", 371 }, 372 "Pentium Pro, II or III", /* Default */ 373 NULL, 374 intel_family_new_probe, 375 intel_cpu_cacheinfo, 376 }, 377 /* Family > 6 */ 378 { 379 CPUCLASS_686, 380 { 381 0, 0, 0, 0, 0, 0, 0, 0, 382 0, 0, 0, 0, 0, 0, 0, 0, 383 }, 384 "Pentium 4", /* Default */ 385 NULL, 386 intel_family_new_probe, 387 intel_cpu_cacheinfo, 388 } } 389 }, 390 { 391 "AuthenticAMD", 392 CPUVENDOR_AMD, 393 "AMD", 394 /* Family 4 */ 395 { { 396 CPUCLASS_486, 397 { 398 0, 0, 0, "Am486DX2 W/T", 399 0, 0, 0, "Am486DX2 W/B", 400 "Am486DX4 W/T or Am5x86 W/T 150", 401 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 402 0, 0, "Am5x86 W/T 133/160", 403 "Am5x86 W/B 133/160", 404 }, 405 "Am486 or Am5x86", /* Default */ 406 NULL, 407 NULL, 408 NULL, 409 }, 410 /* Family 5 */ 411 { 412 CPUCLASS_586, 413 { 414 "K5", "K5", "K5", "K5", 0, 0, "K6", 415 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 416 "K6-2+/III+", 0, 0, 417 }, 418 "K5 or K6", /* Default */ 419 amd_family5_setup, 420 NULL, 421 amd_cpu_cacheinfo, 422 }, 423 /* Family 6 */ 424 { 425 CPUCLASS_686, 426 { 427 0, "Athlon Model 1", "Athlon Model 2", 428 "Duron", "Athlon Model 4 (Thunderbird)", 429 0, "Athlon", "Duron", "Athlon", 0, 430 "Athlon", 0, 0, 0, 0, 0, 431 }, 432 "K7 (Athlon)", /* Default */ 433 NULL, 434 amd_family6_probe, 435 amd_cpu_cacheinfo, 436 }, 437 /* Family > 6 */ 438 { 439 CPUCLASS_686, 440 { 441 0, 0, 0, 0, 0, 0, 0, 0, 442 0, 0, 0, 0, 0, 0, 0, 0, 443 }, 444 "Unknown K8 (Athlon)", /* Default */ 445 NULL, 446 amd_family6_probe, 447 amd_cpu_cacheinfo, 448 } } 449 }, 450 { 451 "CyrixInstead", 452 CPUVENDOR_CYRIX, 453 "Cyrix", 454 /* Family 4 */ 455 { { 456 CPUCLASS_486, 457 { 458 0, 0, 0, 459 "MediaGX", 460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 461 }, 462 "486", /* Default */ 463 cyrix6x86_cpu_setup, /* XXX ?? */ 464 NULL, 465 NULL, 466 }, 467 /* Family 5 */ 468 { 469 CPUCLASS_586, 470 { 471 0, 0, "6x86", 0, 472 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 474 }, 475 "6x86", /* Default */ 476 cyrix6x86_cpu_setup, 477 NULL, 478 NULL, 479 }, 480 /* Family 6 */ 481 { 482 CPUCLASS_686, 483 { 484 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 485 0, 0, 0, 0, 0, 0, 0, 0, 486 }, 487 "6x86MX", /* Default */ 488 cyrix6x86_cpu_setup, 489 NULL, 490 NULL, 491 }, 492 /* Family > 6 */ 493 { 494 CPUCLASS_686, 495 { 496 0, 0, 0, 0, 0, 0, 0, 0, 497 0, 0, 0, 0, 0, 0, 0, 0, 498 }, 499 "Unknown 6x86MX", /* Default */ 500 NULL, 501 NULL, 502 NULL, 503 } } 504 }, 505 { /* MediaGX is now owned by National Semiconductor */ 506 "Geode by NSC", 507 CPUVENDOR_CYRIX, /* XXX */ 508 "National Semiconductor", 509 /* Family 4, NSC never had any of these */ 510 { { 511 CPUCLASS_486, 512 { 513 0, 0, 0, 0, 0, 0, 0, 0, 514 0, 0, 0, 0, 0, 0, 0, 0, 515 }, 516 "486 compatible", /* Default */ 517 NULL, 518 NULL, 519 NULL, 520 }, 521 /* Family 5: Geode family, formerly MediaGX */ 522 { 523 CPUCLASS_586, 524 { 525 0, 0, 0, 0, 526 "Geode GX1", 527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 528 }, 529 "Geode", /* Default */ 530 cyrix6x86_cpu_setup, 531 NULL, 532 amd_cpu_cacheinfo, 533 }, 534 /* Family 6, not yet available from NSC */ 535 { 536 CPUCLASS_686, 537 { 538 0, 0, 0, 0, 0, 0, 0, 0, 539 0, 0, 0, 0, 0, 0, 0, 0, 540 }, 541 "Pentium Pro compatible", /* Default */ 542 NULL, 543 NULL, 544 NULL, 545 }, 546 /* Family > 6, not yet available from NSC */ 547 { 548 CPUCLASS_686, 549 { 550 0, 0, 0, 0, 0, 0, 0, 0, 551 0, 0, 0, 0, 0, 0, 0, 0, 552 }, 553 "Pentium Pro compatible", /* Default */ 554 NULL, 555 NULL, 556 NULL, 557 } } 558 }, 559 { 560 "CentaurHauls", 561 CPUVENDOR_IDT, 562 "IDT", 563 /* Family 4, IDT never had any of these */ 564 { { 565 CPUCLASS_486, 566 { 567 0, 0, 0, 0, 0, 0, 0, 0, 568 0, 0, 0, 0, 0, 0, 0, 0, 569 }, 570 "486 compatible", /* Default */ 571 NULL, 572 NULL, 573 NULL, 574 }, 575 /* Family 5 */ 576 { 577 CPUCLASS_586, 578 { 579 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 580 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 581 }, 582 "WinChip", /* Default */ 583 winchip_cpu_setup, 584 NULL, 585 NULL, 586 }, 587 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 588 { 589 CPUCLASS_686, 590 { 591 0, 0, 0, 0, 0, 0, "C3 Samuel", 592 "C3 Samuel 2/Ezra", "C3 Ezra-T", 593 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 594 0, "VIA Nano", 595 }, 596 "Unknown VIA/IDT", /* Default */ 597 NULL, 598 via_cpu_probe, 599 via_cpu_cacheinfo, 600 }, 601 /* Family > 6, not yet available from VIA */ 602 { 603 CPUCLASS_686, 604 { 605 0, 0, 0, 0, 0, 0, 0, 0, 606 0, 0, 0, 0, 0, 0, 0, 0, 607 }, 608 "Pentium Pro compatible", /* Default */ 609 NULL, 610 NULL, 611 NULL, 612 } } 613 }, 614 { 615 "GenuineTMx86", 616 CPUVENDOR_TRANSMETA, 617 "Transmeta", 618 /* Family 4, Transmeta never had any of these */ 619 { { 620 CPUCLASS_486, 621 { 622 0, 0, 0, 0, 0, 0, 0, 0, 623 0, 0, 0, 0, 0, 0, 0, 0, 624 }, 625 "486 compatible", /* Default */ 626 NULL, 627 NULL, 628 NULL, 629 }, 630 /* Family 5 */ 631 { 632 CPUCLASS_586, 633 { 634 0, 0, 0, 0, 0, 0, 0, 0, 635 0, 0, 0, 0, 0, 0, 0, 0, 636 }, 637 "Crusoe", /* Default */ 638 NULL, 639 NULL, 640 transmeta_cpu_info, 641 }, 642 /* Family 6, not yet available from Transmeta */ 643 { 644 CPUCLASS_686, 645 { 646 0, 0, 0, 0, 0, 0, 0, 0, 647 0, 0, 0, 0, 0, 0, 0, 0, 648 }, 649 "Pentium Pro compatible", /* Default */ 650 NULL, 651 NULL, 652 NULL, 653 }, 654 /* Family > 6, not yet available from Transmeta */ 655 { 656 CPUCLASS_686, 657 { 658 0, 0, 0, 0, 0, 0, 0, 0, 659 0, 0, 0, 0, 0, 0, 0, 0, 660 }, 661 "Pentium Pro compatible", /* Default */ 662 NULL, 663 NULL, 664 NULL, 665 } } 666 } 667 }; 668 669 /* 670 * disable the TSC such that we don't use the TSC in microtime(9) 671 * because some CPUs got the implementation wrong. 672 */ 673 static void 674 disable_tsc(struct cpu_info *ci) 675 { 676 if (ci->ci_feat_val[0] & CPUID_TSC) { 677 ci->ci_feat_val[0] &= ~CPUID_TSC; 678 aprint_error("WARNING: broken TSC disabled\n"); 679 } 680 } 681 682 static void 683 amd_family5_setup(struct cpu_info *ci) 684 { 685 686 switch (ci->ci_model) { 687 case 0: /* AMD-K5 Model 0 */ 688 /* 689 * According to the AMD Processor Recognition App Note, 690 * the AMD-K5 Model 0 uses the wrong bit to indicate 691 * support for global PTEs, instead using bit 9 (APIC) 692 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 693 */ 694 if (ci->ci_feat_val[0] & CPUID_APIC) 695 ci->ci_feat_val[0] = 696 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 697 /* 698 * XXX But pmap_pg_g is already initialized -- need to kick 699 * XXX the pmap somehow. How does the MP branch do this? 700 */ 701 break; 702 } 703 } 704 705 static void 706 cyrix6x86_cpu_setup(struct cpu_info *ci) 707 { 708 709 /* 710 * Do not disable the TSC on the Geode GX, it's reported to 711 * work fine. 712 */ 713 if (ci->ci_signature != 0x552) 714 disable_tsc(ci); 715 } 716 717 static void 718 winchip_cpu_setup(struct cpu_info *ci) 719 { 720 switch (ci->ci_model) { 721 case 4: /* WinChip C6 */ 722 disable_tsc(ci); 723 } 724 } 725 726 727 static const char * 728 intel_family6_name(struct cpu_info *ci) 729 { 730 const char *ret = NULL; 731 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 732 733 if (ci->ci_model == 5) { 734 switch (l2cache) { 735 case 0: 736 case 128 * 1024: 737 ret = "Celeron (Covington)"; 738 break; 739 case 256 * 1024: 740 ret = "Mobile Pentium II (Dixon)"; 741 break; 742 case 512 * 1024: 743 ret = "Pentium II"; 744 break; 745 case 1 * 1024 * 1024: 746 case 2 * 1024 * 1024: 747 ret = "Pentium II Xeon"; 748 break; 749 } 750 } else if (ci->ci_model == 6) { 751 switch (l2cache) { 752 case 256 * 1024: 753 case 512 * 1024: 754 ret = "Mobile Pentium II"; 755 break; 756 } 757 } else if (ci->ci_model == 7) { 758 switch (l2cache) { 759 case 512 * 1024: 760 ret = "Pentium III"; 761 break; 762 case 1 * 1024 * 1024: 763 case 2 * 1024 * 1024: 764 ret = "Pentium III Xeon"; 765 break; 766 } 767 } else if (ci->ci_model >= 8) { 768 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 769 switch (ci->ci_brand_id) { 770 case 0x3: 771 if (ci->ci_signature == 0x6B1) 772 ret = "Celeron"; 773 break; 774 case 0x8: 775 if (ci->ci_signature >= 0xF13) 776 ret = "genuine processor"; 777 break; 778 case 0xB: 779 if (ci->ci_signature >= 0xF13) 780 ret = "Xeon MP"; 781 break; 782 case 0xE: 783 if (ci->ci_signature < 0xF13) 784 ret = "Xeon"; 785 break; 786 } 787 if (ret == NULL) 788 ret = i386_intel_brand[ci->ci_brand_id]; 789 } 790 } 791 792 return ret; 793 } 794 795 /* 796 * Identify AMD64 CPU names from cpuid. 797 * 798 * Based on: 799 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 800 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 801 * "Revision Guide for AMD NPT Family 0Fh Processors" 802 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 803 * and other miscellaneous reports. 804 * 805 * This is all rather pointless, these are cross 'brand' since the raw 806 * silicon is shared. 807 */ 808 static const char * 809 amd_amd64_name(struct cpu_info *ci) 810 { 811 static char family_str[32]; 812 813 /* Only called if family >= 15 */ 814 815 switch (ci->ci_family) { 816 case 15: 817 switch (ci->ci_model) { 818 case 0x21: /* rev JH-E1/E6 */ 819 case 0x41: /* rev JH-F2 */ 820 return "Dual-Core Opteron"; 821 case 0x23: /* rev JH-E6 (Toledo) */ 822 return "Dual-Core Opteron or Athlon 64 X2"; 823 case 0x43: /* rev JH-F2 (Windsor) */ 824 return "Athlon 64 FX or Athlon 64 X2"; 825 case 0x24: /* rev SH-E5 (Lancaster?) */ 826 return "Mobile Athlon 64 or Turion 64"; 827 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 828 return "Opteron or Athlon 64 FX"; 829 case 0x15: /* rev SH-D0 */ 830 case 0x25: /* rev SH-E4 */ 831 return "Opteron"; 832 case 0x27: /* rev DH-E4, SH-E4 */ 833 return "Athlon 64 or Athlon 64 FX or Opteron"; 834 case 0x48: /* rev BH-F2 */ 835 return "Turion 64 X2"; 836 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 837 case 0x07: /* rev SH-CG (ClawHammer) */ 838 case 0x0b: /* rev CH-CG */ 839 case 0x14: /* rev SH-D0 */ 840 case 0x17: /* rev SH-D0 */ 841 case 0x1b: /* rev CH-D0 */ 842 return "Athlon 64"; 843 case 0x2b: /* rev BH-E4 (Manchester) */ 844 case 0x4b: /* rev BH-F2 (Windsor) */ 845 return "Athlon 64 X2"; 846 case 0x6b: /* rev BH-G1 (Brisbane) */ 847 return "Athlon X2 or Athlon 64 X2"; 848 case 0x08: /* rev CH-CG */ 849 case 0x0c: /* rev DH-CG (Newcastle) */ 850 case 0x0e: /* rev DH-CG (Newcastle?) */ 851 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 852 case 0x18: /* rev CH-D0 */ 853 case 0x1c: /* rev DH-D0 (Winchester) */ 854 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 855 case 0x2c: /* rev DH-E3/E6 */ 856 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 857 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 858 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 859 case 0x6f: /* rev DH-G1 */ 860 return "Athlon 64 or Sempron"; 861 default: 862 break; 863 } 864 return "Unknown AMD64 CPU"; 865 866 #if 0 867 case 16: 868 return "Family 10h"; 869 case 17: 870 return "Family 11h"; 871 case 18: 872 return "Family 12h"; 873 case 19: 874 return "Family 14h"; 875 case 20: 876 return "Family 15h"; 877 #endif 878 879 default: 880 break; 881 } 882 883 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 884 return family_str; 885 } 886 887 static void 888 intel_family_new_probe(struct cpu_info *ci) 889 { 890 uint32_t descs[4]; 891 892 x86_cpuid(0x80000000, descs); 893 894 /* 895 * Determine extended feature flags. 896 */ 897 if (descs[0] >= 0x80000001) { 898 x86_cpuid(0x80000001, descs); 899 ci->ci_feat_val[2] |= descs[3]; 900 ci->ci_feat_val[3] |= descs[2]; 901 } 902 } 903 904 static void 905 via_cpu_probe(struct cpu_info *ci) 906 { 907 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 908 u_int descs[4]; 909 u_int lfunc; 910 911 /* 912 * Determine the largest extended function value. 913 */ 914 x86_cpuid(0x80000000, descs); 915 lfunc = descs[0]; 916 917 /* 918 * Determine the extended feature flags. 919 */ 920 if (lfunc >= 0x80000001) { 921 x86_cpuid(0x80000001, descs); 922 ci->ci_feat_val[2] |= descs[3]; 923 } 924 925 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 926 return; 927 928 /* Nehemiah or Esther */ 929 x86_cpuid(0xc0000000, descs); 930 lfunc = descs[0]; 931 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 932 return; 933 934 x86_cpuid(0xc0000001, descs); 935 lfunc = descs[3]; 936 ci->ci_feat_val[4] = lfunc; 937 } 938 939 static void 940 amd_family6_probe(struct cpu_info *ci) 941 { 942 uint32_t descs[4]; 943 char *p; 944 size_t i; 945 946 x86_cpuid(0x80000000, descs); 947 948 /* 949 * Determine the extended feature flags. 950 */ 951 if (descs[0] >= 0x80000001) { 952 x86_cpuid(0x80000001, descs); 953 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 954 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 955 } 956 957 if (*cpu_brand_string == '\0') 958 return; 959 960 for (i = 1; i < __arraycount(amd_brand); i++) 961 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 962 ci->ci_brand_id = i; 963 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 964 break; 965 } 966 } 967 968 static void 969 intel_cpu_cacheinfo(struct cpu_info *ci) 970 { 971 const struct x86_cache_info *cai; 972 u_int descs[4]; 973 int iterations, i, j; 974 int type, level; 975 int ways, partitions, linesize, sets; 976 int caitype = -1; 977 int totalsize; 978 uint8_t desc; 979 980 /* Return if the cpu is old pre-cpuid instruction cpu */ 981 if (ci->ci_cpu_type >= 0) 982 return; 983 984 if (ci->ci_cpuid_level < 2) 985 return; 986 987 /* 988 * Parse the cache info from `cpuid leaf 2', if we have it. 989 * XXX This is kinda ugly, but hey, so is the architecture... 990 */ 991 x86_cpuid(2, descs); 992 iterations = descs[0] & 0xff; 993 while (iterations-- > 0) { 994 for (i = 0; i < 4; i++) { 995 if (descs[i] & 0x80000000) 996 continue; 997 for (j = 0; j < 4; j++) { 998 if (i == 0 && j == 0) 999 continue; 1000 desc = (descs[i] >> (j * 8)) & 0xff; 1001 if (desc == 0) 1002 continue; 1003 cai = cache_info_lookup(intel_cpuid_cache_info, 1004 desc); 1005 if (cai != NULL) 1006 ci->ci_cinfo[cai->cai_index] = *cai; 1007 else if ((verbose != 0) && (desc != 0xff)) 1008 printf("Unknown cacheinfo desc %02x\n", 1009 desc); 1010 } 1011 } 1012 x86_cpuid(2, descs); 1013 } 1014 1015 if (ci->ci_cpuid_level < 4) 1016 return; 1017 1018 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1019 for (i = 0; ; i++) { 1020 x86_cpuid2(4, i, descs); 1021 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1022 if (type == CPUID_DCP_CACHETYPE_N) 1023 break; 1024 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1025 switch (level) { 1026 case 1: 1027 if (type == CPUID_DCP_CACHETYPE_I) 1028 caitype = CAI_ICACHE; 1029 else if (type == CPUID_DCP_CACHETYPE_D) 1030 caitype = CAI_DCACHE; 1031 else 1032 caitype = -1; 1033 break; 1034 case 2: 1035 if (type == CPUID_DCP_CACHETYPE_U) 1036 caitype = CAI_L2CACHE; 1037 else 1038 caitype = -1; 1039 break; 1040 case 3: 1041 if (type == CPUID_DCP_CACHETYPE_U) 1042 caitype = CAI_L3CACHE; 1043 else 1044 caitype = -1; 1045 break; 1046 default: 1047 caitype = -1; 1048 break; 1049 } 1050 if (caitype == -1) { 1051 printf("unknown cache level&type (%d & %d)\n", 1052 level, type); 1053 continue; 1054 } 1055 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1056 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1057 + 1; 1058 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1059 + 1; 1060 sets = descs[2] + 1; 1061 totalsize = ways * partitions * linesize * sets; 1062 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1063 ci->ci_cinfo[caitype].cai_associativity = ways; 1064 ci->ci_cinfo[caitype].cai_linesize = linesize; 1065 } 1066 } 1067 1068 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1069 AMD_L2CACHE_INFO; 1070 1071 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1072 AMD_L3CACHE_INFO; 1073 1074 static void 1075 amd_cpu_cacheinfo(struct cpu_info *ci) 1076 { 1077 const struct x86_cache_info *cp; 1078 struct x86_cache_info *cai; 1079 u_int descs[4]; 1080 u_int lfunc; 1081 1082 /* 1083 * K5 model 0 has none of this info. 1084 */ 1085 if (ci->ci_family == 5 && ci->ci_model == 0) 1086 return; 1087 1088 /* 1089 * Determine the largest extended function value. 1090 */ 1091 x86_cpuid(0x80000000, descs); 1092 lfunc = descs[0]; 1093 1094 /* 1095 * Determine L1 cache/TLB info. 1096 */ 1097 if (lfunc < 0x80000005) { 1098 /* No L1 cache info available. */ 1099 return; 1100 } 1101 1102 x86_cpuid(0x80000005, descs); 1103 1104 /* 1105 * K6-III and higher have large page TLBs. 1106 */ 1107 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1108 cai = &ci->ci_cinfo[CAI_ITLB2]; 1109 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1110 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1111 cai->cai_linesize = largepagesize; 1112 1113 cai = &ci->ci_cinfo[CAI_DTLB2]; 1114 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1115 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1116 cai->cai_linesize = largepagesize; 1117 } 1118 1119 cai = &ci->ci_cinfo[CAI_ITLB]; 1120 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1121 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1122 cai->cai_linesize = (4 * 1024); 1123 1124 cai = &ci->ci_cinfo[CAI_DTLB]; 1125 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1126 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1127 cai->cai_linesize = (4 * 1024); 1128 1129 cai = &ci->ci_cinfo[CAI_DCACHE]; 1130 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1131 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1132 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1133 1134 cai = &ci->ci_cinfo[CAI_ICACHE]; 1135 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1136 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1137 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1138 1139 /* 1140 * Determine L2 cache/TLB info. 1141 */ 1142 if (lfunc < 0x80000006) { 1143 /* No L2 cache info available. */ 1144 return; 1145 } 1146 1147 x86_cpuid(0x80000006, descs); 1148 1149 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1150 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1151 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1152 cai->cai_linesize = (4 * 1024); 1153 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1154 cai->cai_associativity); 1155 if (cp != NULL) 1156 cai->cai_associativity = cp->cai_associativity; 1157 else 1158 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1159 1160 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1161 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1162 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1163 cai->cai_linesize = largepagesize; 1164 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1165 cai->cai_associativity); 1166 if (cp != NULL) 1167 cai->cai_associativity = cp->cai_associativity; 1168 else 1169 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1170 1171 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1172 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1173 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1174 cai->cai_linesize = (4 * 1024); 1175 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1176 cai->cai_associativity); 1177 if (cp != NULL) 1178 cai->cai_associativity = cp->cai_associativity; 1179 else 1180 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1181 1182 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1183 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1184 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1185 cai->cai_linesize = largepagesize; 1186 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1187 cai->cai_associativity); 1188 if (cp != NULL) 1189 cai->cai_associativity = cp->cai_associativity; 1190 else 1191 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1192 1193 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1194 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1195 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1196 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1197 1198 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1199 cai->cai_associativity); 1200 if (cp != NULL) 1201 cai->cai_associativity = cp->cai_associativity; 1202 else 1203 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1204 1205 /* 1206 * Determine L3 cache info on AMD Family 10h and newer processors 1207 */ 1208 if (ci->ci_family >= 0x10) { 1209 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1210 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1211 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1212 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1213 1214 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1215 cai->cai_associativity); 1216 if (cp != NULL) 1217 cai->cai_associativity = cp->cai_associativity; 1218 else 1219 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1220 } 1221 1222 /* 1223 * Determine 1GB TLB info. 1224 */ 1225 if (lfunc < 0x80000019) { 1226 /* No 1GB TLB info available. */ 1227 return; 1228 } 1229 1230 x86_cpuid(0x80000019, descs); 1231 1232 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1233 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1234 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1235 cai->cai_linesize = (1024 * 1024 * 1024); 1236 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1237 cai->cai_associativity); 1238 if (cp != NULL) 1239 cai->cai_associativity = cp->cai_associativity; 1240 else 1241 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1242 1243 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1244 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1245 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1246 cai->cai_linesize = (1024 * 1024 * 1024); 1247 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1248 cai->cai_associativity); 1249 if (cp != NULL) 1250 cai->cai_associativity = cp->cai_associativity; 1251 else 1252 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1253 1254 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1255 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1256 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1257 cai->cai_linesize = (1024 * 1024 * 1024); 1258 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1259 cai->cai_associativity); 1260 if (cp != NULL) 1261 cai->cai_associativity = cp->cai_associativity; 1262 else 1263 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1264 1265 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1266 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1267 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1268 cai->cai_linesize = (1024 * 1024 * 1024); 1269 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1270 cai->cai_associativity); 1271 if (cp != NULL) 1272 cai->cai_associativity = cp->cai_associativity; 1273 else 1274 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1275 } 1276 1277 static void 1278 via_cpu_cacheinfo(struct cpu_info *ci) 1279 { 1280 struct x86_cache_info *cai; 1281 int stepping; 1282 u_int descs[4]; 1283 u_int lfunc; 1284 1285 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1286 1287 /* 1288 * Determine the largest extended function value. 1289 */ 1290 x86_cpuid(0x80000000, descs); 1291 lfunc = descs[0]; 1292 1293 /* 1294 * Determine L1 cache/TLB info. 1295 */ 1296 if (lfunc < 0x80000005) { 1297 /* No L1 cache info available. */ 1298 return; 1299 } 1300 1301 x86_cpuid(0x80000005, descs); 1302 1303 cai = &ci->ci_cinfo[CAI_ITLB]; 1304 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1305 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1306 cai->cai_linesize = (4 * 1024); 1307 1308 cai = &ci->ci_cinfo[CAI_DTLB]; 1309 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1310 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1311 cai->cai_linesize = (4 * 1024); 1312 1313 cai = &ci->ci_cinfo[CAI_DCACHE]; 1314 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1315 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1316 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1317 if (ci->ci_model == 9 && stepping == 8) { 1318 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1319 cai->cai_associativity = 2; 1320 } 1321 1322 cai = &ci->ci_cinfo[CAI_ICACHE]; 1323 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1324 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1325 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1326 if (ci->ci_model == 9 && stepping == 8) { 1327 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1328 cai->cai_associativity = 2; 1329 } 1330 1331 /* 1332 * Determine L2 cache/TLB info. 1333 */ 1334 if (lfunc < 0x80000006) { 1335 /* No L2 cache info available. */ 1336 return; 1337 } 1338 1339 x86_cpuid(0x80000006, descs); 1340 1341 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1342 if (ci->ci_model >= 9) { 1343 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1344 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1345 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1346 } else { 1347 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1348 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1349 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1350 } 1351 } 1352 1353 static void 1354 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1355 { 1356 u_int descs[4]; 1357 1358 x86_cpuid(0x80860007, descs); 1359 *frequency = descs[0]; 1360 *voltage = descs[1]; 1361 *percentage = descs[2]; 1362 } 1363 1364 static void 1365 transmeta_cpu_info(struct cpu_info *ci) 1366 { 1367 u_int descs[4], nreg; 1368 u_int frequency, voltage, percentage; 1369 1370 x86_cpuid(0x80860000, descs); 1371 nreg = descs[0]; 1372 if (nreg >= 0x80860001) { 1373 x86_cpuid(0x80860001, descs); 1374 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1375 (descs[1] >> 24) & 0xff, 1376 (descs[1] >> 16) & 0xff, 1377 (descs[1] >> 8) & 0xff, 1378 descs[1] & 0xff); 1379 } 1380 if (nreg >= 0x80860002) { 1381 x86_cpuid(0x80860002, descs); 1382 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1383 (descs[1] >> 24) & 0xff, 1384 (descs[1] >> 16) & 0xff, 1385 (descs[1] >> 8) & 0xff, 1386 descs[1] & 0xff, 1387 descs[2]); 1388 } 1389 if (nreg >= 0x80860006) { 1390 union { 1391 char text[65]; 1392 u_int descs[4][4]; 1393 } info; 1394 int i; 1395 1396 for (i=0; i<4; i++) { 1397 x86_cpuid(0x80860003 + i, info.descs[i]); 1398 } 1399 info.text[64] = '\0'; 1400 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1401 } 1402 1403 if (nreg >= 0x80860007) { 1404 tmx86_get_longrun_status(&frequency, 1405 &voltage, &percentage); 1406 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1407 frequency, voltage, percentage); 1408 } 1409 } 1410 1411 static void 1412 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1413 { 1414 u_int descs[4]; 1415 int i; 1416 uint32_t brand[12]; 1417 1418 memset(ci, 0, sizeof(*ci)); 1419 ci->ci_dev = cpuname; 1420 1421 ci->ci_cpu_type = x86_identify(); 1422 if (ci->ci_cpu_type >= 0) { 1423 /* Old pre-cpuid instruction cpu */ 1424 ci->ci_cpuid_level = -1; 1425 return; 1426 } 1427 1428 /* 1429 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1430 * function. 1431 */ 1432 1433 /* 1434 * Fn0000_0000: 1435 * - Save cpuid max level. 1436 * - Save vendor string. 1437 */ 1438 x86_cpuid(0, descs); 1439 ci->ci_cpuid_level = descs[0]; 1440 /* Save vendor string */ 1441 ci->ci_vendor[0] = descs[1]; 1442 ci->ci_vendor[2] = descs[2]; 1443 ci->ci_vendor[1] = descs[3]; 1444 ci->ci_vendor[3] = 0; 1445 1446 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1447 ci->ci_cpuid_level); 1448 if (verbose) { 1449 int bf; 1450 1451 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1452 x86_cpuid(bf, descs); 1453 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1454 bf, descs[0], descs[1], descs[2], descs[3]); 1455 } 1456 } 1457 1458 /* 1459 * Fn8000_0000: 1460 * - Get cpuid extended function's max level. 1461 */ 1462 x86_cpuid(0x80000000, descs); 1463 if (descs[0] >= 0x80000000) { 1464 ci->ci_cpuid_extlevel = descs[0]; 1465 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1466 ci->ci_cpuid_extlevel); 1467 } else { 1468 /* Set lower value than 0x80000000 */ 1469 ci->ci_cpuid_extlevel = 0; 1470 } 1471 if (verbose) { 1472 unsigned int ef; 1473 1474 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1475 x86_cpuid(ef, descs); 1476 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1477 ef, descs[0], descs[1], descs[2], descs[3]); 1478 } 1479 } 1480 1481 /* 1482 * Fn8000_000[2-4]: 1483 * - Save brand string. 1484 */ 1485 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1486 x86_cpuid(0x80000002, brand); 1487 x86_cpuid(0x80000003, brand + 4); 1488 x86_cpuid(0x80000004, brand + 8); 1489 for (i = 0; i < 48; i++) 1490 if (((char *) brand)[i] != ' ') 1491 break; 1492 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1493 } 1494 1495 if (ci->ci_cpuid_level < 1) 1496 return; 1497 1498 /* 1499 * Fn0000_0001: 1500 * - Get CPU family, model and stepping (from eax). 1501 * - Initial local APIC ID and brand ID (from ebx) 1502 * - CPUID2 (from ecx) 1503 * - CPUID (from edx) 1504 */ 1505 x86_cpuid(1, descs); 1506 ci->ci_signature = descs[0]; 1507 1508 /* Extract full family/model values */ 1509 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1510 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1511 1512 /* Brand is low order 8 bits of ebx */ 1513 ci->ci_brand_id = descs[1] & 0xff; 1514 /* Initial local APIC ID */ 1515 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1516 1517 ci->ci_feat_val[1] = descs[2]; 1518 ci->ci_feat_val[0] = descs[3]; 1519 1520 if (ci->ci_cpuid_level < 3) 1521 return; 1522 1523 /* 1524 * If the processor serial number misfeature is present and supported, 1525 * extract it here. 1526 */ 1527 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1528 ci->ci_cpu_serial[0] = ci->ci_signature; 1529 x86_cpuid(3, descs); 1530 ci->ci_cpu_serial[2] = descs[2]; 1531 ci->ci_cpu_serial[1] = descs[3]; 1532 } 1533 1534 if (ci->ci_cpuid_level < 0xd) 1535 return; 1536 1537 /* Get support XCR0 bits */ 1538 x86_cpuid2(0xd, 0, descs); 1539 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1540 ci->ci_cur_xsave = descs[1]; 1541 ci->ci_max_xsave = descs[2]; 1542 1543 /* Additional flags (eg xsaveopt support) */ 1544 x86_cpuid2(0xd, 1, descs); 1545 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1546 } 1547 1548 static void 1549 cpu_probe_features(struct cpu_info *ci) 1550 { 1551 const struct cpu_cpuid_nameclass *cpup = NULL; 1552 unsigned int i; 1553 1554 if (ci->ci_cpuid_level < 1) 1555 return; 1556 1557 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1558 if (!strncmp((char *)ci->ci_vendor, 1559 i386_cpuid_cpus[i].cpu_id, 12)) { 1560 cpup = &i386_cpuid_cpus[i]; 1561 break; 1562 } 1563 } 1564 1565 if (cpup == NULL) 1566 return; 1567 1568 i = ci->ci_family - CPU_MINFAMILY; 1569 1570 if (i >= __arraycount(cpup->cpu_family)) 1571 i = __arraycount(cpup->cpu_family) - 1; 1572 1573 if (cpup->cpu_family[i].cpu_probe == NULL) 1574 return; 1575 1576 (*cpup->cpu_family[i].cpu_probe)(ci); 1577 } 1578 1579 static void 1580 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1581 { 1582 char buf[32 * 16]; 1583 char *bp; 1584 1585 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1586 1587 if (val == 0 || fmt == NULL) 1588 return; 1589 1590 snprintb_m(buf, sizeof(buf), fmt, val, 1591 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1592 bp = buf; 1593 while (*bp != '\0') { 1594 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1595 bp += strlen(bp) + 1; 1596 } 1597 } 1598 1599 static void 1600 identifycpu_cpuids(struct cpu_info *ci) 1601 { 1602 const char *cpuname = ci->ci_dev; 1603 u_int lp_max = 1; /* logical processors per package */ 1604 u_int smt_max; /* smt per core */ 1605 u_int core_max = 1; /* core per package */ 1606 u_int smt_bits, core_bits; 1607 uint32_t descs[4]; 1608 1609 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1610 ci->ci_packageid = ci->ci_initapicid; 1611 ci->ci_coreid = 0; 1612 ci->ci_smtid = 0; 1613 if (cpu_vendor != CPUVENDOR_INTEL) { 1614 return; 1615 } 1616 1617 /* 1618 * 253668.pdf 7.10.2 1619 */ 1620 1621 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1622 x86_cpuid(1, descs); 1623 lp_max = (descs[1] >> 16) & 0xff; 1624 } 1625 if (ci->ci_cpuid_level >= 4) { 1626 x86_cpuid2(4, 0, descs); 1627 core_max = (descs[0] >> 26) + 1; 1628 } 1629 assert(lp_max >= core_max); 1630 smt_max = lp_max / core_max; 1631 smt_bits = ilog2(smt_max - 1) + 1; 1632 core_bits = ilog2(core_max - 1) + 1; 1633 if (smt_bits + core_bits) { 1634 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1635 } 1636 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1637 ci->ci_packageid); 1638 if (core_bits) { 1639 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1640 1641 ci->ci_coreid = 1642 __SHIFTOUT(ci->ci_initapicid, core_mask); 1643 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1644 } 1645 if (smt_bits) { 1646 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1647 1648 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1649 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1650 } 1651 } 1652 1653 void 1654 identifycpu(int fd, const char *cpuname) 1655 { 1656 const char *name = "", *modifier, *vendorname, *brand = ""; 1657 int class = CPUCLASS_386; 1658 unsigned int i; 1659 int modif, family; 1660 const struct cpu_cpuid_nameclass *cpup = NULL; 1661 const struct cpu_cpuid_family *cpufam; 1662 struct cpu_info *ci, cistore; 1663 size_t sz; 1664 struct cpu_ucode_version ucode; 1665 union { 1666 struct cpu_ucode_version_amd amd; 1667 struct cpu_ucode_version_intel1 intel1; 1668 } ucvers; 1669 1670 ci = &cistore; 1671 cpu_probe_base_features(ci, cpuname); 1672 cpu_probe_features(ci); 1673 1674 if (ci->ci_cpu_type >= 0) { 1675 /* Old pre-cpuid instruction cpu */ 1676 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1677 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1678 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1679 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1680 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1681 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1682 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1683 modifier = ""; 1684 } else { 1685 /* CPU which support cpuid instruction */ 1686 modif = (ci->ci_signature >> 12) & 0x3; 1687 family = ci->ci_family; 1688 if (family < CPU_MINFAMILY) 1689 errx(1, "identifycpu: strange family value"); 1690 if (family > CPU_MAXFAMILY) 1691 family = CPU_MAXFAMILY; 1692 1693 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1694 if (!strncmp((char *)ci->ci_vendor, 1695 i386_cpuid_cpus[i].cpu_id, 12)) { 1696 cpup = &i386_cpuid_cpus[i]; 1697 break; 1698 } 1699 } 1700 1701 if (cpup == NULL) { 1702 cpu_vendor = CPUVENDOR_UNKNOWN; 1703 if (ci->ci_vendor[0] != '\0') 1704 vendorname = (char *)&ci->ci_vendor[0]; 1705 else 1706 vendorname = "Unknown"; 1707 class = family - 3; 1708 modifier = ""; 1709 name = ""; 1710 ci->ci_info = NULL; 1711 } else { 1712 cpu_vendor = cpup->cpu_vendor; 1713 vendorname = cpup->cpu_vendorname; 1714 modifier = modifiers[modif]; 1715 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1716 name = cpufam->cpu_models[ci->ci_model]; 1717 if (name == NULL || *name == '\0') 1718 name = cpufam->cpu_model_default; 1719 class = cpufam->cpu_class; 1720 ci->ci_info = cpufam->cpu_info; 1721 1722 if (cpu_vendor == CPUVENDOR_INTEL) { 1723 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1724 const char *tmp; 1725 tmp = intel_family6_name(ci); 1726 if (tmp != NULL) 1727 name = tmp; 1728 } 1729 if (ci->ci_family == 15 && 1730 ci->ci_brand_id < 1731 __arraycount(i386_intel_brand) && 1732 i386_intel_brand[ci->ci_brand_id]) 1733 name = 1734 i386_intel_brand[ci->ci_brand_id]; 1735 } 1736 1737 if (cpu_vendor == CPUVENDOR_AMD) { 1738 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1739 if (ci->ci_brand_id == 1) 1740 /* 1741 * It's Duron. We override the 1742 * name, since it might have 1743 * been misidentified as Athlon. 1744 */ 1745 name = 1746 amd_brand[ci->ci_brand_id]; 1747 else 1748 brand = amd_brand_name; 1749 } 1750 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1751 == 0xf) { 1752 /* Identify AMD64 CPU names. */ 1753 const char *tmp; 1754 tmp = amd_amd64_name(ci); 1755 if (tmp != NULL) 1756 name = tmp; 1757 } 1758 } 1759 1760 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1761 vendorname = "VIA"; 1762 } 1763 } 1764 1765 ci->ci_cpu_class = class; 1766 1767 sz = sizeof(ci->ci_tsc_freq); 1768 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1769 sz = sizeof(use_pae); 1770 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1771 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1772 1773 /* 1774 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1775 * we try to determine from the family/model values. 1776 */ 1777 if (*cpu_brand_string != '\0') 1778 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1779 1780 aprint_normal("%s: %s", cpuname, vendorname); 1781 if (*modifier) 1782 aprint_normal(" %s", modifier); 1783 if (*name) 1784 aprint_normal(" %s", name); 1785 if (*brand) 1786 aprint_normal(" %s", brand); 1787 aprint_normal(" (%s-class)", classnames[class]); 1788 1789 if (ci->ci_tsc_freq != 0) 1790 aprint_normal(", %ju.%02ju MHz\n", 1791 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1792 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1793 1794 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1795 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1796 if (ci->ci_signature != 0) 1797 aprint_normal(" (id %#x)", ci->ci_signature); 1798 aprint_normal("\n"); 1799 1800 if (ci->ci_info) 1801 (*ci->ci_info)(ci); 1802 1803 /* 1804 * display CPU feature flags 1805 */ 1806 1807 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1808 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1809 1810 /* These next two are actually common definitions! */ 1811 print_bits(cpuname, "features2", 1812 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1813 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1814 print_bits(cpuname, "features3", 1815 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1816 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1817 1818 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1819 ci->ci_feat_val[4]); 1820 1821 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1822 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1823 ci->ci_feat_val[6]); 1824 1825 if (ci->ci_max_xsave != 0) { 1826 aprint_normal("%s: xsave area size: current %d, maximum %d", 1827 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1828 aprint_normal(", xgetbv %sabled\n", 1829 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1830 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1831 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1832 x86_xgetbv()); 1833 } 1834 1835 x86_print_cache_and_tlb_info(ci); 1836 1837 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1838 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1839 cpuname, 1840 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1841 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1842 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1843 } 1844 1845 if (ci->ci_cpu_class == CPUCLASS_386) { 1846 errx(1, "NetBSD requires an 80486 or later processor"); 1847 } 1848 1849 if (ci->ci_cpu_type == CPU_486DLC) { 1850 #ifndef CYRIX_CACHE_WORKS 1851 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1852 #else 1853 #ifndef CYRIX_CACHE_REALLY_WORKS 1854 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1855 #else 1856 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1857 #endif 1858 #endif 1859 } 1860 1861 /* 1862 * Everything past this point requires a Pentium or later. 1863 */ 1864 if (ci->ci_cpuid_level < 0) 1865 return; 1866 1867 identifycpu_cpuids(ci); 1868 1869 #ifdef INTEL_CORETEMP 1870 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1871 coretemp_register(ci); 1872 #endif 1873 1874 if (cpu_vendor == CPUVENDOR_AMD) { 1875 uint32_t data[4]; 1876 1877 x86_cpuid(0x80000000, data); 1878 if (data[0] >= 0x80000007) 1879 powernow_probe(ci); 1880 1881 if ((data[0] >= 0x8000000a) 1882 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1883 x86_cpuid(0x8000000a, data); 1884 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1885 data[0] & 0xf); 1886 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1887 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1888 data[3]); 1889 } 1890 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1891 uint32_t data[4]; 1892 int32_t bi_index; 1893 1894 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1895 x86_cpuid(bi_index, data); 1896 switch (bi_index) { 1897 case 6: 1898 print_bits(cpuname, "DSPM-eax", 1899 CPUID_DSPM_FLAGS, data[0]); 1900 print_bits(cpuname, "DSPM-ecx", 1901 CPUID_DSPM_FLAGS1, data[2]); 1902 break; 1903 case 7: 1904 aprint_verbose("%s: SEF highest subleaf %08x\n", 1905 cpuname, data[0]); 1906 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1907 data[1]); 1908 break; 1909 #if 0 1910 default: 1911 aprint_verbose("%s: basic %08x-eax %08x\n", 1912 cpuname, bi_index, data[0]); 1913 aprint_verbose("%s: basic %08x-ebx %08x\n", 1914 cpuname, bi_index, data[1]); 1915 aprint_verbose("%s: basic %08x-ecx %08x\n", 1916 cpuname, bi_index, data[2]); 1917 aprint_verbose("%s: basic %08x-edx %08x\n", 1918 cpuname, bi_index, data[3]); 1919 break; 1920 #endif 1921 } 1922 } 1923 } 1924 1925 #ifdef INTEL_ONDEMAND_CLOCKMOD 1926 clockmod_init(); 1927 #endif 1928 1929 if (cpu_vendor == CPUVENDOR_AMD) 1930 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1931 else if (cpu_vendor == CPUVENDOR_INTEL) 1932 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1933 else 1934 return; 1935 1936 ucode.data = &ucvers; 1937 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1938 #ifdef __i386__ 1939 struct cpu_ucode_version_64 ucode_64; 1940 if (errno != ENOTTY) 1941 return; 1942 /* Try the 64 bit ioctl */ 1943 memset(&ucode_64, 0, sizeof ucode_64); 1944 ucode_64.data = &ucvers; 1945 ucode_64.loader_version = ucode.loader_version; 1946 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1947 return; 1948 #endif 1949 } 1950 1951 if (cpu_vendor == CPUVENDOR_AMD) 1952 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1953 else if (cpu_vendor == CPUVENDOR_INTEL) 1954 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1955 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1956 } 1957 1958 static const struct x86_cache_info * 1959 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1960 { 1961 int i; 1962 1963 for (i = 0; cai[i].cai_desc != 0; i++) { 1964 if (cai[i].cai_desc == desc) 1965 return (&cai[i]); 1966 } 1967 1968 return (NULL); 1969 } 1970 1971 static const char * 1972 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1973 const char *sep) 1974 { 1975 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1976 char human_num[HUMAN_BUFSIZE]; 1977 1978 if (cai->cai_totalsize == 0) 1979 return sep; 1980 1981 if (sep == NULL) 1982 aprint_verbose_dev(ci->ci_dev, ""); 1983 else 1984 aprint_verbose("%s", sep); 1985 if (name != NULL) 1986 aprint_verbose("%s ", name); 1987 1988 if (cai->cai_string != NULL) { 1989 aprint_verbose("%s ", cai->cai_string); 1990 } else { 1991 (void)humanize_number(human_num, sizeof(human_num), 1992 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1993 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1994 } 1995 switch (cai->cai_associativity) { 1996 case 0: 1997 aprint_verbose("disabled"); 1998 break; 1999 case 1: 2000 aprint_verbose("direct-mapped"); 2001 break; 2002 case 0xff: 2003 aprint_verbose("fully associative"); 2004 break; 2005 default: 2006 aprint_verbose("%d-way", cai->cai_associativity); 2007 break; 2008 } 2009 return ", "; 2010 } 2011 2012 static const char * 2013 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2014 const char *sep) 2015 { 2016 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2017 char human_num[HUMAN_BUFSIZE]; 2018 2019 if (cai->cai_totalsize == 0) 2020 return sep; 2021 2022 if (sep == NULL) 2023 aprint_verbose_dev(ci->ci_dev, ""); 2024 else 2025 aprint_verbose("%s", sep); 2026 if (name != NULL) 2027 aprint_verbose("%s ", name); 2028 2029 if (cai->cai_string != NULL) { 2030 aprint_verbose("%s", cai->cai_string); 2031 } else { 2032 (void)humanize_number(human_num, sizeof(human_num), 2033 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2034 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2035 human_num); 2036 switch (cai->cai_associativity) { 2037 case 0: 2038 aprint_verbose("disabled"); 2039 break; 2040 case 1: 2041 aprint_verbose("direct-mapped"); 2042 break; 2043 case 0xff: 2044 aprint_verbose("fully associative"); 2045 break; 2046 default: 2047 aprint_verbose("%d-way", cai->cai_associativity); 2048 break; 2049 } 2050 } 2051 return ", "; 2052 } 2053 2054 static void 2055 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2056 { 2057 const char *sep = NULL; 2058 2059 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2060 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2061 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2062 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2063 if (sep != NULL) 2064 aprint_verbose("\n"); 2065 } 2066 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2067 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2068 if (sep != NULL) 2069 aprint_verbose("\n"); 2070 } 2071 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2072 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2073 if (sep != NULL) 2074 aprint_verbose("\n"); 2075 } 2076 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2077 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2078 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2079 if (sep != NULL) 2080 aprint_verbose("\n"); 2081 } 2082 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2083 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2084 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2085 if (sep != NULL) 2086 aprint_verbose("\n"); 2087 } 2088 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2089 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2090 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2091 if (sep != NULL) 2092 aprint_verbose("\n"); 2093 } 2094 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2095 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2096 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2097 if (sep != NULL) 2098 aprint_verbose("\n"); 2099 } 2100 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2101 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2102 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2103 if (sep != NULL) 2104 aprint_verbose("\n"); 2105 } 2106 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2107 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2108 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2109 if (sep != NULL) 2110 aprint_verbose("\n"); 2111 } 2112 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2113 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2114 NULL); 2115 if (sep != NULL) 2116 aprint_verbose("\n"); 2117 } 2118 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2119 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2120 NULL); 2121 if (sep != NULL) 2122 aprint_verbose("\n"); 2123 } 2124 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2125 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2126 NULL); 2127 if (sep != NULL) 2128 aprint_verbose("\n"); 2129 } 2130 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2131 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2132 NULL); 2133 if (sep != NULL) 2134 aprint_verbose("\n"); 2135 } 2136 } 2137 2138 static void 2139 powernow_probe(struct cpu_info *ci) 2140 { 2141 uint32_t regs[4]; 2142 char buf[256]; 2143 2144 x86_cpuid(0x80000007, regs); 2145 2146 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2147 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2148 buf); 2149 } 2150 2151 int 2152 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2153 { 2154 struct cpu_info ci; 2155 int loader_version, res; 2156 struct cpu_ucode_version versreq; 2157 2158 cpu_probe_base_features(&ci, "unknown"); 2159 2160 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2161 loader_version = CPU_UCODE_LOADER_AMD; 2162 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2163 loader_version = CPU_UCODE_LOADER_INTEL1; 2164 else 2165 return -1; 2166 2167 /* check whether the kernel understands this loader version */ 2168 versreq.loader_version = loader_version; 2169 versreq.data = 0; 2170 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2171 if (res) 2172 return -1; 2173 2174 switch (loader_version) { 2175 case CPU_UCODE_LOADER_AMD: 2176 if (uc->cpu_nr != -1) { 2177 /* printf? */ 2178 return -1; 2179 } 2180 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2181 break; 2182 case CPU_UCODE_LOADER_INTEL1: 2183 if (uc->cpu_nr == -1) 2184 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2185 else 2186 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2187 break; 2188 default: /* can't happen */ 2189 return -1; 2190 } 2191 uc->loader_version = loader_version; 2192 return 0; 2193 } 2194
Indexes created Mon Sep 29 21:09:56 GMT 2025