i386.c revision 1.6
1 /* $NetBSD: i386.c,v 1.6 2008/05/30 14:41:57 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.6 2008/05/30 14:41:57 christos Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 68 #include <string.h> 69 #include <stdio.h> 70 #include <stdlib.h> 71 #include <err.h> 72 #include <assert.h> 73 #include <math.h> 74 75 #include <machine/specialreg.h> 76 #include <machine/cpu.h> 77 78 #include <x86/cpuvar.h> 79 #include <x86/cputypes.h> 80 #include <x86/cacheinfo.h> 81 82 #include "../cpuctl.h" 83 84 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 85 86 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 87 void x86_identify(void); 88 89 struct cpu_info { 90 const char *ci_dev; 91 int32_t ci_cpuid_level; 92 uint32_t ci_signature; /* X86 cpuid type */ 93 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 94 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 95 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 96 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 97 uint32_t ci_cpu_class; /* CPU class */ 98 uint32_t ci_brand_id; /* Intel brand id */ 99 uint32_t ci_vendor[4]; /* vendor string */ 100 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 101 uint64_t ci_tsc_freq; /* cpu cycles/second */ 102 uint8_t ci_packageid; 103 uint8_t ci_coreid; 104 uint8_t ci_smtid; 105 uint32_t ci_initapicid; 106 struct x86_cache_info ci_cinfo[CAI_COUNT]; 107 void (*ci_info)(struct cpu_info *); 108 }; 109 110 struct cpu_nocpuid_nameclass { 111 int cpu_vendor; 112 const char *cpu_vendorname; 113 const char *cpu_name; 114 int cpu_class; 115 void (*cpu_setup)(struct cpu_info *); 116 void (*cpu_cacheinfo)(struct cpu_info *); 117 void (*cpu_info)(struct cpu_info *); 118 }; 119 120 121 struct cpu_cpuid_nameclass { 122 const char *cpu_id; 123 int cpu_vendor; 124 const char *cpu_vendorname; 125 struct cpu_cpuid_family { 126 int cpu_class; 127 const char *cpu_models[CPU_MAXMODEL+2]; 128 void (*cpu_setup)(struct cpu_info *); 129 void (*cpu_probe)(struct cpu_info *); 130 void (*cpu_info)(struct cpu_info *); 131 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 132 }; 133 134 static const struct x86_cache_info intel_cpuid_cache_info[] = { 135 { CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL }, 136 { CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL }, 137 { CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL }, 138 { CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL }, 139 { CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL }, 140 { CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL }, 141 { CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL }, 142 { CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024 }, 143 { CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 144 { CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 145 { CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 146 { CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 147 { CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 148 { CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 149 { CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL }, 150 { CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL }, 151 { CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL }, 152 { CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL }, 153 { CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL }, 154 { CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL }, 155 { CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL }, 156 { CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL }, 157 { CAI_L2CACHE, 0x3c, 4, 256 * 1024, 64, NULL }, 158 { CAI_L2CACHE, 0x3d, 6, 384 * 1024, 64, NULL }, 159 { CAI_L2CACHE, 0x3e, 4, 512 * 1024, 64, NULL }, 160 { CAI_L2CACHE, 0x40, 0, 0, 0, "not present" }, 161 { CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL }, 162 { CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL }, 163 { CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL }, 164 { CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL }, 165 { CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL }, 166 { CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL }, 167 { CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL }, 168 { CAI_DCACHE, 0x60, 8, 16 * 1024, 64 }, 169 { CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL }, 170 { CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL }, 171 { CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL }, 172 { CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL }, 173 { CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"}, 174 { CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"}, 175 { CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"}, 176 { CAI_ICACHE, 0x73, 8, 64 * 1024, 64, "64K uOp cache"}, 177 { CAI_L2CACHE, 0x78, 4, 1 * 1024 * 1024, 64, NULL }, 178 { CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL }, 179 { CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL }, 180 { CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL }, 181 { CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL }, 182 { CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL }, 183 { CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL }, 184 { CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL }, 185 { CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL }, 186 { CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL }, 187 { CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL }, 188 { CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL }, 189 { CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL }, 190 { 0, 0, 0, 0, 0, NULL }, 191 }; 192 193 /* 194 * Map Brand ID from cpuid instruction to brand name. 195 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 196 */ 197 static const char * const i386_intel_brand[] = { 198 "", /* Unsupported */ 199 "Celeron", /* Intel (R) Celeron (TM) processor */ 200 "Pentium III", /* Intel (R) Pentium (R) III processor */ 201 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 202 "Pentium III", /* Intel (R) Pentium (R) III processor */ 203 "", /* Reserved */ 204 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 205 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 206 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 207 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 208 "Celeron", /* Intel (R) Celeron (TM) processor */ 209 "Xeon", /* Intel (R) Xeon (TM) processor */ 210 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 211 "", /* Reserved */ 212 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 213 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 214 }; 215 216 /* 217 * AMD processors don't have Brand IDs, so we need these names for probe. 218 */ 219 static const char * const amd_brand[] = { 220 "", 221 "Duron", /* AMD Duron(tm) */ 222 "MP", /* AMD Athlon(tm) MP */ 223 "XP", /* AMD Athlon(tm) XP */ 224 "4" /* AMD Athlon(tm) 4 */ 225 }; 226 227 static int cpu_vendor; 228 static char cpu_brand_string[49]; 229 static char amd_brand_name[48]; 230 231 static void via_cpu_probe(struct cpu_info *); 232 static void amd_family6_probe(struct cpu_info *); 233 static void intel_family_new_probe(struct cpu_info *); 234 static const char *intel_family6_name(struct cpu_info *); 235 static const char *amd_amd64_name(struct cpu_info *); 236 static void amd_family5_setup(struct cpu_info *); 237 static void transmeta_cpu_info(struct cpu_info *); 238 static const char *print_cache_config(struct cpu_info *, int, const char *, 239 const char *); 240 static const char *print_tlb_config(struct cpu_info *, int, const char *, 241 const char *); 242 static void amd_cpu_cacheinfo(struct cpu_info *); 243 static void via_cpu_cacheinfo(struct cpu_info *); 244 static void x86_print_cacheinfo(struct cpu_info *); 245 static const struct x86_cache_info *cache_info_lookup( 246 const struct x86_cache_info *, uint8_t); 247 static void cyrix6x86_cpu_setup(struct cpu_info *); 248 static void winchip_cpu_setup(struct cpu_info *); 249 static void amd_family5_setup(struct cpu_info *); 250 static void powernow_probe(struct cpu_info *); 251 252 /* 253 * Info for CTL_HW 254 */ 255 static char cpu_model[120]; 256 257 /* 258 * Note: these are just the ones that may not have a cpuid instruction. 259 * We deal with the rest in a different way. 260 */ 261 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 262 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 263 NULL, NULL, NULL }, /* CPU_386SX */ 264 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 265 NULL, NULL, NULL }, /* CPU_386 */ 266 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 267 NULL, NULL, NULL }, /* CPU_486SX */ 268 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 269 NULL, NULL, NULL }, /* CPU_486 */ 270 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 271 NULL, NULL, NULL }, /* CPU_486DLC */ 272 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 273 NULL, NULL, NULL }, /* CPU_6x86 */ 274 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 275 NULL, NULL, NULL }, /* CPU_NX586 */ 276 }; 277 278 const char *classnames[] = { 279 "386", 280 "486", 281 "586", 282 "686" 283 }; 284 285 const char *modifiers[] = { 286 "", 287 "OverDrive", 288 "Dual", 289 "" 290 }; 291 292 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 293 { 294 "GenuineIntel", 295 CPUVENDOR_INTEL, 296 "Intel", 297 /* Family 4 */ 298 { { 299 CPUCLASS_486, 300 { 301 "486DX", "486DX", "486SX", "486DX2", "486SL", 302 "486SX2", 0, "486DX2 W/B Enhanced", 303 "486DX4", 0, 0, 0, 0, 0, 0, 0, 304 "486" /* Default */ 305 }, 306 NULL, 307 NULL, 308 NULL, 309 }, 310 /* Family 5 */ 311 { 312 CPUCLASS_586, 313 { 314 "Pentium (P5 A-step)", "Pentium (P5)", 315 "Pentium (P54C)", "Pentium (P24T)", 316 "Pentium/MMX", "Pentium", 0, 317 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 318 0, 0, 0, 0, 0, 0, 0, 319 "Pentium" /* Default */ 320 }, 321 NULL, 322 NULL, 323 NULL, 324 }, 325 /* Family 6 */ 326 { 327 CPUCLASS_686, 328 { 329 "Pentium Pro (A-step)", "Pentium Pro", 0, 330 "Pentium II (Klamath)", "Pentium Pro", 331 "Pentium II/Celeron (Deschutes)", 332 "Celeron (Mendocino)", 333 "Pentium III (Katmai)", 334 "Pentium III (Coppermine)", 335 "Pentium M (Banias)", 336 "Pentium III Xeon (Cascades)", 337 "Pentium III (Tualatin)", 0, 338 "Pentium M (Dothan)", 339 "Pentium M (Yonah)", 340 "Core 2 (Merom)", 341 "Pentium Pro, II or III" /* Default */ 342 }, 343 NULL, 344 intel_family_new_probe, 345 NULL, 346 }, 347 /* Family > 6 */ 348 { 349 CPUCLASS_686, 350 { 351 0, 0, 0, 0, 0, 0, 0, 0, 352 0, 0, 0, 0, 0, 0, 0, 0, 353 "Pentium 4" /* Default */ 354 }, 355 NULL, 356 intel_family_new_probe, 357 NULL, 358 } } 359 }, 360 { 361 "AuthenticAMD", 362 CPUVENDOR_AMD, 363 "AMD", 364 /* Family 4 */ 365 { { 366 CPUCLASS_486, 367 { 368 0, 0, 0, "Am486DX2 W/T", 369 0, 0, 0, "Am486DX2 W/B", 370 "Am486DX4 W/T or Am5x86 W/T 150", 371 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 372 0, 0, "Am5x86 W/T 133/160", 373 "Am5x86 W/B 133/160", 374 "Am486 or Am5x86" /* Default */ 375 }, 376 NULL, 377 NULL, 378 NULL, 379 }, 380 /* Family 5 */ 381 { 382 CPUCLASS_586, 383 { 384 "K5", "K5", "K5", "K5", 0, 0, "K6", 385 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 386 "K6-2+/III+", 0, 0, 387 "K5 or K6" /* Default */ 388 }, 389 amd_family5_setup, 390 NULL, 391 amd_cpu_cacheinfo, 392 }, 393 /* Family 6 */ 394 { 395 CPUCLASS_686, 396 { 397 0, "Athlon Model 1", "Athlon Model 2", 398 "Duron", "Athlon Model 4 (Thunderbird)", 399 0, "Athlon", "Duron", "Athlon", 0, 400 "Athlon", 0, 0, 0, 0, 0, 401 "K7 (Athlon)" /* Default */ 402 }, 403 NULL, 404 amd_family6_probe, 405 amd_cpu_cacheinfo, 406 }, 407 /* Family > 6 */ 408 { 409 CPUCLASS_686, 410 { 411 0, 0, 0, 0, 0, 0, 0, 0, 412 0, 0, 0, 0, 0, 0, 0, 0, 413 "Unknown K8 (Athlon)" /* Default */ 414 }, 415 NULL, 416 amd_family6_probe, 417 amd_cpu_cacheinfo, 418 } } 419 }, 420 { 421 "CyrixInstead", 422 CPUVENDOR_CYRIX, 423 "Cyrix", 424 /* Family 4 */ 425 { { 426 CPUCLASS_486, 427 { 428 0, 0, 0, 429 "MediaGX", 430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 431 "486" /* Default */ 432 }, 433 cyrix6x86_cpu_setup, /* XXX ?? */ 434 NULL, 435 NULL, 436 }, 437 /* Family 5 */ 438 { 439 CPUCLASS_586, 440 { 441 0, 0, "6x86", 0, 442 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 444 "6x86" /* Default */ 445 }, 446 cyrix6x86_cpu_setup, 447 NULL, 448 NULL, 449 }, 450 /* Family 6 */ 451 { 452 CPUCLASS_686, 453 { 454 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 455 0, 0, 0, 0, 0, 0, 0, 0, 456 "6x86MX" /* Default */ 457 }, 458 cyrix6x86_cpu_setup, 459 NULL, 460 NULL, 461 }, 462 /* Family > 6 */ 463 { 464 CPUCLASS_686, 465 { 466 0, 0, 0, 0, 0, 0, 0, 0, 467 0, 0, 0, 0, 0, 0, 0, 0, 468 "Unknown 6x86MX" /* Default */ 469 }, 470 NULL, 471 NULL, 472 NULL, 473 } } 474 }, 475 { /* MediaGX is now owned by National Semiconductor */ 476 "Geode by NSC", 477 CPUVENDOR_CYRIX, /* XXX */ 478 "National Semiconductor", 479 /* Family 4, NSC never had any of these */ 480 { { 481 CPUCLASS_486, 482 { 483 0, 0, 0, 0, 0, 0, 0, 0, 484 0, 0, 0, 0, 0, 0, 0, 0, 485 "486 compatible" /* Default */ 486 }, 487 NULL, 488 NULL, 489 NULL, 490 }, 491 /* Family 5: Geode family, formerly MediaGX */ 492 { 493 CPUCLASS_586, 494 { 495 0, 0, 0, 0, 496 "Geode GX1", 497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 498 "Geode" /* Default */ 499 }, 500 cyrix6x86_cpu_setup, 501 NULL, 502 amd_cpu_cacheinfo, 503 }, 504 /* Family 6, not yet available from NSC */ 505 { 506 CPUCLASS_686, 507 { 508 0, 0, 0, 0, 0, 0, 0, 0, 509 0, 0, 0, 0, 0, 0, 0, 0, 510 "Pentium Pro compatible" /* Default */ 511 }, 512 NULL, 513 NULL, 514 NULL, 515 }, 516 /* Family > 6, not yet available from NSC */ 517 { 518 CPUCLASS_686, 519 { 520 0, 0, 0, 0, 0, 0, 0, 0, 521 0, 0, 0, 0, 0, 0, 0, 0, 522 "Pentium Pro compatible" /* Default */ 523 }, 524 NULL, 525 NULL, 526 NULL, 527 } } 528 }, 529 { 530 "CentaurHauls", 531 CPUVENDOR_IDT, 532 "IDT", 533 /* Family 4, IDT never had any of these */ 534 { { 535 CPUCLASS_486, 536 { 537 0, 0, 0, 0, 0, 0, 0, 0, 538 0, 0, 0, 0, 0, 0, 0, 0, 539 "486 compatible" /* Default */ 540 }, 541 NULL, 542 NULL, 543 NULL, 544 }, 545 /* Family 5 */ 546 { 547 CPUCLASS_586, 548 { 549 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 550 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 551 "WinChip" /* Default */ 552 }, 553 winchip_cpu_setup, 554 NULL, 555 NULL, 556 }, 557 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 558 { 559 CPUCLASS_686, 560 { 561 0, 0, 0, 0, 0, 0, "C3 Samuel", 562 "C3 Samuel 2/Ezra", "C3 Ezra-T", 563 "C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0, 564 "C3" /* Default */ 565 }, 566 NULL, 567 via_cpu_probe, 568 via_cpu_cacheinfo, 569 }, 570 /* Family > 6, not yet available from VIA */ 571 { 572 CPUCLASS_686, 573 { 574 0, 0, 0, 0, 0, 0, 0, 0, 575 0, 0, 0, 0, 0, 0, 0, 0, 576 "Pentium Pro compatible" /* Default */ 577 }, 578 NULL, 579 NULL, 580 NULL, 581 } } 582 }, 583 { 584 "GenuineTMx86", 585 CPUVENDOR_TRANSMETA, 586 "Transmeta", 587 /* Family 4, Transmeta never had any of these */ 588 { { 589 CPUCLASS_486, 590 { 591 0, 0, 0, 0, 0, 0, 0, 0, 592 0, 0, 0, 0, 0, 0, 0, 0, 593 "486 compatible" /* Default */ 594 }, 595 NULL, 596 NULL, 597 NULL, 598 }, 599 /* Family 5 */ 600 { 601 CPUCLASS_586, 602 { 603 0, 0, 0, 0, 0, 0, 0, 0, 604 0, 0, 0, 0, 0, 0, 0, 0, 605 "Crusoe" /* Default */ 606 }, 607 NULL, 608 NULL, 609 transmeta_cpu_info, 610 }, 611 /* Family 6, not yet available from Transmeta */ 612 { 613 CPUCLASS_686, 614 { 615 0, 0, 0, 0, 0, 0, 0, 0, 616 0, 0, 0, 0, 0, 0, 0, 0, 617 "Pentium Pro compatible" /* Default */ 618 }, 619 NULL, 620 NULL, 621 NULL, 622 }, 623 /* Family > 6, not yet available from Transmeta */ 624 { 625 CPUCLASS_686, 626 { 627 0, 0, 0, 0, 0, 0, 0, 0, 628 0, 0, 0, 0, 0, 0, 0, 0, 629 "Pentium Pro compatible" /* Default */ 630 }, 631 NULL, 632 NULL, 633 NULL, 634 } } 635 } 636 }; 637 638 /* 639 * disable the TSC such that we don't use the TSC in microtime(9) 640 * because some CPUs got the implementation wrong. 641 */ 642 static void 643 disable_tsc(struct cpu_info *ci) 644 { 645 if (ci->ci_feature_flags & CPUID_TSC) { 646 ci->ci_feature_flags &= ~CPUID_TSC; 647 aprint_error("WARNING: broken TSC disabled\n"); 648 } 649 } 650 651 static void 652 cyrix6x86_cpu_setup(struct cpu_info *ci) 653 { 654 655 /* 656 * Do not disable the TSC on the Geode GX, it's reported to 657 * work fine. 658 */ 659 if (ci->ci_signature != 0x552) 660 disable_tsc(ci); 661 } 662 663 void 664 winchip_cpu_setup(struct cpu_info *ci) 665 { 666 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 667 case 4: /* WinChip C6 */ 668 disable_tsc(ci); 669 } 670 } 671 672 673 static void 674 identifycpu_cpuids(struct cpu_info *ci) 675 { 676 const char *cpuname = ci->ci_dev; 677 u_int lp_max = 1; /* logical processors per package */ 678 u_int smt_max; /* smt per core */ 679 u_int core_max = 1; /* core per package */ 680 int smt_bits, core_bits; 681 uint32_t descs[4]; 682 683 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 684 ci->ci_packageid = ci->ci_initapicid; 685 ci->ci_coreid = 0; 686 ci->ci_smtid = 0; 687 if (cpu_vendor != CPUVENDOR_INTEL) { 688 return; 689 } 690 691 /* 692 * 253668.pdf 7.10.2 693 */ 694 695 if ((ci->ci_feature_flags & CPUID_HTT) != 0) { 696 x86_cpuid(1, descs); 697 lp_max = (descs[1] >> 16) & 0xff; 698 } 699 x86_cpuid(0, descs); 700 if (descs[0] >= 4) { 701 x86_cpuid2(4, 0, descs); 702 core_max = (descs[0] >> 26) + 1; 703 } 704 assert(lp_max >= core_max); 705 smt_max = lp_max / core_max; 706 smt_bits = ilog2(smt_max - 1) + 1; 707 core_bits = ilog2(core_max - 1) + 1; 708 if (smt_bits + core_bits) { 709 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 710 } 711 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 712 ci->ci_packageid); 713 if (core_bits) { 714 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 715 716 ci->ci_coreid = 717 __SHIFTOUT(ci->ci_initapicid, core_mask); 718 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 719 } 720 if (smt_bits) { 721 u_int smt_mask = __BITS(0, smt_bits - 1); 722 723 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 724 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 725 } 726 } 727 728 static void 729 via_cpu_probe(struct cpu_info *ci) 730 { 731 u_int model = CPUID2MODEL(ci->ci_signature); 732 u_int stepping = CPUID2STEPPING(ci->ci_signature); 733 u_int descs[4]; 734 u_int lfunc; 735 736 /* 737 * Determine the largest extended function value. 738 */ 739 x86_cpuid(0x80000000, descs); 740 lfunc = descs[0]; 741 742 /* 743 * Determine the extended feature flags. 744 */ 745 if (lfunc >= 0x80000001) { 746 x86_cpuid(0x80000001, descs); 747 ci->ci_feature_flags |= descs[3]; 748 } 749 750 if (model < 0x9) 751 return; 752 753 /* Nehemiah or Esther */ 754 x86_cpuid(0xc0000000, descs); 755 lfunc = descs[0]; 756 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 757 return; 758 759 x86_cpuid(0xc0000001, descs); 760 lfunc = descs[3]; 761 if (model > 0x9 || stepping >= 8) { /* ACE */ 762 if (lfunc & CPUID_VIA_HAS_ACE) { 763 ci->ci_padlock_flags = lfunc; 764 } 765 } 766 } 767 768 static const char * 769 intel_family6_name(struct cpu_info *ci) 770 { 771 int model = CPUID2MODEL(ci->ci_signature); 772 const char *ret = NULL; 773 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 774 775 if (model == 5) { 776 switch (l2cache) { 777 case 0: 778 case 128 * 1024: 779 ret = "Celeron (Covington)"; 780 break; 781 case 256 * 1024: 782 ret = "Mobile Pentium II (Dixon)"; 783 break; 784 case 512 * 1024: 785 ret = "Pentium II"; 786 break; 787 case 1 * 1024 * 1024: 788 case 2 * 1024 * 1024: 789 ret = "Pentium II Xeon"; 790 break; 791 } 792 } else if (model == 6) { 793 switch (l2cache) { 794 case 256 * 1024: 795 case 512 * 1024: 796 ret = "Mobile Pentium II"; 797 break; 798 } 799 } else if (model == 7) { 800 switch (l2cache) { 801 case 512 * 1024: 802 ret = "Pentium III"; 803 break; 804 case 1 * 1024 * 1024: 805 case 2 * 1024 * 1024: 806 ret = "Pentium III Xeon"; 807 break; 808 } 809 } else if (model >= 8) { 810 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 811 switch (ci->ci_brand_id) { 812 case 0x3: 813 if (ci->ci_signature == 0x6B1) 814 ret = "Celeron"; 815 break; 816 case 0x8: 817 if (ci->ci_signature >= 0xF13) 818 ret = "genuine processor"; 819 break; 820 case 0xB: 821 if (ci->ci_signature >= 0xF13) 822 ret = "Xeon MP"; 823 break; 824 case 0xE: 825 if (ci->ci_signature < 0xF13) 826 ret = "Xeon"; 827 break; 828 } 829 if (ret == NULL) 830 ret = i386_intel_brand[ci->ci_brand_id]; 831 } 832 } 833 834 return ret; 835 } 836 837 /* 838 * Identify AMD64 CPU names from cpuid. 839 * 840 * Based on: 841 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 842 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 843 * "Revision Guide for AMD NPT Family 0Fh Processors" 844 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 845 * and other miscellaneous reports. 846 */ 847 static const char * 848 amd_amd64_name(struct cpu_info *ci) 849 { 850 int extfamily, extmodel, model; 851 const char *ret = NULL; 852 853 model = CPUID2MODEL(ci->ci_signature); 854 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 855 extmodel = CPUID2EXTMODEL(ci->ci_signature); 856 857 if (extfamily == 0x00) { 858 switch (model) { 859 case 0x1: 860 switch (extmodel) { 861 case 0x2: /* rev JH-E1/E6 */ 862 case 0x4: /* rev JH-F2 */ 863 ret = "Dual-Core Opteron"; 864 break; 865 } 866 break; 867 case 0x3: 868 switch (extmodel) { 869 case 0x2: /* rev JH-E6 (Toledo) */ 870 ret = "Dual-Core Opteron or Athlon 64 X2"; 871 break; 872 case 0x4: /* rev JH-F2 (Windsor) */ 873 ret = "Athlon 64 FX or Athlon 64 X2"; 874 break; 875 } 876 break; 877 case 0x4: 878 switch (extmodel) { 879 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 880 case 0x1: /* rev SH-D0 */ 881 ret = "Athlon 64"; 882 break; 883 case 0x2: /* rev SH-E5 (Lancaster?) */ 884 ret = "Mobile Athlon 64 or Turion 64"; 885 break; 886 } 887 break; 888 case 0x5: 889 switch (extmodel) { 890 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 891 ret = "Opteron or Athlon 64 FX"; 892 break; 893 case 0x1: /* rev SH-D0 */ 894 case 0x2: /* rev SH-E4 */ 895 ret = "Opteron"; 896 break; 897 } 898 break; 899 case 0x7: 900 switch (extmodel) { 901 case 0x0: /* rev SH-CG (ClawHammer) */ 902 case 0x1: /* rev SH-D0 */ 903 ret = "Athlon 64"; 904 break; 905 case 0x2: /* rev DH-E4, SH-E4 */ 906 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 907 break; 908 } 909 break; 910 case 0x8: 911 switch (extmodel) { 912 case 0x0: /* rev CH-CG */ 913 case 0x1: /* rev CH-D0 */ 914 ret = "Athlon 64 or Sempron"; 915 break; 916 case 0x4: /* rev BH-F2 */ 917 ret = "Turion 64 X2"; 918 break; 919 } 920 break; 921 case 0xb: 922 switch (extmodel) { 923 case 0x0: /* rev CH-CG */ 924 case 0x1: /* rev CH-D0 */ 925 ret = "Athlon 64"; 926 break; 927 case 0x2: /* rev BH-E4 (Manchester) */ 928 case 0x4: /* rev BH-F2 (Windsor) */ 929 ret = "Athlon 64 X2"; 930 break; 931 case 0x6: /* rev BH-G1 (Brisbane) */ 932 ret = "Athlon X2 or Athlon 64 X2"; 933 break; 934 } 935 break; 936 case 0xc: 937 switch (extmodel) { 938 case 0x0: /* rev DH-CG (Newcastle) */ 939 case 0x1: /* rev DH-D0 (Winchester) */ 940 case 0x2: /* rev DH-E3/E6 */ 941 ret = "Athlon 64 or Sempron"; 942 break; 943 } 944 break; 945 case 0xe: 946 switch (extmodel) { 947 case 0x0: /* rev DH-CG (Newcastle?) */ 948 ret = "Athlon 64 or Sempron"; 949 break; 950 } 951 break; 952 case 0xf: 953 switch (extmodel) { 954 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 955 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 956 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 957 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 958 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 959 case 0x6: /* rev DH-G1 */ 960 ret = "Athlon 64 or Sempron"; 961 break; 962 } 963 break; 964 default: 965 ret = "Unknown AMD64 CPU"; 966 } 967 } 968 969 return ret; 970 } 971 972 static void 973 cpu_probe_base_features(struct cpu_info *ci) 974 { 975 const struct x86_cache_info *cai; 976 u_int descs[4]; 977 int iterations, i, j; 978 uint8_t desc; 979 uint32_t miscbytes; 980 uint32_t brand[12]; 981 982 if (ci->ci_cpuid_level < 0) 983 return; 984 985 x86_cpuid(0, descs); 986 ci->ci_cpuid_level = descs[0]; 987 ci->ci_vendor[0] = descs[1]; 988 ci->ci_vendor[2] = descs[2]; 989 ci->ci_vendor[1] = descs[3]; 990 ci->ci_vendor[3] = 0; 991 992 x86_cpuid(0x80000000, brand); 993 if (brand[0] >= 0x80000004) { 994 x86_cpuid(0x80000002, brand); 995 x86_cpuid(0x80000003, brand + 4); 996 x86_cpuid(0x80000004, brand + 8); 997 for (i = 0; i < 48; i++) 998 if (((char *) brand)[i] != ' ') 999 break; 1000 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1001 } 1002 1003 if (ci->ci_cpuid_level < 1) 1004 return; 1005 1006 x86_cpuid(1, descs); 1007 ci->ci_signature = descs[0]; 1008 miscbytes = descs[1]; 1009 ci->ci_feature2_flags = descs[2]; 1010 ci->ci_feature_flags = descs[3]; 1011 1012 /* Brand is low order 8 bits of ebx */ 1013 ci->ci_brand_id = miscbytes & 0xff; 1014 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1015 if (ci->ci_cpuid_level < 2) 1016 return; 1017 1018 /* 1019 * Parse the cache info from `cpuid', if we have it. 1020 * XXX This is kinda ugly, but hey, so is the architecture... 1021 */ 1022 1023 x86_cpuid(2, descs); 1024 1025 iterations = descs[0] & 0xff; 1026 while (iterations-- > 0) { 1027 for (i = 0; i < 4; i++) { 1028 if (descs[i] & 0x80000000) 1029 continue; 1030 for (j = 0; j < 4; j++) { 1031 if (i == 0 && j == 0) 1032 continue; 1033 desc = (descs[i] >> (j * 8)) & 0xff; 1034 if (desc == 0) 1035 continue; 1036 cai = cache_info_lookup(intel_cpuid_cache_info, 1037 desc); 1038 if (cai != NULL) 1039 ci->ci_cinfo[cai->cai_index] = *cai; 1040 } 1041 } 1042 x86_cpuid(2, descs); 1043 } 1044 1045 if (ci->ci_cpuid_level < 3) 1046 return; 1047 1048 /* 1049 * If the processor serial number misfeature is present and supported, 1050 * extract it here. 1051 */ 1052 if ((ci->ci_feature_flags & CPUID_PN) != 0) { 1053 ci->ci_cpu_serial[0] = ci->ci_signature; 1054 x86_cpuid(3, descs); 1055 ci->ci_cpu_serial[2] = descs[2]; 1056 ci->ci_cpu_serial[1] = descs[3]; 1057 } 1058 } 1059 1060 static void 1061 cpu_probe_features(struct cpu_info *ci) 1062 { 1063 const struct cpu_cpuid_nameclass *cpup = NULL; 1064 int i, xmax, family; 1065 1066 cpu_probe_base_features(ci); 1067 1068 if (ci->ci_cpuid_level < 1) 1069 return; 1070 1071 xmax = __arraycount(i386_cpuid_cpus); 1072 for (i = 0; i < xmax; i++) { 1073 if (!strncmp((char *)ci->ci_vendor, 1074 i386_cpuid_cpus[i].cpu_id, 12)) { 1075 cpup = &i386_cpuid_cpus[i]; 1076 break; 1077 } 1078 } 1079 1080 if (cpup == NULL) 1081 return; 1082 1083 family = (ci->ci_signature >> 8) & 0xf; 1084 1085 if (family > CPU_MAXFAMILY) { 1086 family = CPU_MAXFAMILY; 1087 } 1088 i = family - CPU_MINFAMILY; 1089 1090 if (cpup->cpu_family[i].cpu_probe == NULL) 1091 return; 1092 1093 (*cpup->cpu_family[i].cpu_probe)(ci); 1094 } 1095 1096 static void 1097 intel_family_new_probe(struct cpu_info *ci) 1098 { 1099 uint32_t descs[4]; 1100 1101 x86_cpuid(0x80000000, descs); 1102 1103 /* 1104 * Determine extended feature flags. 1105 */ 1106 if (descs[0] >= 0x80000001) { 1107 x86_cpuid(0x80000001, descs); 1108 ci->ci_feature3_flags |= descs[3]; 1109 } 1110 } 1111 1112 static void 1113 amd_family6_probe(struct cpu_info *ci) 1114 { 1115 uint32_t descs[4]; 1116 char *p; 1117 int i; 1118 1119 x86_cpuid(0x80000000, descs); 1120 1121 /* 1122 * Determine the extended feature flags. 1123 */ 1124 if (descs[0] >= 0x80000001) { 1125 x86_cpuid(0x80000001, descs); 1126 ci->ci_feature_flags |= descs[3]; 1127 } 1128 1129 if (*cpu_brand_string == '\0') 1130 return; 1131 1132 for (i = 1; i < __arraycount(amd_brand); i++) 1133 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1134 ci->ci_brand_id = i; 1135 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1136 break; 1137 } 1138 } 1139 1140 static void 1141 amd_family5_setup(struct cpu_info *ci) 1142 { 1143 1144 switch (CPUID2MODEL(ci->ci_signature)) { 1145 case 0: /* AMD-K5 Model 0 */ 1146 /* 1147 * According to the AMD Processor Recognition App Note, 1148 * the AMD-K5 Model 0 uses the wrong bit to indicate 1149 * support for global PTEs, instead using bit 9 (APIC) 1150 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1151 */ 1152 if (ci->ci_feature_flags & CPUID_APIC) 1153 ci->ci_feature_flags = (ci->ci_feature_flags & ~CPUID_APIC) | CPUID_PGE; 1154 /* 1155 * XXX But pmap_pg_g is already initialized -- need to kick 1156 * XXX the pmap somehow. How does the MP branch do this? 1157 */ 1158 break; 1159 } 1160 } 1161 1162 static void 1163 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1164 { 1165 u_int descs[4]; 1166 1167 x86_cpuid(0x80860007, descs); 1168 *frequency = descs[0]; 1169 *voltage = descs[1]; 1170 *percentage = descs[2]; 1171 } 1172 1173 static void 1174 transmeta_cpu_info(struct cpu_info *ci) 1175 { 1176 u_int descs[4], nreg; 1177 u_int frequency, voltage, percentage; 1178 1179 x86_cpuid(0x80860000, descs); 1180 nreg = descs[0]; 1181 if (nreg >= 0x80860001) { 1182 x86_cpuid(0x80860001, descs); 1183 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1184 (descs[1] >> 24) & 0xff, 1185 (descs[1] >> 16) & 0xff, 1186 (descs[1] >> 8) & 0xff, 1187 descs[1] & 0xff); 1188 } 1189 if (nreg >= 0x80860002) { 1190 x86_cpuid(0x80860002, descs); 1191 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1192 (descs[1] >> 24) & 0xff, 1193 (descs[1] >> 16) & 0xff, 1194 (descs[1] >> 8) & 0xff, 1195 descs[1] & 0xff, 1196 descs[2]); 1197 } 1198 if (nreg >= 0x80860006) { 1199 union { 1200 char text[65]; 1201 u_int descs[4][4]; 1202 } info; 1203 int i; 1204 1205 for (i=0; i<4; i++) { 1206 x86_cpuid(0x80860003 + i, info.descs[i]); 1207 } 1208 info.text[64] = '\0'; 1209 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1210 } 1211 1212 if (nreg >= 0x80860007) { 1213 tmx86_get_longrun_status(&frequency, 1214 &voltage, &percentage); 1215 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1216 frequency, voltage, percentage); 1217 } 1218 } 1219 1220 void 1221 identifycpu(const char *cpuname) 1222 { 1223 const char *name, *modifier, *vendorname, *brand = ""; 1224 int class = CPUCLASS_386, i, xmax; 1225 int modif, family, model; 1226 const struct cpu_cpuid_nameclass *cpup = NULL; 1227 const struct cpu_cpuid_family *cpufam; 1228 char *buf; 1229 const char *feature_str[3]; 1230 struct cpu_info *ci, cistore; 1231 extern int cpu; 1232 extern int cpu_info_level; 1233 size_t sz; 1234 1235 ci = &cistore; 1236 memset(ci, 0, sizeof(*ci)); 1237 ci->ci_dev = cpuname; 1238 1239 x86_identify(); 1240 ci->ci_cpuid_level = cpu_info_level; 1241 cpu_probe_features(ci); 1242 1243 buf = malloc(MAXPATHLEN); 1244 if (ci->ci_cpuid_level == -1) { 1245 if (cpu < 0 || cpu >= __arraycount(i386_nocpuid_cpus)) 1246 errx(1, "unknown cpu type %d", cpu); 1247 name = i386_nocpuid_cpus[cpu].cpu_name; 1248 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1249 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1250 class = i386_nocpuid_cpus[cpu].cpu_class; 1251 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1252 modifier = ""; 1253 } else { 1254 xmax = __arraycount(i386_cpuid_cpus); 1255 modif = (ci->ci_signature >> 12) & 0x3; 1256 family = CPUID2FAMILY(ci->ci_signature); 1257 if (family < CPU_MINFAMILY) 1258 errx(1, "identifycpu: strange family value"); 1259 model = CPUID2MODEL(ci->ci_signature); 1260 1261 for (i = 0; i < xmax; i++) { 1262 if (!strncmp((char *)ci->ci_vendor, 1263 i386_cpuid_cpus[i].cpu_id, 12)) { 1264 cpup = &i386_cpuid_cpus[i]; 1265 break; 1266 } 1267 } 1268 1269 if (cpup == NULL) { 1270 cpu_vendor = CPUVENDOR_UNKNOWN; 1271 if (ci->ci_vendor[0] != '\0') 1272 vendorname = (char *)&ci->ci_vendor[0]; 1273 else 1274 vendorname = "Unknown"; 1275 if (family >= CPU_MAXFAMILY) 1276 family = CPU_MINFAMILY; 1277 class = family - 3; 1278 modifier = ""; 1279 name = ""; 1280 ci->ci_info = NULL; 1281 } else { 1282 cpu_vendor = cpup->cpu_vendor; 1283 vendorname = cpup->cpu_vendorname; 1284 modifier = modifiers[modif]; 1285 if (family > CPU_MAXFAMILY) { 1286 family = CPU_MAXFAMILY; 1287 model = CPU_DEFMODEL; 1288 } else if (model > CPU_MAXMODEL) 1289 model = CPU_DEFMODEL; 1290 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1291 name = cpufam->cpu_models[model]; 1292 if (name == NULL) 1293 name = cpufam->cpu_models[CPU_DEFMODEL]; 1294 class = cpufam->cpu_class; 1295 ci->ci_info = cpufam->cpu_info; 1296 1297 if (cpu_vendor == CPUVENDOR_INTEL) { 1298 if (family == 6 && model >= 5) { 1299 const char *tmp; 1300 tmp = intel_family6_name(ci); 1301 if (tmp != NULL) 1302 name = tmp; 1303 } 1304 if (family == CPU_MAXFAMILY && 1305 ci->ci_brand_id < 1306 __arraycount(i386_intel_brand) && 1307 i386_intel_brand[ci->ci_brand_id]) 1308 name = 1309 i386_intel_brand[ci->ci_brand_id]; 1310 } 1311 1312 if (cpu_vendor == CPUVENDOR_AMD) { 1313 if (family == 6 && model >= 6) { 1314 if (ci->ci_brand_id == 1) 1315 /* 1316 * It's Duron. We override the 1317 * name, since it might have 1318 * been misidentified as Athlon. 1319 */ 1320 name = 1321 amd_brand[ci->ci_brand_id]; 1322 else 1323 brand = amd_brand_name; 1324 } 1325 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1326 /* 1327 * Identify AMD64 CPU names. 1328 * Note family value is clipped by 1329 * CPU_MAXFAMILY. 1330 */ 1331 const char *tmp; 1332 tmp = amd_amd64_name(ci); 1333 if (tmp != NULL) 1334 name = tmp; 1335 } 1336 } 1337 1338 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1339 vendorname = "VIA"; 1340 } 1341 } 1342 1343 ci->ci_cpu_class = class; 1344 1345 sz = sizeof(ci->ci_tsc_freq); 1346 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1347 1348 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1349 vendorname, 1350 *modifier ? " " : "", modifier, 1351 *name ? " " : "", name, 1352 *brand ? " " : "", brand, 1353 classnames[class]); 1354 aprint_normal("%s: %s", cpuname, cpu_model); 1355 1356 if (ci->ci_tsc_freq != 0) 1357 aprint_normal(", %qd.%02qd MHz", 1358 (ci->ci_tsc_freq + 4999) / 1000000, 1359 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1360 if (ci->ci_signature != 0) 1361 aprint_normal(", id 0x%x", ci->ci_signature); 1362 aprint_normal("\n"); 1363 1364 if (ci->ci_info) 1365 (*ci->ci_info)(ci); 1366 1367 if (cpu_vendor == CPUVENDOR_INTEL) { 1368 feature_str[0] = CPUID_FLAGS1; 1369 feature_str[1] = CPUID_FLAGS2; 1370 feature_str[2] = CPUID_FLAGS3; 1371 } else { 1372 feature_str[0] = CPUID_FLAGS1; 1373 feature_str[1] = CPUID_EXT_FLAGS2; 1374 feature_str[2] = CPUID_EXT_FLAGS3; 1375 } 1376 1377 if (ci->ci_feature_flags) { 1378 if ((ci->ci_feature_flags & CPUID_MASK1) != 0) { 1379 bitmask_snprintf(ci->ci_feature_flags, 1380 feature_str[0], buf, MAXPATHLEN); 1381 aprint_verbose("%s: features %s\n", cpuname, buf); 1382 } 1383 if ((ci->ci_feature_flags & CPUID_MASK2) != 0) { 1384 bitmask_snprintf(ci->ci_feature_flags, 1385 feature_str[1], buf, MAXPATHLEN); 1386 aprint_verbose("%s: features %s\n", cpuname, buf); 1387 } 1388 if ((ci->ci_feature_flags & CPUID_MASK3) != 0) { 1389 bitmask_snprintf(ci->ci_feature_flags, 1390 feature_str[2], buf, MAXPATHLEN); 1391 aprint_verbose("%s: features %s\n", cpuname, buf); 1392 } 1393 } 1394 1395 if (ci->ci_feature2_flags) { 1396 bitmask_snprintf(ci->ci_feature2_flags, 1397 CPUID2_FLAGS, buf, MAXPATHLEN); 1398 aprint_verbose("%s: features2 %s\n", cpuname, buf); 1399 } 1400 1401 if (ci->ci_feature3_flags) { 1402 bitmask_snprintf(ci->ci_feature3_flags, 1403 CPUID_FLAGS4, buf, MAXPATHLEN); 1404 aprint_verbose("%s: features3 %s\n", cpuname, buf); 1405 } 1406 1407 if (ci->ci_padlock_flags) { 1408 bitmask_snprintf(ci->ci_padlock_flags, 1409 CPUID_FLAGS_PADLOCK, buf, MAXPATHLEN); 1410 aprint_verbose("%s: padlock features %s\n", cpuname, buf); 1411 } 1412 1413 free(buf); 1414 1415 if (*cpu_brand_string != '\0') 1416 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1417 1418 x86_print_cacheinfo(ci); 1419 1420 if (ci->ci_cpuid_level >= 3 && (ci->ci_feature_flags & CPUID_PN)) { 1421 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1422 cpuname, 1423 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1424 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1425 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1426 } 1427 1428 if (ci->ci_cpu_class == CPUCLASS_386) { 1429 errx(1, "NetBSD requires an 80486 or later processor"); 1430 } 1431 1432 if (cpu == CPU_486DLC) { 1433 #ifndef CYRIX_CACHE_WORKS 1434 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1435 #else 1436 #ifndef CYRIX_CACHE_REALLY_WORKS 1437 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1438 #else 1439 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1440 #endif 1441 #endif 1442 } 1443 1444 /* 1445 * Everything past this point requires a Pentium or later. 1446 */ 1447 if (ci->ci_cpuid_level < 0) 1448 return; 1449 1450 identifycpu_cpuids(ci); 1451 1452 #ifdef INTEL_CORETEMP 1453 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1454 coretemp_register(ci); 1455 #endif 1456 1457 if (cpu_vendor == CPUVENDOR_AMD) { 1458 powernow_probe(ci); 1459 } 1460 1461 #ifdef INTEL_ONDEMAND_CLOCKMOD 1462 clockmod_init(); 1463 #endif 1464 1465 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1466 "extfamily %02x extmodel %02x\n", CPUID2FAMILY(ci->ci_signature), 1467 CPUID2MODEL(ci->ci_signature), CPUID2EXTFAMILY(ci->ci_signature), 1468 CPUID2EXTMODEL(ci->ci_signature)); 1469 } 1470 1471 static const char * 1472 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1473 const char *sep) 1474 { 1475 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1476 1477 if (cai->cai_totalsize == 0) 1478 return sep; 1479 1480 if (sep == NULL) 1481 aprint_verbose_dev(ci->ci_dev, ""); 1482 else 1483 aprint_verbose("%s", sep); 1484 if (name != NULL) 1485 aprint_verbose("%s ", name); 1486 1487 if (cai->cai_string != NULL) { 1488 aprint_verbose("%s ", cai->cai_string); 1489 } else { 1490 aprint_verbose("%dkB %dB/line ", cai->cai_totalsize / 1024, 1491 cai->cai_linesize); 1492 } 1493 switch (cai->cai_associativity) { 1494 case 0: 1495 aprint_verbose("disabled"); 1496 break; 1497 case 1: 1498 aprint_verbose("direct-mapped"); 1499 break; 1500 case 0xff: 1501 aprint_verbose("fully associative"); 1502 break; 1503 default: 1504 aprint_verbose("%d-way", cai->cai_associativity); 1505 break; 1506 } 1507 return ", "; 1508 } 1509 1510 static const char * 1511 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1512 const char *sep) 1513 { 1514 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1515 1516 if (cai->cai_totalsize == 0) 1517 return sep; 1518 1519 if (sep == NULL) 1520 aprint_verbose_dev(ci->ci_dev, ""); 1521 else 1522 aprint_verbose("%s", sep); 1523 if (name != NULL) 1524 aprint_verbose("%s ", name); 1525 1526 if (cai->cai_string != NULL) { 1527 aprint_verbose("%s", cai->cai_string); 1528 } else { 1529 aprint_verbose("%d %dB entries ", cai->cai_totalsize, 1530 cai->cai_linesize); 1531 switch (cai->cai_associativity) { 1532 case 0: 1533 aprint_verbose("disabled"); 1534 break; 1535 case 1: 1536 aprint_verbose("direct-mapped"); 1537 break; 1538 case 0xff: 1539 aprint_verbose("fully associative"); 1540 break; 1541 default: 1542 aprint_verbose("%d-way", cai->cai_associativity); 1543 break; 1544 } 1545 } 1546 return ", "; 1547 } 1548 1549 static const struct x86_cache_info * 1550 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1551 { 1552 int i; 1553 1554 for (i = 0; cai[i].cai_desc != 0; i++) { 1555 if (cai[i].cai_desc == desc) 1556 return (&cai[i]); 1557 } 1558 1559 return (NULL); 1560 } 1561 1562 1563 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = { 1564 { 0, 0x01, 1, 0, 0, NULL }, 1565 { 0, 0x02, 2, 0, 0, NULL }, 1566 { 0, 0x04, 4, 0, 0, NULL }, 1567 { 0, 0x06, 8, 0, 0, NULL }, 1568 { 0, 0x08, 16, 0, 0, NULL }, 1569 { 0, 0x0f, 0xff, 0, 0, NULL }, 1570 { 0, 0x00, 0, 0, 0, NULL }, 1571 }; 1572 1573 static void 1574 amd_cpu_cacheinfo(struct cpu_info *ci) 1575 { 1576 const struct x86_cache_info *cp; 1577 struct x86_cache_info *cai; 1578 int family, model; 1579 u_int descs[4]; 1580 u_int lfunc; 1581 1582 family = (ci->ci_signature >> 8) & 15; 1583 model = CPUID2MODEL(ci->ci_signature); 1584 1585 /* 1586 * K5 model 0 has none of this info. 1587 */ 1588 if (family == 5 && model == 0) 1589 return; 1590 1591 /* 1592 * Get extended values for K8 and up. 1593 */ 1594 if (family == 0xf) { 1595 family += CPUID2EXTFAMILY(ci->ci_signature); 1596 model += CPUID2EXTMODEL(ci->ci_signature); 1597 } 1598 1599 /* 1600 * Determine the largest extended function value. 1601 */ 1602 x86_cpuid(0x80000000, descs); 1603 lfunc = descs[0]; 1604 1605 /* 1606 * Determine L1 cache/TLB info. 1607 */ 1608 if (lfunc < 0x80000005) { 1609 /* No L1 cache info available. */ 1610 return; 1611 } 1612 1613 x86_cpuid(0x80000005, descs); 1614 1615 /* 1616 * K6-III and higher have large page TLBs. 1617 */ 1618 if ((family == 5 && model >= 9) || family >= 6) { 1619 cai = &ci->ci_cinfo[CAI_ITLB2]; 1620 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1621 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1622 cai->cai_linesize = (4 * 1024 * 1024); 1623 1624 cai = &ci->ci_cinfo[CAI_DTLB2]; 1625 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1626 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1627 cai->cai_linesize = (4 * 1024 * 1024); 1628 } 1629 1630 cai = &ci->ci_cinfo[CAI_ITLB]; 1631 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1632 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1633 cai->cai_linesize = (4 * 1024); 1634 1635 cai = &ci->ci_cinfo[CAI_DTLB]; 1636 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1637 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1638 cai->cai_linesize = (4 * 1024); 1639 1640 cai = &ci->ci_cinfo[CAI_DCACHE]; 1641 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1642 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1643 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1644 1645 cai = &ci->ci_cinfo[CAI_ICACHE]; 1646 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1647 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1648 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1649 1650 /* 1651 * Determine L2 cache/TLB info. 1652 */ 1653 if (lfunc < 0x80000006) { 1654 /* No L2 cache info available. */ 1655 return; 1656 } 1657 1658 x86_cpuid(0x80000006, descs); 1659 1660 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1661 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1662 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1663 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1664 1665 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1666 cai->cai_associativity); 1667 if (cp != NULL) 1668 cai->cai_associativity = cp->cai_associativity; 1669 else 1670 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1671 } 1672 1673 static void 1674 via_cpu_cacheinfo(struct cpu_info *ci) 1675 { 1676 struct x86_cache_info *cai; 1677 int family, model, stepping; 1678 u_int descs[4]; 1679 u_int lfunc; 1680 1681 family = (ci->ci_signature >> 8) & 15; 1682 model = CPUID2MODEL(ci->ci_signature); 1683 stepping = CPUID2STEPPING(ci->ci_signature); 1684 1685 /* 1686 * Determine the largest extended function value. 1687 */ 1688 x86_cpuid(0x80000000, descs); 1689 lfunc = descs[0]; 1690 1691 /* 1692 * Determine L1 cache/TLB info. 1693 */ 1694 if (lfunc < 0x80000005) { 1695 /* No L1 cache info available. */ 1696 return; 1697 } 1698 1699 x86_cpuid(0x80000005, descs); 1700 1701 cai = &ci->ci_cinfo[CAI_ITLB]; 1702 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1703 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1704 cai->cai_linesize = (4 * 1024); 1705 1706 cai = &ci->ci_cinfo[CAI_DTLB]; 1707 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1708 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1709 cai->cai_linesize = (4 * 1024); 1710 1711 cai = &ci->ci_cinfo[CAI_DCACHE]; 1712 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1713 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1714 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1715 if (model == 9 && stepping == 8) { 1716 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1717 cai->cai_associativity = 2; 1718 } 1719 1720 cai = &ci->ci_cinfo[CAI_ICACHE]; 1721 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1722 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1723 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1724 if (model == 9 && stepping == 8) { 1725 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1726 cai->cai_associativity = 2; 1727 } 1728 1729 /* 1730 * Determine L2 cache/TLB info. 1731 */ 1732 if (lfunc < 0x80000006) { 1733 /* No L2 cache info available. */ 1734 return; 1735 } 1736 1737 x86_cpuid(0x80000006, descs); 1738 1739 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1740 if (model >= 9) { 1741 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1742 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1743 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1744 } else { 1745 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1746 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1747 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1748 } 1749 } 1750 1751 static void 1752 x86_print_cacheinfo(struct cpu_info *ci) 1753 { 1754 const char *sep; 1755 1756 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1757 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1758 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1759 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1760 if (sep != NULL) 1761 aprint_verbose("\n"); 1762 } 1763 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1764 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1765 if (sep != NULL) 1766 aprint_verbose("\n"); 1767 } 1768 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1769 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1770 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1771 if (sep != NULL) 1772 aprint_verbose("\n"); 1773 } 1774 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1775 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1776 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1777 if (sep != NULL) 1778 aprint_verbose("\n"); 1779 } 1780 } 1781 1782 static void 1783 powernow_probe(struct cpu_info *ci) 1784 { 1785 uint32_t regs[4]; 1786 char line[256]; 1787 1788 x86_cpuid(0x80000000, regs); 1789 1790 /* We need CPUID(0x80000007) */ 1791 if (regs[0] < 0x80000007) 1792 return; 1793 x86_cpuid(0x80000007, regs); 1794 1795 1796 1797 bitmask_snprintf(regs[3], "\20\11TscInv\10HwPState\7Clk100MHz" 1798 "\6STC\5TM\4TTP\3VID\2FID\1TS", line, sizeof(line)); 1799 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1800 line); 1801 } 1802
Indexes created Thu Sep 25 16:09:42 GMT 2025