i386.c revision 1.61
1 /* $NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.61 2014/11/11 08:23:17 skrll Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] XCR0 bits (d:0 %eax) 108 * [6] xsave flags (d:1 %eax) 109 */ 110 uint32_t ci_cpu_class; /* CPU class */ 111 uint32_t ci_brand_id; /* Intel brand id */ 112 uint32_t ci_vendor[4]; /* vendor string */ 113 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 114 uint64_t ci_tsc_freq; /* cpu cycles/second */ 115 uint8_t ci_packageid; 116 uint8_t ci_coreid; 117 uint8_t ci_smtid; 118 uint32_t ci_initapicid; 119 120 uint32_t ci_cur_xsave; 121 uint32_t ci_max_xsave; 122 123 struct x86_cache_info ci_cinfo[CAI_COUNT]; 124 void (*ci_info)(struct cpu_info *); 125 }; 126 127 struct cpu_nocpuid_nameclass { 128 int cpu_vendor; 129 const char *cpu_vendorname; 130 const char *cpu_name; 131 int cpu_class; 132 void (*cpu_setup)(struct cpu_info *); 133 void (*cpu_cacheinfo)(struct cpu_info *); 134 void (*cpu_info)(struct cpu_info *); 135 }; 136 137 struct cpu_cpuid_nameclass { 138 const char *cpu_id; 139 int cpu_vendor; 140 const char *cpu_vendorname; 141 struct cpu_cpuid_family { 142 int cpu_class; 143 const char *cpu_models[256]; 144 const char *cpu_model_default; 145 void (*cpu_setup)(struct cpu_info *); 146 void (*cpu_probe)(struct cpu_info *); 147 void (*cpu_info)(struct cpu_info *); 148 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 149 }; 150 151 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 152 153 /* 154 * Map Brand ID from cpuid instruction to brand name. 155 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 156 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 157 * Architectures Software Developer's Manual, Volume 2A". 158 */ 159 static const char * const i386_intel_brand[] = { 160 "", /* Unsupported */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Pentium III", /* Intel (R) Pentium (R) III processor */ 163 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "", /* 0x05: Reserved */ 166 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 167 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 170 "Celeron", /* Intel (R) Celeron (TM) processor */ 171 "Xeon", /* Intel (R) Xeon (TM) processor */ 172 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 173 "", /* 0x0d: Reserved */ 174 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 175 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 176 "", /* 0x10: Reserved */ 177 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 178 "Celeron M", /* Intel (R) Celeron (R) M processor */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "Celeron", /* Intel (R) Celeron (R) processor */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Pentium M", /* Intel (R) Pentium (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 }; 185 186 /* 187 * AMD processors don't have Brand IDs, so we need these names for probe. 188 */ 189 static const char * const amd_brand[] = { 190 "", 191 "Duron", /* AMD Duron(tm) */ 192 "MP", /* AMD Athlon(tm) MP */ 193 "XP", /* AMD Athlon(tm) XP */ 194 "4" /* AMD Athlon(tm) 4 */ 195 }; 196 197 static int cpu_vendor; 198 static char cpu_brand_string[49]; 199 static char amd_brand_name[48]; 200 static int use_pae, largepagesize; 201 202 /* Setup functions */ 203 static void disable_tsc(struct cpu_info *); 204 static void amd_family5_setup(struct cpu_info *); 205 static void cyrix6x86_cpu_setup(struct cpu_info *); 206 static void winchip_cpu_setup(struct cpu_info *); 207 /* Brand/Model name functions */ 208 static const char *intel_family6_name(struct cpu_info *); 209 static const char *amd_amd64_name(struct cpu_info *); 210 /* Probe functions */ 211 static void amd_family6_probe(struct cpu_info *); 212 static void powernow_probe(struct cpu_info *); 213 static void intel_family_new_probe(struct cpu_info *); 214 static void via_cpu_probe(struct cpu_info *); 215 /* (Cache) Info functions */ 216 static void intel_cpu_cacheinfo(struct cpu_info *); 217 static void amd_cpu_cacheinfo(struct cpu_info *); 218 static void via_cpu_cacheinfo(struct cpu_info *); 219 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 220 static void transmeta_cpu_info(struct cpu_info *); 221 /* Common functions */ 222 static void cpu_probe_base_features(struct cpu_info *, const char *); 223 static void cpu_probe_hv_features(struct cpu_info *, const char *); 224 static void cpu_probe_features(struct cpu_info *); 225 static void print_bits(const char *, const char *, const char *, uint32_t); 226 static void identifycpu_cpuids(struct cpu_info *); 227 static const struct x86_cache_info *cache_info_lookup( 228 const struct x86_cache_info *, uint8_t); 229 static const char *print_cache_config(struct cpu_info *, int, const char *, 230 const char *); 231 static const char *print_tlb_config(struct cpu_info *, int, const char *, 232 const char *); 233 static void x86_print_cache_and_tlb_info(struct cpu_info *); 234 235 /* 236 * Note: these are just the ones that may not have a cpuid instruction. 237 * We deal with the rest in a different way. 238 */ 239 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 240 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 241 NULL, NULL, NULL }, /* CPU_386SX */ 242 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386 */ 244 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 245 NULL, NULL, NULL }, /* CPU_486SX */ 246 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486 */ 248 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486DLC */ 250 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_6x86 */ 252 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 253 NULL, NULL, NULL }, /* CPU_NX586 */ 254 }; 255 256 const char *classnames[] = { 257 "386", 258 "486", 259 "586", 260 "686" 261 }; 262 263 const char *modifiers[] = { 264 "", 265 "OverDrive", 266 "Dual", 267 "" 268 }; 269 270 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 271 { 272 /* 273 * For Intel processors, check Chapter 35Model-specific 274 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 275 * Software Developer's Manual, Volume 3C". 276 */ 277 "GenuineIntel", 278 CPUVENDOR_INTEL, 279 "Intel", 280 /* Family 4 */ 281 { { 282 CPUCLASS_486, 283 { 284 "486DX", "486DX", "486SX", "486DX2", "486SL", 285 "486SX2", 0, "486DX2 W/B Enhanced", 286 "486DX4", 0, 0, 0, 0, 0, 0, 0, 287 }, 288 "486", /* Default */ 289 NULL, 290 NULL, 291 intel_cpu_cacheinfo, 292 }, 293 /* Family 5 */ 294 { 295 CPUCLASS_586, 296 { 297 "Pentium (P5 A-step)", "Pentium (P5)", 298 "Pentium (P54C)", "Pentium (P24T)", 299 "Pentium/MMX", "Pentium", 0, 300 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 301 0, 0, 0, 0, 0, 0, 0, 302 }, 303 "Pentium", /* Default */ 304 NULL, 305 NULL, 306 intel_cpu_cacheinfo, 307 }, 308 /* Family 6 */ 309 { 310 CPUCLASS_686, 311 { 312 [0x00] = "Pentium Pro (A-step)", 313 [0x01] = "Pentium Pro", 314 [0x03] = "Pentium II (Klamath)", 315 [0x04] = "Pentium Pro", 316 [0x05] = "Pentium II/Celeron (Deschutes)", 317 [0x06] = "Celeron (Mendocino)", 318 [0x07] = "Pentium III (Katmai)", 319 [0x08] = "Pentium III (Coppermine)", 320 [0x09] = "Pentium M (Banias)", 321 [0x0a] = "Pentium III Xeon (Cascades)", 322 [0x0b] = "Pentium III (Tualatin)", 323 [0x0d] = "Pentium M (Dothan)", 324 [0x0e] = "Pentium Core Duo, Core solo", 325 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 326 "Core 2 Quad 6xxx, " 327 "Core 2 Extreme 6xxx, " 328 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 329 "and Pentium DC", 330 [0x15] = "EP80579 Integrated Processor", 331 [0x16] = "Celeron (45nm)", 332 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 333 "Core 2 Quad 8xxx and 9xxx", 334 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 335 "(Nehalem)", 336 [0x1c] = "Atom Family", 337 [0x1d] = "XeonMP 74xx (Nehalem)", 338 [0x1e] = "Core i7 and i5", 339 [0x1f] = "Core i7 and i5", 340 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 341 [0x26] = "Atom Family", 342 [0x27] = "Atom Family", 343 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 344 "i3 2xxx", 345 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 346 [0x2d] = "Xeon E5 Sandy Bridge family, " 347 "Core i7-39xx Extreme", 348 [0x2e] = "Xeon 75xx & 65xx", 349 [0x2f] = "Xeon E7 family", 350 [0x35] = "Atom Family", 351 [0x36] = "Atom S1000", 352 [0x37] = "Atom E3000, Z3000", 353 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 354 "Ivy Bridge", 355 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 356 "(Haswell)", 357 [0x3d] = "Core M-5xxx (Broadwell)", 358 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 359 "Core i7-49xx Extreme", 360 [0x3f] = "Xeon E5-2600/1600 v3 (Haswell-E), " 361 "Core i7-59xx Extreme", 362 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 363 "(Haswell)", 364 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x4a] = "Future Atom E3000, Z3000", 367 [0x4d] = "Atom C2000", 368 [0x4e] = "Future Core", 369 [0x56] = "Future Xeon", 370 [0x5a] = "Future Atom E3000, Z3000", 371 [0x5d] = "Future Atom E3000, Z3000", 372 }, 373 "Pentium Pro, II or III", /* Default */ 374 NULL, 375 intel_family_new_probe, 376 intel_cpu_cacheinfo, 377 }, 378 /* Family > 6 */ 379 { 380 CPUCLASS_686, 381 { 382 0, 0, 0, 0, 0, 0, 0, 0, 383 0, 0, 0, 0, 0, 0, 0, 0, 384 }, 385 "Pentium 4", /* Default */ 386 NULL, 387 intel_family_new_probe, 388 intel_cpu_cacheinfo, 389 } } 390 }, 391 { 392 "AuthenticAMD", 393 CPUVENDOR_AMD, 394 "AMD", 395 /* Family 4 */ 396 { { 397 CPUCLASS_486, 398 { 399 0, 0, 0, "Am486DX2 W/T", 400 0, 0, 0, "Am486DX2 W/B", 401 "Am486DX4 W/T or Am5x86 W/T 150", 402 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 403 0, 0, "Am5x86 W/T 133/160", 404 "Am5x86 W/B 133/160", 405 }, 406 "Am486 or Am5x86", /* Default */ 407 NULL, 408 NULL, 409 NULL, 410 }, 411 /* Family 5 */ 412 { 413 CPUCLASS_586, 414 { 415 "K5", "K5", "K5", "K5", 0, 0, "K6", 416 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 417 "K6-2+/III+", 0, 0, 418 }, 419 "K5 or K6", /* Default */ 420 amd_family5_setup, 421 NULL, 422 amd_cpu_cacheinfo, 423 }, 424 /* Family 6 */ 425 { 426 CPUCLASS_686, 427 { 428 0, "Athlon Model 1", "Athlon Model 2", 429 "Duron", "Athlon Model 4 (Thunderbird)", 430 0, "Athlon", "Duron", "Athlon", 0, 431 "Athlon", 0, 0, 0, 0, 0, 432 }, 433 "K7 (Athlon)", /* Default */ 434 NULL, 435 amd_family6_probe, 436 amd_cpu_cacheinfo, 437 }, 438 /* Family > 6 */ 439 { 440 CPUCLASS_686, 441 { 442 0, 0, 0, 0, 0, 0, 0, 0, 443 0, 0, 0, 0, 0, 0, 0, 0, 444 }, 445 "Unknown K8 (Athlon)", /* Default */ 446 NULL, 447 amd_family6_probe, 448 amd_cpu_cacheinfo, 449 } } 450 }, 451 { 452 "CyrixInstead", 453 CPUVENDOR_CYRIX, 454 "Cyrix", 455 /* Family 4 */ 456 { { 457 CPUCLASS_486, 458 { 459 0, 0, 0, 460 "MediaGX", 461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 }, 463 "486", /* Default */ 464 cyrix6x86_cpu_setup, /* XXX ?? */ 465 NULL, 466 NULL, 467 }, 468 /* Family 5 */ 469 { 470 CPUCLASS_586, 471 { 472 0, 0, "6x86", 0, 473 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 475 }, 476 "6x86", /* Default */ 477 cyrix6x86_cpu_setup, 478 NULL, 479 NULL, 480 }, 481 /* Family 6 */ 482 { 483 CPUCLASS_686, 484 { 485 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 486 0, 0, 0, 0, 0, 0, 0, 0, 487 }, 488 "6x86MX", /* Default */ 489 cyrix6x86_cpu_setup, 490 NULL, 491 NULL, 492 }, 493 /* Family > 6 */ 494 { 495 CPUCLASS_686, 496 { 497 0, 0, 0, 0, 0, 0, 0, 0, 498 0, 0, 0, 0, 0, 0, 0, 0, 499 }, 500 "Unknown 6x86MX", /* Default */ 501 NULL, 502 NULL, 503 NULL, 504 } } 505 }, 506 { /* MediaGX is now owned by National Semiconductor */ 507 "Geode by NSC", 508 CPUVENDOR_CYRIX, /* XXX */ 509 "National Semiconductor", 510 /* Family 4, NSC never had any of these */ 511 { { 512 CPUCLASS_486, 513 { 514 0, 0, 0, 0, 0, 0, 0, 0, 515 0, 0, 0, 0, 0, 0, 0, 0, 516 }, 517 "486 compatible", /* Default */ 518 NULL, 519 NULL, 520 NULL, 521 }, 522 /* Family 5: Geode family, formerly MediaGX */ 523 { 524 CPUCLASS_586, 525 { 526 0, 0, 0, 0, 527 "Geode GX1", 528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 529 }, 530 "Geode", /* Default */ 531 cyrix6x86_cpu_setup, 532 NULL, 533 amd_cpu_cacheinfo, 534 }, 535 /* Family 6, not yet available from NSC */ 536 { 537 CPUCLASS_686, 538 { 539 0, 0, 0, 0, 0, 0, 0, 0, 540 0, 0, 0, 0, 0, 0, 0, 0, 541 }, 542 "Pentium Pro compatible", /* Default */ 543 NULL, 544 NULL, 545 NULL, 546 }, 547 /* Family > 6, not yet available from NSC */ 548 { 549 CPUCLASS_686, 550 { 551 0, 0, 0, 0, 0, 0, 0, 0, 552 0, 0, 0, 0, 0, 0, 0, 0, 553 }, 554 "Pentium Pro compatible", /* Default */ 555 NULL, 556 NULL, 557 NULL, 558 } } 559 }, 560 { 561 "CentaurHauls", 562 CPUVENDOR_IDT, 563 "IDT", 564 /* Family 4, IDT never had any of these */ 565 { { 566 CPUCLASS_486, 567 { 568 0, 0, 0, 0, 0, 0, 0, 0, 569 0, 0, 0, 0, 0, 0, 0, 0, 570 }, 571 "486 compatible", /* Default */ 572 NULL, 573 NULL, 574 NULL, 575 }, 576 /* Family 5 */ 577 { 578 CPUCLASS_586, 579 { 580 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 581 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 582 }, 583 "WinChip", /* Default */ 584 winchip_cpu_setup, 585 NULL, 586 NULL, 587 }, 588 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 589 { 590 CPUCLASS_686, 591 { 592 0, 0, 0, 0, 0, 0, "C3 Samuel", 593 "C3 Samuel 2/Ezra", "C3 Ezra-T", 594 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 595 0, "VIA Nano", 596 }, 597 "Unknown VIA/IDT", /* Default */ 598 NULL, 599 via_cpu_probe, 600 via_cpu_cacheinfo, 601 }, 602 /* Family > 6, not yet available from VIA */ 603 { 604 CPUCLASS_686, 605 { 606 0, 0, 0, 0, 0, 0, 0, 0, 607 0, 0, 0, 0, 0, 0, 0, 0, 608 }, 609 "Pentium Pro compatible", /* Default */ 610 NULL, 611 NULL, 612 NULL, 613 } } 614 }, 615 { 616 "GenuineTMx86", 617 CPUVENDOR_TRANSMETA, 618 "Transmeta", 619 /* Family 4, Transmeta never had any of these */ 620 { { 621 CPUCLASS_486, 622 { 623 0, 0, 0, 0, 0, 0, 0, 0, 624 0, 0, 0, 0, 0, 0, 0, 0, 625 }, 626 "486 compatible", /* Default */ 627 NULL, 628 NULL, 629 NULL, 630 }, 631 /* Family 5 */ 632 { 633 CPUCLASS_586, 634 { 635 0, 0, 0, 0, 0, 0, 0, 0, 636 0, 0, 0, 0, 0, 0, 0, 0, 637 }, 638 "Crusoe", /* Default */ 639 NULL, 640 NULL, 641 transmeta_cpu_info, 642 }, 643 /* Family 6, not yet available from Transmeta */ 644 { 645 CPUCLASS_686, 646 { 647 0, 0, 0, 0, 0, 0, 0, 0, 648 0, 0, 0, 0, 0, 0, 0, 0, 649 }, 650 "Pentium Pro compatible", /* Default */ 651 NULL, 652 NULL, 653 NULL, 654 }, 655 /* Family > 6, not yet available from Transmeta */ 656 { 657 CPUCLASS_686, 658 { 659 0, 0, 0, 0, 0, 0, 0, 0, 660 0, 0, 0, 0, 0, 0, 0, 0, 661 }, 662 "Pentium Pro compatible", /* Default */ 663 NULL, 664 NULL, 665 NULL, 666 } } 667 } 668 }; 669 670 /* 671 * disable the TSC such that we don't use the TSC in microtime(9) 672 * because some CPUs got the implementation wrong. 673 */ 674 static void 675 disable_tsc(struct cpu_info *ci) 676 { 677 if (ci->ci_feat_val[0] & CPUID_TSC) { 678 ci->ci_feat_val[0] &= ~CPUID_TSC; 679 aprint_error("WARNING: broken TSC disabled\n"); 680 } 681 } 682 683 static void 684 amd_family5_setup(struct cpu_info *ci) 685 { 686 687 switch (ci->ci_model) { 688 case 0: /* AMD-K5 Model 0 */ 689 /* 690 * According to the AMD Processor Recognition App Note, 691 * the AMD-K5 Model 0 uses the wrong bit to indicate 692 * support for global PTEs, instead using bit 9 (APIC) 693 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 694 */ 695 if (ci->ci_feat_val[0] & CPUID_APIC) 696 ci->ci_feat_val[0] = 697 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 698 /* 699 * XXX But pmap_pg_g is already initialized -- need to kick 700 * XXX the pmap somehow. How does the MP branch do this? 701 */ 702 break; 703 } 704 } 705 706 static void 707 cyrix6x86_cpu_setup(struct cpu_info *ci) 708 { 709 710 /* 711 * Do not disable the TSC on the Geode GX, it's reported to 712 * work fine. 713 */ 714 if (ci->ci_signature != 0x552) 715 disable_tsc(ci); 716 } 717 718 static void 719 winchip_cpu_setup(struct cpu_info *ci) 720 { 721 switch (ci->ci_model) { 722 case 4: /* WinChip C6 */ 723 disable_tsc(ci); 724 } 725 } 726 727 728 static const char * 729 intel_family6_name(struct cpu_info *ci) 730 { 731 const char *ret = NULL; 732 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 733 734 if (ci->ci_model == 5) { 735 switch (l2cache) { 736 case 0: 737 case 128 * 1024: 738 ret = "Celeron (Covington)"; 739 break; 740 case 256 * 1024: 741 ret = "Mobile Pentium II (Dixon)"; 742 break; 743 case 512 * 1024: 744 ret = "Pentium II"; 745 break; 746 case 1 * 1024 * 1024: 747 case 2 * 1024 * 1024: 748 ret = "Pentium II Xeon"; 749 break; 750 } 751 } else if (ci->ci_model == 6) { 752 switch (l2cache) { 753 case 256 * 1024: 754 case 512 * 1024: 755 ret = "Mobile Pentium II"; 756 break; 757 } 758 } else if (ci->ci_model == 7) { 759 switch (l2cache) { 760 case 512 * 1024: 761 ret = "Pentium III"; 762 break; 763 case 1 * 1024 * 1024: 764 case 2 * 1024 * 1024: 765 ret = "Pentium III Xeon"; 766 break; 767 } 768 } else if (ci->ci_model >= 8) { 769 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 770 switch (ci->ci_brand_id) { 771 case 0x3: 772 if (ci->ci_signature == 0x6B1) 773 ret = "Celeron"; 774 break; 775 case 0x8: 776 if (ci->ci_signature >= 0xF13) 777 ret = "genuine processor"; 778 break; 779 case 0xB: 780 if (ci->ci_signature >= 0xF13) 781 ret = "Xeon MP"; 782 break; 783 case 0xE: 784 if (ci->ci_signature < 0xF13) 785 ret = "Xeon"; 786 break; 787 } 788 if (ret == NULL) 789 ret = i386_intel_brand[ci->ci_brand_id]; 790 } 791 } 792 793 return ret; 794 } 795 796 /* 797 * Identify AMD64 CPU names from cpuid. 798 * 799 * Based on: 800 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 801 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 802 * "Revision Guide for AMD NPT Family 0Fh Processors" 803 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 804 * and other miscellaneous reports. 805 * 806 * This is all rather pointless, these are cross 'brand' since the raw 807 * silicon is shared. 808 */ 809 static const char * 810 amd_amd64_name(struct cpu_info *ci) 811 { 812 static char family_str[32]; 813 814 /* Only called if family >= 15 */ 815 816 switch (ci->ci_family) { 817 case 15: 818 switch (ci->ci_model) { 819 case 0x21: /* rev JH-E1/E6 */ 820 case 0x41: /* rev JH-F2 */ 821 return "Dual-Core Opteron"; 822 case 0x23: /* rev JH-E6 (Toledo) */ 823 return "Dual-Core Opteron or Athlon 64 X2"; 824 case 0x43: /* rev JH-F2 (Windsor) */ 825 return "Athlon 64 FX or Athlon 64 X2"; 826 case 0x24: /* rev SH-E5 (Lancaster?) */ 827 return "Mobile Athlon 64 or Turion 64"; 828 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 829 return "Opteron or Athlon 64 FX"; 830 case 0x15: /* rev SH-D0 */ 831 case 0x25: /* rev SH-E4 */ 832 return "Opteron"; 833 case 0x27: /* rev DH-E4, SH-E4 */ 834 return "Athlon 64 or Athlon 64 FX or Opteron"; 835 case 0x48: /* rev BH-F2 */ 836 return "Turion 64 X2"; 837 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 838 case 0x07: /* rev SH-CG (ClawHammer) */ 839 case 0x0b: /* rev CH-CG */ 840 case 0x14: /* rev SH-D0 */ 841 case 0x17: /* rev SH-D0 */ 842 case 0x1b: /* rev CH-D0 */ 843 return "Athlon 64"; 844 case 0x2b: /* rev BH-E4 (Manchester) */ 845 case 0x4b: /* rev BH-F2 (Windsor) */ 846 return "Athlon 64 X2"; 847 case 0x6b: /* rev BH-G1 (Brisbane) */ 848 return "Athlon X2 or Athlon 64 X2"; 849 case 0x08: /* rev CH-CG */ 850 case 0x0c: /* rev DH-CG (Newcastle) */ 851 case 0x0e: /* rev DH-CG (Newcastle?) */ 852 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 853 case 0x18: /* rev CH-D0 */ 854 case 0x1c: /* rev DH-D0 (Winchester) */ 855 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 856 case 0x2c: /* rev DH-E3/E6 */ 857 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 858 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 859 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 860 case 0x6f: /* rev DH-G1 */ 861 return "Athlon 64 or Sempron"; 862 default: 863 break; 864 } 865 return "Unknown AMD64 CPU"; 866 867 #if 0 868 case 16: 869 return "Family 10h"; 870 case 17: 871 return "Family 11h"; 872 case 18: 873 return "Family 12h"; 874 case 19: 875 return "Family 14h"; 876 case 20: 877 return "Family 15h"; 878 #endif 879 880 default: 881 break; 882 } 883 884 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 885 return family_str; 886 } 887 888 static void 889 intel_family_new_probe(struct cpu_info *ci) 890 { 891 uint32_t descs[4]; 892 893 x86_cpuid(0x80000000, descs); 894 895 /* 896 * Determine extended feature flags. 897 */ 898 if (descs[0] >= 0x80000001) { 899 x86_cpuid(0x80000001, descs); 900 ci->ci_feat_val[2] |= descs[3]; 901 ci->ci_feat_val[3] |= descs[2]; 902 } 903 } 904 905 static void 906 via_cpu_probe(struct cpu_info *ci) 907 { 908 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 909 u_int descs[4]; 910 u_int lfunc; 911 912 /* 913 * Determine the largest extended function value. 914 */ 915 x86_cpuid(0x80000000, descs); 916 lfunc = descs[0]; 917 918 /* 919 * Determine the extended feature flags. 920 */ 921 if (lfunc >= 0x80000001) { 922 x86_cpuid(0x80000001, descs); 923 ci->ci_feat_val[2] |= descs[3]; 924 } 925 926 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 927 return; 928 929 /* Nehemiah or Esther */ 930 x86_cpuid(0xc0000000, descs); 931 lfunc = descs[0]; 932 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 933 return; 934 935 x86_cpuid(0xc0000001, descs); 936 lfunc = descs[3]; 937 ci->ci_feat_val[4] = lfunc; 938 } 939 940 static void 941 amd_family6_probe(struct cpu_info *ci) 942 { 943 uint32_t descs[4]; 944 char *p; 945 size_t i; 946 947 x86_cpuid(0x80000000, descs); 948 949 /* 950 * Determine the extended feature flags. 951 */ 952 if (descs[0] >= 0x80000001) { 953 x86_cpuid(0x80000001, descs); 954 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 955 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 956 } 957 958 if (*cpu_brand_string == '\0') 959 return; 960 961 for (i = 1; i < __arraycount(amd_brand); i++) 962 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 963 ci->ci_brand_id = i; 964 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 965 break; 966 } 967 } 968 969 static void 970 intel_cpu_cacheinfo(struct cpu_info *ci) 971 { 972 const struct x86_cache_info *cai; 973 u_int descs[4]; 974 int iterations, i, j; 975 int type, level; 976 int ways, partitions, linesize, sets; 977 int caitype = -1; 978 int totalsize; 979 uint8_t desc; 980 981 /* Return if the cpu is old pre-cpuid instruction cpu */ 982 if (ci->ci_cpu_type >= 0) 983 return; 984 985 if (ci->ci_cpuid_level < 2) 986 return; 987 988 /* 989 * Parse the cache info from `cpuid leaf 2', if we have it. 990 * XXX This is kinda ugly, but hey, so is the architecture... 991 */ 992 x86_cpuid(2, descs); 993 iterations = descs[0] & 0xff; 994 while (iterations-- > 0) { 995 for (i = 0; i < 4; i++) { 996 if (descs[i] & 0x80000000) 997 continue; 998 for (j = 0; j < 4; j++) { 999 if (i == 0 && j == 0) 1000 continue; 1001 desc = (descs[i] >> (j * 8)) & 0xff; 1002 if (desc == 0) 1003 continue; 1004 cai = cache_info_lookup(intel_cpuid_cache_info, 1005 desc); 1006 if (cai != NULL) 1007 ci->ci_cinfo[cai->cai_index] = *cai; 1008 else if ((verbose != 0) && (desc != 0xff)) 1009 printf("Unknown cacheinfo desc %02x\n", 1010 desc); 1011 } 1012 } 1013 x86_cpuid(2, descs); 1014 } 1015 1016 if (ci->ci_cpuid_level < 4) 1017 return; 1018 1019 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1020 for (i = 0; ; i++) { 1021 x86_cpuid2(4, i, descs); 1022 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1023 if (type == CPUID_DCP_CACHETYPE_N) 1024 break; 1025 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1026 switch (level) { 1027 case 1: 1028 if (type == CPUID_DCP_CACHETYPE_I) 1029 caitype = CAI_ICACHE; 1030 else if (type == CPUID_DCP_CACHETYPE_D) 1031 caitype = CAI_DCACHE; 1032 else 1033 caitype = -1; 1034 break; 1035 case 2: 1036 if (type == CPUID_DCP_CACHETYPE_U) 1037 caitype = CAI_L2CACHE; 1038 else 1039 caitype = -1; 1040 break; 1041 case 3: 1042 if (type == CPUID_DCP_CACHETYPE_U) 1043 caitype = CAI_L3CACHE; 1044 else 1045 caitype = -1; 1046 break; 1047 default: 1048 caitype = -1; 1049 break; 1050 } 1051 if (caitype == -1) { 1052 printf("unknown cache level&type (%d & %d)\n", 1053 level, type); 1054 continue; 1055 } 1056 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1057 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1058 + 1; 1059 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1060 + 1; 1061 sets = descs[2] + 1; 1062 totalsize = ways * partitions * linesize * sets; 1063 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1064 ci->ci_cinfo[caitype].cai_associativity = ways; 1065 ci->ci_cinfo[caitype].cai_linesize = linesize; 1066 } 1067 } 1068 1069 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1070 AMD_L2CACHE_INFO; 1071 1072 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1073 AMD_L3CACHE_INFO; 1074 1075 static void 1076 amd_cpu_cacheinfo(struct cpu_info *ci) 1077 { 1078 const struct x86_cache_info *cp; 1079 struct x86_cache_info *cai; 1080 u_int descs[4]; 1081 u_int lfunc; 1082 1083 /* 1084 * K5 model 0 has none of this info. 1085 */ 1086 if (ci->ci_family == 5 && ci->ci_model == 0) 1087 return; 1088 1089 /* 1090 * Determine the largest extended function value. 1091 */ 1092 x86_cpuid(0x80000000, descs); 1093 lfunc = descs[0]; 1094 1095 /* 1096 * Determine L1 cache/TLB info. 1097 */ 1098 if (lfunc < 0x80000005) { 1099 /* No L1 cache info available. */ 1100 return; 1101 } 1102 1103 x86_cpuid(0x80000005, descs); 1104 1105 /* 1106 * K6-III and higher have large page TLBs. 1107 */ 1108 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1109 cai = &ci->ci_cinfo[CAI_ITLB2]; 1110 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1111 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1112 cai->cai_linesize = largepagesize; 1113 1114 cai = &ci->ci_cinfo[CAI_DTLB2]; 1115 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1116 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1117 cai->cai_linesize = largepagesize; 1118 } 1119 1120 cai = &ci->ci_cinfo[CAI_ITLB]; 1121 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1122 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1123 cai->cai_linesize = (4 * 1024); 1124 1125 cai = &ci->ci_cinfo[CAI_DTLB]; 1126 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1127 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1128 cai->cai_linesize = (4 * 1024); 1129 1130 cai = &ci->ci_cinfo[CAI_DCACHE]; 1131 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1132 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1133 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1134 1135 cai = &ci->ci_cinfo[CAI_ICACHE]; 1136 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1137 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1138 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1139 1140 /* 1141 * Determine L2 cache/TLB info. 1142 */ 1143 if (lfunc < 0x80000006) { 1144 /* No L2 cache info available. */ 1145 return; 1146 } 1147 1148 x86_cpuid(0x80000006, descs); 1149 1150 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1151 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1152 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1153 cai->cai_linesize = (4 * 1024); 1154 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1155 cai->cai_associativity); 1156 if (cp != NULL) 1157 cai->cai_associativity = cp->cai_associativity; 1158 else 1159 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1160 1161 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1162 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1163 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1164 cai->cai_linesize = largepagesize; 1165 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1166 cai->cai_associativity); 1167 if (cp != NULL) 1168 cai->cai_associativity = cp->cai_associativity; 1169 else 1170 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1171 1172 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1173 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1174 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1175 cai->cai_linesize = (4 * 1024); 1176 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1177 cai->cai_associativity); 1178 if (cp != NULL) 1179 cai->cai_associativity = cp->cai_associativity; 1180 else 1181 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1182 1183 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1184 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1185 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1186 cai->cai_linesize = largepagesize; 1187 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1188 cai->cai_associativity); 1189 if (cp != NULL) 1190 cai->cai_associativity = cp->cai_associativity; 1191 else 1192 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1193 1194 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1195 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1196 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1197 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1198 1199 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1200 cai->cai_associativity); 1201 if (cp != NULL) 1202 cai->cai_associativity = cp->cai_associativity; 1203 else 1204 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1205 1206 /* 1207 * Determine L3 cache info on AMD Family 10h and newer processors 1208 */ 1209 if (ci->ci_family >= 0x10) { 1210 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1211 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1212 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1213 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1214 1215 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1216 cai->cai_associativity); 1217 if (cp != NULL) 1218 cai->cai_associativity = cp->cai_associativity; 1219 else 1220 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1221 } 1222 1223 /* 1224 * Determine 1GB TLB info. 1225 */ 1226 if (lfunc < 0x80000019) { 1227 /* No 1GB TLB info available. */ 1228 return; 1229 } 1230 1231 x86_cpuid(0x80000019, descs); 1232 1233 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1234 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1235 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1236 cai->cai_linesize = (1024 * 1024 * 1024); 1237 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1238 cai->cai_associativity); 1239 if (cp != NULL) 1240 cai->cai_associativity = cp->cai_associativity; 1241 else 1242 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1243 1244 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1245 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1246 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1247 cai->cai_linesize = (1024 * 1024 * 1024); 1248 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1249 cai->cai_associativity); 1250 if (cp != NULL) 1251 cai->cai_associativity = cp->cai_associativity; 1252 else 1253 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1254 1255 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1256 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1257 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1258 cai->cai_linesize = (1024 * 1024 * 1024); 1259 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1260 cai->cai_associativity); 1261 if (cp != NULL) 1262 cai->cai_associativity = cp->cai_associativity; 1263 else 1264 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1265 1266 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1267 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1268 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1269 cai->cai_linesize = (1024 * 1024 * 1024); 1270 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1271 cai->cai_associativity); 1272 if (cp != NULL) 1273 cai->cai_associativity = cp->cai_associativity; 1274 else 1275 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1276 } 1277 1278 static void 1279 via_cpu_cacheinfo(struct cpu_info *ci) 1280 { 1281 struct x86_cache_info *cai; 1282 int stepping; 1283 u_int descs[4]; 1284 u_int lfunc; 1285 1286 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1287 1288 /* 1289 * Determine the largest extended function value. 1290 */ 1291 x86_cpuid(0x80000000, descs); 1292 lfunc = descs[0]; 1293 1294 /* 1295 * Determine L1 cache/TLB info. 1296 */ 1297 if (lfunc < 0x80000005) { 1298 /* No L1 cache info available. */ 1299 return; 1300 } 1301 1302 x86_cpuid(0x80000005, descs); 1303 1304 cai = &ci->ci_cinfo[CAI_ITLB]; 1305 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1306 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1307 cai->cai_linesize = (4 * 1024); 1308 1309 cai = &ci->ci_cinfo[CAI_DTLB]; 1310 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1311 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1312 cai->cai_linesize = (4 * 1024); 1313 1314 cai = &ci->ci_cinfo[CAI_DCACHE]; 1315 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1316 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1317 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1318 if (ci->ci_model == 9 && stepping == 8) { 1319 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1320 cai->cai_associativity = 2; 1321 } 1322 1323 cai = &ci->ci_cinfo[CAI_ICACHE]; 1324 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1325 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1326 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1327 if (ci->ci_model == 9 && stepping == 8) { 1328 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1329 cai->cai_associativity = 2; 1330 } 1331 1332 /* 1333 * Determine L2 cache/TLB info. 1334 */ 1335 if (lfunc < 0x80000006) { 1336 /* No L2 cache info available. */ 1337 return; 1338 } 1339 1340 x86_cpuid(0x80000006, descs); 1341 1342 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1343 if (ci->ci_model >= 9) { 1344 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1345 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1346 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1347 } else { 1348 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1349 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1350 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1351 } 1352 } 1353 1354 static void 1355 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1356 { 1357 u_int descs[4]; 1358 1359 x86_cpuid(0x80860007, descs); 1360 *frequency = descs[0]; 1361 *voltage = descs[1]; 1362 *percentage = descs[2]; 1363 } 1364 1365 static void 1366 transmeta_cpu_info(struct cpu_info *ci) 1367 { 1368 u_int descs[4], nreg; 1369 u_int frequency, voltage, percentage; 1370 1371 x86_cpuid(0x80860000, descs); 1372 nreg = descs[0]; 1373 if (nreg >= 0x80860001) { 1374 x86_cpuid(0x80860001, descs); 1375 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1376 (descs[1] >> 24) & 0xff, 1377 (descs[1] >> 16) & 0xff, 1378 (descs[1] >> 8) & 0xff, 1379 descs[1] & 0xff); 1380 } 1381 if (nreg >= 0x80860002) { 1382 x86_cpuid(0x80860002, descs); 1383 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1384 (descs[1] >> 24) & 0xff, 1385 (descs[1] >> 16) & 0xff, 1386 (descs[1] >> 8) & 0xff, 1387 descs[1] & 0xff, 1388 descs[2]); 1389 } 1390 if (nreg >= 0x80860006) { 1391 union { 1392 char text[65]; 1393 u_int descs[4][4]; 1394 } info; 1395 int i; 1396 1397 for (i=0; i<4; i++) { 1398 x86_cpuid(0x80860003 + i, info.descs[i]); 1399 } 1400 info.text[64] = '\0'; 1401 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1402 } 1403 1404 if (nreg >= 0x80860007) { 1405 tmx86_get_longrun_status(&frequency, 1406 &voltage, &percentage); 1407 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1408 frequency, voltage, percentage); 1409 } 1410 } 1411 1412 static void 1413 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1414 { 1415 u_int descs[4]; 1416 int i; 1417 uint32_t brand[12]; 1418 1419 memset(ci, 0, sizeof(*ci)); 1420 ci->ci_dev = cpuname; 1421 1422 ci->ci_cpu_type = x86_identify(); 1423 if (ci->ci_cpu_type >= 0) { 1424 /* Old pre-cpuid instruction cpu */ 1425 ci->ci_cpuid_level = -1; 1426 return; 1427 } 1428 1429 /* 1430 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1431 * function. 1432 */ 1433 1434 /* 1435 * Fn0000_0000: 1436 * - Save cpuid max level. 1437 * - Save vendor string. 1438 */ 1439 x86_cpuid(0, descs); 1440 ci->ci_cpuid_level = descs[0]; 1441 /* Save vendor string */ 1442 ci->ci_vendor[0] = descs[1]; 1443 ci->ci_vendor[2] = descs[2]; 1444 ci->ci_vendor[1] = descs[3]; 1445 ci->ci_vendor[3] = 0; 1446 1447 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1448 ci->ci_cpuid_level); 1449 if (verbose) { 1450 int bf; 1451 1452 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1453 x86_cpuid(bf, descs); 1454 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1455 bf, descs[0], descs[1], descs[2], descs[3]); 1456 } 1457 } 1458 1459 /* 1460 * Fn8000_0000: 1461 * - Get cpuid extended function's max level. 1462 */ 1463 x86_cpuid(0x80000000, descs); 1464 if (descs[0] >= 0x80000000) { 1465 ci->ci_cpuid_extlevel = descs[0]; 1466 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1467 ci->ci_cpuid_extlevel); 1468 } else { 1469 /* Set lower value than 0x80000000 */ 1470 ci->ci_cpuid_extlevel = 0; 1471 } 1472 if (verbose) { 1473 unsigned int ef; 1474 1475 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1476 x86_cpuid(ef, descs); 1477 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1478 ef, descs[0], descs[1], descs[2], descs[3]); 1479 } 1480 } 1481 1482 /* 1483 * Fn8000_000[2-4]: 1484 * - Save brand string. 1485 */ 1486 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1487 x86_cpuid(0x80000002, brand); 1488 x86_cpuid(0x80000003, brand + 4); 1489 x86_cpuid(0x80000004, brand + 8); 1490 for (i = 0; i < 48; i++) 1491 if (((char *) brand)[i] != ' ') 1492 break; 1493 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1494 } 1495 1496 if (ci->ci_cpuid_level < 1) 1497 return; 1498 1499 /* 1500 * Fn0000_0001: 1501 * - Get CPU family, model and stepping (from eax). 1502 * - Initial local APIC ID and brand ID (from ebx) 1503 * - CPUID2 (from ecx) 1504 * - CPUID (from edx) 1505 */ 1506 x86_cpuid(1, descs); 1507 ci->ci_signature = descs[0]; 1508 1509 /* Extract full family/model values */ 1510 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1511 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1512 1513 /* Brand is low order 8 bits of ebx */ 1514 ci->ci_brand_id = descs[1] & 0xff; 1515 /* Initial local APIC ID */ 1516 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1517 1518 ci->ci_feat_val[1] = descs[2]; 1519 ci->ci_feat_val[0] = descs[3]; 1520 1521 if (ci->ci_cpuid_level < 3) 1522 return; 1523 1524 /* 1525 * If the processor serial number misfeature is present and supported, 1526 * extract it here. 1527 */ 1528 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1529 ci->ci_cpu_serial[0] = ci->ci_signature; 1530 x86_cpuid(3, descs); 1531 ci->ci_cpu_serial[2] = descs[2]; 1532 ci->ci_cpu_serial[1] = descs[3]; 1533 } 1534 1535 if (ci->ci_cpuid_level < 0xd) 1536 return; 1537 1538 /* Get support XCR0 bits */ 1539 x86_cpuid2(0xd, 0, descs); 1540 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1541 ci->ci_cur_xsave = descs[1]; 1542 ci->ci_max_xsave = descs[2]; 1543 1544 /* Additional flags (eg xsaveopt support) */ 1545 x86_cpuid2(0xd, 1, descs); 1546 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1547 } 1548 1549 static void 1550 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1551 { 1552 uint32_t descs[4]; 1553 char hv_sig[13]; 1554 char *p; 1555 const char *hv_name; 1556 int i; 1557 1558 /* 1559 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1560 * http://lkml.org/lkml/2008/10/1/246 1561 * 1562 * KB1009458: Mechanisms to determine if software is running in 1563 * a VMware virtual machine 1564 * http://kb.vmware.com/kb/1009458 1565 */ 1566 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1567 x86_cpuid(0x40000000, descs); 1568 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1569 memcpy(p, &descs[i], sizeof(descs[i])); 1570 *p = '\0'; 1571 /* 1572 * HV vendor ID string 1573 * ------------+-------------- 1574 * KVM "KVMKVMKVM" 1575 * Microsoft "Microsoft Hv" 1576 * VMware "VMwareVMware" 1577 * Xen "XenVMMXenVMM" 1578 */ 1579 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1580 hv_name = "KVM"; 1581 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1582 hv_name = "Hyper-V"; 1583 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1584 hv_name = "VMware"; 1585 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1586 hv_name = "Xen"; 1587 else 1588 hv_name = "unknown"; 1589 1590 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1591 } 1592 } 1593 1594 static void 1595 cpu_probe_features(struct cpu_info *ci) 1596 { 1597 const struct cpu_cpuid_nameclass *cpup = NULL; 1598 unsigned int i; 1599 1600 if (ci->ci_cpuid_level < 1) 1601 return; 1602 1603 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1604 if (!strncmp((char *)ci->ci_vendor, 1605 i386_cpuid_cpus[i].cpu_id, 12)) { 1606 cpup = &i386_cpuid_cpus[i]; 1607 break; 1608 } 1609 } 1610 1611 if (cpup == NULL) 1612 return; 1613 1614 i = ci->ci_family - CPU_MINFAMILY; 1615 1616 if (i >= __arraycount(cpup->cpu_family)) 1617 i = __arraycount(cpup->cpu_family) - 1; 1618 1619 if (cpup->cpu_family[i].cpu_probe == NULL) 1620 return; 1621 1622 (*cpup->cpu_family[i].cpu_probe)(ci); 1623 } 1624 1625 static void 1626 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1627 { 1628 char buf[32 * 16]; 1629 char *bp; 1630 1631 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1632 1633 if (val == 0 || fmt == NULL) 1634 return; 1635 1636 snprintb_m(buf, sizeof(buf), fmt, val, 1637 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1638 bp = buf; 1639 while (*bp != '\0') { 1640 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1641 bp += strlen(bp) + 1; 1642 } 1643 } 1644 1645 static void 1646 identifycpu_cpuids(struct cpu_info *ci) 1647 { 1648 const char *cpuname = ci->ci_dev; 1649 u_int lp_max = 1; /* logical processors per package */ 1650 u_int smt_max; /* smt per core */ 1651 u_int core_max = 1; /* core per package */ 1652 u_int smt_bits, core_bits; 1653 uint32_t descs[4]; 1654 1655 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1656 ci->ci_packageid = ci->ci_initapicid; 1657 ci->ci_coreid = 0; 1658 ci->ci_smtid = 0; 1659 if (cpu_vendor != CPUVENDOR_INTEL) { 1660 return; 1661 } 1662 1663 /* 1664 * 253668.pdf 7.10.2 1665 */ 1666 1667 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1668 x86_cpuid(1, descs); 1669 lp_max = (descs[1] >> 16) & 0xff; 1670 } 1671 if (ci->ci_cpuid_level >= 4) { 1672 x86_cpuid2(4, 0, descs); 1673 core_max = (descs[0] >> 26) + 1; 1674 } 1675 assert(lp_max >= core_max); 1676 smt_max = lp_max / core_max; 1677 smt_bits = ilog2(smt_max - 1) + 1; 1678 core_bits = ilog2(core_max - 1) + 1; 1679 if (smt_bits + core_bits) { 1680 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1681 } 1682 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1683 ci->ci_packageid); 1684 if (core_bits) { 1685 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1686 1687 ci->ci_coreid = 1688 __SHIFTOUT(ci->ci_initapicid, core_mask); 1689 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1690 } 1691 if (smt_bits) { 1692 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1693 1694 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1695 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1696 } 1697 } 1698 1699 void 1700 identifycpu(int fd, const char *cpuname) 1701 { 1702 const char *name = "", *modifier, *vendorname, *brand = ""; 1703 int class = CPUCLASS_386; 1704 unsigned int i; 1705 int modif, family; 1706 const struct cpu_cpuid_nameclass *cpup = NULL; 1707 const struct cpu_cpuid_family *cpufam; 1708 struct cpu_info *ci, cistore; 1709 size_t sz; 1710 struct cpu_ucode_version ucode; 1711 union { 1712 struct cpu_ucode_version_amd amd; 1713 struct cpu_ucode_version_intel1 intel1; 1714 } ucvers; 1715 1716 ci = &cistore; 1717 cpu_probe_base_features(ci, cpuname); 1718 cpu_probe_hv_features(ci, cpuname); 1719 cpu_probe_features(ci); 1720 1721 if (ci->ci_cpu_type >= 0) { 1722 /* Old pre-cpuid instruction cpu */ 1723 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1724 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1725 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1726 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1727 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1728 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1729 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1730 modifier = ""; 1731 } else { 1732 /* CPU which support cpuid instruction */ 1733 modif = (ci->ci_signature >> 12) & 0x3; 1734 family = ci->ci_family; 1735 if (family < CPU_MINFAMILY) 1736 errx(1, "identifycpu: strange family value"); 1737 if (family > CPU_MAXFAMILY) 1738 family = CPU_MAXFAMILY; 1739 1740 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1741 if (!strncmp((char *)ci->ci_vendor, 1742 i386_cpuid_cpus[i].cpu_id, 12)) { 1743 cpup = &i386_cpuid_cpus[i]; 1744 break; 1745 } 1746 } 1747 1748 if (cpup == NULL) { 1749 cpu_vendor = CPUVENDOR_UNKNOWN; 1750 if (ci->ci_vendor[0] != '\0') 1751 vendorname = (char *)&ci->ci_vendor[0]; 1752 else 1753 vendorname = "Unknown"; 1754 class = family - 3; 1755 modifier = ""; 1756 name = ""; 1757 ci->ci_info = NULL; 1758 } else { 1759 cpu_vendor = cpup->cpu_vendor; 1760 vendorname = cpup->cpu_vendorname; 1761 modifier = modifiers[modif]; 1762 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1763 name = cpufam->cpu_models[ci->ci_model]; 1764 if (name == NULL || *name == '\0') 1765 name = cpufam->cpu_model_default; 1766 class = cpufam->cpu_class; 1767 ci->ci_info = cpufam->cpu_info; 1768 1769 if (cpu_vendor == CPUVENDOR_INTEL) { 1770 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1771 const char *tmp; 1772 tmp = intel_family6_name(ci); 1773 if (tmp != NULL) 1774 name = tmp; 1775 } 1776 if (ci->ci_family == 15 && 1777 ci->ci_brand_id < 1778 __arraycount(i386_intel_brand) && 1779 i386_intel_brand[ci->ci_brand_id]) 1780 name = 1781 i386_intel_brand[ci->ci_brand_id]; 1782 } 1783 1784 if (cpu_vendor == CPUVENDOR_AMD) { 1785 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1786 if (ci->ci_brand_id == 1) 1787 /* 1788 * It's Duron. We override the 1789 * name, since it might have 1790 * been misidentified as Athlon. 1791 */ 1792 name = 1793 amd_brand[ci->ci_brand_id]; 1794 else 1795 brand = amd_brand_name; 1796 } 1797 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1798 == 0xf) { 1799 /* Identify AMD64 CPU names. */ 1800 const char *tmp; 1801 tmp = amd_amd64_name(ci); 1802 if (tmp != NULL) 1803 name = tmp; 1804 } 1805 } 1806 1807 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1808 vendorname = "VIA"; 1809 } 1810 } 1811 1812 ci->ci_cpu_class = class; 1813 1814 sz = sizeof(ci->ci_tsc_freq); 1815 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1816 sz = sizeof(use_pae); 1817 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1818 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1819 1820 /* 1821 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1822 * we try to determine from the family/model values. 1823 */ 1824 if (*cpu_brand_string != '\0') 1825 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1826 1827 aprint_normal("%s: %s", cpuname, vendorname); 1828 if (*modifier) 1829 aprint_normal(" %s", modifier); 1830 if (*name) 1831 aprint_normal(" %s", name); 1832 if (*brand) 1833 aprint_normal(" %s", brand); 1834 aprint_normal(" (%s-class)", classnames[class]); 1835 1836 if (ci->ci_tsc_freq != 0) 1837 aprint_normal(", %ju.%02ju MHz\n", 1838 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1839 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1840 1841 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1842 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1843 if (ci->ci_signature != 0) 1844 aprint_normal(" (id %#x)", ci->ci_signature); 1845 aprint_normal("\n"); 1846 1847 if (ci->ci_info) 1848 (*ci->ci_info)(ci); 1849 1850 /* 1851 * display CPU feature flags 1852 */ 1853 1854 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1855 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1856 1857 /* These next two are actually common definitions! */ 1858 print_bits(cpuname, "features2", 1859 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1860 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1861 print_bits(cpuname, "features3", 1862 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1863 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1864 1865 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1866 ci->ci_feat_val[4]); 1867 1868 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1869 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1870 ci->ci_feat_val[6]); 1871 1872 if (ci->ci_max_xsave != 0) { 1873 aprint_normal("%s: xsave area size: current %d, maximum %d", 1874 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1875 aprint_normal(", xgetbv %sabled\n", 1876 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1877 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1878 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1879 x86_xgetbv()); 1880 } 1881 1882 x86_print_cache_and_tlb_info(ci); 1883 1884 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1885 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1886 cpuname, 1887 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1888 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1889 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1890 } 1891 1892 if (ci->ci_cpu_class == CPUCLASS_386) { 1893 errx(1, "NetBSD requires an 80486 or later processor"); 1894 } 1895 1896 if (ci->ci_cpu_type == CPU_486DLC) { 1897 #ifndef CYRIX_CACHE_WORKS 1898 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1899 #else 1900 #ifndef CYRIX_CACHE_REALLY_WORKS 1901 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1902 #else 1903 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1904 #endif 1905 #endif 1906 } 1907 1908 /* 1909 * Everything past this point requires a Pentium or later. 1910 */ 1911 if (ci->ci_cpuid_level < 0) 1912 return; 1913 1914 identifycpu_cpuids(ci); 1915 1916 #ifdef INTEL_CORETEMP 1917 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1918 coretemp_register(ci); 1919 #endif 1920 1921 if (cpu_vendor == CPUVENDOR_AMD) { 1922 uint32_t data[4]; 1923 1924 x86_cpuid(0x80000000, data); 1925 if (data[0] >= 0x80000007) 1926 powernow_probe(ci); 1927 1928 if ((data[0] >= 0x8000000a) 1929 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1930 x86_cpuid(0x8000000a, data); 1931 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1932 data[0] & 0xf); 1933 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1934 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1935 data[3]); 1936 } 1937 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1938 uint32_t data[4]; 1939 int32_t bi_index; 1940 1941 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1942 x86_cpuid(bi_index, data); 1943 switch (bi_index) { 1944 case 6: 1945 print_bits(cpuname, "DSPM-eax", 1946 CPUID_DSPM_FLAGS, data[0]); 1947 print_bits(cpuname, "DSPM-ecx", 1948 CPUID_DSPM_FLAGS1, data[2]); 1949 break; 1950 case 7: 1951 aprint_verbose("%s: SEF highest subleaf %08x\n", 1952 cpuname, data[0]); 1953 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1954 data[1]); 1955 break; 1956 #if 0 1957 default: 1958 aprint_verbose("%s: basic %08x-eax %08x\n", 1959 cpuname, bi_index, data[0]); 1960 aprint_verbose("%s: basic %08x-ebx %08x\n", 1961 cpuname, bi_index, data[1]); 1962 aprint_verbose("%s: basic %08x-ecx %08x\n", 1963 cpuname, bi_index, data[2]); 1964 aprint_verbose("%s: basic %08x-edx %08x\n", 1965 cpuname, bi_index, data[3]); 1966 break; 1967 #endif 1968 } 1969 } 1970 } 1971 1972 #ifdef INTEL_ONDEMAND_CLOCKMOD 1973 clockmod_init(); 1974 #endif 1975 1976 if (cpu_vendor == CPUVENDOR_AMD) 1977 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1978 else if (cpu_vendor == CPUVENDOR_INTEL) 1979 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1980 else 1981 return; 1982 1983 ucode.data = &ucvers; 1984 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1985 #ifdef __i386__ 1986 struct cpu_ucode_version_64 ucode_64; 1987 if (errno != ENOTTY) 1988 return; 1989 /* Try the 64 bit ioctl */ 1990 memset(&ucode_64, 0, sizeof ucode_64); 1991 ucode_64.data = &ucvers; 1992 ucode_64.loader_version = ucode.loader_version; 1993 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1994 return; 1995 #endif 1996 } 1997 1998 if (cpu_vendor == CPUVENDOR_AMD) 1999 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2000 else if (cpu_vendor == CPUVENDOR_INTEL) 2001 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2002 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2003 } 2004 2005 static const struct x86_cache_info * 2006 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2007 { 2008 int i; 2009 2010 for (i = 0; cai[i].cai_desc != 0; i++) { 2011 if (cai[i].cai_desc == desc) 2012 return (&cai[i]); 2013 } 2014 2015 return (NULL); 2016 } 2017 2018 static const char * 2019 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2020 const char *sep) 2021 { 2022 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2023 char human_num[HUMAN_BUFSIZE]; 2024 2025 if (cai->cai_totalsize == 0) 2026 return sep; 2027 2028 if (sep == NULL) 2029 aprint_verbose_dev(ci->ci_dev, ""); 2030 else 2031 aprint_verbose("%s", sep); 2032 if (name != NULL) 2033 aprint_verbose("%s ", name); 2034 2035 if (cai->cai_string != NULL) { 2036 aprint_verbose("%s ", cai->cai_string); 2037 } else { 2038 (void)humanize_number(human_num, sizeof(human_num), 2039 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2040 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2041 } 2042 switch (cai->cai_associativity) { 2043 case 0: 2044 aprint_verbose("disabled"); 2045 break; 2046 case 1: 2047 aprint_verbose("direct-mapped"); 2048 break; 2049 case 0xff: 2050 aprint_verbose("fully associative"); 2051 break; 2052 default: 2053 aprint_verbose("%d-way", cai->cai_associativity); 2054 break; 2055 } 2056 return ", "; 2057 } 2058 2059 static const char * 2060 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2061 const char *sep) 2062 { 2063 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2064 char human_num[HUMAN_BUFSIZE]; 2065 2066 if (cai->cai_totalsize == 0) 2067 return sep; 2068 2069 if (sep == NULL) 2070 aprint_verbose_dev(ci->ci_dev, ""); 2071 else 2072 aprint_verbose("%s", sep); 2073 if (name != NULL) 2074 aprint_verbose("%s ", name); 2075 2076 if (cai->cai_string != NULL) { 2077 aprint_verbose("%s", cai->cai_string); 2078 } else { 2079 (void)humanize_number(human_num, sizeof(human_num), 2080 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2081 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2082 human_num); 2083 switch (cai->cai_associativity) { 2084 case 0: 2085 aprint_verbose("disabled"); 2086 break; 2087 case 1: 2088 aprint_verbose("direct-mapped"); 2089 break; 2090 case 0xff: 2091 aprint_verbose("fully associative"); 2092 break; 2093 default: 2094 aprint_verbose("%d-way", cai->cai_associativity); 2095 break; 2096 } 2097 } 2098 return ", "; 2099 } 2100 2101 static void 2102 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2103 { 2104 const char *sep = NULL; 2105 2106 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2107 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2108 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2109 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2110 if (sep != NULL) 2111 aprint_verbose("\n"); 2112 } 2113 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2114 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2115 if (sep != NULL) 2116 aprint_verbose("\n"); 2117 } 2118 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2119 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2120 if (sep != NULL) 2121 aprint_verbose("\n"); 2122 } 2123 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2124 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2125 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2126 if (sep != NULL) 2127 aprint_verbose("\n"); 2128 } 2129 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2130 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2131 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2132 if (sep != NULL) 2133 aprint_verbose("\n"); 2134 } 2135 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2136 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2137 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2138 if (sep != NULL) 2139 aprint_verbose("\n"); 2140 } 2141 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2142 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2143 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2144 if (sep != NULL) 2145 aprint_verbose("\n"); 2146 } 2147 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2148 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2149 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2150 if (sep != NULL) 2151 aprint_verbose("\n"); 2152 } 2153 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2154 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2155 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2156 if (sep != NULL) 2157 aprint_verbose("\n"); 2158 } 2159 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2160 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2161 NULL); 2162 if (sep != NULL) 2163 aprint_verbose("\n"); 2164 } 2165 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2166 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2167 NULL); 2168 if (sep != NULL) 2169 aprint_verbose("\n"); 2170 } 2171 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2172 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2173 NULL); 2174 if (sep != NULL) 2175 aprint_verbose("\n"); 2176 } 2177 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2178 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2179 NULL); 2180 if (sep != NULL) 2181 aprint_verbose("\n"); 2182 } 2183 } 2184 2185 static void 2186 powernow_probe(struct cpu_info *ci) 2187 { 2188 uint32_t regs[4]; 2189 char buf[256]; 2190 2191 x86_cpuid(0x80000007, regs); 2192 2193 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2194 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2195 buf); 2196 } 2197 2198 int 2199 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2200 { 2201 struct cpu_info ci; 2202 int loader_version, res; 2203 struct cpu_ucode_version versreq; 2204 2205 cpu_probe_base_features(&ci, "unknown"); 2206 2207 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2208 loader_version = CPU_UCODE_LOADER_AMD; 2209 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2210 loader_version = CPU_UCODE_LOADER_INTEL1; 2211 else 2212 return -1; 2213 2214 /* check whether the kernel understands this loader version */ 2215 versreq.loader_version = loader_version; 2216 versreq.data = 0; 2217 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2218 if (res) 2219 return -1; 2220 2221 switch (loader_version) { 2222 case CPU_UCODE_LOADER_AMD: 2223 if (uc->cpu_nr != -1) { 2224 /* printf? */ 2225 return -1; 2226 } 2227 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2228 break; 2229 case CPU_UCODE_LOADER_INTEL1: 2230 if (uc->cpu_nr == -1) 2231 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2232 else 2233 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2234 break; 2235 default: /* can't happen */ 2236 return -1; 2237 } 2238 uc->loader_version = loader_version; 2239 return 0; 2240 } 2241
Indexes created Sun Sep 28 07:09:56 GMT 2025