i386.c revision 1.71
1 /* $NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.71 2016/04/27 06:58:06 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[9]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] XCR0 bits (d:0 %eax) 110 * [8] xsave flags (d:1 %eax) 111 */ 112 uint32_t ci_cpu_class; /* CPU class */ 113 uint32_t ci_brand_id; /* Intel brand id */ 114 uint32_t ci_vendor[4]; /* vendor string */ 115 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 116 uint64_t ci_tsc_freq; /* cpu cycles/second */ 117 uint8_t ci_packageid; 118 uint8_t ci_coreid; 119 uint8_t ci_smtid; 120 uint32_t ci_initapicid; 121 122 uint32_t ci_cur_xsave; 123 uint32_t ci_max_xsave; 124 125 struct x86_cache_info ci_cinfo[CAI_COUNT]; 126 void (*ci_info)(struct cpu_info *); 127 }; 128 129 struct cpu_nocpuid_nameclass { 130 int cpu_vendor; 131 const char *cpu_vendorname; 132 const char *cpu_name; 133 int cpu_class; 134 void (*cpu_setup)(struct cpu_info *); 135 void (*cpu_cacheinfo)(struct cpu_info *); 136 void (*cpu_info)(struct cpu_info *); 137 }; 138 139 struct cpu_cpuid_nameclass { 140 const char *cpu_id; 141 int cpu_vendor; 142 const char *cpu_vendorname; 143 struct cpu_cpuid_family { 144 int cpu_class; 145 const char *cpu_models[256]; 146 const char *cpu_model_default; 147 void (*cpu_setup)(struct cpu_info *); 148 void (*cpu_probe)(struct cpu_info *); 149 void (*cpu_info)(struct cpu_info *); 150 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 151 }; 152 153 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 154 155 /* 156 * Map Brand ID from cpuid instruction to brand name. 157 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 158 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 159 * Architectures Software Developer's Manual, Volume 2A". 160 */ 161 static const char * const i386_intel_brand[] = { 162 "", /* Unsupported */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "", /* 0x05: Reserved */ 168 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Celeron", /* Intel (R) Celeron (TM) processor */ 173 "Xeon", /* Intel (R) Xeon (TM) processor */ 174 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 175 "", /* 0x0d: Reserved */ 176 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 177 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 178 "", /* 0x10: Reserved */ 179 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 180 "Celeron M", /* Intel (R) Celeron (R) M processor */ 181 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 182 "Celeron", /* Intel (R) Celeron (R) processor */ 183 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 184 "Pentium M", /* Intel (R) Pentium (R) M processor */ 185 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 186 }; 187 188 /* 189 * AMD processors don't have Brand IDs, so we need these names for probe. 190 */ 191 static const char * const amd_brand[] = { 192 "", 193 "Duron", /* AMD Duron(tm) */ 194 "MP", /* AMD Athlon(tm) MP */ 195 "XP", /* AMD Athlon(tm) XP */ 196 "4" /* AMD Athlon(tm) 4 */ 197 }; 198 199 static int cpu_vendor; 200 static char cpu_brand_string[49]; 201 static char amd_brand_name[48]; 202 static int use_pae, largepagesize; 203 204 /* Setup functions */ 205 static void disable_tsc(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 /* Brand/Model name functions */ 210 static const char *intel_family6_name(struct cpu_info *); 211 static const char *amd_amd64_name(struct cpu_info *); 212 /* Probe functions */ 213 static void amd_family6_probe(struct cpu_info *); 214 static void powernow_probe(struct cpu_info *); 215 static void intel_family_new_probe(struct cpu_info *); 216 static void via_cpu_probe(struct cpu_info *); 217 /* (Cache) Info functions */ 218 static void intel_cpu_cacheinfo(struct cpu_info *); 219 static void amd_cpu_cacheinfo(struct cpu_info *); 220 static void via_cpu_cacheinfo(struct cpu_info *); 221 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 222 static void transmeta_cpu_info(struct cpu_info *); 223 /* Common functions */ 224 static void cpu_probe_base_features(struct cpu_info *, const char *); 225 static void cpu_probe_hv_features(struct cpu_info *, const char *); 226 static void cpu_probe_features(struct cpu_info *); 227 static void print_bits(const char *, const char *, const char *, uint32_t); 228 static void identifycpu_cpuids(struct cpu_info *); 229 static const struct x86_cache_info *cache_info_lookup( 230 const struct x86_cache_info *, uint8_t); 231 static const char *print_cache_config(struct cpu_info *, int, const char *, 232 const char *); 233 static const char *print_tlb_config(struct cpu_info *, int, const char *, 234 const char *); 235 static void x86_print_cache_and_tlb_info(struct cpu_info *); 236 237 /* 238 * Note: these are just the ones that may not have a cpuid instruction. 239 * We deal with the rest in a different way. 240 */ 241 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 242 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386SX */ 244 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386 */ 246 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486SX */ 248 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486 */ 250 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486DLC */ 252 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_6x86 */ 254 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 255 NULL, NULL, NULL }, /* CPU_NX586 */ 256 }; 257 258 const char *classnames[] = { 259 "386", 260 "486", 261 "586", 262 "686" 263 }; 264 265 const char *modifiers[] = { 266 "", 267 "OverDrive", 268 "Dual", 269 "" 270 }; 271 272 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 273 { 274 /* 275 * For Intel processors, check Chapter 35Model-specific 276 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 277 * Software Developer's Manual, Volume 3C". 278 */ 279 "GenuineIntel", 280 CPUVENDOR_INTEL, 281 "Intel", 282 /* Family 4 */ 283 { { 284 CPUCLASS_486, 285 { 286 "486DX", "486DX", "486SX", "486DX2", "486SL", 287 "486SX2", 0, "486DX2 W/B Enhanced", 288 "486DX4", 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "486", /* Default */ 291 NULL, 292 NULL, 293 intel_cpu_cacheinfo, 294 }, 295 /* Family 5 */ 296 { 297 CPUCLASS_586, 298 { 299 "Pentium (P5 A-step)", "Pentium (P5)", 300 "Pentium (P54C)", "Pentium (P24T)", 301 "Pentium/MMX", "Pentium", 0, 302 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 303 0, 0, 0, 0, 0, 0, 0, 304 }, 305 "Pentium", /* Default */ 306 NULL, 307 NULL, 308 intel_cpu_cacheinfo, 309 }, 310 /* Family 6 */ 311 { 312 CPUCLASS_686, 313 { 314 [0x00] = "Pentium Pro (A-step)", 315 [0x01] = "Pentium Pro", 316 [0x03] = "Pentium II (Klamath)", 317 [0x04] = "Pentium Pro", 318 [0x05] = "Pentium II/Celeron (Deschutes)", 319 [0x06] = "Celeron (Mendocino)", 320 [0x07] = "Pentium III (Katmai)", 321 [0x08] = "Pentium III (Coppermine)", 322 [0x09] = "Pentium M (Banias)", 323 [0x0a] = "Pentium III Xeon (Cascades)", 324 [0x0b] = "Pentium III (Tualatin)", 325 [0x0d] = "Pentium M (Dothan)", 326 [0x0e] = "Pentium Core Duo, Core solo", 327 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 328 "Core 2 Quad 6xxx, " 329 "Core 2 Extreme 6xxx, " 330 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 331 "and Pentium DC", 332 [0x15] = "EP80579 Integrated Processor", 333 [0x16] = "Celeron (45nm)", 334 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 335 "Core 2 Quad 8xxx and 9xxx", 336 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 337 "(Nehalem)", 338 [0x1c] = "45nm Atom Family", 339 [0x1d] = "XeonMP 74xx (Nehalem)", 340 [0x1e] = "Core i7 and i5", 341 [0x1f] = "Core i7 and i5", 342 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x26] = "Atom Family", 344 [0x27] = "Atom Family", 345 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 346 "i3 2xxx", 347 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 348 [0x2d] = "Xeon E5 Sandy Bridge family, " 349 "Core i7-39xx Extreme", 350 [0x2e] = "Xeon 75xx & 65xx", 351 [0x2f] = "Xeon E7 family", 352 [0x35] = "Atom Family", 353 [0x36] = "Atom S1000", 354 [0x37] = "Atom E3000, Z3[67]00", 355 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 356 "Ivy Bridge", 357 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 360 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 361 "Core i7-49xx Extreme", 362 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 363 "Core i7-59xx Extreme", 364 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 369 [0x4a] = "Atom Z3400", 370 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 371 [0x4d] = "Atom C2000", 372 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 373 [0x4f] = "Future gen Xeon (Broadwell)", 374 [0x56] = "Xeon D-1500 (Broadwell)", 375 [0x57] = "Next gen Xeon Phi", 376 [0x5a] = "Atom E3500", 377 [0x5d] = "Atom X3-C3000 (Silvermont)", 378 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 379 }, 380 "Pentium Pro, II or III", /* Default */ 381 NULL, 382 intel_family_new_probe, 383 intel_cpu_cacheinfo, 384 }, 385 /* Family > 6 */ 386 { 387 CPUCLASS_686, 388 { 389 0, 0, 0, 0, 0, 0, 0, 0, 390 0, 0, 0, 0, 0, 0, 0, 0, 391 }, 392 "Pentium 4", /* Default */ 393 NULL, 394 intel_family_new_probe, 395 intel_cpu_cacheinfo, 396 } } 397 }, 398 { 399 "AuthenticAMD", 400 CPUVENDOR_AMD, 401 "AMD", 402 /* Family 4 */ 403 { { 404 CPUCLASS_486, 405 { 406 0, 0, 0, "Am486DX2 W/T", 407 0, 0, 0, "Am486DX2 W/B", 408 "Am486DX4 W/T or Am5x86 W/T 150", 409 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 410 0, 0, "Am5x86 W/T 133/160", 411 "Am5x86 W/B 133/160", 412 }, 413 "Am486 or Am5x86", /* Default */ 414 NULL, 415 NULL, 416 NULL, 417 }, 418 /* Family 5 */ 419 { 420 CPUCLASS_586, 421 { 422 "K5", "K5", "K5", "K5", 0, 0, "K6", 423 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 424 "K6-2+/III+", 0, 0, 425 }, 426 "K5 or K6", /* Default */ 427 amd_family5_setup, 428 NULL, 429 amd_cpu_cacheinfo, 430 }, 431 /* Family 6 */ 432 { 433 CPUCLASS_686, 434 { 435 0, "Athlon Model 1", "Athlon Model 2", 436 "Duron", "Athlon Model 4 (Thunderbird)", 437 0, "Athlon", "Duron", "Athlon", 0, 438 "Athlon", 0, 0, 0, 0, 0, 439 }, 440 "K7 (Athlon)", /* Default */ 441 NULL, 442 amd_family6_probe, 443 amd_cpu_cacheinfo, 444 }, 445 /* Family > 6 */ 446 { 447 CPUCLASS_686, 448 { 449 0, 0, 0, 0, 0, 0, 0, 0, 450 0, 0, 0, 0, 0, 0, 0, 0, 451 }, 452 "Unknown K8 (Athlon)", /* Default */ 453 NULL, 454 amd_family6_probe, 455 amd_cpu_cacheinfo, 456 } } 457 }, 458 { 459 "CyrixInstead", 460 CPUVENDOR_CYRIX, 461 "Cyrix", 462 /* Family 4 */ 463 { { 464 CPUCLASS_486, 465 { 466 0, 0, 0, 467 "MediaGX", 468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 469 }, 470 "486", /* Default */ 471 cyrix6x86_cpu_setup, /* XXX ?? */ 472 NULL, 473 NULL, 474 }, 475 /* Family 5 */ 476 { 477 CPUCLASS_586, 478 { 479 0, 0, "6x86", 0, 480 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 482 }, 483 "6x86", /* Default */ 484 cyrix6x86_cpu_setup, 485 NULL, 486 NULL, 487 }, 488 /* Family 6 */ 489 { 490 CPUCLASS_686, 491 { 492 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 494 }, 495 "6x86MX", /* Default */ 496 cyrix6x86_cpu_setup, 497 NULL, 498 NULL, 499 }, 500 /* Family > 6 */ 501 { 502 CPUCLASS_686, 503 { 504 0, 0, 0, 0, 0, 0, 0, 0, 505 0, 0, 0, 0, 0, 0, 0, 0, 506 }, 507 "Unknown 6x86MX", /* Default */ 508 NULL, 509 NULL, 510 NULL, 511 } } 512 }, 513 { /* MediaGX is now owned by National Semiconductor */ 514 "Geode by NSC", 515 CPUVENDOR_CYRIX, /* XXX */ 516 "National Semiconductor", 517 /* Family 4, NSC never had any of these */ 518 { { 519 CPUCLASS_486, 520 { 521 0, 0, 0, 0, 0, 0, 0, 0, 522 0, 0, 0, 0, 0, 0, 0, 0, 523 }, 524 "486 compatible", /* Default */ 525 NULL, 526 NULL, 527 NULL, 528 }, 529 /* Family 5: Geode family, formerly MediaGX */ 530 { 531 CPUCLASS_586, 532 { 533 0, 0, 0, 0, 534 "Geode GX1", 535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 536 }, 537 "Geode", /* Default */ 538 cyrix6x86_cpu_setup, 539 NULL, 540 amd_cpu_cacheinfo, 541 }, 542 /* Family 6, not yet available from NSC */ 543 { 544 CPUCLASS_686, 545 { 546 0, 0, 0, 0, 0, 0, 0, 0, 547 0, 0, 0, 0, 0, 0, 0, 0, 548 }, 549 "Pentium Pro compatible", /* Default */ 550 NULL, 551 NULL, 552 NULL, 553 }, 554 /* Family > 6, not yet available from NSC */ 555 { 556 CPUCLASS_686, 557 { 558 0, 0, 0, 0, 0, 0, 0, 0, 559 0, 0, 0, 0, 0, 0, 0, 0, 560 }, 561 "Pentium Pro compatible", /* Default */ 562 NULL, 563 NULL, 564 NULL, 565 } } 566 }, 567 { 568 "CentaurHauls", 569 CPUVENDOR_IDT, 570 "IDT", 571 /* Family 4, IDT never had any of these */ 572 { { 573 CPUCLASS_486, 574 { 575 0, 0, 0, 0, 0, 0, 0, 0, 576 0, 0, 0, 0, 0, 0, 0, 0, 577 }, 578 "486 compatible", /* Default */ 579 NULL, 580 NULL, 581 NULL, 582 }, 583 /* Family 5 */ 584 { 585 CPUCLASS_586, 586 { 587 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 588 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 589 }, 590 "WinChip", /* Default */ 591 winchip_cpu_setup, 592 NULL, 593 NULL, 594 }, 595 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 596 { 597 CPUCLASS_686, 598 { 599 0, 0, 0, 0, 0, 0, "C3 Samuel", 600 "C3 Samuel 2/Ezra", "C3 Ezra-T", 601 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 602 0, "VIA Nano", 603 }, 604 "Unknown VIA/IDT", /* Default */ 605 NULL, 606 via_cpu_probe, 607 via_cpu_cacheinfo, 608 }, 609 /* Family > 6, not yet available from VIA */ 610 { 611 CPUCLASS_686, 612 { 613 0, 0, 0, 0, 0, 0, 0, 0, 614 0, 0, 0, 0, 0, 0, 0, 0, 615 }, 616 "Pentium Pro compatible", /* Default */ 617 NULL, 618 NULL, 619 NULL, 620 } } 621 }, 622 { 623 "GenuineTMx86", 624 CPUVENDOR_TRANSMETA, 625 "Transmeta", 626 /* Family 4, Transmeta never had any of these */ 627 { { 628 CPUCLASS_486, 629 { 630 0, 0, 0, 0, 0, 0, 0, 0, 631 0, 0, 0, 0, 0, 0, 0, 0, 632 }, 633 "486 compatible", /* Default */ 634 NULL, 635 NULL, 636 NULL, 637 }, 638 /* Family 5 */ 639 { 640 CPUCLASS_586, 641 { 642 0, 0, 0, 0, 0, 0, 0, 0, 643 0, 0, 0, 0, 0, 0, 0, 0, 644 }, 645 "Crusoe", /* Default */ 646 NULL, 647 NULL, 648 transmeta_cpu_info, 649 }, 650 /* Family 6, not yet available from Transmeta */ 651 { 652 CPUCLASS_686, 653 { 654 0, 0, 0, 0, 0, 0, 0, 0, 655 0, 0, 0, 0, 0, 0, 0, 0, 656 }, 657 "Pentium Pro compatible", /* Default */ 658 NULL, 659 NULL, 660 NULL, 661 }, 662 /* Family > 6, not yet available from Transmeta */ 663 { 664 CPUCLASS_686, 665 { 666 0, 0, 0, 0, 0, 0, 0, 0, 667 0, 0, 0, 0, 0, 0, 0, 0, 668 }, 669 "Pentium Pro compatible", /* Default */ 670 NULL, 671 NULL, 672 NULL, 673 } } 674 } 675 }; 676 677 /* 678 * disable the TSC such that we don't use the TSC in microtime(9) 679 * because some CPUs got the implementation wrong. 680 */ 681 static void 682 disable_tsc(struct cpu_info *ci) 683 { 684 if (ci->ci_feat_val[0] & CPUID_TSC) { 685 ci->ci_feat_val[0] &= ~CPUID_TSC; 686 aprint_error("WARNING: broken TSC disabled\n"); 687 } 688 } 689 690 static void 691 amd_family5_setup(struct cpu_info *ci) 692 { 693 694 switch (ci->ci_model) { 695 case 0: /* AMD-K5 Model 0 */ 696 /* 697 * According to the AMD Processor Recognition App Note, 698 * the AMD-K5 Model 0 uses the wrong bit to indicate 699 * support for global PTEs, instead using bit 9 (APIC) 700 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 701 */ 702 if (ci->ci_feat_val[0] & CPUID_APIC) 703 ci->ci_feat_val[0] = 704 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 705 /* 706 * XXX But pmap_pg_g is already initialized -- need to kick 707 * XXX the pmap somehow. How does the MP branch do this? 708 */ 709 break; 710 } 711 } 712 713 static void 714 cyrix6x86_cpu_setup(struct cpu_info *ci) 715 { 716 717 /* 718 * Do not disable the TSC on the Geode GX, it's reported to 719 * work fine. 720 */ 721 if (ci->ci_signature != 0x552) 722 disable_tsc(ci); 723 } 724 725 static void 726 winchip_cpu_setup(struct cpu_info *ci) 727 { 728 switch (ci->ci_model) { 729 case 4: /* WinChip C6 */ 730 disable_tsc(ci); 731 } 732 } 733 734 735 static const char * 736 intel_family6_name(struct cpu_info *ci) 737 { 738 const char *ret = NULL; 739 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 740 741 if (ci->ci_model == 5) { 742 switch (l2cache) { 743 case 0: 744 case 128 * 1024: 745 ret = "Celeron (Covington)"; 746 break; 747 case 256 * 1024: 748 ret = "Mobile Pentium II (Dixon)"; 749 break; 750 case 512 * 1024: 751 ret = "Pentium II"; 752 break; 753 case 1 * 1024 * 1024: 754 case 2 * 1024 * 1024: 755 ret = "Pentium II Xeon"; 756 break; 757 } 758 } else if (ci->ci_model == 6) { 759 switch (l2cache) { 760 case 256 * 1024: 761 case 512 * 1024: 762 ret = "Mobile Pentium II"; 763 break; 764 } 765 } else if (ci->ci_model == 7) { 766 switch (l2cache) { 767 case 512 * 1024: 768 ret = "Pentium III"; 769 break; 770 case 1 * 1024 * 1024: 771 case 2 * 1024 * 1024: 772 ret = "Pentium III Xeon"; 773 break; 774 } 775 } else if (ci->ci_model >= 8) { 776 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 777 switch (ci->ci_brand_id) { 778 case 0x3: 779 if (ci->ci_signature == 0x6B1) 780 ret = "Celeron"; 781 break; 782 case 0x8: 783 if (ci->ci_signature >= 0xF13) 784 ret = "genuine processor"; 785 break; 786 case 0xB: 787 if (ci->ci_signature >= 0xF13) 788 ret = "Xeon MP"; 789 break; 790 case 0xE: 791 if (ci->ci_signature < 0xF13) 792 ret = "Xeon"; 793 break; 794 } 795 if (ret == NULL) 796 ret = i386_intel_brand[ci->ci_brand_id]; 797 } 798 } 799 800 return ret; 801 } 802 803 /* 804 * Identify AMD64 CPU names from cpuid. 805 * 806 * Based on: 807 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 808 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 809 * "Revision Guide for AMD NPT Family 0Fh Processors" 810 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 811 * and other miscellaneous reports. 812 * 813 * This is all rather pointless, these are cross 'brand' since the raw 814 * silicon is shared. 815 */ 816 static const char * 817 amd_amd64_name(struct cpu_info *ci) 818 { 819 static char family_str[32]; 820 821 /* Only called if family >= 15 */ 822 823 switch (ci->ci_family) { 824 case 15: 825 switch (ci->ci_model) { 826 case 0x21: /* rev JH-E1/E6 */ 827 case 0x41: /* rev JH-F2 */ 828 return "Dual-Core Opteron"; 829 case 0x23: /* rev JH-E6 (Toledo) */ 830 return "Dual-Core Opteron or Athlon 64 X2"; 831 case 0x43: /* rev JH-F2 (Windsor) */ 832 return "Athlon 64 FX or Athlon 64 X2"; 833 case 0x24: /* rev SH-E5 (Lancaster?) */ 834 return "Mobile Athlon 64 or Turion 64"; 835 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 836 return "Opteron or Athlon 64 FX"; 837 case 0x15: /* rev SH-D0 */ 838 case 0x25: /* rev SH-E4 */ 839 return "Opteron"; 840 case 0x27: /* rev DH-E4, SH-E4 */ 841 return "Athlon 64 or Athlon 64 FX or Opteron"; 842 case 0x48: /* rev BH-F2 */ 843 return "Turion 64 X2"; 844 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 845 case 0x07: /* rev SH-CG (ClawHammer) */ 846 case 0x0b: /* rev CH-CG */ 847 case 0x14: /* rev SH-D0 */ 848 case 0x17: /* rev SH-D0 */ 849 case 0x1b: /* rev CH-D0 */ 850 return "Athlon 64"; 851 case 0x2b: /* rev BH-E4 (Manchester) */ 852 case 0x4b: /* rev BH-F2 (Windsor) */ 853 return "Athlon 64 X2"; 854 case 0x6b: /* rev BH-G1 (Brisbane) */ 855 return "Athlon X2 or Athlon 64 X2"; 856 case 0x08: /* rev CH-CG */ 857 case 0x0c: /* rev DH-CG (Newcastle) */ 858 case 0x0e: /* rev DH-CG (Newcastle?) */ 859 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 860 case 0x18: /* rev CH-D0 */ 861 case 0x1c: /* rev DH-D0 (Winchester) */ 862 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 863 case 0x2c: /* rev DH-E3/E6 */ 864 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 865 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 866 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 867 case 0x6f: /* rev DH-G1 */ 868 return "Athlon 64 or Sempron"; 869 default: 870 break; 871 } 872 return "Unknown AMD64 CPU"; 873 874 #if 0 875 case 16: 876 return "Family 10h"; 877 case 17: 878 return "Family 11h"; 879 case 18: 880 return "Family 12h"; 881 case 19: 882 return "Family 14h"; 883 case 20: 884 return "Family 15h"; 885 #endif 886 887 default: 888 break; 889 } 890 891 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 892 return family_str; 893 } 894 895 static void 896 intel_family_new_probe(struct cpu_info *ci) 897 { 898 uint32_t descs[4]; 899 900 x86_cpuid(0x80000000, descs); 901 902 /* 903 * Determine extended feature flags. 904 */ 905 if (descs[0] >= 0x80000001) { 906 x86_cpuid(0x80000001, descs); 907 ci->ci_feat_val[2] |= descs[3]; 908 ci->ci_feat_val[3] |= descs[2]; 909 } 910 } 911 912 static void 913 via_cpu_probe(struct cpu_info *ci) 914 { 915 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 916 u_int descs[4]; 917 u_int lfunc; 918 919 /* 920 * Determine the largest extended function value. 921 */ 922 x86_cpuid(0x80000000, descs); 923 lfunc = descs[0]; 924 925 /* 926 * Determine the extended feature flags. 927 */ 928 if (lfunc >= 0x80000001) { 929 x86_cpuid(0x80000001, descs); 930 ci->ci_feat_val[2] |= descs[3]; 931 } 932 933 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 934 return; 935 936 /* Nehemiah or Esther */ 937 x86_cpuid(0xc0000000, descs); 938 lfunc = descs[0]; 939 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 940 return; 941 942 x86_cpuid(0xc0000001, descs); 943 lfunc = descs[3]; 944 ci->ci_feat_val[4] = lfunc; 945 } 946 947 static void 948 amd_family6_probe(struct cpu_info *ci) 949 { 950 uint32_t descs[4]; 951 char *p; 952 size_t i; 953 954 x86_cpuid(0x80000000, descs); 955 956 /* 957 * Determine the extended feature flags. 958 */ 959 if (descs[0] >= 0x80000001) { 960 x86_cpuid(0x80000001, descs); 961 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 962 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 963 } 964 965 if (*cpu_brand_string == '\0') 966 return; 967 968 for (i = 1; i < __arraycount(amd_brand); i++) 969 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 970 ci->ci_brand_id = i; 971 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 972 break; 973 } 974 } 975 976 static void 977 intel_cpu_cacheinfo(struct cpu_info *ci) 978 { 979 const struct x86_cache_info *cai; 980 u_int descs[4]; 981 int iterations, i, j; 982 int type, level; 983 int ways, partitions, linesize, sets; 984 int caitype = -1; 985 int totalsize; 986 uint8_t desc; 987 988 /* Return if the cpu is old pre-cpuid instruction cpu */ 989 if (ci->ci_cpu_type >= 0) 990 return; 991 992 if (ci->ci_cpuid_level < 2) 993 return; 994 995 /* 996 * Parse the cache info from `cpuid leaf 2', if we have it. 997 * XXX This is kinda ugly, but hey, so is the architecture... 998 */ 999 x86_cpuid(2, descs); 1000 iterations = descs[0] & 0xff; 1001 while (iterations-- > 0) { 1002 for (i = 0; i < 4; i++) { 1003 if (descs[i] & 0x80000000) 1004 continue; 1005 for (j = 0; j < 4; j++) { 1006 /* 1007 * The least significant byte in EAX 1008 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1009 * it should be ignored. 1010 */ 1011 if (i == 0 && j == 0) 1012 continue; 1013 desc = (descs[i] >> (j * 8)) & 0xff; 1014 if (desc == 0) 1015 continue; 1016 cai = cache_info_lookup(intel_cpuid_cache_info, 1017 desc); 1018 if (cai != NULL) 1019 ci->ci_cinfo[cai->cai_index] = *cai; 1020 else if ((verbose != 0) && (desc != 0xff)) 1021 printf("Unknown cacheinfo desc %02x\n", 1022 desc); 1023 } 1024 } 1025 x86_cpuid(2, descs); 1026 } 1027 1028 if (ci->ci_cpuid_level < 4) 1029 return; 1030 1031 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1032 for (i = 0; ; i++) { 1033 x86_cpuid2(4, i, descs); 1034 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1035 if (type == CPUID_DCP_CACHETYPE_N) 1036 break; 1037 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1038 switch (level) { 1039 case 1: 1040 if (type == CPUID_DCP_CACHETYPE_I) 1041 caitype = CAI_ICACHE; 1042 else if (type == CPUID_DCP_CACHETYPE_D) 1043 caitype = CAI_DCACHE; 1044 else 1045 caitype = -1; 1046 break; 1047 case 2: 1048 if (type == CPUID_DCP_CACHETYPE_U) 1049 caitype = CAI_L2CACHE; 1050 else 1051 caitype = -1; 1052 break; 1053 case 3: 1054 if (type == CPUID_DCP_CACHETYPE_U) 1055 caitype = CAI_L3CACHE; 1056 else 1057 caitype = -1; 1058 break; 1059 default: 1060 caitype = -1; 1061 break; 1062 } 1063 if (caitype == -1) { 1064 printf("unknown cache level&type (%d & %d)\n", 1065 level, type); 1066 continue; 1067 } 1068 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1069 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1070 + 1; 1071 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1072 + 1; 1073 sets = descs[2] + 1; 1074 totalsize = ways * partitions * linesize * sets; 1075 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1076 ci->ci_cinfo[caitype].cai_associativity = ways; 1077 ci->ci_cinfo[caitype].cai_linesize = linesize; 1078 } 1079 } 1080 1081 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1082 AMD_L2CACHE_INFO; 1083 1084 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1085 AMD_L3CACHE_INFO; 1086 1087 static void 1088 amd_cpu_cacheinfo(struct cpu_info *ci) 1089 { 1090 const struct x86_cache_info *cp; 1091 struct x86_cache_info *cai; 1092 u_int descs[4]; 1093 u_int lfunc; 1094 1095 /* 1096 * K5 model 0 has none of this info. 1097 */ 1098 if (ci->ci_family == 5 && ci->ci_model == 0) 1099 return; 1100 1101 /* 1102 * Determine the largest extended function value. 1103 */ 1104 x86_cpuid(0x80000000, descs); 1105 lfunc = descs[0]; 1106 1107 /* 1108 * Determine L1 cache/TLB info. 1109 */ 1110 if (lfunc < 0x80000005) { 1111 /* No L1 cache info available. */ 1112 return; 1113 } 1114 1115 x86_cpuid(0x80000005, descs); 1116 1117 /* 1118 * K6-III and higher have large page TLBs. 1119 */ 1120 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1121 cai = &ci->ci_cinfo[CAI_ITLB2]; 1122 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1123 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1124 cai->cai_linesize = largepagesize; 1125 1126 cai = &ci->ci_cinfo[CAI_DTLB2]; 1127 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1128 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1129 cai->cai_linesize = largepagesize; 1130 } 1131 1132 cai = &ci->ci_cinfo[CAI_ITLB]; 1133 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1134 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1135 cai->cai_linesize = (4 * 1024); 1136 1137 cai = &ci->ci_cinfo[CAI_DTLB]; 1138 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1139 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1140 cai->cai_linesize = (4 * 1024); 1141 1142 cai = &ci->ci_cinfo[CAI_DCACHE]; 1143 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1144 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1145 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1146 1147 cai = &ci->ci_cinfo[CAI_ICACHE]; 1148 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1149 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1150 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1151 1152 /* 1153 * Determine L2 cache/TLB info. 1154 */ 1155 if (lfunc < 0x80000006) { 1156 /* No L2 cache info available. */ 1157 return; 1158 } 1159 1160 x86_cpuid(0x80000006, descs); 1161 1162 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1163 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1164 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1165 cai->cai_linesize = (4 * 1024); 1166 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1167 cai->cai_associativity); 1168 if (cp != NULL) 1169 cai->cai_associativity = cp->cai_associativity; 1170 else 1171 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1172 1173 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1174 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1175 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1176 cai->cai_linesize = largepagesize; 1177 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1178 cai->cai_associativity); 1179 if (cp != NULL) 1180 cai->cai_associativity = cp->cai_associativity; 1181 else 1182 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1183 1184 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1185 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1186 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1187 cai->cai_linesize = (4 * 1024); 1188 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1189 cai->cai_associativity); 1190 if (cp != NULL) 1191 cai->cai_associativity = cp->cai_associativity; 1192 else 1193 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1194 1195 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1196 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1197 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1198 cai->cai_linesize = largepagesize; 1199 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1200 cai->cai_associativity); 1201 if (cp != NULL) 1202 cai->cai_associativity = cp->cai_associativity; 1203 else 1204 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1205 1206 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1207 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1208 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1209 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1210 1211 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1212 cai->cai_associativity); 1213 if (cp != NULL) 1214 cai->cai_associativity = cp->cai_associativity; 1215 else 1216 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1217 1218 /* 1219 * Determine L3 cache info on AMD Family 10h and newer processors 1220 */ 1221 if (ci->ci_family >= 0x10) { 1222 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1223 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1224 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1225 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1226 1227 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1228 cai->cai_associativity); 1229 if (cp != NULL) 1230 cai->cai_associativity = cp->cai_associativity; 1231 else 1232 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1233 } 1234 1235 /* 1236 * Determine 1GB TLB info. 1237 */ 1238 if (lfunc < 0x80000019) { 1239 /* No 1GB TLB info available. */ 1240 return; 1241 } 1242 1243 x86_cpuid(0x80000019, descs); 1244 1245 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1246 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1247 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1248 cai->cai_linesize = (1024 * 1024 * 1024); 1249 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1250 cai->cai_associativity); 1251 if (cp != NULL) 1252 cai->cai_associativity = cp->cai_associativity; 1253 else 1254 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1255 1256 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1257 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1258 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1259 cai->cai_linesize = (1024 * 1024 * 1024); 1260 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1261 cai->cai_associativity); 1262 if (cp != NULL) 1263 cai->cai_associativity = cp->cai_associativity; 1264 else 1265 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1266 1267 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1268 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1269 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1270 cai->cai_linesize = (1024 * 1024 * 1024); 1271 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1272 cai->cai_associativity); 1273 if (cp != NULL) 1274 cai->cai_associativity = cp->cai_associativity; 1275 else 1276 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1277 1278 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1279 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1280 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1281 cai->cai_linesize = (1024 * 1024 * 1024); 1282 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1283 cai->cai_associativity); 1284 if (cp != NULL) 1285 cai->cai_associativity = cp->cai_associativity; 1286 else 1287 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1288 } 1289 1290 static void 1291 via_cpu_cacheinfo(struct cpu_info *ci) 1292 { 1293 struct x86_cache_info *cai; 1294 int stepping; 1295 u_int descs[4]; 1296 u_int lfunc; 1297 1298 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1299 1300 /* 1301 * Determine the largest extended function value. 1302 */ 1303 x86_cpuid(0x80000000, descs); 1304 lfunc = descs[0]; 1305 1306 /* 1307 * Determine L1 cache/TLB info. 1308 */ 1309 if (lfunc < 0x80000005) { 1310 /* No L1 cache info available. */ 1311 return; 1312 } 1313 1314 x86_cpuid(0x80000005, descs); 1315 1316 cai = &ci->ci_cinfo[CAI_ITLB]; 1317 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1318 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1319 cai->cai_linesize = (4 * 1024); 1320 1321 cai = &ci->ci_cinfo[CAI_DTLB]; 1322 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1323 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1324 cai->cai_linesize = (4 * 1024); 1325 1326 cai = &ci->ci_cinfo[CAI_DCACHE]; 1327 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1328 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1329 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1330 if (ci->ci_model == 9 && stepping == 8) { 1331 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1332 cai->cai_associativity = 2; 1333 } 1334 1335 cai = &ci->ci_cinfo[CAI_ICACHE]; 1336 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1337 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1338 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1339 if (ci->ci_model == 9 && stepping == 8) { 1340 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1341 cai->cai_associativity = 2; 1342 } 1343 1344 /* 1345 * Determine L2 cache/TLB info. 1346 */ 1347 if (lfunc < 0x80000006) { 1348 /* No L2 cache info available. */ 1349 return; 1350 } 1351 1352 x86_cpuid(0x80000006, descs); 1353 1354 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1355 if (ci->ci_model >= 9) { 1356 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1357 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1358 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1359 } else { 1360 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1361 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1362 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1363 } 1364 } 1365 1366 static void 1367 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1368 { 1369 u_int descs[4]; 1370 1371 x86_cpuid(0x80860007, descs); 1372 *frequency = descs[0]; 1373 *voltage = descs[1]; 1374 *percentage = descs[2]; 1375 } 1376 1377 static void 1378 transmeta_cpu_info(struct cpu_info *ci) 1379 { 1380 u_int descs[4], nreg; 1381 u_int frequency, voltage, percentage; 1382 1383 x86_cpuid(0x80860000, descs); 1384 nreg = descs[0]; 1385 if (nreg >= 0x80860001) { 1386 x86_cpuid(0x80860001, descs); 1387 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1388 (descs[1] >> 24) & 0xff, 1389 (descs[1] >> 16) & 0xff, 1390 (descs[1] >> 8) & 0xff, 1391 descs[1] & 0xff); 1392 } 1393 if (nreg >= 0x80860002) { 1394 x86_cpuid(0x80860002, descs); 1395 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1396 (descs[1] >> 24) & 0xff, 1397 (descs[1] >> 16) & 0xff, 1398 (descs[1] >> 8) & 0xff, 1399 descs[1] & 0xff, 1400 descs[2]); 1401 } 1402 if (nreg >= 0x80860006) { 1403 union { 1404 char text[65]; 1405 u_int descs[4][4]; 1406 } info; 1407 int i; 1408 1409 for (i=0; i<4; i++) { 1410 x86_cpuid(0x80860003 + i, info.descs[i]); 1411 } 1412 info.text[64] = '\0'; 1413 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1414 } 1415 1416 if (nreg >= 0x80860007) { 1417 tmx86_get_longrun_status(&frequency, 1418 &voltage, &percentage); 1419 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1420 frequency, voltage, percentage); 1421 } 1422 } 1423 1424 static void 1425 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1426 { 1427 u_int descs[4]; 1428 int i; 1429 uint32_t brand[12]; 1430 1431 memset(ci, 0, sizeof(*ci)); 1432 ci->ci_dev = cpuname; 1433 1434 ci->ci_cpu_type = x86_identify(); 1435 if (ci->ci_cpu_type >= 0) { 1436 /* Old pre-cpuid instruction cpu */ 1437 ci->ci_cpuid_level = -1; 1438 return; 1439 } 1440 1441 /* 1442 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1443 * function. 1444 */ 1445 1446 /* 1447 * Fn0000_0000: 1448 * - Save cpuid max level. 1449 * - Save vendor string. 1450 */ 1451 x86_cpuid(0, descs); 1452 ci->ci_cpuid_level = descs[0]; 1453 /* Save vendor string */ 1454 ci->ci_vendor[0] = descs[1]; 1455 ci->ci_vendor[2] = descs[2]; 1456 ci->ci_vendor[1] = descs[3]; 1457 ci->ci_vendor[3] = 0; 1458 1459 /* 1460 * Fn8000_0000: 1461 * - Get cpuid extended function's max level. 1462 */ 1463 x86_cpuid(0x80000000, descs); 1464 if (descs[0] >= 0x80000000) 1465 ci->ci_cpuid_extlevel = descs[0]; 1466 else { 1467 /* Set lower value than 0x80000000 */ 1468 ci->ci_cpuid_extlevel = 0; 1469 } 1470 1471 /* 1472 * Fn8000_000[2-4]: 1473 * - Save brand string. 1474 */ 1475 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1476 x86_cpuid(0x80000002, brand); 1477 x86_cpuid(0x80000003, brand + 4); 1478 x86_cpuid(0x80000004, brand + 8); 1479 for (i = 0; i < 48; i++) 1480 if (((char *) brand)[i] != ' ') 1481 break; 1482 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1483 } 1484 1485 if (ci->ci_cpuid_level < 1) 1486 return; 1487 1488 /* 1489 * Fn0000_0001: 1490 * - Get CPU family, model and stepping (from eax). 1491 * - Initial local APIC ID and brand ID (from ebx) 1492 * - CPUID2 (from ecx) 1493 * - CPUID (from edx) 1494 */ 1495 x86_cpuid(1, descs); 1496 ci->ci_signature = descs[0]; 1497 1498 /* Extract full family/model values */ 1499 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1500 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1501 1502 /* Brand is low order 8 bits of ebx */ 1503 ci->ci_brand_id = descs[1] & 0xff; 1504 /* Initial local APIC ID */ 1505 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1506 1507 ci->ci_feat_val[1] = descs[2]; 1508 ci->ci_feat_val[0] = descs[3]; 1509 1510 if (ci->ci_cpuid_level < 3) 1511 return; 1512 1513 /* 1514 * If the processor serial number misfeature is present and supported, 1515 * extract it here. 1516 */ 1517 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1518 ci->ci_cpu_serial[0] = ci->ci_signature; 1519 x86_cpuid(3, descs); 1520 ci->ci_cpu_serial[2] = descs[2]; 1521 ci->ci_cpu_serial[1] = descs[3]; 1522 } 1523 1524 if (ci->ci_cpuid_level < 0x7) 1525 return; 1526 1527 x86_cpuid(7, descs); 1528 ci->ci_feat_val[5] = descs[1]; 1529 ci->ci_feat_val[6] = descs[2]; 1530 1531 if (ci->ci_cpuid_level < 0xd) 1532 return; 1533 1534 /* Get support XCR0 bits */ 1535 x86_cpuid2(0xd, 0, descs); 1536 ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */ 1537 ci->ci_cur_xsave = descs[1]; 1538 ci->ci_max_xsave = descs[2]; 1539 1540 /* Additional flags (eg xsaveopt support) */ 1541 x86_cpuid2(0xd, 1, descs); 1542 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1543 } 1544 1545 static void 1546 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1547 { 1548 uint32_t descs[4]; 1549 char hv_sig[13]; 1550 char *p; 1551 const char *hv_name; 1552 int i; 1553 1554 /* 1555 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1556 * http://lkml.org/lkml/2008/10/1/246 1557 * 1558 * KB1009458: Mechanisms to determine if software is running in 1559 * a VMware virtual machine 1560 * http://kb.vmware.com/kb/1009458 1561 */ 1562 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1563 x86_cpuid(0x40000000, descs); 1564 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1565 memcpy(p, &descs[i], sizeof(descs[i])); 1566 *p = '\0'; 1567 /* 1568 * HV vendor ID string 1569 * ------------+-------------- 1570 * KVM "KVMKVMKVM" 1571 * Microsoft "Microsoft Hv" 1572 * VMware "VMwareVMware" 1573 * Xen "XenVMMXenVMM" 1574 */ 1575 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1576 hv_name = "KVM"; 1577 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1578 hv_name = "Hyper-V"; 1579 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1580 hv_name = "VMware"; 1581 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1582 hv_name = "Xen"; 1583 else 1584 hv_name = "unknown"; 1585 1586 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1587 } 1588 } 1589 1590 static void 1591 cpu_probe_features(struct cpu_info *ci) 1592 { 1593 const struct cpu_cpuid_nameclass *cpup = NULL; 1594 unsigned int i; 1595 1596 if (ci->ci_cpuid_level < 1) 1597 return; 1598 1599 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1600 if (!strncmp((char *)ci->ci_vendor, 1601 i386_cpuid_cpus[i].cpu_id, 12)) { 1602 cpup = &i386_cpuid_cpus[i]; 1603 break; 1604 } 1605 } 1606 1607 if (cpup == NULL) 1608 return; 1609 1610 i = ci->ci_family - CPU_MINFAMILY; 1611 1612 if (i >= __arraycount(cpup->cpu_family)) 1613 i = __arraycount(cpup->cpu_family) - 1; 1614 1615 if (cpup->cpu_family[i].cpu_probe == NULL) 1616 return; 1617 1618 (*cpup->cpu_family[i].cpu_probe)(ci); 1619 } 1620 1621 static void 1622 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1623 { 1624 char buf[32 * 16]; 1625 char *bp; 1626 1627 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1628 1629 if (val == 0 || fmt == NULL) 1630 return; 1631 1632 snprintb_m(buf, sizeof(buf), fmt, val, 1633 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1634 bp = buf; 1635 while (*bp != '\0') { 1636 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1637 bp += strlen(bp) + 1; 1638 } 1639 } 1640 1641 static void 1642 identifycpu_cpuids(struct cpu_info *ci) 1643 { 1644 const char *cpuname = ci->ci_dev; 1645 u_int lp_max = 1; /* logical processors per package */ 1646 u_int smt_max; /* smt per core */ 1647 u_int core_max = 1; /* core per package */ 1648 u_int smt_bits, core_bits; 1649 uint32_t descs[4]; 1650 1651 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1652 ci->ci_packageid = ci->ci_initapicid; 1653 ci->ci_coreid = 0; 1654 ci->ci_smtid = 0; 1655 if (cpu_vendor != CPUVENDOR_INTEL) { 1656 return; 1657 } 1658 1659 /* 1660 * 253668.pdf 7.10.2 1661 */ 1662 1663 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1664 x86_cpuid(1, descs); 1665 lp_max = (descs[1] >> 16) & 0xff; 1666 } 1667 if (ci->ci_cpuid_level >= 4) { 1668 x86_cpuid2(4, 0, descs); 1669 core_max = (descs[0] >> 26) + 1; 1670 } 1671 assert(lp_max >= core_max); 1672 smt_max = lp_max / core_max; 1673 smt_bits = ilog2(smt_max - 1) + 1; 1674 core_bits = ilog2(core_max - 1) + 1; 1675 if (smt_bits + core_bits) { 1676 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1677 } 1678 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1679 ci->ci_packageid); 1680 if (core_bits) { 1681 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1682 1683 ci->ci_coreid = 1684 __SHIFTOUT(ci->ci_initapicid, core_mask); 1685 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1686 } 1687 if (smt_bits) { 1688 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1689 1690 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1691 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1692 } 1693 } 1694 1695 void 1696 identifycpu(int fd, const char *cpuname) 1697 { 1698 const char *name = "", *modifier, *vendorname, *brand = ""; 1699 int class = CPUCLASS_386; 1700 unsigned int i; 1701 int modif, family; 1702 const struct cpu_cpuid_nameclass *cpup = NULL; 1703 const struct cpu_cpuid_family *cpufam; 1704 struct cpu_info *ci, cistore; 1705 u_int descs[4]; 1706 size_t sz; 1707 struct cpu_ucode_version ucode; 1708 union { 1709 struct cpu_ucode_version_amd amd; 1710 struct cpu_ucode_version_intel1 intel1; 1711 } ucvers; 1712 1713 ci = &cistore; 1714 cpu_probe_base_features(ci, cpuname); 1715 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1716 ci->ci_cpuid_level); 1717 if (verbose) { 1718 int bf; 1719 1720 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1721 x86_cpuid(bf, descs); 1722 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1723 bf, descs[0], descs[1], descs[2], descs[3]); 1724 } 1725 } 1726 if (ci->ci_cpuid_extlevel >= 0x80000000) 1727 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1728 ci->ci_cpuid_extlevel); 1729 if (verbose) { 1730 unsigned int ef; 1731 1732 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1733 x86_cpuid(ef, descs); 1734 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1735 ef, descs[0], descs[1], descs[2], descs[3]); 1736 } 1737 } 1738 1739 cpu_probe_hv_features(ci, cpuname); 1740 cpu_probe_features(ci); 1741 1742 if (ci->ci_cpu_type >= 0) { 1743 /* Old pre-cpuid instruction cpu */ 1744 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1745 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1746 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1747 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1748 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1749 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1750 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1751 modifier = ""; 1752 } else { 1753 /* CPU which support cpuid instruction */ 1754 modif = (ci->ci_signature >> 12) & 0x3; 1755 family = ci->ci_family; 1756 if (family < CPU_MINFAMILY) 1757 errx(1, "identifycpu: strange family value"); 1758 if (family > CPU_MAXFAMILY) 1759 family = CPU_MAXFAMILY; 1760 1761 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1762 if (!strncmp((char *)ci->ci_vendor, 1763 i386_cpuid_cpus[i].cpu_id, 12)) { 1764 cpup = &i386_cpuid_cpus[i]; 1765 break; 1766 } 1767 } 1768 1769 if (cpup == NULL) { 1770 cpu_vendor = CPUVENDOR_UNKNOWN; 1771 if (ci->ci_vendor[0] != '\0') 1772 vendorname = (char *)&ci->ci_vendor[0]; 1773 else 1774 vendorname = "Unknown"; 1775 class = family - 3; 1776 modifier = ""; 1777 name = ""; 1778 ci->ci_info = NULL; 1779 } else { 1780 cpu_vendor = cpup->cpu_vendor; 1781 vendorname = cpup->cpu_vendorname; 1782 modifier = modifiers[modif]; 1783 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1784 name = cpufam->cpu_models[ci->ci_model]; 1785 if (name == NULL || *name == '\0') 1786 name = cpufam->cpu_model_default; 1787 class = cpufam->cpu_class; 1788 ci->ci_info = cpufam->cpu_info; 1789 1790 if (cpu_vendor == CPUVENDOR_INTEL) { 1791 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1792 const char *tmp; 1793 tmp = intel_family6_name(ci); 1794 if (tmp != NULL) 1795 name = tmp; 1796 } 1797 if (ci->ci_family == 15 && 1798 ci->ci_brand_id < 1799 __arraycount(i386_intel_brand) && 1800 i386_intel_brand[ci->ci_brand_id]) 1801 name = 1802 i386_intel_brand[ci->ci_brand_id]; 1803 } 1804 1805 if (cpu_vendor == CPUVENDOR_AMD) { 1806 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1807 if (ci->ci_brand_id == 1) 1808 /* 1809 * It's Duron. We override the 1810 * name, since it might have 1811 * been misidentified as Athlon. 1812 */ 1813 name = 1814 amd_brand[ci->ci_brand_id]; 1815 else 1816 brand = amd_brand_name; 1817 } 1818 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1819 == 0xf) { 1820 /* Identify AMD64 CPU names. */ 1821 const char *tmp; 1822 tmp = amd_amd64_name(ci); 1823 if (tmp != NULL) 1824 name = tmp; 1825 } 1826 } 1827 1828 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1829 vendorname = "VIA"; 1830 } 1831 } 1832 1833 ci->ci_cpu_class = class; 1834 1835 sz = sizeof(ci->ci_tsc_freq); 1836 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1837 sz = sizeof(use_pae); 1838 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1839 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1840 1841 /* 1842 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1843 * we try to determine from the family/model values. 1844 */ 1845 if (*cpu_brand_string != '\0') 1846 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1847 1848 aprint_normal("%s: %s", cpuname, vendorname); 1849 if (*modifier) 1850 aprint_normal(" %s", modifier); 1851 if (*name) 1852 aprint_normal(" %s", name); 1853 if (*brand) 1854 aprint_normal(" %s", brand); 1855 aprint_normal(" (%s-class)", classnames[class]); 1856 1857 if (ci->ci_tsc_freq != 0) 1858 aprint_normal(", %ju.%02ju MHz", 1859 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1860 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1861 aprint_normal("\n"); 1862 1863 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1864 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1865 if (ci->ci_signature != 0) 1866 aprint_normal(" (id %#x)", ci->ci_signature); 1867 aprint_normal("\n"); 1868 1869 if (ci->ci_info) 1870 (*ci->ci_info)(ci); 1871 1872 /* 1873 * display CPU feature flags 1874 */ 1875 1876 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1877 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1878 1879 /* These next two are actually common definitions! */ 1880 print_bits(cpuname, "features2", 1881 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1882 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1883 print_bits(cpuname, "features3", 1884 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1885 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1886 1887 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1888 ci->ci_feat_val[4]); 1889 1890 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]); 1891 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1892 ci->ci_feat_val[8]); 1893 1894 if (ci->ci_max_xsave != 0) { 1895 aprint_normal("%s: xsave area size: current %d, maximum %d", 1896 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1897 aprint_normal(", xgetbv %sabled\n", 1898 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1899 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1900 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1901 x86_xgetbv()); 1902 } 1903 1904 x86_print_cache_and_tlb_info(ci); 1905 1906 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1907 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1908 cpuname, 1909 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1910 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1911 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1912 } 1913 1914 if (ci->ci_cpu_class == CPUCLASS_386) 1915 errx(1, "NetBSD requires an 80486 or later processor"); 1916 1917 if (ci->ci_cpu_type == CPU_486DLC) { 1918 #ifndef CYRIX_CACHE_WORKS 1919 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1920 #else 1921 #ifndef CYRIX_CACHE_REALLY_WORKS 1922 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1923 #else 1924 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1925 #endif 1926 #endif 1927 } 1928 1929 /* 1930 * Everything past this point requires a Pentium or later. 1931 */ 1932 if (ci->ci_cpuid_level < 0) 1933 return; 1934 1935 identifycpu_cpuids(ci); 1936 1937 #ifdef INTEL_CORETEMP 1938 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1939 coretemp_register(ci); 1940 #endif 1941 1942 if (cpu_vendor == CPUVENDOR_AMD) { 1943 uint32_t data[4]; 1944 1945 x86_cpuid(0x80000000, data); 1946 if (data[0] >= 0x80000007) 1947 powernow_probe(ci); 1948 1949 if ((data[0] >= 0x8000000a) 1950 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1951 x86_cpuid(0x8000000a, data); 1952 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1953 data[0] & 0xf); 1954 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1955 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1956 data[3]); 1957 } 1958 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1959 uint32_t data[4]; 1960 int32_t bi_index; 1961 1962 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1963 x86_cpuid(bi_index, data); 1964 switch (bi_index) { 1965 case 6: 1966 print_bits(cpuname, "DSPM-eax", 1967 CPUID_DSPM_FLAGS, data[0]); 1968 print_bits(cpuname, "DSPM-ecx", 1969 CPUID_DSPM_FLAGS1, data[2]); 1970 break; 1971 case 7: 1972 aprint_verbose("%s: SEF highest subleaf %08x\n", 1973 cpuname, data[0]); 1974 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1975 data[1]); 1976 break; 1977 #if 0 1978 default: 1979 aprint_verbose("%s: basic %08x-eax %08x\n", 1980 cpuname, bi_index, data[0]); 1981 aprint_verbose("%s: basic %08x-ebx %08x\n", 1982 cpuname, bi_index, data[1]); 1983 aprint_verbose("%s: basic %08x-ecx %08x\n", 1984 cpuname, bi_index, data[2]); 1985 aprint_verbose("%s: basic %08x-edx %08x\n", 1986 cpuname, bi_index, data[3]); 1987 break; 1988 #endif 1989 } 1990 } 1991 } 1992 1993 #ifdef INTEL_ONDEMAND_CLOCKMOD 1994 clockmod_init(); 1995 #endif 1996 1997 if (cpu_vendor == CPUVENDOR_AMD) 1998 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1999 else if (cpu_vendor == CPUVENDOR_INTEL) 2000 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2001 else 2002 return; 2003 2004 ucode.data = &ucvers; 2005 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2006 #ifdef __i386__ 2007 struct cpu_ucode_version_64 ucode_64; 2008 if (errno != ENOTTY) 2009 return; 2010 /* Try the 64 bit ioctl */ 2011 memset(&ucode_64, 0, sizeof ucode_64); 2012 ucode_64.data = &ucvers; 2013 ucode_64.loader_version = ucode.loader_version; 2014 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2015 return; 2016 #else 2017 return; 2018 #endif 2019 } 2020 2021 if (cpu_vendor == CPUVENDOR_AMD) 2022 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2023 else if (cpu_vendor == CPUVENDOR_INTEL) 2024 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2025 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2026 } 2027 2028 static const struct x86_cache_info * 2029 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2030 { 2031 int i; 2032 2033 for (i = 0; cai[i].cai_desc != 0; i++) { 2034 if (cai[i].cai_desc == desc) 2035 return (&cai[i]); 2036 } 2037 2038 return (NULL); 2039 } 2040 2041 static const char * 2042 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2043 const char *sep) 2044 { 2045 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2046 char human_num[HUMAN_BUFSIZE]; 2047 2048 if (cai->cai_totalsize == 0) 2049 return sep; 2050 2051 if (sep == NULL) 2052 aprint_verbose_dev(ci->ci_dev, ""); 2053 else 2054 aprint_verbose("%s", sep); 2055 if (name != NULL) 2056 aprint_verbose("%s ", name); 2057 2058 if (cai->cai_string != NULL) { 2059 aprint_verbose("%s ", cai->cai_string); 2060 } else { 2061 (void)humanize_number(human_num, sizeof(human_num), 2062 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2063 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2064 } 2065 switch (cai->cai_associativity) { 2066 case 0: 2067 aprint_verbose("disabled"); 2068 break; 2069 case 1: 2070 aprint_verbose("direct-mapped"); 2071 break; 2072 case 0xff: 2073 aprint_verbose("fully associative"); 2074 break; 2075 default: 2076 aprint_verbose("%d-way", cai->cai_associativity); 2077 break; 2078 } 2079 return ", "; 2080 } 2081 2082 static const char * 2083 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2084 const char *sep) 2085 { 2086 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2087 char human_num[HUMAN_BUFSIZE]; 2088 2089 if (cai->cai_totalsize == 0) 2090 return sep; 2091 2092 if (sep == NULL) 2093 aprint_verbose_dev(ci->ci_dev, ""); 2094 else 2095 aprint_verbose("%s", sep); 2096 if (name != NULL) 2097 aprint_verbose("%s ", name); 2098 2099 if (cai->cai_string != NULL) { 2100 aprint_verbose("%s", cai->cai_string); 2101 } else { 2102 (void)humanize_number(human_num, sizeof(human_num), 2103 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2104 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2105 human_num); 2106 switch (cai->cai_associativity) { 2107 case 0: 2108 aprint_verbose("disabled"); 2109 break; 2110 case 1: 2111 aprint_verbose("direct-mapped"); 2112 break; 2113 case 0xff: 2114 aprint_verbose("fully associative"); 2115 break; 2116 default: 2117 aprint_verbose("%d-way", cai->cai_associativity); 2118 break; 2119 } 2120 } 2121 return ", "; 2122 } 2123 2124 static void 2125 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2126 { 2127 const char *sep = NULL; 2128 2129 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2130 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2131 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2132 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2133 if (sep != NULL) 2134 aprint_verbose("\n"); 2135 } 2136 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2137 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2138 if (sep != NULL) 2139 aprint_verbose("\n"); 2140 } 2141 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2142 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2143 if (sep != NULL) 2144 aprint_verbose("\n"); 2145 } 2146 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2147 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2148 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2149 if (sep != NULL) 2150 aprint_verbose("\n"); 2151 } 2152 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2153 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2154 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2155 if (sep != NULL) 2156 aprint_verbose("\n"); 2157 } 2158 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2159 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2160 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2161 if (sep != NULL) 2162 aprint_verbose("\n"); 2163 } 2164 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2165 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2166 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2167 if (sep != NULL) 2168 aprint_verbose("\n"); 2169 } 2170 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2171 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2172 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2173 if (sep != NULL) 2174 aprint_verbose("\n"); 2175 } 2176 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2177 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2178 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2179 if (sep != NULL) 2180 aprint_verbose("\n"); 2181 } 2182 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2183 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2184 NULL); 2185 if (sep != NULL) 2186 aprint_verbose("\n"); 2187 } 2188 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2189 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2190 NULL); 2191 if (sep != NULL) 2192 aprint_verbose("\n"); 2193 } 2194 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2195 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2196 NULL); 2197 if (sep != NULL) 2198 aprint_verbose("\n"); 2199 } 2200 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2201 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2202 NULL); 2203 if (sep != NULL) 2204 aprint_verbose("\n"); 2205 } 2206 } 2207 2208 static void 2209 powernow_probe(struct cpu_info *ci) 2210 { 2211 uint32_t regs[4]; 2212 char buf[256]; 2213 2214 x86_cpuid(0x80000007, regs); 2215 2216 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2217 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2218 buf); 2219 } 2220 2221 int 2222 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2223 { 2224 struct cpu_info ci; 2225 int loader_version, res; 2226 struct cpu_ucode_version versreq; 2227 2228 cpu_probe_base_features(&ci, "unknown"); 2229 2230 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2231 loader_version = CPU_UCODE_LOADER_AMD; 2232 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2233 loader_version = CPU_UCODE_LOADER_INTEL1; 2234 else 2235 return -1; 2236 2237 /* check whether the kernel understands this loader version */ 2238 versreq.loader_version = loader_version; 2239 versreq.data = 0; 2240 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2241 if (res) 2242 return -1; 2243 2244 switch (loader_version) { 2245 case CPU_UCODE_LOADER_AMD: 2246 if (uc->cpu_nr != -1) { 2247 /* printf? */ 2248 return -1; 2249 } 2250 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2251 break; 2252 case CPU_UCODE_LOADER_INTEL1: 2253 if (uc->cpu_nr == -1) 2254 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2255 else 2256 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2257 break; 2258 default: /* can't happen */ 2259 return -1; 2260 } 2261 uc->loader_version = loader_version; 2262 return 0; 2263 } 2264
Indexes created Mon Sep 29 21:09:56 GMT 2025