i386.c revision 1.72
1 /* $NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.72 2016/04/27 08:53:28 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[9]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] XCR0 bits (d:0 %eax) 110 * [8] xsave flags (d:1 %eax) 111 */ 112 uint32_t ci_cpu_class; /* CPU class */ 113 uint32_t ci_brand_id; /* Intel brand id */ 114 uint32_t ci_vendor[4]; /* vendor string */ 115 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 116 uint64_t ci_tsc_freq; /* cpu cycles/second */ 117 uint8_t ci_packageid; 118 uint8_t ci_coreid; 119 uint8_t ci_smtid; 120 uint32_t ci_initapicid; 121 122 uint32_t ci_cur_xsave; 123 uint32_t ci_max_xsave; 124 125 struct x86_cache_info ci_cinfo[CAI_COUNT]; 126 void (*ci_info)(struct cpu_info *); 127 }; 128 129 struct cpu_nocpuid_nameclass { 130 int cpu_vendor; 131 const char *cpu_vendorname; 132 const char *cpu_name; 133 int cpu_class; 134 void (*cpu_setup)(struct cpu_info *); 135 void (*cpu_cacheinfo)(struct cpu_info *); 136 void (*cpu_info)(struct cpu_info *); 137 }; 138 139 struct cpu_cpuid_nameclass { 140 const char *cpu_id; 141 int cpu_vendor; 142 const char *cpu_vendorname; 143 struct cpu_cpuid_family { 144 int cpu_class; 145 const char *cpu_models[256]; 146 const char *cpu_model_default; 147 void (*cpu_setup)(struct cpu_info *); 148 void (*cpu_probe)(struct cpu_info *); 149 void (*cpu_info)(struct cpu_info *); 150 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 151 }; 152 153 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 154 155 /* 156 * Map Brand ID from cpuid instruction to brand name. 157 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 158 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 159 * Architectures Software Developer's Manual, Volume 2A". 160 */ 161 static const char * const i386_intel_brand[] = { 162 "", /* Unsupported */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "", /* 0x05: Reserved */ 168 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Celeron", /* Intel (R) Celeron (TM) processor */ 173 "Xeon", /* Intel (R) Xeon (TM) processor */ 174 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 175 "", /* 0x0d: Reserved */ 176 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 177 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 178 "", /* 0x10: Reserved */ 179 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 180 "Celeron M", /* Intel (R) Celeron (R) M processor */ 181 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 182 "Celeron", /* Intel (R) Celeron (R) processor */ 183 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 184 "Pentium M", /* Intel (R) Pentium (R) M processor */ 185 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 186 }; 187 188 /* 189 * AMD processors don't have Brand IDs, so we need these names for probe. 190 */ 191 static const char * const amd_brand[] = { 192 "", 193 "Duron", /* AMD Duron(tm) */ 194 "MP", /* AMD Athlon(tm) MP */ 195 "XP", /* AMD Athlon(tm) XP */ 196 "4" /* AMD Athlon(tm) 4 */ 197 }; 198 199 static int cpu_vendor; 200 static char cpu_brand_string[49]; 201 static char amd_brand_name[48]; 202 static int use_pae, largepagesize; 203 204 /* Setup functions */ 205 static void disable_tsc(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 /* Brand/Model name functions */ 210 static const char *intel_family6_name(struct cpu_info *); 211 static const char *amd_amd64_name(struct cpu_info *); 212 /* Probe functions */ 213 static void amd_family6_probe(struct cpu_info *); 214 static void powernow_probe(struct cpu_info *); 215 static void intel_family_new_probe(struct cpu_info *); 216 static void via_cpu_probe(struct cpu_info *); 217 /* (Cache) Info functions */ 218 static void intel_cpu_cacheinfo(struct cpu_info *); 219 static void amd_cpu_cacheinfo(struct cpu_info *); 220 static void via_cpu_cacheinfo(struct cpu_info *); 221 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 222 static void transmeta_cpu_info(struct cpu_info *); 223 /* Common functions */ 224 static void cpu_probe_base_features(struct cpu_info *, const char *); 225 static void cpu_probe_hv_features(struct cpu_info *, const char *); 226 static void cpu_probe_features(struct cpu_info *); 227 static void print_bits(const char *, const char *, const char *, uint32_t); 228 static void identifycpu_cpuids(struct cpu_info *); 229 static const struct x86_cache_info *cache_info_lookup( 230 const struct x86_cache_info *, uint8_t); 231 static const char *print_cache_config(struct cpu_info *, int, const char *, 232 const char *); 233 static const char *print_tlb_config(struct cpu_info *, int, const char *, 234 const char *); 235 static void x86_print_cache_and_tlb_info(struct cpu_info *); 236 237 /* 238 * Note: these are just the ones that may not have a cpuid instruction. 239 * We deal with the rest in a different way. 240 */ 241 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 242 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386SX */ 244 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386 */ 246 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486SX */ 248 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486 */ 250 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486DLC */ 252 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_6x86 */ 254 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 255 NULL, NULL, NULL }, /* CPU_NX586 */ 256 }; 257 258 const char *classnames[] = { 259 "386", 260 "486", 261 "586", 262 "686" 263 }; 264 265 const char *modifiers[] = { 266 "", 267 "OverDrive", 268 "Dual", 269 "" 270 }; 271 272 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 273 { 274 /* 275 * For Intel processors, check Chapter 35Model-specific 276 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 277 * Software Developer's Manual, Volume 3C". 278 */ 279 "GenuineIntel", 280 CPUVENDOR_INTEL, 281 "Intel", 282 /* Family 4 */ 283 { { 284 CPUCLASS_486, 285 { 286 "486DX", "486DX", "486SX", "486DX2", "486SL", 287 "486SX2", 0, "486DX2 W/B Enhanced", 288 "486DX4", 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "486", /* Default */ 291 NULL, 292 NULL, 293 intel_cpu_cacheinfo, 294 }, 295 /* Family 5 */ 296 { 297 CPUCLASS_586, 298 { 299 "Pentium (P5 A-step)", "Pentium (P5)", 300 "Pentium (P54C)", "Pentium (P24T)", 301 "Pentium/MMX", "Pentium", 0, 302 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 303 "Quark X1000", 0, 0, 0, 0, 0, 0, 304 }, 305 "Pentium", /* Default */ 306 NULL, 307 NULL, 308 intel_cpu_cacheinfo, 309 }, 310 /* Family 6 */ 311 { 312 CPUCLASS_686, 313 { 314 [0x00] = "Pentium Pro (A-step)", 315 [0x01] = "Pentium Pro", 316 [0x03] = "Pentium II (Klamath)", 317 [0x04] = "Pentium Pro", 318 [0x05] = "Pentium II/Celeron (Deschutes)", 319 [0x06] = "Celeron (Mendocino)", 320 [0x07] = "Pentium III (Katmai)", 321 [0x08] = "Pentium III (Coppermine)", 322 [0x09] = "Pentium M (Banias)", 323 [0x0a] = "Pentium III Xeon (Cascades)", 324 [0x0b] = "Pentium III (Tualatin)", 325 [0x0d] = "Pentium M (Dothan)", 326 [0x0e] = "Pentium Core Duo, Core solo", 327 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 328 "Core 2 Quad 6xxx, " 329 "Core 2 Extreme 6xxx, " 330 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 331 "and Pentium DC", 332 [0x15] = "EP80579 Integrated Processor", 333 [0x16] = "Celeron (45nm)", 334 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 335 "Core 2 Quad 8xxx and 9xxx", 336 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 337 "(Nehalem)", 338 [0x1c] = "45nm Atom Family", 339 [0x1d] = "XeonMP 74xx (Nehalem)", 340 [0x1e] = "Core i7 and i5", 341 [0x1f] = "Core i7 and i5", 342 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x26] = "Atom Family", 344 [0x27] = "Atom Family", 345 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 346 "i3 2xxx", 347 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 348 [0x2d] = "Xeon E5 Sandy Bridge family, " 349 "Core i7-39xx Extreme", 350 [0x2e] = "Xeon 75xx & 65xx", 351 [0x2f] = "Xeon E7 family", 352 [0x35] = "Atom Family", 353 [0x36] = "Atom S1000", 354 [0x37] = "Atom E3000, Z3[67]00", 355 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 356 "Ivy Bridge", 357 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 360 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 361 "Core i7-49xx Extreme", 362 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 363 "Core i7-59xx Extreme", 364 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 369 [0x4a] = "Atom Z3400", 370 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 371 [0x4d] = "Atom C2000", 372 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 373 [0x4f] = "Xeon E5 v4 (Broadwell)", 374 [0x55] = "Future Xeon", 375 [0x56] = "Xeon D-1500 (Broadwell)", 376 [0x57] = "Next gen Xeon Phi", 377 [0x5a] = "Atom E3500", 378 [0x5c] = "Next Atom (Goldmont)", 379 [0x5d] = "Atom X3-C3000 (Silvermont)", 380 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 381 [0x5f] = "Future Atom (Goldmont)", 382 [0x8e] = "Future Core", 383 [0x9e] = "Future Core", 384 }, 385 "Pentium Pro, II or III", /* Default */ 386 NULL, 387 intel_family_new_probe, 388 intel_cpu_cacheinfo, 389 }, 390 /* Family > 6 */ 391 { 392 CPUCLASS_686, 393 { 394 0, 0, 0, 0, 0, 0, 0, 0, 395 0, 0, 0, 0, 0, 0, 0, 0, 396 }, 397 "Pentium 4", /* Default */ 398 NULL, 399 intel_family_new_probe, 400 intel_cpu_cacheinfo, 401 } } 402 }, 403 { 404 "AuthenticAMD", 405 CPUVENDOR_AMD, 406 "AMD", 407 /* Family 4 */ 408 { { 409 CPUCLASS_486, 410 { 411 0, 0, 0, "Am486DX2 W/T", 412 0, 0, 0, "Am486DX2 W/B", 413 "Am486DX4 W/T or Am5x86 W/T 150", 414 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 415 0, 0, "Am5x86 W/T 133/160", 416 "Am5x86 W/B 133/160", 417 }, 418 "Am486 or Am5x86", /* Default */ 419 NULL, 420 NULL, 421 NULL, 422 }, 423 /* Family 5 */ 424 { 425 CPUCLASS_586, 426 { 427 "K5", "K5", "K5", "K5", 0, 0, "K6", 428 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 429 "K6-2+/III+", 0, 0, 430 }, 431 "K5 or K6", /* Default */ 432 amd_family5_setup, 433 NULL, 434 amd_cpu_cacheinfo, 435 }, 436 /* Family 6 */ 437 { 438 CPUCLASS_686, 439 { 440 0, "Athlon Model 1", "Athlon Model 2", 441 "Duron", "Athlon Model 4 (Thunderbird)", 442 0, "Athlon", "Duron", "Athlon", 0, 443 "Athlon", 0, 0, 0, 0, 0, 444 }, 445 "K7 (Athlon)", /* Default */ 446 NULL, 447 amd_family6_probe, 448 amd_cpu_cacheinfo, 449 }, 450 /* Family > 6 */ 451 { 452 CPUCLASS_686, 453 { 454 0, 0, 0, 0, 0, 0, 0, 0, 455 0, 0, 0, 0, 0, 0, 0, 0, 456 }, 457 "Unknown K8 (Athlon)", /* Default */ 458 NULL, 459 amd_family6_probe, 460 amd_cpu_cacheinfo, 461 } } 462 }, 463 { 464 "CyrixInstead", 465 CPUVENDOR_CYRIX, 466 "Cyrix", 467 /* Family 4 */ 468 { { 469 CPUCLASS_486, 470 { 471 0, 0, 0, 472 "MediaGX", 473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 474 }, 475 "486", /* Default */ 476 cyrix6x86_cpu_setup, /* XXX ?? */ 477 NULL, 478 NULL, 479 }, 480 /* Family 5 */ 481 { 482 CPUCLASS_586, 483 { 484 0, 0, "6x86", 0, 485 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 487 }, 488 "6x86", /* Default */ 489 cyrix6x86_cpu_setup, 490 NULL, 491 NULL, 492 }, 493 /* Family 6 */ 494 { 495 CPUCLASS_686, 496 { 497 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 498 0, 0, 0, 0, 0, 0, 0, 0, 499 }, 500 "6x86MX", /* Default */ 501 cyrix6x86_cpu_setup, 502 NULL, 503 NULL, 504 }, 505 /* Family > 6 */ 506 { 507 CPUCLASS_686, 508 { 509 0, 0, 0, 0, 0, 0, 0, 0, 510 0, 0, 0, 0, 0, 0, 0, 0, 511 }, 512 "Unknown 6x86MX", /* Default */ 513 NULL, 514 NULL, 515 NULL, 516 } } 517 }, 518 { /* MediaGX is now owned by National Semiconductor */ 519 "Geode by NSC", 520 CPUVENDOR_CYRIX, /* XXX */ 521 "National Semiconductor", 522 /* Family 4, NSC never had any of these */ 523 { { 524 CPUCLASS_486, 525 { 526 0, 0, 0, 0, 0, 0, 0, 0, 527 0, 0, 0, 0, 0, 0, 0, 0, 528 }, 529 "486 compatible", /* Default */ 530 NULL, 531 NULL, 532 NULL, 533 }, 534 /* Family 5: Geode family, formerly MediaGX */ 535 { 536 CPUCLASS_586, 537 { 538 0, 0, 0, 0, 539 "Geode GX1", 540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 541 }, 542 "Geode", /* Default */ 543 cyrix6x86_cpu_setup, 544 NULL, 545 amd_cpu_cacheinfo, 546 }, 547 /* Family 6, not yet available from NSC */ 548 { 549 CPUCLASS_686, 550 { 551 0, 0, 0, 0, 0, 0, 0, 0, 552 0, 0, 0, 0, 0, 0, 0, 0, 553 }, 554 "Pentium Pro compatible", /* Default */ 555 NULL, 556 NULL, 557 NULL, 558 }, 559 /* Family > 6, not yet available from NSC */ 560 { 561 CPUCLASS_686, 562 { 563 0, 0, 0, 0, 0, 0, 0, 0, 564 0, 0, 0, 0, 0, 0, 0, 0, 565 }, 566 "Pentium Pro compatible", /* Default */ 567 NULL, 568 NULL, 569 NULL, 570 } } 571 }, 572 { 573 "CentaurHauls", 574 CPUVENDOR_IDT, 575 "IDT", 576 /* Family 4, IDT never had any of these */ 577 { { 578 CPUCLASS_486, 579 { 580 0, 0, 0, 0, 0, 0, 0, 0, 581 0, 0, 0, 0, 0, 0, 0, 0, 582 }, 583 "486 compatible", /* Default */ 584 NULL, 585 NULL, 586 NULL, 587 }, 588 /* Family 5 */ 589 { 590 CPUCLASS_586, 591 { 592 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 593 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 594 }, 595 "WinChip", /* Default */ 596 winchip_cpu_setup, 597 NULL, 598 NULL, 599 }, 600 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 601 { 602 CPUCLASS_686, 603 { 604 0, 0, 0, 0, 0, 0, "C3 Samuel", 605 "C3 Samuel 2/Ezra", "C3 Ezra-T", 606 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 607 0, "VIA Nano", 608 }, 609 "Unknown VIA/IDT", /* Default */ 610 NULL, 611 via_cpu_probe, 612 via_cpu_cacheinfo, 613 }, 614 /* Family > 6, not yet available from VIA */ 615 { 616 CPUCLASS_686, 617 { 618 0, 0, 0, 0, 0, 0, 0, 0, 619 0, 0, 0, 0, 0, 0, 0, 0, 620 }, 621 "Pentium Pro compatible", /* Default */ 622 NULL, 623 NULL, 624 NULL, 625 } } 626 }, 627 { 628 "GenuineTMx86", 629 CPUVENDOR_TRANSMETA, 630 "Transmeta", 631 /* Family 4, Transmeta never had any of these */ 632 { { 633 CPUCLASS_486, 634 { 635 0, 0, 0, 0, 0, 0, 0, 0, 636 0, 0, 0, 0, 0, 0, 0, 0, 637 }, 638 "486 compatible", /* Default */ 639 NULL, 640 NULL, 641 NULL, 642 }, 643 /* Family 5 */ 644 { 645 CPUCLASS_586, 646 { 647 0, 0, 0, 0, 0, 0, 0, 0, 648 0, 0, 0, 0, 0, 0, 0, 0, 649 }, 650 "Crusoe", /* Default */ 651 NULL, 652 NULL, 653 transmeta_cpu_info, 654 }, 655 /* Family 6, not yet available from Transmeta */ 656 { 657 CPUCLASS_686, 658 { 659 0, 0, 0, 0, 0, 0, 0, 0, 660 0, 0, 0, 0, 0, 0, 0, 0, 661 }, 662 "Pentium Pro compatible", /* Default */ 663 NULL, 664 NULL, 665 NULL, 666 }, 667 /* Family > 6, not yet available from Transmeta */ 668 { 669 CPUCLASS_686, 670 { 671 0, 0, 0, 0, 0, 0, 0, 0, 672 0, 0, 0, 0, 0, 0, 0, 0, 673 }, 674 "Pentium Pro compatible", /* Default */ 675 NULL, 676 NULL, 677 NULL, 678 } } 679 } 680 }; 681 682 /* 683 * disable the TSC such that we don't use the TSC in microtime(9) 684 * because some CPUs got the implementation wrong. 685 */ 686 static void 687 disable_tsc(struct cpu_info *ci) 688 { 689 if (ci->ci_feat_val[0] & CPUID_TSC) { 690 ci->ci_feat_val[0] &= ~CPUID_TSC; 691 aprint_error("WARNING: broken TSC disabled\n"); 692 } 693 } 694 695 static void 696 amd_family5_setup(struct cpu_info *ci) 697 { 698 699 switch (ci->ci_model) { 700 case 0: /* AMD-K5 Model 0 */ 701 /* 702 * According to the AMD Processor Recognition App Note, 703 * the AMD-K5 Model 0 uses the wrong bit to indicate 704 * support for global PTEs, instead using bit 9 (APIC) 705 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 706 */ 707 if (ci->ci_feat_val[0] & CPUID_APIC) 708 ci->ci_feat_val[0] = 709 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 710 /* 711 * XXX But pmap_pg_g is already initialized -- need to kick 712 * XXX the pmap somehow. How does the MP branch do this? 713 */ 714 break; 715 } 716 } 717 718 static void 719 cyrix6x86_cpu_setup(struct cpu_info *ci) 720 { 721 722 /* 723 * Do not disable the TSC on the Geode GX, it's reported to 724 * work fine. 725 */ 726 if (ci->ci_signature != 0x552) 727 disable_tsc(ci); 728 } 729 730 static void 731 winchip_cpu_setup(struct cpu_info *ci) 732 { 733 switch (ci->ci_model) { 734 case 4: /* WinChip C6 */ 735 disable_tsc(ci); 736 } 737 } 738 739 740 static const char * 741 intel_family6_name(struct cpu_info *ci) 742 { 743 const char *ret = NULL; 744 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 745 746 if (ci->ci_model == 5) { 747 switch (l2cache) { 748 case 0: 749 case 128 * 1024: 750 ret = "Celeron (Covington)"; 751 break; 752 case 256 * 1024: 753 ret = "Mobile Pentium II (Dixon)"; 754 break; 755 case 512 * 1024: 756 ret = "Pentium II"; 757 break; 758 case 1 * 1024 * 1024: 759 case 2 * 1024 * 1024: 760 ret = "Pentium II Xeon"; 761 break; 762 } 763 } else if (ci->ci_model == 6) { 764 switch (l2cache) { 765 case 256 * 1024: 766 case 512 * 1024: 767 ret = "Mobile Pentium II"; 768 break; 769 } 770 } else if (ci->ci_model == 7) { 771 switch (l2cache) { 772 case 512 * 1024: 773 ret = "Pentium III"; 774 break; 775 case 1 * 1024 * 1024: 776 case 2 * 1024 * 1024: 777 ret = "Pentium III Xeon"; 778 break; 779 } 780 } else if (ci->ci_model >= 8) { 781 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 782 switch (ci->ci_brand_id) { 783 case 0x3: 784 if (ci->ci_signature == 0x6B1) 785 ret = "Celeron"; 786 break; 787 case 0x8: 788 if (ci->ci_signature >= 0xF13) 789 ret = "genuine processor"; 790 break; 791 case 0xB: 792 if (ci->ci_signature >= 0xF13) 793 ret = "Xeon MP"; 794 break; 795 case 0xE: 796 if (ci->ci_signature < 0xF13) 797 ret = "Xeon"; 798 break; 799 } 800 if (ret == NULL) 801 ret = i386_intel_brand[ci->ci_brand_id]; 802 } 803 } 804 805 return ret; 806 } 807 808 /* 809 * Identify AMD64 CPU names from cpuid. 810 * 811 * Based on: 812 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 813 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 814 * "Revision Guide for AMD NPT Family 0Fh Processors" 815 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 816 * and other miscellaneous reports. 817 * 818 * This is all rather pointless, these are cross 'brand' since the raw 819 * silicon is shared. 820 */ 821 static const char * 822 amd_amd64_name(struct cpu_info *ci) 823 { 824 static char family_str[32]; 825 826 /* Only called if family >= 15 */ 827 828 switch (ci->ci_family) { 829 case 15: 830 switch (ci->ci_model) { 831 case 0x21: /* rev JH-E1/E6 */ 832 case 0x41: /* rev JH-F2 */ 833 return "Dual-Core Opteron"; 834 case 0x23: /* rev JH-E6 (Toledo) */ 835 return "Dual-Core Opteron or Athlon 64 X2"; 836 case 0x43: /* rev JH-F2 (Windsor) */ 837 return "Athlon 64 FX or Athlon 64 X2"; 838 case 0x24: /* rev SH-E5 (Lancaster?) */ 839 return "Mobile Athlon 64 or Turion 64"; 840 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 841 return "Opteron or Athlon 64 FX"; 842 case 0x15: /* rev SH-D0 */ 843 case 0x25: /* rev SH-E4 */ 844 return "Opteron"; 845 case 0x27: /* rev DH-E4, SH-E4 */ 846 return "Athlon 64 or Athlon 64 FX or Opteron"; 847 case 0x48: /* rev BH-F2 */ 848 return "Turion 64 X2"; 849 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 850 case 0x07: /* rev SH-CG (ClawHammer) */ 851 case 0x0b: /* rev CH-CG */ 852 case 0x14: /* rev SH-D0 */ 853 case 0x17: /* rev SH-D0 */ 854 case 0x1b: /* rev CH-D0 */ 855 return "Athlon 64"; 856 case 0x2b: /* rev BH-E4 (Manchester) */ 857 case 0x4b: /* rev BH-F2 (Windsor) */ 858 return "Athlon 64 X2"; 859 case 0x6b: /* rev BH-G1 (Brisbane) */ 860 return "Athlon X2 or Athlon 64 X2"; 861 case 0x08: /* rev CH-CG */ 862 case 0x0c: /* rev DH-CG (Newcastle) */ 863 case 0x0e: /* rev DH-CG (Newcastle?) */ 864 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 865 case 0x18: /* rev CH-D0 */ 866 case 0x1c: /* rev DH-D0 (Winchester) */ 867 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 868 case 0x2c: /* rev DH-E3/E6 */ 869 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 870 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 871 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 872 case 0x6f: /* rev DH-G1 */ 873 return "Athlon 64 or Sempron"; 874 default: 875 break; 876 } 877 return "Unknown AMD64 CPU"; 878 879 #if 0 880 case 16: 881 return "Family 10h"; 882 case 17: 883 return "Family 11h"; 884 case 18: 885 return "Family 12h"; 886 case 19: 887 return "Family 14h"; 888 case 20: 889 return "Family 15h"; 890 #endif 891 892 default: 893 break; 894 } 895 896 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 897 return family_str; 898 } 899 900 static void 901 intel_family_new_probe(struct cpu_info *ci) 902 { 903 uint32_t descs[4]; 904 905 x86_cpuid(0x80000000, descs); 906 907 /* 908 * Determine extended feature flags. 909 */ 910 if (descs[0] >= 0x80000001) { 911 x86_cpuid(0x80000001, descs); 912 ci->ci_feat_val[2] |= descs[3]; 913 ci->ci_feat_val[3] |= descs[2]; 914 } 915 } 916 917 static void 918 via_cpu_probe(struct cpu_info *ci) 919 { 920 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 921 u_int descs[4]; 922 u_int lfunc; 923 924 /* 925 * Determine the largest extended function value. 926 */ 927 x86_cpuid(0x80000000, descs); 928 lfunc = descs[0]; 929 930 /* 931 * Determine the extended feature flags. 932 */ 933 if (lfunc >= 0x80000001) { 934 x86_cpuid(0x80000001, descs); 935 ci->ci_feat_val[2] |= descs[3]; 936 } 937 938 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 939 return; 940 941 /* Nehemiah or Esther */ 942 x86_cpuid(0xc0000000, descs); 943 lfunc = descs[0]; 944 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 945 return; 946 947 x86_cpuid(0xc0000001, descs); 948 lfunc = descs[3]; 949 ci->ci_feat_val[4] = lfunc; 950 } 951 952 static void 953 amd_family6_probe(struct cpu_info *ci) 954 { 955 uint32_t descs[4]; 956 char *p; 957 size_t i; 958 959 x86_cpuid(0x80000000, descs); 960 961 /* 962 * Determine the extended feature flags. 963 */ 964 if (descs[0] >= 0x80000001) { 965 x86_cpuid(0x80000001, descs); 966 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 967 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 968 } 969 970 if (*cpu_brand_string == '\0') 971 return; 972 973 for (i = 1; i < __arraycount(amd_brand); i++) 974 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 975 ci->ci_brand_id = i; 976 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 977 break; 978 } 979 } 980 981 static void 982 intel_cpu_cacheinfo(struct cpu_info *ci) 983 { 984 const struct x86_cache_info *cai; 985 u_int descs[4]; 986 int iterations, i, j; 987 int type, level; 988 int ways, partitions, linesize, sets; 989 int caitype = -1; 990 int totalsize; 991 uint8_t desc; 992 993 /* Return if the cpu is old pre-cpuid instruction cpu */ 994 if (ci->ci_cpu_type >= 0) 995 return; 996 997 if (ci->ci_cpuid_level < 2) 998 return; 999 1000 /* 1001 * Parse the cache info from `cpuid leaf 2', if we have it. 1002 * XXX This is kinda ugly, but hey, so is the architecture... 1003 */ 1004 x86_cpuid(2, descs); 1005 iterations = descs[0] & 0xff; 1006 while (iterations-- > 0) { 1007 for (i = 0; i < 4; i++) { 1008 if (descs[i] & 0x80000000) 1009 continue; 1010 for (j = 0; j < 4; j++) { 1011 /* 1012 * The least significant byte in EAX 1013 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1014 * it should be ignored. 1015 */ 1016 if (i == 0 && j == 0) 1017 continue; 1018 desc = (descs[i] >> (j * 8)) & 0xff; 1019 if (desc == 0) 1020 continue; 1021 cai = cache_info_lookup(intel_cpuid_cache_info, 1022 desc); 1023 if (cai != NULL) 1024 ci->ci_cinfo[cai->cai_index] = *cai; 1025 else if ((verbose != 0) && (desc != 0xff)) 1026 printf("Unknown cacheinfo desc %02x\n", 1027 desc); 1028 } 1029 } 1030 x86_cpuid(2, descs); 1031 } 1032 1033 if (ci->ci_cpuid_level < 4) 1034 return; 1035 1036 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1037 for (i = 0; ; i++) { 1038 x86_cpuid2(4, i, descs); 1039 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1040 if (type == CPUID_DCP_CACHETYPE_N) 1041 break; 1042 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1043 switch (level) { 1044 case 1: 1045 if (type == CPUID_DCP_CACHETYPE_I) 1046 caitype = CAI_ICACHE; 1047 else if (type == CPUID_DCP_CACHETYPE_D) 1048 caitype = CAI_DCACHE; 1049 else 1050 caitype = -1; 1051 break; 1052 case 2: 1053 if (type == CPUID_DCP_CACHETYPE_U) 1054 caitype = CAI_L2CACHE; 1055 else 1056 caitype = -1; 1057 break; 1058 case 3: 1059 if (type == CPUID_DCP_CACHETYPE_U) 1060 caitype = CAI_L3CACHE; 1061 else 1062 caitype = -1; 1063 break; 1064 default: 1065 caitype = -1; 1066 break; 1067 } 1068 if (caitype == -1) { 1069 printf("unknown cache level&type (%d & %d)\n", 1070 level, type); 1071 continue; 1072 } 1073 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1074 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1075 + 1; 1076 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1077 + 1; 1078 sets = descs[2] + 1; 1079 totalsize = ways * partitions * linesize * sets; 1080 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1081 ci->ci_cinfo[caitype].cai_associativity = ways; 1082 ci->ci_cinfo[caitype].cai_linesize = linesize; 1083 } 1084 } 1085 1086 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1087 AMD_L2CACHE_INFO; 1088 1089 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1090 AMD_L3CACHE_INFO; 1091 1092 static void 1093 amd_cpu_cacheinfo(struct cpu_info *ci) 1094 { 1095 const struct x86_cache_info *cp; 1096 struct x86_cache_info *cai; 1097 u_int descs[4]; 1098 u_int lfunc; 1099 1100 /* 1101 * K5 model 0 has none of this info. 1102 */ 1103 if (ci->ci_family == 5 && ci->ci_model == 0) 1104 return; 1105 1106 /* 1107 * Determine the largest extended function value. 1108 */ 1109 x86_cpuid(0x80000000, descs); 1110 lfunc = descs[0]; 1111 1112 /* 1113 * Determine L1 cache/TLB info. 1114 */ 1115 if (lfunc < 0x80000005) { 1116 /* No L1 cache info available. */ 1117 return; 1118 } 1119 1120 x86_cpuid(0x80000005, descs); 1121 1122 /* 1123 * K6-III and higher have large page TLBs. 1124 */ 1125 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1126 cai = &ci->ci_cinfo[CAI_ITLB2]; 1127 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1128 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1129 cai->cai_linesize = largepagesize; 1130 1131 cai = &ci->ci_cinfo[CAI_DTLB2]; 1132 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1133 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1134 cai->cai_linesize = largepagesize; 1135 } 1136 1137 cai = &ci->ci_cinfo[CAI_ITLB]; 1138 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1139 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1140 cai->cai_linesize = (4 * 1024); 1141 1142 cai = &ci->ci_cinfo[CAI_DTLB]; 1143 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1144 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1145 cai->cai_linesize = (4 * 1024); 1146 1147 cai = &ci->ci_cinfo[CAI_DCACHE]; 1148 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1149 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1150 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1151 1152 cai = &ci->ci_cinfo[CAI_ICACHE]; 1153 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1154 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1155 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1156 1157 /* 1158 * Determine L2 cache/TLB info. 1159 */ 1160 if (lfunc < 0x80000006) { 1161 /* No L2 cache info available. */ 1162 return; 1163 } 1164 1165 x86_cpuid(0x80000006, descs); 1166 1167 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1168 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1169 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1170 cai->cai_linesize = (4 * 1024); 1171 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1172 cai->cai_associativity); 1173 if (cp != NULL) 1174 cai->cai_associativity = cp->cai_associativity; 1175 else 1176 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1177 1178 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1179 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1180 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1181 cai->cai_linesize = largepagesize; 1182 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1183 cai->cai_associativity); 1184 if (cp != NULL) 1185 cai->cai_associativity = cp->cai_associativity; 1186 else 1187 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1188 1189 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1190 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1191 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1192 cai->cai_linesize = (4 * 1024); 1193 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1194 cai->cai_associativity); 1195 if (cp != NULL) 1196 cai->cai_associativity = cp->cai_associativity; 1197 else 1198 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1199 1200 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1201 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1202 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1203 cai->cai_linesize = largepagesize; 1204 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1205 cai->cai_associativity); 1206 if (cp != NULL) 1207 cai->cai_associativity = cp->cai_associativity; 1208 else 1209 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1210 1211 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1212 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1213 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1214 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1215 1216 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1217 cai->cai_associativity); 1218 if (cp != NULL) 1219 cai->cai_associativity = cp->cai_associativity; 1220 else 1221 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1222 1223 /* 1224 * Determine L3 cache info on AMD Family 10h and newer processors 1225 */ 1226 if (ci->ci_family >= 0x10) { 1227 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1228 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1229 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1230 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1231 1232 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1233 cai->cai_associativity); 1234 if (cp != NULL) 1235 cai->cai_associativity = cp->cai_associativity; 1236 else 1237 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1238 } 1239 1240 /* 1241 * Determine 1GB TLB info. 1242 */ 1243 if (lfunc < 0x80000019) { 1244 /* No 1GB TLB info available. */ 1245 return; 1246 } 1247 1248 x86_cpuid(0x80000019, descs); 1249 1250 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1251 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1252 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1253 cai->cai_linesize = (1024 * 1024 * 1024); 1254 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1255 cai->cai_associativity); 1256 if (cp != NULL) 1257 cai->cai_associativity = cp->cai_associativity; 1258 else 1259 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1260 1261 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1262 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1263 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1264 cai->cai_linesize = (1024 * 1024 * 1024); 1265 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1266 cai->cai_associativity); 1267 if (cp != NULL) 1268 cai->cai_associativity = cp->cai_associativity; 1269 else 1270 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1271 1272 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1273 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1274 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1275 cai->cai_linesize = (1024 * 1024 * 1024); 1276 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1277 cai->cai_associativity); 1278 if (cp != NULL) 1279 cai->cai_associativity = cp->cai_associativity; 1280 else 1281 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1282 1283 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1284 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1285 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1286 cai->cai_linesize = (1024 * 1024 * 1024); 1287 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1288 cai->cai_associativity); 1289 if (cp != NULL) 1290 cai->cai_associativity = cp->cai_associativity; 1291 else 1292 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1293 } 1294 1295 static void 1296 via_cpu_cacheinfo(struct cpu_info *ci) 1297 { 1298 struct x86_cache_info *cai; 1299 int stepping; 1300 u_int descs[4]; 1301 u_int lfunc; 1302 1303 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1304 1305 /* 1306 * Determine the largest extended function value. 1307 */ 1308 x86_cpuid(0x80000000, descs); 1309 lfunc = descs[0]; 1310 1311 /* 1312 * Determine L1 cache/TLB info. 1313 */ 1314 if (lfunc < 0x80000005) { 1315 /* No L1 cache info available. */ 1316 return; 1317 } 1318 1319 x86_cpuid(0x80000005, descs); 1320 1321 cai = &ci->ci_cinfo[CAI_ITLB]; 1322 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1323 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1324 cai->cai_linesize = (4 * 1024); 1325 1326 cai = &ci->ci_cinfo[CAI_DTLB]; 1327 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1328 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1329 cai->cai_linesize = (4 * 1024); 1330 1331 cai = &ci->ci_cinfo[CAI_DCACHE]; 1332 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1333 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1334 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1335 if (ci->ci_model == 9 && stepping == 8) { 1336 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1337 cai->cai_associativity = 2; 1338 } 1339 1340 cai = &ci->ci_cinfo[CAI_ICACHE]; 1341 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1342 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1343 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1344 if (ci->ci_model == 9 && stepping == 8) { 1345 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1346 cai->cai_associativity = 2; 1347 } 1348 1349 /* 1350 * Determine L2 cache/TLB info. 1351 */ 1352 if (lfunc < 0x80000006) { 1353 /* No L2 cache info available. */ 1354 return; 1355 } 1356 1357 x86_cpuid(0x80000006, descs); 1358 1359 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1360 if (ci->ci_model >= 9) { 1361 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1362 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1363 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1364 } else { 1365 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1366 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1367 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1368 } 1369 } 1370 1371 static void 1372 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1373 { 1374 u_int descs[4]; 1375 1376 x86_cpuid(0x80860007, descs); 1377 *frequency = descs[0]; 1378 *voltage = descs[1]; 1379 *percentage = descs[2]; 1380 } 1381 1382 static void 1383 transmeta_cpu_info(struct cpu_info *ci) 1384 { 1385 u_int descs[4], nreg; 1386 u_int frequency, voltage, percentage; 1387 1388 x86_cpuid(0x80860000, descs); 1389 nreg = descs[0]; 1390 if (nreg >= 0x80860001) { 1391 x86_cpuid(0x80860001, descs); 1392 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1393 (descs[1] >> 24) & 0xff, 1394 (descs[1] >> 16) & 0xff, 1395 (descs[1] >> 8) & 0xff, 1396 descs[1] & 0xff); 1397 } 1398 if (nreg >= 0x80860002) { 1399 x86_cpuid(0x80860002, descs); 1400 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1401 (descs[1] >> 24) & 0xff, 1402 (descs[1] >> 16) & 0xff, 1403 (descs[1] >> 8) & 0xff, 1404 descs[1] & 0xff, 1405 descs[2]); 1406 } 1407 if (nreg >= 0x80860006) { 1408 union { 1409 char text[65]; 1410 u_int descs[4][4]; 1411 } info; 1412 int i; 1413 1414 for (i=0; i<4; i++) { 1415 x86_cpuid(0x80860003 + i, info.descs[i]); 1416 } 1417 info.text[64] = '\0'; 1418 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1419 } 1420 1421 if (nreg >= 0x80860007) { 1422 tmx86_get_longrun_status(&frequency, 1423 &voltage, &percentage); 1424 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1425 frequency, voltage, percentage); 1426 } 1427 } 1428 1429 static void 1430 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1431 { 1432 u_int descs[4]; 1433 int i; 1434 uint32_t brand[12]; 1435 1436 memset(ci, 0, sizeof(*ci)); 1437 ci->ci_dev = cpuname; 1438 1439 ci->ci_cpu_type = x86_identify(); 1440 if (ci->ci_cpu_type >= 0) { 1441 /* Old pre-cpuid instruction cpu */ 1442 ci->ci_cpuid_level = -1; 1443 return; 1444 } 1445 1446 /* 1447 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1448 * function. 1449 */ 1450 1451 /* 1452 * Fn0000_0000: 1453 * - Save cpuid max level. 1454 * - Save vendor string. 1455 */ 1456 x86_cpuid(0, descs); 1457 ci->ci_cpuid_level = descs[0]; 1458 /* Save vendor string */ 1459 ci->ci_vendor[0] = descs[1]; 1460 ci->ci_vendor[2] = descs[2]; 1461 ci->ci_vendor[1] = descs[3]; 1462 ci->ci_vendor[3] = 0; 1463 1464 /* 1465 * Fn8000_0000: 1466 * - Get cpuid extended function's max level. 1467 */ 1468 x86_cpuid(0x80000000, descs); 1469 if (descs[0] >= 0x80000000) 1470 ci->ci_cpuid_extlevel = descs[0]; 1471 else { 1472 /* Set lower value than 0x80000000 */ 1473 ci->ci_cpuid_extlevel = 0; 1474 } 1475 1476 /* 1477 * Fn8000_000[2-4]: 1478 * - Save brand string. 1479 */ 1480 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1481 x86_cpuid(0x80000002, brand); 1482 x86_cpuid(0x80000003, brand + 4); 1483 x86_cpuid(0x80000004, brand + 8); 1484 for (i = 0; i < 48; i++) 1485 if (((char *) brand)[i] != ' ') 1486 break; 1487 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1488 } 1489 1490 if (ci->ci_cpuid_level < 1) 1491 return; 1492 1493 /* 1494 * Fn0000_0001: 1495 * - Get CPU family, model and stepping (from eax). 1496 * - Initial local APIC ID and brand ID (from ebx) 1497 * - CPUID2 (from ecx) 1498 * - CPUID (from edx) 1499 */ 1500 x86_cpuid(1, descs); 1501 ci->ci_signature = descs[0]; 1502 1503 /* Extract full family/model values */ 1504 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1505 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1506 1507 /* Brand is low order 8 bits of ebx */ 1508 ci->ci_brand_id = descs[1] & 0xff; 1509 /* Initial local APIC ID */ 1510 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 1511 1512 ci->ci_feat_val[1] = descs[2]; 1513 ci->ci_feat_val[0] = descs[3]; 1514 1515 if (ci->ci_cpuid_level < 3) 1516 return; 1517 1518 /* 1519 * If the processor serial number misfeature is present and supported, 1520 * extract it here. 1521 */ 1522 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1523 ci->ci_cpu_serial[0] = ci->ci_signature; 1524 x86_cpuid(3, descs); 1525 ci->ci_cpu_serial[2] = descs[2]; 1526 ci->ci_cpu_serial[1] = descs[3]; 1527 } 1528 1529 if (ci->ci_cpuid_level < 0x7) 1530 return; 1531 1532 x86_cpuid(7, descs); 1533 ci->ci_feat_val[5] = descs[1]; 1534 ci->ci_feat_val[6] = descs[2]; 1535 1536 if (ci->ci_cpuid_level < 0xd) 1537 return; 1538 1539 /* Get support XCR0 bits */ 1540 x86_cpuid2(0xd, 0, descs); 1541 ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */ 1542 ci->ci_cur_xsave = descs[1]; 1543 ci->ci_max_xsave = descs[2]; 1544 1545 /* Additional flags (eg xsaveopt support) */ 1546 x86_cpuid2(0xd, 1, descs); 1547 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1548 } 1549 1550 static void 1551 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1552 { 1553 uint32_t descs[4]; 1554 char hv_sig[13]; 1555 char *p; 1556 const char *hv_name; 1557 int i; 1558 1559 /* 1560 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1561 * http://lkml.org/lkml/2008/10/1/246 1562 * 1563 * KB1009458: Mechanisms to determine if software is running in 1564 * a VMware virtual machine 1565 * http://kb.vmware.com/kb/1009458 1566 */ 1567 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1568 x86_cpuid(0x40000000, descs); 1569 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1570 memcpy(p, &descs[i], sizeof(descs[i])); 1571 *p = '\0'; 1572 /* 1573 * HV vendor ID string 1574 * ------------+-------------- 1575 * KVM "KVMKVMKVM" 1576 * Microsoft "Microsoft Hv" 1577 * VMware "VMwareVMware" 1578 * Xen "XenVMMXenVMM" 1579 */ 1580 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1581 hv_name = "KVM"; 1582 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1583 hv_name = "Hyper-V"; 1584 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1585 hv_name = "VMware"; 1586 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1587 hv_name = "Xen"; 1588 else 1589 hv_name = "unknown"; 1590 1591 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1592 } 1593 } 1594 1595 static void 1596 cpu_probe_features(struct cpu_info *ci) 1597 { 1598 const struct cpu_cpuid_nameclass *cpup = NULL; 1599 unsigned int i; 1600 1601 if (ci->ci_cpuid_level < 1) 1602 return; 1603 1604 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1605 if (!strncmp((char *)ci->ci_vendor, 1606 i386_cpuid_cpus[i].cpu_id, 12)) { 1607 cpup = &i386_cpuid_cpus[i]; 1608 break; 1609 } 1610 } 1611 1612 if (cpup == NULL) 1613 return; 1614 1615 i = ci->ci_family - CPU_MINFAMILY; 1616 1617 if (i >= __arraycount(cpup->cpu_family)) 1618 i = __arraycount(cpup->cpu_family) - 1; 1619 1620 if (cpup->cpu_family[i].cpu_probe == NULL) 1621 return; 1622 1623 (*cpup->cpu_family[i].cpu_probe)(ci); 1624 } 1625 1626 static void 1627 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1628 { 1629 char buf[32 * 16]; 1630 char *bp; 1631 1632 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1633 1634 if (val == 0 || fmt == NULL) 1635 return; 1636 1637 snprintb_m(buf, sizeof(buf), fmt, val, 1638 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1639 bp = buf; 1640 while (*bp != '\0') { 1641 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1642 bp += strlen(bp) + 1; 1643 } 1644 } 1645 1646 static void 1647 identifycpu_cpuids(struct cpu_info *ci) 1648 { 1649 const char *cpuname = ci->ci_dev; 1650 u_int lp_max = 1; /* logical processors per package */ 1651 u_int smt_max; /* smt per core */ 1652 u_int core_max = 1; /* core per package */ 1653 u_int smt_bits, core_bits; 1654 uint32_t descs[4]; 1655 1656 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1657 ci->ci_packageid = ci->ci_initapicid; 1658 ci->ci_coreid = 0; 1659 ci->ci_smtid = 0; 1660 if (cpu_vendor != CPUVENDOR_INTEL) { 1661 return; 1662 } 1663 1664 /* 1665 * 253668.pdf 7.10.2 1666 */ 1667 1668 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1669 x86_cpuid(1, descs); 1670 lp_max = (descs[1] >> 16) & 0xff; 1671 } 1672 if (ci->ci_cpuid_level >= 4) { 1673 x86_cpuid2(4, 0, descs); 1674 core_max = (descs[0] >> 26) + 1; 1675 } 1676 assert(lp_max >= core_max); 1677 smt_max = lp_max / core_max; 1678 smt_bits = ilog2(smt_max - 1) + 1; 1679 core_bits = ilog2(core_max - 1) + 1; 1680 if (smt_bits + core_bits) { 1681 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1682 } 1683 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1684 ci->ci_packageid); 1685 if (core_bits) { 1686 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1687 1688 ci->ci_coreid = 1689 __SHIFTOUT(ci->ci_initapicid, core_mask); 1690 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1691 } 1692 if (smt_bits) { 1693 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1694 1695 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1696 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1697 } 1698 } 1699 1700 void 1701 identifycpu(int fd, const char *cpuname) 1702 { 1703 const char *name = "", *modifier, *vendorname, *brand = ""; 1704 int class = CPUCLASS_386; 1705 unsigned int i; 1706 int modif, family; 1707 const struct cpu_cpuid_nameclass *cpup = NULL; 1708 const struct cpu_cpuid_family *cpufam; 1709 struct cpu_info *ci, cistore; 1710 u_int descs[4]; 1711 size_t sz; 1712 struct cpu_ucode_version ucode; 1713 union { 1714 struct cpu_ucode_version_amd amd; 1715 struct cpu_ucode_version_intel1 intel1; 1716 } ucvers; 1717 1718 ci = &cistore; 1719 cpu_probe_base_features(ci, cpuname); 1720 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1721 ci->ci_cpuid_level); 1722 if (verbose) { 1723 int bf; 1724 1725 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1726 x86_cpuid(bf, descs); 1727 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1728 bf, descs[0], descs[1], descs[2], descs[3]); 1729 } 1730 } 1731 if (ci->ci_cpuid_extlevel >= 0x80000000) 1732 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1733 ci->ci_cpuid_extlevel); 1734 if (verbose) { 1735 unsigned int ef; 1736 1737 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1738 x86_cpuid(ef, descs); 1739 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1740 ef, descs[0], descs[1], descs[2], descs[3]); 1741 } 1742 } 1743 1744 cpu_probe_hv_features(ci, cpuname); 1745 cpu_probe_features(ci); 1746 1747 if (ci->ci_cpu_type >= 0) { 1748 /* Old pre-cpuid instruction cpu */ 1749 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1750 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1751 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1752 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1753 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1754 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1755 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1756 modifier = ""; 1757 } else { 1758 /* CPU which support cpuid instruction */ 1759 modif = (ci->ci_signature >> 12) & 0x3; 1760 family = ci->ci_family; 1761 if (family < CPU_MINFAMILY) 1762 errx(1, "identifycpu: strange family value"); 1763 if (family > CPU_MAXFAMILY) 1764 family = CPU_MAXFAMILY; 1765 1766 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1767 if (!strncmp((char *)ci->ci_vendor, 1768 i386_cpuid_cpus[i].cpu_id, 12)) { 1769 cpup = &i386_cpuid_cpus[i]; 1770 break; 1771 } 1772 } 1773 1774 if (cpup == NULL) { 1775 cpu_vendor = CPUVENDOR_UNKNOWN; 1776 if (ci->ci_vendor[0] != '\0') 1777 vendorname = (char *)&ci->ci_vendor[0]; 1778 else 1779 vendorname = "Unknown"; 1780 class = family - 3; 1781 modifier = ""; 1782 name = ""; 1783 ci->ci_info = NULL; 1784 } else { 1785 cpu_vendor = cpup->cpu_vendor; 1786 vendorname = cpup->cpu_vendorname; 1787 modifier = modifiers[modif]; 1788 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1789 name = cpufam->cpu_models[ci->ci_model]; 1790 if (name == NULL || *name == '\0') 1791 name = cpufam->cpu_model_default; 1792 class = cpufam->cpu_class; 1793 ci->ci_info = cpufam->cpu_info; 1794 1795 if (cpu_vendor == CPUVENDOR_INTEL) { 1796 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1797 const char *tmp; 1798 tmp = intel_family6_name(ci); 1799 if (tmp != NULL) 1800 name = tmp; 1801 } 1802 if (ci->ci_family == 15 && 1803 ci->ci_brand_id < 1804 __arraycount(i386_intel_brand) && 1805 i386_intel_brand[ci->ci_brand_id]) 1806 name = 1807 i386_intel_brand[ci->ci_brand_id]; 1808 } 1809 1810 if (cpu_vendor == CPUVENDOR_AMD) { 1811 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1812 if (ci->ci_brand_id == 1) 1813 /* 1814 * It's Duron. We override the 1815 * name, since it might have 1816 * been misidentified as Athlon. 1817 */ 1818 name = 1819 amd_brand[ci->ci_brand_id]; 1820 else 1821 brand = amd_brand_name; 1822 } 1823 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1824 == 0xf) { 1825 /* Identify AMD64 CPU names. */ 1826 const char *tmp; 1827 tmp = amd_amd64_name(ci); 1828 if (tmp != NULL) 1829 name = tmp; 1830 } 1831 } 1832 1833 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1834 vendorname = "VIA"; 1835 } 1836 } 1837 1838 ci->ci_cpu_class = class; 1839 1840 sz = sizeof(ci->ci_tsc_freq); 1841 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1842 sz = sizeof(use_pae); 1843 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1844 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1845 1846 /* 1847 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1848 * we try to determine from the family/model values. 1849 */ 1850 if (*cpu_brand_string != '\0') 1851 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1852 1853 aprint_normal("%s: %s", cpuname, vendorname); 1854 if (*modifier) 1855 aprint_normal(" %s", modifier); 1856 if (*name) 1857 aprint_normal(" %s", name); 1858 if (*brand) 1859 aprint_normal(" %s", brand); 1860 aprint_normal(" (%s-class)", classnames[class]); 1861 1862 if (ci->ci_tsc_freq != 0) 1863 aprint_normal(", %ju.%02ju MHz", 1864 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1865 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1866 aprint_normal("\n"); 1867 1868 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1869 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1870 if (ci->ci_signature != 0) 1871 aprint_normal(" (id %#x)", ci->ci_signature); 1872 aprint_normal("\n"); 1873 1874 if (ci->ci_info) 1875 (*ci->ci_info)(ci); 1876 1877 /* 1878 * display CPU feature flags 1879 */ 1880 1881 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1882 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1883 1884 /* These next two are actually common definitions! */ 1885 print_bits(cpuname, "features2", 1886 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1887 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1888 print_bits(cpuname, "features3", 1889 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1890 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1891 1892 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1893 ci->ci_feat_val[4]); 1894 1895 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]); 1896 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1897 ci->ci_feat_val[8]); 1898 1899 if (ci->ci_max_xsave != 0) { 1900 aprint_normal("%s: xsave area size: current %d, maximum %d", 1901 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1902 aprint_normal(", xgetbv %sabled\n", 1903 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1904 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1905 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1906 x86_xgetbv()); 1907 } 1908 1909 x86_print_cache_and_tlb_info(ci); 1910 1911 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1912 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1913 cpuname, 1914 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1915 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1916 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1917 } 1918 1919 if (ci->ci_cpu_class == CPUCLASS_386) 1920 errx(1, "NetBSD requires an 80486 or later processor"); 1921 1922 if (ci->ci_cpu_type == CPU_486DLC) { 1923 #ifndef CYRIX_CACHE_WORKS 1924 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1925 #else 1926 #ifndef CYRIX_CACHE_REALLY_WORKS 1927 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1928 #else 1929 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1930 #endif 1931 #endif 1932 } 1933 1934 /* 1935 * Everything past this point requires a Pentium or later. 1936 */ 1937 if (ci->ci_cpuid_level < 0) 1938 return; 1939 1940 identifycpu_cpuids(ci); 1941 1942 #ifdef INTEL_CORETEMP 1943 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1944 coretemp_register(ci); 1945 #endif 1946 1947 if (cpu_vendor == CPUVENDOR_AMD) { 1948 uint32_t data[4]; 1949 1950 x86_cpuid(0x80000000, data); 1951 if (data[0] >= 0x80000007) 1952 powernow_probe(ci); 1953 1954 if ((data[0] >= 0x8000000a) 1955 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1956 x86_cpuid(0x8000000a, data); 1957 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1958 data[0] & 0xf); 1959 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1960 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1961 data[3]); 1962 } 1963 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1964 uint32_t data[4]; 1965 int32_t bi_index; 1966 1967 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1968 x86_cpuid(bi_index, data); 1969 switch (bi_index) { 1970 case 6: 1971 print_bits(cpuname, "DSPM-eax", 1972 CPUID_DSPM_FLAGS, data[0]); 1973 print_bits(cpuname, "DSPM-ecx", 1974 CPUID_DSPM_FLAGS1, data[2]); 1975 break; 1976 case 7: 1977 aprint_verbose("%s: SEF highest subleaf %08x\n", 1978 cpuname, data[0]); 1979 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1980 data[1]); 1981 break; 1982 #if 0 1983 default: 1984 aprint_verbose("%s: basic %08x-eax %08x\n", 1985 cpuname, bi_index, data[0]); 1986 aprint_verbose("%s: basic %08x-ebx %08x\n", 1987 cpuname, bi_index, data[1]); 1988 aprint_verbose("%s: basic %08x-ecx %08x\n", 1989 cpuname, bi_index, data[2]); 1990 aprint_verbose("%s: basic %08x-edx %08x\n", 1991 cpuname, bi_index, data[3]); 1992 break; 1993 #endif 1994 } 1995 } 1996 } 1997 1998 #ifdef INTEL_ONDEMAND_CLOCKMOD 1999 clockmod_init(); 2000 #endif 2001 2002 if (cpu_vendor == CPUVENDOR_AMD) 2003 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2004 else if (cpu_vendor == CPUVENDOR_INTEL) 2005 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2006 else 2007 return; 2008 2009 ucode.data = &ucvers; 2010 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2011 #ifdef __i386__ 2012 struct cpu_ucode_version_64 ucode_64; 2013 if (errno != ENOTTY) 2014 return; 2015 /* Try the 64 bit ioctl */ 2016 memset(&ucode_64, 0, sizeof ucode_64); 2017 ucode_64.data = &ucvers; 2018 ucode_64.loader_version = ucode.loader_version; 2019 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2020 return; 2021 #else 2022 return; 2023 #endif 2024 } 2025 2026 if (cpu_vendor == CPUVENDOR_AMD) 2027 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2028 else if (cpu_vendor == CPUVENDOR_INTEL) 2029 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2030 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2031 } 2032 2033 static const struct x86_cache_info * 2034 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2035 { 2036 int i; 2037 2038 for (i = 0; cai[i].cai_desc != 0; i++) { 2039 if (cai[i].cai_desc == desc) 2040 return (&cai[i]); 2041 } 2042 2043 return (NULL); 2044 } 2045 2046 static const char * 2047 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2048 const char *sep) 2049 { 2050 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2051 char human_num[HUMAN_BUFSIZE]; 2052 2053 if (cai->cai_totalsize == 0) 2054 return sep; 2055 2056 if (sep == NULL) 2057 aprint_verbose_dev(ci->ci_dev, ""); 2058 else 2059 aprint_verbose("%s", sep); 2060 if (name != NULL) 2061 aprint_verbose("%s ", name); 2062 2063 if (cai->cai_string != NULL) { 2064 aprint_verbose("%s ", cai->cai_string); 2065 } else { 2066 (void)humanize_number(human_num, sizeof(human_num), 2067 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2068 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2069 } 2070 switch (cai->cai_associativity) { 2071 case 0: 2072 aprint_verbose("disabled"); 2073 break; 2074 case 1: 2075 aprint_verbose("direct-mapped"); 2076 break; 2077 case 0xff: 2078 aprint_verbose("fully associative"); 2079 break; 2080 default: 2081 aprint_verbose("%d-way", cai->cai_associativity); 2082 break; 2083 } 2084 return ", "; 2085 } 2086 2087 static const char * 2088 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2089 const char *sep) 2090 { 2091 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2092 char human_num[HUMAN_BUFSIZE]; 2093 2094 if (cai->cai_totalsize == 0) 2095 return sep; 2096 2097 if (sep == NULL) 2098 aprint_verbose_dev(ci->ci_dev, ""); 2099 else 2100 aprint_verbose("%s", sep); 2101 if (name != NULL) 2102 aprint_verbose("%s ", name); 2103 2104 if (cai->cai_string != NULL) { 2105 aprint_verbose("%s", cai->cai_string); 2106 } else { 2107 (void)humanize_number(human_num, sizeof(human_num), 2108 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2109 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2110 human_num); 2111 switch (cai->cai_associativity) { 2112 case 0: 2113 aprint_verbose("disabled"); 2114 break; 2115 case 1: 2116 aprint_verbose("direct-mapped"); 2117 break; 2118 case 0xff: 2119 aprint_verbose("fully associative"); 2120 break; 2121 default: 2122 aprint_verbose("%d-way", cai->cai_associativity); 2123 break; 2124 } 2125 } 2126 return ", "; 2127 } 2128 2129 static void 2130 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2131 { 2132 const char *sep = NULL; 2133 2134 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2135 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2136 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2137 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2138 if (sep != NULL) 2139 aprint_verbose("\n"); 2140 } 2141 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2142 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2143 if (sep != NULL) 2144 aprint_verbose("\n"); 2145 } 2146 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2147 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2148 if (sep != NULL) 2149 aprint_verbose("\n"); 2150 } 2151 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2152 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2153 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2154 if (sep != NULL) 2155 aprint_verbose("\n"); 2156 } 2157 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2158 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2159 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2160 if (sep != NULL) 2161 aprint_verbose("\n"); 2162 } 2163 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2164 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2165 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2166 if (sep != NULL) 2167 aprint_verbose("\n"); 2168 } 2169 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2170 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2171 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2172 if (sep != NULL) 2173 aprint_verbose("\n"); 2174 } 2175 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2176 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2177 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2178 if (sep != NULL) 2179 aprint_verbose("\n"); 2180 } 2181 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2182 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2183 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2184 if (sep != NULL) 2185 aprint_verbose("\n"); 2186 } 2187 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2188 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2189 NULL); 2190 if (sep != NULL) 2191 aprint_verbose("\n"); 2192 } 2193 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2194 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2195 NULL); 2196 if (sep != NULL) 2197 aprint_verbose("\n"); 2198 } 2199 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2200 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2201 NULL); 2202 if (sep != NULL) 2203 aprint_verbose("\n"); 2204 } 2205 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2206 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2207 NULL); 2208 if (sep != NULL) 2209 aprint_verbose("\n"); 2210 } 2211 } 2212 2213 static void 2214 powernow_probe(struct cpu_info *ci) 2215 { 2216 uint32_t regs[4]; 2217 char buf[256]; 2218 2219 x86_cpuid(0x80000007, regs); 2220 2221 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2222 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2223 buf); 2224 } 2225 2226 int 2227 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2228 { 2229 struct cpu_info ci; 2230 int loader_version, res; 2231 struct cpu_ucode_version versreq; 2232 2233 cpu_probe_base_features(&ci, "unknown"); 2234 2235 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2236 loader_version = CPU_UCODE_LOADER_AMD; 2237 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2238 loader_version = CPU_UCODE_LOADER_INTEL1; 2239 else 2240 return -1; 2241 2242 /* check whether the kernel understands this loader version */ 2243 versreq.loader_version = loader_version; 2244 versreq.data = 0; 2245 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2246 if (res) 2247 return -1; 2248 2249 switch (loader_version) { 2250 case CPU_UCODE_LOADER_AMD: 2251 if (uc->cpu_nr != -1) { 2252 /* printf? */ 2253 return -1; 2254 } 2255 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2256 break; 2257 case CPU_UCODE_LOADER_INTEL1: 2258 if (uc->cpu_nr == -1) 2259 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2260 else 2261 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2262 break; 2263 default: /* can't happen */ 2264 return -1; 2265 } 2266 uc->loader_version = loader_version; 2267 return 0; 2268 } 2269
Indexes created Fri Sep 26 20:09:58 GMT 2025