i386.c revision 1.74.6.6
1 /* $NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] structure ext. feat. %edx 110 * [8] XCR0 bits (d:0 %eax) 111 * [9] xsave flags (d:1 %eax) 112 */ 113 uint32_t ci_cpu_class; /* CPU class */ 114 uint32_t ci_brand_id; /* Intel brand id */ 115 uint32_t ci_vendor[4]; /* vendor string */ 116 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 117 uint64_t ci_tsc_freq; /* cpu cycles/second */ 118 uint8_t ci_packageid; 119 uint8_t ci_coreid; 120 uint8_t ci_smtid; 121 uint32_t ci_initapicid; 122 123 uint32_t ci_cur_xsave; 124 uint32_t ci_max_xsave; 125 126 struct x86_cache_info ci_cinfo[CAI_COUNT]; 127 void (*ci_info)(struct cpu_info *); 128 }; 129 130 struct cpu_nocpuid_nameclass { 131 int cpu_vendor; 132 const char *cpu_vendorname; 133 const char *cpu_name; 134 int cpu_class; 135 void (*cpu_setup)(struct cpu_info *); 136 void (*cpu_cacheinfo)(struct cpu_info *); 137 void (*cpu_info)(struct cpu_info *); 138 }; 139 140 struct cpu_cpuid_nameclass { 141 const char *cpu_id; 142 int cpu_vendor; 143 const char *cpu_vendorname; 144 struct cpu_cpuid_family { 145 int cpu_class; 146 const char *cpu_models[256]; 147 const char *cpu_model_default; 148 void (*cpu_setup)(struct cpu_info *); 149 void (*cpu_probe)(struct cpu_info *); 150 void (*cpu_info)(struct cpu_info *); 151 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 152 }; 153 154 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 155 156 /* 157 * Map Brand ID from cpuid instruction to brand name. 158 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 159 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 160 * Architectures Software Developer's Manual, Volume 2A". 161 */ 162 static const char * const i386_intel_brand[] = { 163 "", /* Unsupported */ 164 "Celeron", /* Intel (R) Celeron (TM) processor */ 165 "Pentium III", /* Intel (R) Pentium (R) III processor */ 166 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 167 "Pentium III", /* Intel (R) Pentium (R) III processor */ 168 "", /* 0x05: Reserved */ 169 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 170 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 173 "Celeron", /* Intel (R) Celeron (TM) processor */ 174 "Xeon", /* Intel (R) Xeon (TM) processor */ 175 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 176 "", /* 0x0d: Reserved */ 177 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "", /* 0x10: Reserved */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Celeron M", /* Intel (R) Celeron (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 "Celeron", /* Intel (R) Celeron (R) processor */ 184 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 185 "Pentium M", /* Intel (R) Pentium (R) M processor */ 186 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 187 }; 188 189 /* 190 * AMD processors don't have Brand IDs, so we need these names for probe. 191 */ 192 static const char * const amd_brand[] = { 193 "", 194 "Duron", /* AMD Duron(tm) */ 195 "MP", /* AMD Athlon(tm) MP */ 196 "XP", /* AMD Athlon(tm) XP */ 197 "4" /* AMD Athlon(tm) 4 */ 198 }; 199 200 static int cpu_vendor; 201 static char cpu_brand_string[49]; 202 static char amd_brand_name[48]; 203 static int use_pae, largepagesize; 204 205 /* Setup functions */ 206 static void disable_tsc(struct cpu_info *); 207 static void amd_family5_setup(struct cpu_info *); 208 static void cyrix6x86_cpu_setup(struct cpu_info *); 209 static void winchip_cpu_setup(struct cpu_info *); 210 /* Brand/Model name functions */ 211 static const char *intel_family6_name(struct cpu_info *); 212 static const char *amd_amd64_name(struct cpu_info *); 213 /* Probe functions */ 214 static void amd_family6_probe(struct cpu_info *); 215 static void powernow_probe(struct cpu_info *); 216 static void intel_family_new_probe(struct cpu_info *); 217 static void via_cpu_probe(struct cpu_info *); 218 /* (Cache) Info functions */ 219 static void intel_cpu_cacheinfo(struct cpu_info *); 220 static void amd_cpu_cacheinfo(struct cpu_info *); 221 static void via_cpu_cacheinfo(struct cpu_info *); 222 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 223 static void transmeta_cpu_info(struct cpu_info *); 224 /* Common functions */ 225 static void cpu_probe_base_features(struct cpu_info *, const char *); 226 static void cpu_probe_hv_features(struct cpu_info *, const char *); 227 static void cpu_probe_features(struct cpu_info *); 228 static void print_bits(const char *, const char *, const char *, uint32_t); 229 static void identifycpu_cpuids(struct cpu_info *); 230 static const struct x86_cache_info *cache_info_lookup( 231 const struct x86_cache_info *, uint8_t); 232 static const char *print_cache_config(struct cpu_info *, int, const char *, 233 const char *); 234 static const char *print_tlb_config(struct cpu_info *, int, const char *, 235 const char *); 236 static void x86_print_cache_and_tlb_info(struct cpu_info *); 237 238 /* 239 * Note: these are just the ones that may not have a cpuid instruction. 240 * We deal with the rest in a different way. 241 */ 242 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 243 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 244 NULL, NULL, NULL }, /* CPU_386SX */ 245 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 246 NULL, NULL, NULL }, /* CPU_386 */ 247 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486SX */ 249 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_486 */ 251 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 252 NULL, NULL, NULL }, /* CPU_486DLC */ 253 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 254 NULL, NULL, NULL }, /* CPU_6x86 */ 255 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 256 NULL, NULL, NULL }, /* CPU_NX586 */ 257 }; 258 259 const char *classnames[] = { 260 "386", 261 "486", 262 "586", 263 "686" 264 }; 265 266 const char *modifiers[] = { 267 "", 268 "OverDrive", 269 "Dual", 270 "" 271 }; 272 273 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 274 { 275 /* 276 * For Intel processors, check Chapter 35Model-specific 277 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 278 * Software Developer's Manual, Volume 3C". 279 */ 280 "GenuineIntel", 281 CPUVENDOR_INTEL, 282 "Intel", 283 /* Family 4 */ 284 { { 285 CPUCLASS_486, 286 { 287 "486DX", "486DX", "486SX", "486DX2", "486SL", 288 "486SX2", 0, "486DX2 W/B Enhanced", 289 "486DX4", 0, 0, 0, 0, 0, 0, 0, 290 }, 291 "486", /* Default */ 292 NULL, 293 NULL, 294 intel_cpu_cacheinfo, 295 }, 296 /* Family 5 */ 297 { 298 CPUCLASS_586, 299 { 300 "Pentium (P5 A-step)", "Pentium (P5)", 301 "Pentium (P54C)", "Pentium (P24T)", 302 "Pentium/MMX", "Pentium", 0, 303 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 304 "Quark X1000", 0, 0, 0, 0, 0, 0, 305 }, 306 "Pentium", /* Default */ 307 NULL, 308 NULL, 309 intel_cpu_cacheinfo, 310 }, 311 /* Family 6 */ 312 { 313 CPUCLASS_686, 314 { 315 [0x00] = "Pentium Pro (A-step)", 316 [0x01] = "Pentium Pro", 317 [0x03] = "Pentium II (Klamath)", 318 [0x04] = "Pentium Pro", 319 [0x05] = "Pentium II/Celeron (Deschutes)", 320 [0x06] = "Celeron (Mendocino)", 321 [0x07] = "Pentium III (Katmai)", 322 [0x08] = "Pentium III (Coppermine)", 323 [0x09] = "Pentium M (Banias)", 324 [0x0a] = "Pentium III Xeon (Cascades)", 325 [0x0b] = "Pentium III (Tualatin)", 326 [0x0d] = "Pentium M (Dothan)", 327 [0x0e] = "Pentium Core Duo, Core solo", 328 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 329 "Core 2 Quad 6xxx, " 330 "Core 2 Extreme 6xxx, " 331 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 332 "and Pentium DC", 333 [0x15] = "EP80579 Integrated Processor", 334 [0x16] = "Celeron (45nm)", 335 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 336 "Core 2 Quad 8xxx and 9xxx", 337 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 338 "(Nehalem)", 339 [0x1c] = "45nm Atom Family", 340 [0x1d] = "XeonMP 74xx (Nehalem)", 341 [0x1e] = "Core i7 and i5", 342 [0x1f] = "Core i7 and i5", 343 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 344 [0x26] = "Atom Family", 345 [0x27] = "Atom Family", 346 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 347 "i3 2xxx", 348 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 349 [0x2d] = "Xeon E5 Sandy Bridge family, " 350 "Core i7-39xx Extreme", 351 [0x2e] = "Xeon 75xx & 65xx", 352 [0x2f] = "Xeon E7 family", 353 [0x35] = "Atom Family", 354 [0x36] = "Atom S1000", 355 [0x37] = "Atom E3000, Z3[67]00", 356 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 357 "Ivy Bridge", 358 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 359 "(Haswell)", 360 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 361 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 362 "Core i7-49xx Extreme", 363 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 364 "Core i7-59xx Extreme", 365 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 366 "(Haswell)", 367 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 368 "(Haswell)", 369 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 370 [0x4a] = "Atom Z3400", 371 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 372 [0x4d] = "Atom C2000", 373 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 374 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 375 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 376 [0x56] = "Xeon D-1500 (Broadwell)", 377 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 378 [0x5a] = "Atom E3500", 379 [0x5c] = "Atom (Goldmont)", 380 [0x5d] = "Atom X3-C3000 (Silvermont)", 381 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 382 [0x5f] = "Atom (Goldmont, Denverton)", 383 [0x66] = "8th gen Core i3 (Cannon Lake)", 384 [0x6a] = "Future Xeon (Ice Lake)", 385 [0x6c] = "Future Xeon (Ice Lake)", 386 [0x7a] = "Atom (Goldmont Plus)", 387 [0x7d] = "Future Core (Ice Lake)", 388 [0x7e] = "Future Core (Ice Lake)", 389 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 390 [0x86] = "Atom (Tremont)", 391 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 392 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 393 }, 394 "Pentium Pro, II or III", /* Default */ 395 NULL, 396 intel_family_new_probe, 397 intel_cpu_cacheinfo, 398 }, 399 /* Family > 6 */ 400 { 401 CPUCLASS_686, 402 { 403 0, 0, 0, 0, 0, 0, 0, 0, 404 0, 0, 0, 0, 0, 0, 0, 0, 405 }, 406 "Pentium 4", /* Default */ 407 NULL, 408 intel_family_new_probe, 409 intel_cpu_cacheinfo, 410 } } 411 }, 412 { 413 "AuthenticAMD", 414 CPUVENDOR_AMD, 415 "AMD", 416 /* Family 4 */ 417 { { 418 CPUCLASS_486, 419 { 420 0, 0, 0, "Am486DX2 W/T", 421 0, 0, 0, "Am486DX2 W/B", 422 "Am486DX4 W/T or Am5x86 W/T 150", 423 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 424 0, 0, "Am5x86 W/T 133/160", 425 "Am5x86 W/B 133/160", 426 }, 427 "Am486 or Am5x86", /* Default */ 428 NULL, 429 NULL, 430 NULL, 431 }, 432 /* Family 5 */ 433 { 434 CPUCLASS_586, 435 { 436 "K5", "K5", "K5", "K5", 0, 0, "K6", 437 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 438 "K6-2+/III+", 0, 0, 439 }, 440 "K5 or K6", /* Default */ 441 amd_family5_setup, 442 NULL, 443 amd_cpu_cacheinfo, 444 }, 445 /* Family 6 */ 446 { 447 CPUCLASS_686, 448 { 449 0, "Athlon Model 1", "Athlon Model 2", 450 "Duron", "Athlon Model 4 (Thunderbird)", 451 0, "Athlon", "Duron", "Athlon", 0, 452 "Athlon", 0, 0, 0, 0, 0, 453 }, 454 "K7 (Athlon)", /* Default */ 455 NULL, 456 amd_family6_probe, 457 amd_cpu_cacheinfo, 458 }, 459 /* Family > 6 */ 460 { 461 CPUCLASS_686, 462 { 463 0, 0, 0, 0, 0, 0, 0, 0, 464 0, 0, 0, 0, 0, 0, 0, 0, 465 }, 466 "Unknown K8 (Athlon)", /* Default */ 467 NULL, 468 amd_family6_probe, 469 amd_cpu_cacheinfo, 470 } } 471 }, 472 { 473 "CyrixInstead", 474 CPUVENDOR_CYRIX, 475 "Cyrix", 476 /* Family 4 */ 477 { { 478 CPUCLASS_486, 479 { 480 0, 0, 0, 481 "MediaGX", 482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 483 }, 484 "486", /* Default */ 485 cyrix6x86_cpu_setup, /* XXX ?? */ 486 NULL, 487 NULL, 488 }, 489 /* Family 5 */ 490 { 491 CPUCLASS_586, 492 { 493 0, 0, "6x86", 0, 494 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 496 }, 497 "6x86", /* Default */ 498 cyrix6x86_cpu_setup, 499 NULL, 500 NULL, 501 }, 502 /* Family 6 */ 503 { 504 CPUCLASS_686, 505 { 506 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 507 0, 0, 0, 0, 0, 0, 0, 0, 508 }, 509 "6x86MX", /* Default */ 510 cyrix6x86_cpu_setup, 511 NULL, 512 NULL, 513 }, 514 /* Family > 6 */ 515 { 516 CPUCLASS_686, 517 { 518 0, 0, 0, 0, 0, 0, 0, 0, 519 0, 0, 0, 0, 0, 0, 0, 0, 520 }, 521 "Unknown 6x86MX", /* Default */ 522 NULL, 523 NULL, 524 NULL, 525 } } 526 }, 527 { /* MediaGX is now owned by National Semiconductor */ 528 "Geode by NSC", 529 CPUVENDOR_CYRIX, /* XXX */ 530 "National Semiconductor", 531 /* Family 4, NSC never had any of these */ 532 { { 533 CPUCLASS_486, 534 { 535 0, 0, 0, 0, 0, 0, 0, 0, 536 0, 0, 0, 0, 0, 0, 0, 0, 537 }, 538 "486 compatible", /* Default */ 539 NULL, 540 NULL, 541 NULL, 542 }, 543 /* Family 5: Geode family, formerly MediaGX */ 544 { 545 CPUCLASS_586, 546 { 547 0, 0, 0, 0, 548 "Geode GX1", 549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 550 }, 551 "Geode", /* Default */ 552 cyrix6x86_cpu_setup, 553 NULL, 554 amd_cpu_cacheinfo, 555 }, 556 /* Family 6, not yet available from NSC */ 557 { 558 CPUCLASS_686, 559 { 560 0, 0, 0, 0, 0, 0, 0, 0, 561 0, 0, 0, 0, 0, 0, 0, 0, 562 }, 563 "Pentium Pro compatible", /* Default */ 564 NULL, 565 NULL, 566 NULL, 567 }, 568 /* Family > 6, not yet available from NSC */ 569 { 570 CPUCLASS_686, 571 { 572 0, 0, 0, 0, 0, 0, 0, 0, 573 0, 0, 0, 0, 0, 0, 0, 0, 574 }, 575 "Pentium Pro compatible", /* Default */ 576 NULL, 577 NULL, 578 NULL, 579 } } 580 }, 581 { 582 "CentaurHauls", 583 CPUVENDOR_IDT, 584 "IDT", 585 /* Family 4, IDT never had any of these */ 586 { { 587 CPUCLASS_486, 588 { 589 0, 0, 0, 0, 0, 0, 0, 0, 590 0, 0, 0, 0, 0, 0, 0, 0, 591 }, 592 "486 compatible", /* Default */ 593 NULL, 594 NULL, 595 NULL, 596 }, 597 /* Family 5 */ 598 { 599 CPUCLASS_586, 600 { 601 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 602 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 603 }, 604 "WinChip", /* Default */ 605 winchip_cpu_setup, 606 NULL, 607 NULL, 608 }, 609 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 610 { 611 CPUCLASS_686, 612 { 613 0, 0, 0, 0, 0, 0, "C3 Samuel", 614 "C3 Samuel 2/Ezra", "C3 Ezra-T", 615 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 616 0, "VIA Nano", 617 }, 618 "Unknown VIA/IDT", /* Default */ 619 NULL, 620 via_cpu_probe, 621 via_cpu_cacheinfo, 622 }, 623 /* Family > 6, not yet available from VIA */ 624 { 625 CPUCLASS_686, 626 { 627 0, 0, 0, 0, 0, 0, 0, 0, 628 0, 0, 0, 0, 0, 0, 0, 0, 629 }, 630 "Pentium Pro compatible", /* Default */ 631 NULL, 632 NULL, 633 NULL, 634 } } 635 }, 636 { 637 "GenuineTMx86", 638 CPUVENDOR_TRANSMETA, 639 "Transmeta", 640 /* Family 4, Transmeta never had any of these */ 641 { { 642 CPUCLASS_486, 643 { 644 0, 0, 0, 0, 0, 0, 0, 0, 645 0, 0, 0, 0, 0, 0, 0, 0, 646 }, 647 "486 compatible", /* Default */ 648 NULL, 649 NULL, 650 NULL, 651 }, 652 /* Family 5 */ 653 { 654 CPUCLASS_586, 655 { 656 0, 0, 0, 0, 0, 0, 0, 0, 657 0, 0, 0, 0, 0, 0, 0, 0, 658 }, 659 "Crusoe", /* Default */ 660 NULL, 661 NULL, 662 transmeta_cpu_info, 663 }, 664 /* Family 6, not yet available from Transmeta */ 665 { 666 CPUCLASS_686, 667 { 668 0, 0, 0, 0, 0, 0, 0, 0, 669 0, 0, 0, 0, 0, 0, 0, 0, 670 }, 671 "Pentium Pro compatible", /* Default */ 672 NULL, 673 NULL, 674 NULL, 675 }, 676 /* Family > 6, not yet available from Transmeta */ 677 { 678 CPUCLASS_686, 679 { 680 0, 0, 0, 0, 0, 0, 0, 0, 681 0, 0, 0, 0, 0, 0, 0, 0, 682 }, 683 "Pentium Pro compatible", /* Default */ 684 NULL, 685 NULL, 686 NULL, 687 } } 688 } 689 }; 690 691 /* 692 * disable the TSC such that we don't use the TSC in microtime(9) 693 * because some CPUs got the implementation wrong. 694 */ 695 static void 696 disable_tsc(struct cpu_info *ci) 697 { 698 if (ci->ci_feat_val[0] & CPUID_TSC) { 699 ci->ci_feat_val[0] &= ~CPUID_TSC; 700 aprint_error("WARNING: broken TSC disabled\n"); 701 } 702 } 703 704 static void 705 amd_family5_setup(struct cpu_info *ci) 706 { 707 708 switch (ci->ci_model) { 709 case 0: /* AMD-K5 Model 0 */ 710 /* 711 * According to the AMD Processor Recognition App Note, 712 * the AMD-K5 Model 0 uses the wrong bit to indicate 713 * support for global PTEs, instead using bit 9 (APIC) 714 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 715 */ 716 if (ci->ci_feat_val[0] & CPUID_APIC) 717 ci->ci_feat_val[0] = 718 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 719 /* 720 * XXX But pmap_pg_g is already initialized -- need to kick 721 * XXX the pmap somehow. How does the MP branch do this? 722 */ 723 break; 724 } 725 } 726 727 static void 728 cyrix6x86_cpu_setup(struct cpu_info *ci) 729 { 730 731 /* 732 * Do not disable the TSC on the Geode GX, it's reported to 733 * work fine. 734 */ 735 if (ci->ci_signature != 0x552) 736 disable_tsc(ci); 737 } 738 739 static void 740 winchip_cpu_setup(struct cpu_info *ci) 741 { 742 switch (ci->ci_model) { 743 case 4: /* WinChip C6 */ 744 disable_tsc(ci); 745 } 746 } 747 748 749 static const char * 750 intel_family6_name(struct cpu_info *ci) 751 { 752 const char *ret = NULL; 753 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 754 755 if (ci->ci_model == 5) { 756 switch (l2cache) { 757 case 0: 758 case 128 * 1024: 759 ret = "Celeron (Covington)"; 760 break; 761 case 256 * 1024: 762 ret = "Mobile Pentium II (Dixon)"; 763 break; 764 case 512 * 1024: 765 ret = "Pentium II"; 766 break; 767 case 1 * 1024 * 1024: 768 case 2 * 1024 * 1024: 769 ret = "Pentium II Xeon"; 770 break; 771 } 772 } else if (ci->ci_model == 6) { 773 switch (l2cache) { 774 case 256 * 1024: 775 case 512 * 1024: 776 ret = "Mobile Pentium II"; 777 break; 778 } 779 } else if (ci->ci_model == 7) { 780 switch (l2cache) { 781 case 512 * 1024: 782 ret = "Pentium III"; 783 break; 784 case 1 * 1024 * 1024: 785 case 2 * 1024 * 1024: 786 ret = "Pentium III Xeon"; 787 break; 788 } 789 } else if (ci->ci_model >= 8) { 790 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 791 switch (ci->ci_brand_id) { 792 case 0x3: 793 if (ci->ci_signature == 0x6B1) 794 ret = "Celeron"; 795 break; 796 case 0x8: 797 if (ci->ci_signature >= 0xF13) 798 ret = "genuine processor"; 799 break; 800 case 0xB: 801 if (ci->ci_signature >= 0xF13) 802 ret = "Xeon MP"; 803 break; 804 case 0xE: 805 if (ci->ci_signature < 0xF13) 806 ret = "Xeon"; 807 break; 808 } 809 if (ret == NULL) 810 ret = i386_intel_brand[ci->ci_brand_id]; 811 } 812 } 813 814 return ret; 815 } 816 817 /* 818 * Identify AMD64 CPU names from cpuid. 819 * 820 * Based on: 821 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 822 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 823 * "Revision Guide for AMD NPT Family 0Fh Processors" 824 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 825 * and other miscellaneous reports. 826 * 827 * This is all rather pointless, these are cross 'brand' since the raw 828 * silicon is shared. 829 */ 830 static const char * 831 amd_amd64_name(struct cpu_info *ci) 832 { 833 static char family_str[32]; 834 835 /* Only called if family >= 15 */ 836 837 switch (ci->ci_family) { 838 case 15: 839 switch (ci->ci_model) { 840 case 0x21: /* rev JH-E1/E6 */ 841 case 0x41: /* rev JH-F2 */ 842 return "Dual-Core Opteron"; 843 case 0x23: /* rev JH-E6 (Toledo) */ 844 return "Dual-Core Opteron or Athlon 64 X2"; 845 case 0x43: /* rev JH-F2 (Windsor) */ 846 return "Athlon 64 FX or Athlon 64 X2"; 847 case 0x24: /* rev SH-E5 (Lancaster?) */ 848 return "Mobile Athlon 64 or Turion 64"; 849 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 850 return "Opteron or Athlon 64 FX"; 851 case 0x15: /* rev SH-D0 */ 852 case 0x25: /* rev SH-E4 */ 853 return "Opteron"; 854 case 0x27: /* rev DH-E4, SH-E4 */ 855 return "Athlon 64 or Athlon 64 FX or Opteron"; 856 case 0x48: /* rev BH-F2 */ 857 return "Turion 64 X2"; 858 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 859 case 0x07: /* rev SH-CG (ClawHammer) */ 860 case 0x0b: /* rev CH-CG */ 861 case 0x14: /* rev SH-D0 */ 862 case 0x17: /* rev SH-D0 */ 863 case 0x1b: /* rev CH-D0 */ 864 return "Athlon 64"; 865 case 0x2b: /* rev BH-E4 (Manchester) */ 866 case 0x4b: /* rev BH-F2 (Windsor) */ 867 return "Athlon 64 X2"; 868 case 0x6b: /* rev BH-G1 (Brisbane) */ 869 return "Athlon X2 or Athlon 64 X2"; 870 case 0x08: /* rev CH-CG */ 871 case 0x0c: /* rev DH-CG (Newcastle) */ 872 case 0x0e: /* rev DH-CG (Newcastle?) */ 873 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 874 case 0x18: /* rev CH-D0 */ 875 case 0x1c: /* rev DH-D0 (Winchester) */ 876 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 877 case 0x2c: /* rev DH-E3/E6 */ 878 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 879 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 880 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 881 case 0x6f: /* rev DH-G1 */ 882 return "Athlon 64 or Sempron"; 883 default: 884 break; 885 } 886 return "Unknown AMD64 CPU"; 887 888 #if 0 889 case 16: 890 return "Family 10h"; 891 case 17: 892 return "Family 11h"; 893 case 18: 894 return "Family 12h"; 895 case 19: 896 return "Family 14h"; 897 case 20: 898 return "Family 15h"; 899 #endif 900 901 default: 902 break; 903 } 904 905 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 906 return family_str; 907 } 908 909 static void 910 intel_family_new_probe(struct cpu_info *ci) 911 { 912 uint32_t descs[4]; 913 914 x86_cpuid(0x80000000, descs); 915 916 /* 917 * Determine extended feature flags. 918 */ 919 if (descs[0] >= 0x80000001) { 920 x86_cpuid(0x80000001, descs); 921 ci->ci_feat_val[2] |= descs[3]; 922 ci->ci_feat_val[3] |= descs[2]; 923 } 924 } 925 926 static void 927 via_cpu_probe(struct cpu_info *ci) 928 { 929 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 930 u_int descs[4]; 931 u_int lfunc; 932 933 /* 934 * Determine the largest extended function value. 935 */ 936 x86_cpuid(0x80000000, descs); 937 lfunc = descs[0]; 938 939 /* 940 * Determine the extended feature flags. 941 */ 942 if (lfunc >= 0x80000001) { 943 x86_cpuid(0x80000001, descs); 944 ci->ci_feat_val[2] |= descs[3]; 945 } 946 947 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 948 return; 949 950 /* Nehemiah or Esther */ 951 x86_cpuid(0xc0000000, descs); 952 lfunc = descs[0]; 953 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 954 return; 955 956 x86_cpuid(0xc0000001, descs); 957 lfunc = descs[3]; 958 ci->ci_feat_val[4] = lfunc; 959 } 960 961 static void 962 amd_family6_probe(struct cpu_info *ci) 963 { 964 uint32_t descs[4]; 965 char *p; 966 size_t i; 967 968 x86_cpuid(0x80000000, descs); 969 970 /* 971 * Determine the extended feature flags. 972 */ 973 if (descs[0] >= 0x80000001) { 974 x86_cpuid(0x80000001, descs); 975 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 976 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 977 } 978 979 if (*cpu_brand_string == '\0') 980 return; 981 982 for (i = 1; i < __arraycount(amd_brand); i++) 983 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 984 ci->ci_brand_id = i; 985 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 986 break; 987 } 988 } 989 990 static void 991 intel_cpu_cacheinfo(struct cpu_info *ci) 992 { 993 const struct x86_cache_info *cai; 994 u_int descs[4]; 995 int iterations, i, j; 996 int type, level; 997 int ways, partitions, linesize, sets; 998 int caitype = -1; 999 int totalsize; 1000 uint8_t desc; 1001 1002 /* Return if the cpu is old pre-cpuid instruction cpu */ 1003 if (ci->ci_cpu_type >= 0) 1004 return; 1005 1006 if (ci->ci_cpuid_level < 2) 1007 return; 1008 1009 /* 1010 * Parse the cache info from `cpuid leaf 2', if we have it. 1011 * XXX This is kinda ugly, but hey, so is the architecture... 1012 */ 1013 x86_cpuid(2, descs); 1014 iterations = descs[0] & 0xff; 1015 while (iterations-- > 0) { 1016 for (i = 0; i < 4; i++) { 1017 if (descs[i] & 0x80000000) 1018 continue; 1019 for (j = 0; j < 4; j++) { 1020 /* 1021 * The least significant byte in EAX 1022 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1023 * it should be ignored. 1024 */ 1025 if (i == 0 && j == 0) 1026 continue; 1027 desc = (descs[i] >> (j * 8)) & 0xff; 1028 if (desc == 0) 1029 continue; 1030 cai = cache_info_lookup(intel_cpuid_cache_info, 1031 desc); 1032 if (cai != NULL) 1033 ci->ci_cinfo[cai->cai_index] = *cai; 1034 else if ((verbose != 0) && (desc != 0xff) 1035 && (desc != 0xfe)) 1036 aprint_error_dev(ci->ci_dev, "error:" 1037 " Unknown cacheinfo desc %02x\n", 1038 desc); 1039 } 1040 } 1041 x86_cpuid(2, descs); 1042 } 1043 1044 if (ci->ci_cpuid_level < 4) 1045 return; 1046 1047 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1048 for (i = 0; ; i++) { 1049 x86_cpuid2(4, i, descs); 1050 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1051 if (type == CPUID_DCP_CACHETYPE_N) 1052 break; 1053 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1054 switch (level) { 1055 case 1: 1056 if (type == CPUID_DCP_CACHETYPE_I) 1057 caitype = CAI_ICACHE; 1058 else if (type == CPUID_DCP_CACHETYPE_D) 1059 caitype = CAI_DCACHE; 1060 else 1061 caitype = -1; 1062 break; 1063 case 2: 1064 if (type == CPUID_DCP_CACHETYPE_U) 1065 caitype = CAI_L2CACHE; 1066 else 1067 caitype = -1; 1068 break; 1069 case 3: 1070 if (type == CPUID_DCP_CACHETYPE_U) 1071 caitype = CAI_L3CACHE; 1072 else 1073 caitype = -1; 1074 break; 1075 default: 1076 caitype = -1; 1077 break; 1078 } 1079 if (caitype == -1) { 1080 aprint_error_dev(ci->ci_dev, 1081 "error: unknown cache level&type (%d & %d)\n", 1082 level, type); 1083 continue; 1084 } 1085 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1086 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1087 + 1; 1088 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1089 + 1; 1090 sets = descs[2] + 1; 1091 totalsize = ways * partitions * linesize * sets; 1092 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1093 ci->ci_cinfo[caitype].cai_associativity = ways; 1094 ci->ci_cinfo[caitype].cai_linesize = linesize; 1095 } 1096 1097 if (ci->ci_cpuid_level < 0x18) 1098 return; 1099 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1100 x86_cpuid(0x18, descs); 1101 iterations = descs[0]; 1102 for (i = 0; i <= iterations; i++) { 1103 uint32_t pgsize; 1104 bool full; 1105 1106 x86_cpuid2(0x18, i, descs); 1107 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1108 if (type == CPUID_DATP_TCTYPE_N) 1109 continue; 1110 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1111 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1112 switch (level) { 1113 case 1: 1114 if (type == CPUID_DATP_TCTYPE_I) { 1115 switch (pgsize) { 1116 case CPUID_DATP_PGSIZE_4KB: 1117 caitype = CAI_ITLB; 1118 break; 1119 case CPUID_DATP_PGSIZE_2MB 1120 | CPUID_DATP_PGSIZE_4MB: 1121 caitype = CAI_ITLB2; 1122 break; 1123 case CPUID_DATP_PGSIZE_1GB: 1124 caitype = CAI_L1_1GBITLB; 1125 break; 1126 default: 1127 aprint_error_dev(ci->ci_dev, 1128 "error: unknown ITLB size (%d)\n", 1129 pgsize); 1130 caitype = CAI_ITLB; 1131 break; 1132 } 1133 } else if (type == CPUID_DATP_TCTYPE_D) { 1134 switch (pgsize) { 1135 case CPUID_DATP_PGSIZE_4KB: 1136 caitype = CAI_DTLB; 1137 break; 1138 case CPUID_DATP_PGSIZE_2MB 1139 | CPUID_DATP_PGSIZE_4MB: 1140 caitype = CAI_DTLB2; 1141 break; 1142 case CPUID_DATP_PGSIZE_1GB: 1143 caitype = CAI_L1_1GBDTLB; 1144 break; 1145 default: 1146 aprint_error_dev(ci->ci_dev, 1147 "error: unknown DTLB size (%d)\n", 1148 pgsize); 1149 caitype = CAI_DTLB; 1150 break; 1151 } 1152 } else 1153 caitype = -1; 1154 break; 1155 case 2: 1156 if (type == CPUID_DATP_TCTYPE_I) 1157 caitype = CAI_L2_ITLB; 1158 else if (type == CPUID_DATP_TCTYPE_D) 1159 caitype = CAI_L2_DTLB; 1160 else if (type == CPUID_DATP_TCTYPE_U) { 1161 switch (pgsize) { 1162 case CPUID_DATP_PGSIZE_4KB: 1163 caitype = CAI_L2_STLB; 1164 break; 1165 case CPUID_DATP_PGSIZE_4KB 1166 | CPUID_DATP_PGSIZE_2MB: 1167 caitype = CAI_L2_STLB2; 1168 break; 1169 case CPUID_DATP_PGSIZE_2MB 1170 | CPUID_DATP_PGSIZE_4MB: 1171 caitype = CAI_L2_STLB3; 1172 break; 1173 default: 1174 aprint_error_dev(ci->ci_dev, 1175 "error: unknown L2 STLB size (%d)\n", 1176 pgsize); 1177 caitype = CAI_DTLB; 1178 break; 1179 } 1180 } else 1181 caitype = -1; 1182 break; 1183 case 3: 1184 /* XXX need work for L3 TLB */ 1185 caitype = CAI_L3CACHE; 1186 break; 1187 default: 1188 caitype = -1; 1189 break; 1190 } 1191 if (caitype == -1) { 1192 aprint_error_dev(ci->ci_dev, 1193 "error: unknown TLB level&type (%d & %d)\n", 1194 level, type); 1195 continue; 1196 } 1197 switch (pgsize) { 1198 case CPUID_DATP_PGSIZE_4KB: 1199 linesize = 4 * 1024; 1200 break; 1201 case CPUID_DATP_PGSIZE_2MB: 1202 linesize = 2 * 1024 * 1024; 1203 break; 1204 case CPUID_DATP_PGSIZE_4MB: 1205 linesize = 4 * 1024 * 1024; 1206 break; 1207 case CPUID_DATP_PGSIZE_1GB: 1208 linesize = 1024 * 1024 * 1024; 1209 break; 1210 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1211 aprint_error_dev(ci->ci_dev, 1212 "WARINING: Currently 2M/4M info can't print correctly\n"); 1213 linesize = 4 * 1024 * 1024; 1214 break; 1215 default: 1216 aprint_error_dev(ci->ci_dev, 1217 "error: Unknown size combination\n"); 1218 linesize = 4 * 1024; 1219 break; 1220 } 1221 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1222 sets = descs[2]; 1223 full = descs[3] & CPUID_DATP_FULLASSOC; 1224 ci->ci_cinfo[caitype].cai_totalsize 1225 = ways * sets; /* entries */ 1226 ci->ci_cinfo[caitype].cai_associativity 1227 = full ? 0xff : ways; 1228 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1229 } 1230 } 1231 1232 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1233 AMD_L2CACHE_INFO; 1234 1235 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1236 AMD_L3CACHE_INFO; 1237 1238 static void 1239 amd_cpu_cacheinfo(struct cpu_info *ci) 1240 { 1241 const struct x86_cache_info *cp; 1242 struct x86_cache_info *cai; 1243 u_int descs[4]; 1244 u_int lfunc; 1245 1246 /* 1247 * K5 model 0 has none of this info. 1248 */ 1249 if (ci->ci_family == 5 && ci->ci_model == 0) 1250 return; 1251 1252 /* 1253 * Determine the largest extended function value. 1254 */ 1255 x86_cpuid(0x80000000, descs); 1256 lfunc = descs[0]; 1257 1258 /* 1259 * Determine L1 cache/TLB info. 1260 */ 1261 if (lfunc < 0x80000005) { 1262 /* No L1 cache info available. */ 1263 return; 1264 } 1265 1266 x86_cpuid(0x80000005, descs); 1267 1268 /* 1269 * K6-III and higher have large page TLBs. 1270 */ 1271 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1272 cai = &ci->ci_cinfo[CAI_ITLB2]; 1273 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1274 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1275 cai->cai_linesize = largepagesize; 1276 1277 cai = &ci->ci_cinfo[CAI_DTLB2]; 1278 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1279 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1280 cai->cai_linesize = largepagesize; 1281 } 1282 1283 cai = &ci->ci_cinfo[CAI_ITLB]; 1284 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1285 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1286 cai->cai_linesize = (4 * 1024); 1287 1288 cai = &ci->ci_cinfo[CAI_DTLB]; 1289 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1290 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1291 cai->cai_linesize = (4 * 1024); 1292 1293 cai = &ci->ci_cinfo[CAI_DCACHE]; 1294 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1295 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1296 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1297 1298 cai = &ci->ci_cinfo[CAI_ICACHE]; 1299 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1300 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1301 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1302 1303 /* 1304 * Determine L2 cache/TLB info. 1305 */ 1306 if (lfunc < 0x80000006) { 1307 /* No L2 cache info available. */ 1308 return; 1309 } 1310 1311 x86_cpuid(0x80000006, descs); 1312 1313 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1314 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1315 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1316 cai->cai_linesize = (4 * 1024); 1317 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1318 cai->cai_associativity); 1319 if (cp != NULL) 1320 cai->cai_associativity = cp->cai_associativity; 1321 else 1322 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1323 1324 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1325 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1326 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1327 cai->cai_linesize = largepagesize; 1328 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1329 cai->cai_associativity); 1330 if (cp != NULL) 1331 cai->cai_associativity = cp->cai_associativity; 1332 else 1333 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1334 1335 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1336 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1337 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1338 cai->cai_linesize = (4 * 1024); 1339 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1340 cai->cai_associativity); 1341 if (cp != NULL) 1342 cai->cai_associativity = cp->cai_associativity; 1343 else 1344 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1345 1346 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1347 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1348 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1349 cai->cai_linesize = largepagesize; 1350 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1351 cai->cai_associativity); 1352 if (cp != NULL) 1353 cai->cai_associativity = cp->cai_associativity; 1354 else 1355 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1356 1357 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1358 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1359 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1360 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1361 1362 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1363 cai->cai_associativity); 1364 if (cp != NULL) 1365 cai->cai_associativity = cp->cai_associativity; 1366 else 1367 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1368 1369 /* 1370 * Determine L3 cache info on AMD Family 10h and newer processors 1371 */ 1372 if (ci->ci_family >= 0x10) { 1373 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1374 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1375 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1376 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1377 1378 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1379 cai->cai_associativity); 1380 if (cp != NULL) 1381 cai->cai_associativity = cp->cai_associativity; 1382 else 1383 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1384 } 1385 1386 /* 1387 * Determine 1GB TLB info. 1388 */ 1389 if (lfunc < 0x80000019) { 1390 /* No 1GB TLB info available. */ 1391 return; 1392 } 1393 1394 x86_cpuid(0x80000019, descs); 1395 1396 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1397 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1398 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1399 cai->cai_linesize = (1024 * 1024 * 1024); 1400 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1401 cai->cai_associativity); 1402 if (cp != NULL) 1403 cai->cai_associativity = cp->cai_associativity; 1404 else 1405 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1406 1407 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1408 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1409 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1410 cai->cai_linesize = (1024 * 1024 * 1024); 1411 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1412 cai->cai_associativity); 1413 if (cp != NULL) 1414 cai->cai_associativity = cp->cai_associativity; 1415 else 1416 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1417 1418 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1419 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1420 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1421 cai->cai_linesize = (1024 * 1024 * 1024); 1422 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1423 cai->cai_associativity); 1424 if (cp != NULL) 1425 cai->cai_associativity = cp->cai_associativity; 1426 else 1427 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1428 1429 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1430 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1431 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1432 cai->cai_linesize = (1024 * 1024 * 1024); 1433 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1434 cai->cai_associativity); 1435 if (cp != NULL) 1436 cai->cai_associativity = cp->cai_associativity; 1437 else 1438 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1439 } 1440 1441 static void 1442 via_cpu_cacheinfo(struct cpu_info *ci) 1443 { 1444 struct x86_cache_info *cai; 1445 int stepping; 1446 u_int descs[4]; 1447 u_int lfunc; 1448 1449 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1450 1451 /* 1452 * Determine the largest extended function value. 1453 */ 1454 x86_cpuid(0x80000000, descs); 1455 lfunc = descs[0]; 1456 1457 /* 1458 * Determine L1 cache/TLB info. 1459 */ 1460 if (lfunc < 0x80000005) { 1461 /* No L1 cache info available. */ 1462 return; 1463 } 1464 1465 x86_cpuid(0x80000005, descs); 1466 1467 cai = &ci->ci_cinfo[CAI_ITLB]; 1468 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1469 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1470 cai->cai_linesize = (4 * 1024); 1471 1472 cai = &ci->ci_cinfo[CAI_DTLB]; 1473 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1474 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1475 cai->cai_linesize = (4 * 1024); 1476 1477 cai = &ci->ci_cinfo[CAI_DCACHE]; 1478 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1479 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1480 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1481 if (ci->ci_model == 9 && stepping == 8) { 1482 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1483 cai->cai_associativity = 2; 1484 } 1485 1486 cai = &ci->ci_cinfo[CAI_ICACHE]; 1487 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1488 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1489 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1490 if (ci->ci_model == 9 && stepping == 8) { 1491 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1492 cai->cai_associativity = 2; 1493 } 1494 1495 /* 1496 * Determine L2 cache/TLB info. 1497 */ 1498 if (lfunc < 0x80000006) { 1499 /* No L2 cache info available. */ 1500 return; 1501 } 1502 1503 x86_cpuid(0x80000006, descs); 1504 1505 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1506 if (ci->ci_model >= 9) { 1507 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1508 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1509 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1510 } else { 1511 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1512 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1513 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1514 } 1515 } 1516 1517 static void 1518 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1519 { 1520 u_int descs[4]; 1521 1522 x86_cpuid(0x80860007, descs); 1523 *frequency = descs[0]; 1524 *voltage = descs[1]; 1525 *percentage = descs[2]; 1526 } 1527 1528 static void 1529 transmeta_cpu_info(struct cpu_info *ci) 1530 { 1531 u_int descs[4], nreg; 1532 u_int frequency, voltage, percentage; 1533 1534 x86_cpuid(0x80860000, descs); 1535 nreg = descs[0]; 1536 if (nreg >= 0x80860001) { 1537 x86_cpuid(0x80860001, descs); 1538 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1539 (descs[1] >> 24) & 0xff, 1540 (descs[1] >> 16) & 0xff, 1541 (descs[1] >> 8) & 0xff, 1542 descs[1] & 0xff); 1543 } 1544 if (nreg >= 0x80860002) { 1545 x86_cpuid(0x80860002, descs); 1546 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1547 (descs[1] >> 24) & 0xff, 1548 (descs[1] >> 16) & 0xff, 1549 (descs[1] >> 8) & 0xff, 1550 descs[1] & 0xff, 1551 descs[2]); 1552 } 1553 if (nreg >= 0x80860006) { 1554 union { 1555 char text[65]; 1556 u_int descs[4][4]; 1557 } info; 1558 int i; 1559 1560 for (i=0; i<4; i++) { 1561 x86_cpuid(0x80860003 + i, info.descs[i]); 1562 } 1563 info.text[64] = '\0'; 1564 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1565 } 1566 1567 if (nreg >= 0x80860007) { 1568 tmx86_get_longrun_status(&frequency, 1569 &voltage, &percentage); 1570 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1571 frequency, voltage, percentage); 1572 } 1573 } 1574 1575 static void 1576 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1577 { 1578 u_int descs[4]; 1579 int i; 1580 uint32_t brand[12]; 1581 1582 memset(ci, 0, sizeof(*ci)); 1583 ci->ci_dev = cpuname; 1584 1585 ci->ci_cpu_type = x86_identify(); 1586 if (ci->ci_cpu_type >= 0) { 1587 /* Old pre-cpuid instruction cpu */ 1588 ci->ci_cpuid_level = -1; 1589 return; 1590 } 1591 1592 /* 1593 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1594 * function. 1595 */ 1596 1597 /* 1598 * Fn0000_0000: 1599 * - Save cpuid max level. 1600 * - Save vendor string. 1601 */ 1602 x86_cpuid(0, descs); 1603 ci->ci_cpuid_level = descs[0]; 1604 /* Save vendor string */ 1605 ci->ci_vendor[0] = descs[1]; 1606 ci->ci_vendor[2] = descs[2]; 1607 ci->ci_vendor[1] = descs[3]; 1608 ci->ci_vendor[3] = 0; 1609 1610 /* 1611 * Fn8000_0000: 1612 * - Get cpuid extended function's max level. 1613 */ 1614 x86_cpuid(0x80000000, descs); 1615 if (descs[0] >= 0x80000000) 1616 ci->ci_cpuid_extlevel = descs[0]; 1617 else { 1618 /* Set lower value than 0x80000000 */ 1619 ci->ci_cpuid_extlevel = 0; 1620 } 1621 1622 /* 1623 * Fn8000_000[2-4]: 1624 * - Save brand string. 1625 */ 1626 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1627 x86_cpuid(0x80000002, brand); 1628 x86_cpuid(0x80000003, brand + 4); 1629 x86_cpuid(0x80000004, brand + 8); 1630 for (i = 0; i < 48; i++) 1631 if (((char *) brand)[i] != ' ') 1632 break; 1633 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1634 } 1635 1636 if (ci->ci_cpuid_level < 1) 1637 return; 1638 1639 /* 1640 * Fn0000_0001: 1641 * - Get CPU family, model and stepping (from eax). 1642 * - Initial local APIC ID and brand ID (from ebx) 1643 * - CPUID2 (from ecx) 1644 * - CPUID (from edx) 1645 */ 1646 x86_cpuid(1, descs); 1647 ci->ci_signature = descs[0]; 1648 1649 /* Extract full family/model values */ 1650 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1651 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1652 1653 /* Brand is low order 8 bits of ebx */ 1654 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1655 /* Initial local APIC ID */ 1656 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1657 1658 ci->ci_feat_val[1] = descs[2]; 1659 ci->ci_feat_val[0] = descs[3]; 1660 1661 if (ci->ci_cpuid_level < 3) 1662 return; 1663 1664 /* 1665 * If the processor serial number misfeature is present and supported, 1666 * extract it here. 1667 */ 1668 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1669 ci->ci_cpu_serial[0] = ci->ci_signature; 1670 x86_cpuid(3, descs); 1671 ci->ci_cpu_serial[2] = descs[2]; 1672 ci->ci_cpu_serial[1] = descs[3]; 1673 } 1674 1675 if (ci->ci_cpuid_level < 0x7) 1676 return; 1677 1678 x86_cpuid(7, descs); 1679 ci->ci_feat_val[5] = descs[1]; 1680 ci->ci_feat_val[6] = descs[2]; 1681 ci->ci_feat_val[7] = descs[3]; 1682 1683 if (ci->ci_cpuid_level < 0xd) 1684 return; 1685 1686 /* Get support XCR0 bits */ 1687 x86_cpuid2(0xd, 0, descs); 1688 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1689 ci->ci_cur_xsave = descs[1]; 1690 ci->ci_max_xsave = descs[2]; 1691 1692 /* Additional flags (eg xsaveopt support) */ 1693 x86_cpuid2(0xd, 1, descs); 1694 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1695 } 1696 1697 static void 1698 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1699 { 1700 uint32_t descs[4]; 1701 char hv_sig[13]; 1702 char *p; 1703 const char *hv_name; 1704 int i; 1705 1706 /* 1707 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1708 * http://lkml.org/lkml/2008/10/1/246 1709 * 1710 * KB1009458: Mechanisms to determine if software is running in 1711 * a VMware virtual machine 1712 * http://kb.vmware.com/kb/1009458 1713 */ 1714 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1715 x86_cpuid(0x40000000, descs); 1716 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1717 memcpy(p, &descs[i], sizeof(descs[i])); 1718 *p = '\0'; 1719 /* 1720 * HV vendor ID string 1721 * ------------+-------------- 1722 * HAXM "HAXMHAXMHAXM" 1723 * KVM "KVMKVMKVM" 1724 * Microsoft "Microsoft Hv" 1725 * QEMU(TCG) "TCGTCGTCGTCG" 1726 * VMware "VMwareVMware" 1727 * Xen "XenVMMXenVMM" 1728 * NetBSD "___ NVMM ___" 1729 */ 1730 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1731 hv_name = "HAXM"; 1732 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1733 hv_name = "KVM"; 1734 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1735 hv_name = "Hyper-V"; 1736 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1737 hv_name = "QEMU(TCG)"; 1738 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1739 hv_name = "VMware"; 1740 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1741 hv_name = "Xen"; 1742 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1743 hv_name = "NVMM"; 1744 else 1745 hv_name = "unknown"; 1746 1747 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1748 } 1749 } 1750 1751 static void 1752 cpu_probe_features(struct cpu_info *ci) 1753 { 1754 const struct cpu_cpuid_nameclass *cpup = NULL; 1755 unsigned int i; 1756 1757 if (ci->ci_cpuid_level < 1) 1758 return; 1759 1760 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1761 if (!strncmp((char *)ci->ci_vendor, 1762 i386_cpuid_cpus[i].cpu_id, 12)) { 1763 cpup = &i386_cpuid_cpus[i]; 1764 break; 1765 } 1766 } 1767 1768 if (cpup == NULL) 1769 return; 1770 1771 i = ci->ci_family - CPU_MINFAMILY; 1772 1773 if (i >= __arraycount(cpup->cpu_family)) 1774 i = __arraycount(cpup->cpu_family) - 1; 1775 1776 if (cpup->cpu_family[i].cpu_probe == NULL) 1777 return; 1778 1779 (*cpup->cpu_family[i].cpu_probe)(ci); 1780 } 1781 1782 static void 1783 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1784 { 1785 char buf[32 * 16]; 1786 char *bp; 1787 1788 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1789 1790 if (val == 0 || fmt == NULL) 1791 return; 1792 1793 snprintb_m(buf, sizeof(buf), fmt, val, 1794 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1795 bp = buf; 1796 while (*bp != '\0') { 1797 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1798 bp += strlen(bp) + 1; 1799 } 1800 } 1801 1802 static void 1803 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1804 const char *blockname) 1805 { 1806 uint32_t descs[4]; 1807 uint32_t leaf; 1808 1809 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1810 leafend); 1811 1812 if (verbose) { 1813 for (leaf = leafstart; leaf <= leafend; leaf++) { 1814 x86_cpuid(leaf, descs); 1815 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1816 leaf, descs[0], descs[1], descs[2], descs[3]); 1817 } 1818 } 1819 } 1820 1821 static void 1822 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1823 { 1824 u_int lp_max = 1; /* logical processors per package */ 1825 u_int smt_max; /* smt per core */ 1826 u_int core_max = 1; /* core per package */ 1827 u_int smt_bits, core_bits; 1828 uint32_t descs[4]; 1829 1830 /* 1831 * 253668.pdf 7.10.2 1832 */ 1833 1834 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1835 x86_cpuid(1, descs); 1836 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1837 } 1838 x86_cpuid2(4, 0, descs); 1839 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1840 1841 assert(lp_max >= core_max); 1842 smt_max = lp_max / core_max; 1843 smt_bits = ilog2(smt_max - 1) + 1; 1844 core_bits = ilog2(core_max - 1) + 1; 1845 1846 if (smt_bits + core_bits) 1847 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1848 1849 if (core_bits) 1850 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1851 __BITS(smt_bits, smt_bits + core_bits - 1)); 1852 1853 if (smt_bits) 1854 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1855 __BITS((int)0, (int)(smt_bits - 1))); 1856 } 1857 1858 static void 1859 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1860 { 1861 const char *cpuname = ci->ci_dev; 1862 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1863 uint32_t descs[4]; 1864 int i; 1865 1866 x86_cpuid(0x0b, descs); 1867 if (descs[1] == 0) { 1868 identifycpu_cpuids_intel_0x04(ci); 1869 return; 1870 } 1871 1872 for (i = 0; ; i++) { 1873 unsigned int shiftnum, lvltype; 1874 x86_cpuid2(0x0b, i, descs); 1875 1876 /* On invalid level, (EAX and) EBX return 0 */ 1877 if (descs[1] == 0) 1878 break; 1879 1880 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1881 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1882 switch (lvltype) { 1883 case CPUID_TOP_LVLTYPE_SMT: 1884 core_shift = shiftnum; 1885 break; 1886 case CPUID_TOP_LVLTYPE_CORE: 1887 pkg_shift = shiftnum; 1888 break; 1889 case CPUID_TOP_LVLTYPE_INVAL: 1890 aprint_verbose("%s: Invalid level type\n", cpuname); 1891 break; 1892 default: 1893 aprint_verbose("%s: Unknown level type(%d) \n", 1894 cpuname, lvltype); 1895 break; 1896 } 1897 } 1898 1899 assert(pkg_shift >= core_shift); 1900 smt_bits = core_shift; 1901 core_bits = pkg_shift - core_shift; 1902 1903 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1904 1905 if (core_bits) 1906 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1907 __BITS(core_shift, pkg_shift - 1)); 1908 1909 if (smt_bits) 1910 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1911 __BITS((int)0, core_shift - 1)); 1912 } 1913 1914 static void 1915 identifycpu_cpuids_intel(struct cpu_info *ci) 1916 { 1917 const char *cpuname = ci->ci_dev; 1918 1919 if (ci->ci_cpuid_level >= 0x0b) 1920 identifycpu_cpuids_intel_0x0b(ci); 1921 else if (ci->ci_cpuid_level >= 4) 1922 identifycpu_cpuids_intel_0x04(ci); 1923 1924 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1925 ci->ci_packageid); 1926 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1927 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1928 } 1929 1930 static void 1931 identifycpu_cpuids(struct cpu_info *ci) 1932 { 1933 const char *cpuname = ci->ci_dev; 1934 1935 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1936 ci->ci_packageid = ci->ci_initapicid; 1937 ci->ci_coreid = 0; 1938 ci->ci_smtid = 0; 1939 1940 if (cpu_vendor == CPUVENDOR_INTEL) 1941 identifycpu_cpuids_intel(ci); 1942 } 1943 1944 void 1945 identifycpu(int fd, const char *cpuname) 1946 { 1947 const char *name = "", *modifier, *vendorname, *brand = ""; 1948 int class = CPUCLASS_386; 1949 unsigned int i; 1950 int modif, family; 1951 const struct cpu_cpuid_nameclass *cpup = NULL; 1952 const struct cpu_cpuid_family *cpufam; 1953 struct cpu_info *ci, cistore; 1954 u_int descs[4]; 1955 size_t sz; 1956 struct cpu_ucode_version ucode; 1957 union { 1958 struct cpu_ucode_version_amd amd; 1959 struct cpu_ucode_version_intel1 intel1; 1960 } ucvers; 1961 1962 ci = &cistore; 1963 cpu_probe_base_features(ci, cpuname); 1964 dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic"); 1965 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1966 x86_cpuid(0x40000000, descs); 1967 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1968 } 1969 dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended"); 1970 1971 cpu_probe_hv_features(ci, cpuname); 1972 cpu_probe_features(ci); 1973 1974 if (ci->ci_cpu_type >= 0) { 1975 /* Old pre-cpuid instruction cpu */ 1976 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1977 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1978 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1979 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1980 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1981 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1982 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1983 modifier = ""; 1984 } else { 1985 /* CPU which support cpuid instruction */ 1986 modif = (ci->ci_signature >> 12) & 0x3; 1987 family = ci->ci_family; 1988 if (family < CPU_MINFAMILY) 1989 errx(1, "identifycpu: strange family value"); 1990 if (family > CPU_MAXFAMILY) 1991 family = CPU_MAXFAMILY; 1992 1993 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1994 if (!strncmp((char *)ci->ci_vendor, 1995 i386_cpuid_cpus[i].cpu_id, 12)) { 1996 cpup = &i386_cpuid_cpus[i]; 1997 break; 1998 } 1999 } 2000 2001 if (cpup == NULL) { 2002 cpu_vendor = CPUVENDOR_UNKNOWN; 2003 if (ci->ci_vendor[0] != '\0') 2004 vendorname = (char *)&ci->ci_vendor[0]; 2005 else 2006 vendorname = "Unknown"; 2007 class = family - 3; 2008 modifier = ""; 2009 name = ""; 2010 ci->ci_info = NULL; 2011 } else { 2012 cpu_vendor = cpup->cpu_vendor; 2013 vendorname = cpup->cpu_vendorname; 2014 modifier = modifiers[modif]; 2015 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2016 name = cpufam->cpu_models[ci->ci_model]; 2017 if (name == NULL || *name == '\0') 2018 name = cpufam->cpu_model_default; 2019 class = cpufam->cpu_class; 2020 ci->ci_info = cpufam->cpu_info; 2021 2022 if (cpu_vendor == CPUVENDOR_INTEL) { 2023 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2024 const char *tmp; 2025 tmp = intel_family6_name(ci); 2026 if (tmp != NULL) 2027 name = tmp; 2028 } 2029 if (ci->ci_family == 15 && 2030 ci->ci_brand_id < 2031 __arraycount(i386_intel_brand) && 2032 i386_intel_brand[ci->ci_brand_id]) 2033 name = 2034 i386_intel_brand[ci->ci_brand_id]; 2035 } 2036 2037 if (cpu_vendor == CPUVENDOR_AMD) { 2038 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2039 if (ci->ci_brand_id == 1) 2040 /* 2041 * It's Duron. We override the 2042 * name, since it might have 2043 * been misidentified as Athlon. 2044 */ 2045 name = 2046 amd_brand[ci->ci_brand_id]; 2047 else 2048 brand = amd_brand_name; 2049 } 2050 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2051 == 0xf) { 2052 /* Identify AMD64 CPU names. */ 2053 const char *tmp; 2054 tmp = amd_amd64_name(ci); 2055 if (tmp != NULL) 2056 name = tmp; 2057 } 2058 } 2059 2060 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2061 vendorname = "VIA"; 2062 } 2063 } 2064 2065 ci->ci_cpu_class = class; 2066 2067 sz = sizeof(ci->ci_tsc_freq); 2068 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2069 sz = sizeof(use_pae); 2070 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2071 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2072 2073 /* 2074 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2075 * we try to determine from the family/model values. 2076 */ 2077 if (*cpu_brand_string != '\0') 2078 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2079 2080 aprint_normal("%s: %s", cpuname, vendorname); 2081 if (*modifier) 2082 aprint_normal(" %s", modifier); 2083 if (*name) 2084 aprint_normal(" %s", name); 2085 if (*brand) 2086 aprint_normal(" %s", brand); 2087 aprint_normal(" (%s-class)", classnames[class]); 2088 2089 if (ci->ci_tsc_freq != 0) 2090 aprint_normal(", %ju.%02ju MHz", 2091 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2092 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2093 aprint_normal("\n"); 2094 2095 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2096 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2097 if (ci->ci_signature != 0) 2098 aprint_normal(" (id %#x)", ci->ci_signature); 2099 aprint_normal("\n"); 2100 2101 if (ci->ci_info) 2102 (*ci->ci_info)(ci); 2103 2104 /* 2105 * display CPU feature flags 2106 */ 2107 2108 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2109 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2110 2111 /* These next two are actually common definitions! */ 2112 print_bits(cpuname, "features2", 2113 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2114 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2115 print_bits(cpuname, "features3", 2116 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2117 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2118 2119 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2120 ci->ci_feat_val[4]); 2121 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2122 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2123 ci->ci_feat_val[5]); 2124 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2125 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2126 ci->ci_feat_val[6]); 2127 2128 if (cpu_vendor == CPUVENDOR_INTEL) 2129 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2130 ci->ci_feat_val[7]); 2131 2132 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2133 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2134 ci->ci_feat_val[9]); 2135 2136 if (ci->ci_max_xsave != 0) { 2137 aprint_normal("%s: xsave area size: current %d, maximum %d", 2138 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2139 aprint_normal(", xgetbv %sabled\n", 2140 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2141 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2142 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2143 x86_xgetbv()); 2144 } 2145 2146 x86_print_cache_and_tlb_info(ci); 2147 2148 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2149 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2150 cpuname, 2151 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2152 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2153 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2154 } 2155 2156 if (ci->ci_cpu_class == CPUCLASS_386) 2157 errx(1, "NetBSD requires an 80486 or later processor"); 2158 2159 if (ci->ci_cpu_type == CPU_486DLC) { 2160 #ifndef CYRIX_CACHE_WORKS 2161 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2162 #else 2163 #ifndef CYRIX_CACHE_REALLY_WORKS 2164 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2165 #else 2166 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2167 #endif 2168 #endif 2169 } 2170 2171 /* 2172 * Everything past this point requires a Pentium or later. 2173 */ 2174 if (ci->ci_cpuid_level < 0) 2175 return; 2176 2177 identifycpu_cpuids(ci); 2178 2179 if ((ci->ci_cpuid_level >= 5) 2180 && ((cpu_vendor == CPUVENDOR_INTEL) 2181 || (cpu_vendor == CPUVENDOR_AMD))) { 2182 uint16_t lmin, lmax; 2183 x86_cpuid(5, descs); 2184 2185 print_bits(cpuname, "MONITOR/MWAIT extensions", 2186 CPUID_MON_FLAGS, descs[2]); 2187 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2188 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2189 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2190 if (lmin != lmax) 2191 aprint_normal("-%hu", lmax); 2192 aprint_normal("\n"); 2193 2194 for (i = 0; i <= 7; i++) { 2195 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2196 2197 if (num != 0) 2198 aprint_normal("%s: C%u substates %u\n", 2199 cpuname, i, num); 2200 } 2201 } 2202 if ((ci->ci_cpuid_level >= 6) 2203 && ((cpu_vendor == CPUVENDOR_INTEL) 2204 || (cpu_vendor == CPUVENDOR_AMD))) { 2205 x86_cpuid(6, descs); 2206 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2207 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2208 } 2209 if ((ci->ci_cpuid_level >= 7) 2210 && ((cpu_vendor == CPUVENDOR_INTEL) 2211 || (cpu_vendor == CPUVENDOR_AMD))) { 2212 x86_cpuid(7, descs); 2213 aprint_verbose("%s: SEF highest subleaf %08x\n", 2214 cpuname, descs[0]); 2215 } 2216 2217 if (cpu_vendor == CPUVENDOR_AMD) { 2218 x86_cpuid(0x80000000, descs); 2219 if (descs[0] >= 0x80000007) 2220 powernow_probe(ci); 2221 2222 if ((descs[0] >= 0x8000000a) 2223 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2224 x86_cpuid(0x8000000a, descs); 2225 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2226 descs[0] & 0xf); 2227 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2228 descs[1]); 2229 print_bits(cpuname, "SVM features", 2230 CPUID_AMD_SVM_FLAGS, descs[3]); 2231 } 2232 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2233 int32_t bi_index; 2234 2235 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2236 x86_cpuid(bi_index, descs); 2237 switch (bi_index) { 2238 case 0x0a: 2239 print_bits(cpuname, "Perfmon-eax", 2240 CPUID_PERF_FLAGS0, descs[0]); 2241 print_bits(cpuname, "Perfmon-ebx", 2242 CPUID_PERF_FLAGS1, descs[1]); 2243 print_bits(cpuname, "Perfmon-edx", 2244 CPUID_PERF_FLAGS3, descs[3]); 2245 break; 2246 default: 2247 #if 0 2248 aprint_verbose("%s: basic %08x-eax %08x\n", 2249 cpuname, bi_index, descs[0]); 2250 aprint_verbose("%s: basic %08x-ebx %08x\n", 2251 cpuname, bi_index, descs[1]); 2252 aprint_verbose("%s: basic %08x-ecx %08x\n", 2253 cpuname, bi_index, descs[2]); 2254 aprint_verbose("%s: basic %08x-edx %08x\n", 2255 cpuname, bi_index, descs[3]); 2256 #endif 2257 break; 2258 } 2259 } 2260 } 2261 2262 #ifdef INTEL_ONDEMAND_CLOCKMOD 2263 clockmod_init(); 2264 #endif 2265 2266 if (cpu_vendor == CPUVENDOR_AMD) 2267 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2268 else if (cpu_vendor == CPUVENDOR_INTEL) 2269 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2270 else 2271 return; 2272 2273 ucode.data = &ucvers; 2274 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2275 #ifdef __i386__ 2276 struct cpu_ucode_version_64 ucode_64; 2277 if (errno != ENOTTY) 2278 return; 2279 /* Try the 64 bit ioctl */ 2280 memset(&ucode_64, 0, sizeof ucode_64); 2281 ucode_64.data = &ucvers; 2282 ucode_64.loader_version = ucode.loader_version; 2283 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2284 return; 2285 #else 2286 return; 2287 #endif 2288 } 2289 2290 if (cpu_vendor == CPUVENDOR_AMD) 2291 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2292 else if (cpu_vendor == CPUVENDOR_INTEL) 2293 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2294 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2295 } 2296 2297 static const struct x86_cache_info * 2298 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2299 { 2300 int i; 2301 2302 for (i = 0; cai[i].cai_desc != 0; i++) { 2303 if (cai[i].cai_desc == desc) 2304 return (&cai[i]); 2305 } 2306 2307 return (NULL); 2308 } 2309 2310 static const char * 2311 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2312 const char *sep) 2313 { 2314 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2315 char human_num[HUMAN_BUFSIZE]; 2316 2317 if (cai->cai_totalsize == 0) 2318 return sep; 2319 2320 if (sep == NULL) 2321 aprint_verbose_dev(ci->ci_dev, ""); 2322 else 2323 aprint_verbose("%s", sep); 2324 if (name != NULL) 2325 aprint_verbose("%s ", name); 2326 2327 if (cai->cai_string != NULL) { 2328 aprint_verbose("%s ", cai->cai_string); 2329 } else { 2330 (void)humanize_number(human_num, sizeof(human_num), 2331 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2332 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2333 } 2334 switch (cai->cai_associativity) { 2335 case 0: 2336 aprint_verbose("disabled"); 2337 break; 2338 case 1: 2339 aprint_verbose("direct-mapped"); 2340 break; 2341 case 0xff: 2342 aprint_verbose("fully associative"); 2343 break; 2344 default: 2345 aprint_verbose("%d-way", cai->cai_associativity); 2346 break; 2347 } 2348 return ", "; 2349 } 2350 2351 static const char * 2352 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2353 const char *sep) 2354 { 2355 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2356 char human_num[HUMAN_BUFSIZE]; 2357 2358 if (cai->cai_totalsize == 0) 2359 return sep; 2360 2361 if (sep == NULL) 2362 aprint_verbose_dev(ci->ci_dev, ""); 2363 else 2364 aprint_verbose("%s", sep); 2365 if (name != NULL) 2366 aprint_verbose("%s ", name); 2367 2368 if (cai->cai_string != NULL) { 2369 aprint_verbose("%s", cai->cai_string); 2370 } else { 2371 (void)humanize_number(human_num, sizeof(human_num), 2372 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2373 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2374 human_num); 2375 switch (cai->cai_associativity) { 2376 case 0: 2377 aprint_verbose("disabled"); 2378 break; 2379 case 1: 2380 aprint_verbose("direct-mapped"); 2381 break; 2382 case 0xff: 2383 aprint_verbose("fully associative"); 2384 break; 2385 default: 2386 aprint_verbose("%d-way", cai->cai_associativity); 2387 break; 2388 } 2389 } 2390 return ", "; 2391 } 2392 2393 static void 2394 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2395 { 2396 const char *sep = NULL; 2397 2398 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2399 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2400 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2401 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2402 if (sep != NULL) 2403 aprint_verbose("\n"); 2404 } 2405 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2406 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2407 if (sep != NULL) 2408 aprint_verbose("\n"); 2409 } 2410 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2411 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2412 if (sep != NULL) 2413 aprint_verbose("\n"); 2414 } 2415 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2416 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2417 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2418 if (sep != NULL) 2419 aprint_verbose("\n"); 2420 } 2421 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2422 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2423 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2424 if (sep != NULL) 2425 aprint_verbose("\n"); 2426 } 2427 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2428 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2429 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2430 if (sep != NULL) 2431 aprint_verbose("\n"); 2432 } 2433 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2434 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2435 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2436 if (sep != NULL) 2437 aprint_verbose("\n"); 2438 } 2439 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2440 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2441 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2442 if (sep != NULL) 2443 aprint_verbose("\n"); 2444 } 2445 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2446 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2447 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2448 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2449 if (sep != NULL) 2450 aprint_verbose("\n"); 2451 } 2452 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2453 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2454 NULL); 2455 if (sep != NULL) 2456 aprint_verbose("\n"); 2457 } 2458 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2459 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2460 NULL); 2461 if (sep != NULL) 2462 aprint_verbose("\n"); 2463 } 2464 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2465 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2466 NULL); 2467 if (sep != NULL) 2468 aprint_verbose("\n"); 2469 } 2470 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2471 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2472 NULL); 2473 if (sep != NULL) 2474 aprint_verbose("\n"); 2475 } 2476 } 2477 2478 static void 2479 powernow_probe(struct cpu_info *ci) 2480 { 2481 uint32_t regs[4]; 2482 char buf[256]; 2483 2484 x86_cpuid(0x80000007, regs); 2485 2486 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2487 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2488 buf); 2489 } 2490 2491 int 2492 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2493 { 2494 struct cpu_info ci; 2495 int loader_version, res; 2496 struct cpu_ucode_version versreq; 2497 2498 cpu_probe_base_features(&ci, "unknown"); 2499 2500 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2501 loader_version = CPU_UCODE_LOADER_AMD; 2502 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2503 loader_version = CPU_UCODE_LOADER_INTEL1; 2504 else 2505 return -1; 2506 2507 /* check whether the kernel understands this loader version */ 2508 versreq.loader_version = loader_version; 2509 versreq.data = 0; 2510 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2511 if (res) 2512 return -1; 2513 2514 switch (loader_version) { 2515 case CPU_UCODE_LOADER_AMD: 2516 if (uc->cpu_nr != -1) { 2517 /* printf? */ 2518 return -1; 2519 } 2520 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2521 break; 2522 case CPU_UCODE_LOADER_INTEL1: 2523 if (uc->cpu_nr == -1) 2524 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2525 else 2526 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2527 break; 2528 default: /* can't happen */ 2529 return -1; 2530 } 2531 uc->loader_version = loader_version; 2532 return 0; 2533 } 2534
Indexes created Thu Oct 23 22:10:10 GMT 2025