i386.c revision 1.76
1 /* $NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.76 2017/10/16 10:10:48 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[9]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] XCR0 bits (d:0 %eax) 110 * [8] xsave flags (d:1 %eax) 111 */ 112 uint32_t ci_cpu_class; /* CPU class */ 113 uint32_t ci_brand_id; /* Intel brand id */ 114 uint32_t ci_vendor[4]; /* vendor string */ 115 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 116 uint64_t ci_tsc_freq; /* cpu cycles/second */ 117 uint8_t ci_packageid; 118 uint8_t ci_coreid; 119 uint8_t ci_smtid; 120 uint32_t ci_initapicid; 121 122 uint32_t ci_cur_xsave; 123 uint32_t ci_max_xsave; 124 125 struct x86_cache_info ci_cinfo[CAI_COUNT]; 126 void (*ci_info)(struct cpu_info *); 127 }; 128 129 struct cpu_nocpuid_nameclass { 130 int cpu_vendor; 131 const char *cpu_vendorname; 132 const char *cpu_name; 133 int cpu_class; 134 void (*cpu_setup)(struct cpu_info *); 135 void (*cpu_cacheinfo)(struct cpu_info *); 136 void (*cpu_info)(struct cpu_info *); 137 }; 138 139 struct cpu_cpuid_nameclass { 140 const char *cpu_id; 141 int cpu_vendor; 142 const char *cpu_vendorname; 143 struct cpu_cpuid_family { 144 int cpu_class; 145 const char *cpu_models[256]; 146 const char *cpu_model_default; 147 void (*cpu_setup)(struct cpu_info *); 148 void (*cpu_probe)(struct cpu_info *); 149 void (*cpu_info)(struct cpu_info *); 150 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 151 }; 152 153 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 154 155 /* 156 * Map Brand ID from cpuid instruction to brand name. 157 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 158 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 159 * Architectures Software Developer's Manual, Volume 2A". 160 */ 161 static const char * const i386_intel_brand[] = { 162 "", /* Unsupported */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "", /* 0x05: Reserved */ 168 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Celeron", /* Intel (R) Celeron (TM) processor */ 173 "Xeon", /* Intel (R) Xeon (TM) processor */ 174 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 175 "", /* 0x0d: Reserved */ 176 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 177 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 178 "", /* 0x10: Reserved */ 179 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 180 "Celeron M", /* Intel (R) Celeron (R) M processor */ 181 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 182 "Celeron", /* Intel (R) Celeron (R) processor */ 183 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 184 "Pentium M", /* Intel (R) Pentium (R) M processor */ 185 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 186 }; 187 188 /* 189 * AMD processors don't have Brand IDs, so we need these names for probe. 190 */ 191 static const char * const amd_brand[] = { 192 "", 193 "Duron", /* AMD Duron(tm) */ 194 "MP", /* AMD Athlon(tm) MP */ 195 "XP", /* AMD Athlon(tm) XP */ 196 "4" /* AMD Athlon(tm) 4 */ 197 }; 198 199 static int cpu_vendor; 200 static char cpu_brand_string[49]; 201 static char amd_brand_name[48]; 202 static int use_pae, largepagesize; 203 204 /* Setup functions */ 205 static void disable_tsc(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 /* Brand/Model name functions */ 210 static const char *intel_family6_name(struct cpu_info *); 211 static const char *amd_amd64_name(struct cpu_info *); 212 /* Probe functions */ 213 static void amd_family6_probe(struct cpu_info *); 214 static void powernow_probe(struct cpu_info *); 215 static void intel_family_new_probe(struct cpu_info *); 216 static void via_cpu_probe(struct cpu_info *); 217 /* (Cache) Info functions */ 218 static void intel_cpu_cacheinfo(struct cpu_info *); 219 static void amd_cpu_cacheinfo(struct cpu_info *); 220 static void via_cpu_cacheinfo(struct cpu_info *); 221 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 222 static void transmeta_cpu_info(struct cpu_info *); 223 /* Common functions */ 224 static void cpu_probe_base_features(struct cpu_info *, const char *); 225 static void cpu_probe_hv_features(struct cpu_info *, const char *); 226 static void cpu_probe_features(struct cpu_info *); 227 static void print_bits(const char *, const char *, const char *, uint32_t); 228 static void identifycpu_cpuids(struct cpu_info *); 229 static const struct x86_cache_info *cache_info_lookup( 230 const struct x86_cache_info *, uint8_t); 231 static const char *print_cache_config(struct cpu_info *, int, const char *, 232 const char *); 233 static const char *print_tlb_config(struct cpu_info *, int, const char *, 234 const char *); 235 static void x86_print_cache_and_tlb_info(struct cpu_info *); 236 237 /* 238 * Note: these are just the ones that may not have a cpuid instruction. 239 * We deal with the rest in a different way. 240 */ 241 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 242 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386SX */ 244 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386 */ 246 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486SX */ 248 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486 */ 250 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486DLC */ 252 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_6x86 */ 254 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 255 NULL, NULL, NULL }, /* CPU_NX586 */ 256 }; 257 258 const char *classnames[] = { 259 "386", 260 "486", 261 "586", 262 "686" 263 }; 264 265 const char *modifiers[] = { 266 "", 267 "OverDrive", 268 "Dual", 269 "" 270 }; 271 272 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 273 { 274 /* 275 * For Intel processors, check Chapter 35Model-specific 276 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 277 * Software Developer's Manual, Volume 3C". 278 */ 279 "GenuineIntel", 280 CPUVENDOR_INTEL, 281 "Intel", 282 /* Family 4 */ 283 { { 284 CPUCLASS_486, 285 { 286 "486DX", "486DX", "486SX", "486DX2", "486SL", 287 "486SX2", 0, "486DX2 W/B Enhanced", 288 "486DX4", 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "486", /* Default */ 291 NULL, 292 NULL, 293 intel_cpu_cacheinfo, 294 }, 295 /* Family 5 */ 296 { 297 CPUCLASS_586, 298 { 299 "Pentium (P5 A-step)", "Pentium (P5)", 300 "Pentium (P54C)", "Pentium (P24T)", 301 "Pentium/MMX", "Pentium", 0, 302 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 303 "Quark X1000", 0, 0, 0, 0, 0, 0, 304 }, 305 "Pentium", /* Default */ 306 NULL, 307 NULL, 308 intel_cpu_cacheinfo, 309 }, 310 /* Family 6 */ 311 { 312 CPUCLASS_686, 313 { 314 [0x00] = "Pentium Pro (A-step)", 315 [0x01] = "Pentium Pro", 316 [0x03] = "Pentium II (Klamath)", 317 [0x04] = "Pentium Pro", 318 [0x05] = "Pentium II/Celeron (Deschutes)", 319 [0x06] = "Celeron (Mendocino)", 320 [0x07] = "Pentium III (Katmai)", 321 [0x08] = "Pentium III (Coppermine)", 322 [0x09] = "Pentium M (Banias)", 323 [0x0a] = "Pentium III Xeon (Cascades)", 324 [0x0b] = "Pentium III (Tualatin)", 325 [0x0d] = "Pentium M (Dothan)", 326 [0x0e] = "Pentium Core Duo, Core solo", 327 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 328 "Core 2 Quad 6xxx, " 329 "Core 2 Extreme 6xxx, " 330 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 331 "and Pentium DC", 332 [0x15] = "EP80579 Integrated Processor", 333 [0x16] = "Celeron (45nm)", 334 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 335 "Core 2 Quad 8xxx and 9xxx", 336 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 337 "(Nehalem)", 338 [0x1c] = "45nm Atom Family", 339 [0x1d] = "XeonMP 74xx (Nehalem)", 340 [0x1e] = "Core i7 and i5", 341 [0x1f] = "Core i7 and i5", 342 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x26] = "Atom Family", 344 [0x27] = "Atom Family", 345 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 346 "i3 2xxx", 347 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 348 [0x2d] = "Xeon E5 Sandy Bridge family, " 349 "Core i7-39xx Extreme", 350 [0x2e] = "Xeon 75xx & 65xx", 351 [0x2f] = "Xeon E7 family", 352 [0x35] = "Atom Family", 353 [0x36] = "Atom S1000", 354 [0x37] = "Atom E3000, Z3[67]00", 355 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 356 "Ivy Bridge", 357 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 360 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 361 "Core i7-49xx Extreme", 362 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 363 "Core i7-59xx Extreme", 364 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 369 [0x4a] = "Atom Z3400", 370 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 371 [0x4d] = "Atom C2000", 372 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 373 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 374 [0x55] = "Future Xeon", 375 [0x56] = "Xeon D-1500 (Broadwell)", 376 [0x57] = "Xeon Phi [357]200", 377 [0x5a] = "Atom E3500", 378 [0x5c] = "Next Atom (Goldmont)", 379 [0x5d] = "Atom X3-C3000 (Silvermont)", 380 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 381 [0x5f] = "Future Atom (Denverton)", 382 [0x85] = "Future Xeon Phi", 383 [0x8e] = "7th gen Core (Kaby Lake)", 384 [0x9e] = "7th gen Core (Kaby Lake)", 385 }, 386 "Pentium Pro, II or III", /* Default */ 387 NULL, 388 intel_family_new_probe, 389 intel_cpu_cacheinfo, 390 }, 391 /* Family > 6 */ 392 { 393 CPUCLASS_686, 394 { 395 0, 0, 0, 0, 0, 0, 0, 0, 396 0, 0, 0, 0, 0, 0, 0, 0, 397 }, 398 "Pentium 4", /* Default */ 399 NULL, 400 intel_family_new_probe, 401 intel_cpu_cacheinfo, 402 } } 403 }, 404 { 405 "AuthenticAMD", 406 CPUVENDOR_AMD, 407 "AMD", 408 /* Family 4 */ 409 { { 410 CPUCLASS_486, 411 { 412 0, 0, 0, "Am486DX2 W/T", 413 0, 0, 0, "Am486DX2 W/B", 414 "Am486DX4 W/T or Am5x86 W/T 150", 415 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 416 0, 0, "Am5x86 W/T 133/160", 417 "Am5x86 W/B 133/160", 418 }, 419 "Am486 or Am5x86", /* Default */ 420 NULL, 421 NULL, 422 NULL, 423 }, 424 /* Family 5 */ 425 { 426 CPUCLASS_586, 427 { 428 "K5", "K5", "K5", "K5", 0, 0, "K6", 429 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 430 "K6-2+/III+", 0, 0, 431 }, 432 "K5 or K6", /* Default */ 433 amd_family5_setup, 434 NULL, 435 amd_cpu_cacheinfo, 436 }, 437 /* Family 6 */ 438 { 439 CPUCLASS_686, 440 { 441 0, "Athlon Model 1", "Athlon Model 2", 442 "Duron", "Athlon Model 4 (Thunderbird)", 443 0, "Athlon", "Duron", "Athlon", 0, 444 "Athlon", 0, 0, 0, 0, 0, 445 }, 446 "K7 (Athlon)", /* Default */ 447 NULL, 448 amd_family6_probe, 449 amd_cpu_cacheinfo, 450 }, 451 /* Family > 6 */ 452 { 453 CPUCLASS_686, 454 { 455 0, 0, 0, 0, 0, 0, 0, 0, 456 0, 0, 0, 0, 0, 0, 0, 0, 457 }, 458 "Unknown K8 (Athlon)", /* Default */ 459 NULL, 460 amd_family6_probe, 461 amd_cpu_cacheinfo, 462 } } 463 }, 464 { 465 "CyrixInstead", 466 CPUVENDOR_CYRIX, 467 "Cyrix", 468 /* Family 4 */ 469 { { 470 CPUCLASS_486, 471 { 472 0, 0, 0, 473 "MediaGX", 474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 475 }, 476 "486", /* Default */ 477 cyrix6x86_cpu_setup, /* XXX ?? */ 478 NULL, 479 NULL, 480 }, 481 /* Family 5 */ 482 { 483 CPUCLASS_586, 484 { 485 0, 0, "6x86", 0, 486 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 488 }, 489 "6x86", /* Default */ 490 cyrix6x86_cpu_setup, 491 NULL, 492 NULL, 493 }, 494 /* Family 6 */ 495 { 496 CPUCLASS_686, 497 { 498 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 499 0, 0, 0, 0, 0, 0, 0, 0, 500 }, 501 "6x86MX", /* Default */ 502 cyrix6x86_cpu_setup, 503 NULL, 504 NULL, 505 }, 506 /* Family > 6 */ 507 { 508 CPUCLASS_686, 509 { 510 0, 0, 0, 0, 0, 0, 0, 0, 511 0, 0, 0, 0, 0, 0, 0, 0, 512 }, 513 "Unknown 6x86MX", /* Default */ 514 NULL, 515 NULL, 516 NULL, 517 } } 518 }, 519 { /* MediaGX is now owned by National Semiconductor */ 520 "Geode by NSC", 521 CPUVENDOR_CYRIX, /* XXX */ 522 "National Semiconductor", 523 /* Family 4, NSC never had any of these */ 524 { { 525 CPUCLASS_486, 526 { 527 0, 0, 0, 0, 0, 0, 0, 0, 528 0, 0, 0, 0, 0, 0, 0, 0, 529 }, 530 "486 compatible", /* Default */ 531 NULL, 532 NULL, 533 NULL, 534 }, 535 /* Family 5: Geode family, formerly MediaGX */ 536 { 537 CPUCLASS_586, 538 { 539 0, 0, 0, 0, 540 "Geode GX1", 541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 542 }, 543 "Geode", /* Default */ 544 cyrix6x86_cpu_setup, 545 NULL, 546 amd_cpu_cacheinfo, 547 }, 548 /* Family 6, not yet available from NSC */ 549 { 550 CPUCLASS_686, 551 { 552 0, 0, 0, 0, 0, 0, 0, 0, 553 0, 0, 0, 0, 0, 0, 0, 0, 554 }, 555 "Pentium Pro compatible", /* Default */ 556 NULL, 557 NULL, 558 NULL, 559 }, 560 /* Family > 6, not yet available from NSC */ 561 { 562 CPUCLASS_686, 563 { 564 0, 0, 0, 0, 0, 0, 0, 0, 565 0, 0, 0, 0, 0, 0, 0, 0, 566 }, 567 "Pentium Pro compatible", /* Default */ 568 NULL, 569 NULL, 570 NULL, 571 } } 572 }, 573 { 574 "CentaurHauls", 575 CPUVENDOR_IDT, 576 "IDT", 577 /* Family 4, IDT never had any of these */ 578 { { 579 CPUCLASS_486, 580 { 581 0, 0, 0, 0, 0, 0, 0, 0, 582 0, 0, 0, 0, 0, 0, 0, 0, 583 }, 584 "486 compatible", /* Default */ 585 NULL, 586 NULL, 587 NULL, 588 }, 589 /* Family 5 */ 590 { 591 CPUCLASS_586, 592 { 593 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 594 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 595 }, 596 "WinChip", /* Default */ 597 winchip_cpu_setup, 598 NULL, 599 NULL, 600 }, 601 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 602 { 603 CPUCLASS_686, 604 { 605 0, 0, 0, 0, 0, 0, "C3 Samuel", 606 "C3 Samuel 2/Ezra", "C3 Ezra-T", 607 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 608 0, "VIA Nano", 609 }, 610 "Unknown VIA/IDT", /* Default */ 611 NULL, 612 via_cpu_probe, 613 via_cpu_cacheinfo, 614 }, 615 /* Family > 6, not yet available from VIA */ 616 { 617 CPUCLASS_686, 618 { 619 0, 0, 0, 0, 0, 0, 0, 0, 620 0, 0, 0, 0, 0, 0, 0, 0, 621 }, 622 "Pentium Pro compatible", /* Default */ 623 NULL, 624 NULL, 625 NULL, 626 } } 627 }, 628 { 629 "GenuineTMx86", 630 CPUVENDOR_TRANSMETA, 631 "Transmeta", 632 /* Family 4, Transmeta never had any of these */ 633 { { 634 CPUCLASS_486, 635 { 636 0, 0, 0, 0, 0, 0, 0, 0, 637 0, 0, 0, 0, 0, 0, 0, 0, 638 }, 639 "486 compatible", /* Default */ 640 NULL, 641 NULL, 642 NULL, 643 }, 644 /* Family 5 */ 645 { 646 CPUCLASS_586, 647 { 648 0, 0, 0, 0, 0, 0, 0, 0, 649 0, 0, 0, 0, 0, 0, 0, 0, 650 }, 651 "Crusoe", /* Default */ 652 NULL, 653 NULL, 654 transmeta_cpu_info, 655 }, 656 /* Family 6, not yet available from Transmeta */ 657 { 658 CPUCLASS_686, 659 { 660 0, 0, 0, 0, 0, 0, 0, 0, 661 0, 0, 0, 0, 0, 0, 0, 0, 662 }, 663 "Pentium Pro compatible", /* Default */ 664 NULL, 665 NULL, 666 NULL, 667 }, 668 /* Family > 6, not yet available from Transmeta */ 669 { 670 CPUCLASS_686, 671 { 672 0, 0, 0, 0, 0, 0, 0, 0, 673 0, 0, 0, 0, 0, 0, 0, 0, 674 }, 675 "Pentium Pro compatible", /* Default */ 676 NULL, 677 NULL, 678 NULL, 679 } } 680 } 681 }; 682 683 /* 684 * disable the TSC such that we don't use the TSC in microtime(9) 685 * because some CPUs got the implementation wrong. 686 */ 687 static void 688 disable_tsc(struct cpu_info *ci) 689 { 690 if (ci->ci_feat_val[0] & CPUID_TSC) { 691 ci->ci_feat_val[0] &= ~CPUID_TSC; 692 aprint_error("WARNING: broken TSC disabled\n"); 693 } 694 } 695 696 static void 697 amd_family5_setup(struct cpu_info *ci) 698 { 699 700 switch (ci->ci_model) { 701 case 0: /* AMD-K5 Model 0 */ 702 /* 703 * According to the AMD Processor Recognition App Note, 704 * the AMD-K5 Model 0 uses the wrong bit to indicate 705 * support for global PTEs, instead using bit 9 (APIC) 706 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 707 */ 708 if (ci->ci_feat_val[0] & CPUID_APIC) 709 ci->ci_feat_val[0] = 710 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 711 /* 712 * XXX But pmap_pg_g is already initialized -- need to kick 713 * XXX the pmap somehow. How does the MP branch do this? 714 */ 715 break; 716 } 717 } 718 719 static void 720 cyrix6x86_cpu_setup(struct cpu_info *ci) 721 { 722 723 /* 724 * Do not disable the TSC on the Geode GX, it's reported to 725 * work fine. 726 */ 727 if (ci->ci_signature != 0x552) 728 disable_tsc(ci); 729 } 730 731 static void 732 winchip_cpu_setup(struct cpu_info *ci) 733 { 734 switch (ci->ci_model) { 735 case 4: /* WinChip C6 */ 736 disable_tsc(ci); 737 } 738 } 739 740 741 static const char * 742 intel_family6_name(struct cpu_info *ci) 743 { 744 const char *ret = NULL; 745 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 746 747 if (ci->ci_model == 5) { 748 switch (l2cache) { 749 case 0: 750 case 128 * 1024: 751 ret = "Celeron (Covington)"; 752 break; 753 case 256 * 1024: 754 ret = "Mobile Pentium II (Dixon)"; 755 break; 756 case 512 * 1024: 757 ret = "Pentium II"; 758 break; 759 case 1 * 1024 * 1024: 760 case 2 * 1024 * 1024: 761 ret = "Pentium II Xeon"; 762 break; 763 } 764 } else if (ci->ci_model == 6) { 765 switch (l2cache) { 766 case 256 * 1024: 767 case 512 * 1024: 768 ret = "Mobile Pentium II"; 769 break; 770 } 771 } else if (ci->ci_model == 7) { 772 switch (l2cache) { 773 case 512 * 1024: 774 ret = "Pentium III"; 775 break; 776 case 1 * 1024 * 1024: 777 case 2 * 1024 * 1024: 778 ret = "Pentium III Xeon"; 779 break; 780 } 781 } else if (ci->ci_model >= 8) { 782 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 783 switch (ci->ci_brand_id) { 784 case 0x3: 785 if (ci->ci_signature == 0x6B1) 786 ret = "Celeron"; 787 break; 788 case 0x8: 789 if (ci->ci_signature >= 0xF13) 790 ret = "genuine processor"; 791 break; 792 case 0xB: 793 if (ci->ci_signature >= 0xF13) 794 ret = "Xeon MP"; 795 break; 796 case 0xE: 797 if (ci->ci_signature < 0xF13) 798 ret = "Xeon"; 799 break; 800 } 801 if (ret == NULL) 802 ret = i386_intel_brand[ci->ci_brand_id]; 803 } 804 } 805 806 return ret; 807 } 808 809 /* 810 * Identify AMD64 CPU names from cpuid. 811 * 812 * Based on: 813 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 814 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 815 * "Revision Guide for AMD NPT Family 0Fh Processors" 816 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 817 * and other miscellaneous reports. 818 * 819 * This is all rather pointless, these are cross 'brand' since the raw 820 * silicon is shared. 821 */ 822 static const char * 823 amd_amd64_name(struct cpu_info *ci) 824 { 825 static char family_str[32]; 826 827 /* Only called if family >= 15 */ 828 829 switch (ci->ci_family) { 830 case 15: 831 switch (ci->ci_model) { 832 case 0x21: /* rev JH-E1/E6 */ 833 case 0x41: /* rev JH-F2 */ 834 return "Dual-Core Opteron"; 835 case 0x23: /* rev JH-E6 (Toledo) */ 836 return "Dual-Core Opteron or Athlon 64 X2"; 837 case 0x43: /* rev JH-F2 (Windsor) */ 838 return "Athlon 64 FX or Athlon 64 X2"; 839 case 0x24: /* rev SH-E5 (Lancaster?) */ 840 return "Mobile Athlon 64 or Turion 64"; 841 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 842 return "Opteron or Athlon 64 FX"; 843 case 0x15: /* rev SH-D0 */ 844 case 0x25: /* rev SH-E4 */ 845 return "Opteron"; 846 case 0x27: /* rev DH-E4, SH-E4 */ 847 return "Athlon 64 or Athlon 64 FX or Opteron"; 848 case 0x48: /* rev BH-F2 */ 849 return "Turion 64 X2"; 850 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 851 case 0x07: /* rev SH-CG (ClawHammer) */ 852 case 0x0b: /* rev CH-CG */ 853 case 0x14: /* rev SH-D0 */ 854 case 0x17: /* rev SH-D0 */ 855 case 0x1b: /* rev CH-D0 */ 856 return "Athlon 64"; 857 case 0x2b: /* rev BH-E4 (Manchester) */ 858 case 0x4b: /* rev BH-F2 (Windsor) */ 859 return "Athlon 64 X2"; 860 case 0x6b: /* rev BH-G1 (Brisbane) */ 861 return "Athlon X2 or Athlon 64 X2"; 862 case 0x08: /* rev CH-CG */ 863 case 0x0c: /* rev DH-CG (Newcastle) */ 864 case 0x0e: /* rev DH-CG (Newcastle?) */ 865 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 866 case 0x18: /* rev CH-D0 */ 867 case 0x1c: /* rev DH-D0 (Winchester) */ 868 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 869 case 0x2c: /* rev DH-E3/E6 */ 870 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 871 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 872 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 873 case 0x6f: /* rev DH-G1 */ 874 return "Athlon 64 or Sempron"; 875 default: 876 break; 877 } 878 return "Unknown AMD64 CPU"; 879 880 #if 0 881 case 16: 882 return "Family 10h"; 883 case 17: 884 return "Family 11h"; 885 case 18: 886 return "Family 12h"; 887 case 19: 888 return "Family 14h"; 889 case 20: 890 return "Family 15h"; 891 #endif 892 893 default: 894 break; 895 } 896 897 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 898 return family_str; 899 } 900 901 static void 902 intel_family_new_probe(struct cpu_info *ci) 903 { 904 uint32_t descs[4]; 905 906 x86_cpuid(0x80000000, descs); 907 908 /* 909 * Determine extended feature flags. 910 */ 911 if (descs[0] >= 0x80000001) { 912 x86_cpuid(0x80000001, descs); 913 ci->ci_feat_val[2] |= descs[3]; 914 ci->ci_feat_val[3] |= descs[2]; 915 } 916 } 917 918 static void 919 via_cpu_probe(struct cpu_info *ci) 920 { 921 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 922 u_int descs[4]; 923 u_int lfunc; 924 925 /* 926 * Determine the largest extended function value. 927 */ 928 x86_cpuid(0x80000000, descs); 929 lfunc = descs[0]; 930 931 /* 932 * Determine the extended feature flags. 933 */ 934 if (lfunc >= 0x80000001) { 935 x86_cpuid(0x80000001, descs); 936 ci->ci_feat_val[2] |= descs[3]; 937 } 938 939 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 940 return; 941 942 /* Nehemiah or Esther */ 943 x86_cpuid(0xc0000000, descs); 944 lfunc = descs[0]; 945 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 946 return; 947 948 x86_cpuid(0xc0000001, descs); 949 lfunc = descs[3]; 950 ci->ci_feat_val[4] = lfunc; 951 } 952 953 static void 954 amd_family6_probe(struct cpu_info *ci) 955 { 956 uint32_t descs[4]; 957 char *p; 958 size_t i; 959 960 x86_cpuid(0x80000000, descs); 961 962 /* 963 * Determine the extended feature flags. 964 */ 965 if (descs[0] >= 0x80000001) { 966 x86_cpuid(0x80000001, descs); 967 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 968 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 969 } 970 971 if (*cpu_brand_string == '\0') 972 return; 973 974 for (i = 1; i < __arraycount(amd_brand); i++) 975 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 976 ci->ci_brand_id = i; 977 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 978 break; 979 } 980 } 981 982 static void 983 intel_cpu_cacheinfo(struct cpu_info *ci) 984 { 985 const struct x86_cache_info *cai; 986 u_int descs[4]; 987 int iterations, i, j; 988 int type, level; 989 int ways, partitions, linesize, sets; 990 int caitype = -1; 991 int totalsize; 992 uint8_t desc; 993 994 /* Return if the cpu is old pre-cpuid instruction cpu */ 995 if (ci->ci_cpu_type >= 0) 996 return; 997 998 if (ci->ci_cpuid_level < 2) 999 return; 1000 1001 /* 1002 * Parse the cache info from `cpuid leaf 2', if we have it. 1003 * XXX This is kinda ugly, but hey, so is the architecture... 1004 */ 1005 x86_cpuid(2, descs); 1006 iterations = descs[0] & 0xff; 1007 while (iterations-- > 0) { 1008 for (i = 0; i < 4; i++) { 1009 if (descs[i] & 0x80000000) 1010 continue; 1011 for (j = 0; j < 4; j++) { 1012 /* 1013 * The least significant byte in EAX 1014 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1015 * it should be ignored. 1016 */ 1017 if (i == 0 && j == 0) 1018 continue; 1019 desc = (descs[i] >> (j * 8)) & 0xff; 1020 if (desc == 0) 1021 continue; 1022 cai = cache_info_lookup(intel_cpuid_cache_info, 1023 desc); 1024 if (cai != NULL) 1025 ci->ci_cinfo[cai->cai_index] = *cai; 1026 else if ((verbose != 0) && (desc != 0xff)) 1027 printf("Unknown cacheinfo desc %02x\n", 1028 desc); 1029 } 1030 } 1031 x86_cpuid(2, descs); 1032 } 1033 1034 if (ci->ci_cpuid_level < 4) 1035 return; 1036 1037 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1038 for (i = 0; ; i++) { 1039 x86_cpuid2(4, i, descs); 1040 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1041 if (type == CPUID_DCP_CACHETYPE_N) 1042 break; 1043 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1044 switch (level) { 1045 case 1: 1046 if (type == CPUID_DCP_CACHETYPE_I) 1047 caitype = CAI_ICACHE; 1048 else if (type == CPUID_DCP_CACHETYPE_D) 1049 caitype = CAI_DCACHE; 1050 else 1051 caitype = -1; 1052 break; 1053 case 2: 1054 if (type == CPUID_DCP_CACHETYPE_U) 1055 caitype = CAI_L2CACHE; 1056 else 1057 caitype = -1; 1058 break; 1059 case 3: 1060 if (type == CPUID_DCP_CACHETYPE_U) 1061 caitype = CAI_L3CACHE; 1062 else 1063 caitype = -1; 1064 break; 1065 default: 1066 caitype = -1; 1067 break; 1068 } 1069 if (caitype == -1) { 1070 printf("unknown cache level&type (%d & %d)\n", 1071 level, type); 1072 continue; 1073 } 1074 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1075 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1076 + 1; 1077 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1078 + 1; 1079 sets = descs[2] + 1; 1080 totalsize = ways * partitions * linesize * sets; 1081 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1082 ci->ci_cinfo[caitype].cai_associativity = ways; 1083 ci->ci_cinfo[caitype].cai_linesize = linesize; 1084 } 1085 } 1086 1087 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1088 AMD_L2CACHE_INFO; 1089 1090 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1091 AMD_L3CACHE_INFO; 1092 1093 static void 1094 amd_cpu_cacheinfo(struct cpu_info *ci) 1095 { 1096 const struct x86_cache_info *cp; 1097 struct x86_cache_info *cai; 1098 u_int descs[4]; 1099 u_int lfunc; 1100 1101 /* 1102 * K5 model 0 has none of this info. 1103 */ 1104 if (ci->ci_family == 5 && ci->ci_model == 0) 1105 return; 1106 1107 /* 1108 * Determine the largest extended function value. 1109 */ 1110 x86_cpuid(0x80000000, descs); 1111 lfunc = descs[0]; 1112 1113 /* 1114 * Determine L1 cache/TLB info. 1115 */ 1116 if (lfunc < 0x80000005) { 1117 /* No L1 cache info available. */ 1118 return; 1119 } 1120 1121 x86_cpuid(0x80000005, descs); 1122 1123 /* 1124 * K6-III and higher have large page TLBs. 1125 */ 1126 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1127 cai = &ci->ci_cinfo[CAI_ITLB2]; 1128 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1129 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1130 cai->cai_linesize = largepagesize; 1131 1132 cai = &ci->ci_cinfo[CAI_DTLB2]; 1133 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1134 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1135 cai->cai_linesize = largepagesize; 1136 } 1137 1138 cai = &ci->ci_cinfo[CAI_ITLB]; 1139 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1140 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1141 cai->cai_linesize = (4 * 1024); 1142 1143 cai = &ci->ci_cinfo[CAI_DTLB]; 1144 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1145 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1146 cai->cai_linesize = (4 * 1024); 1147 1148 cai = &ci->ci_cinfo[CAI_DCACHE]; 1149 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1150 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1151 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1152 1153 cai = &ci->ci_cinfo[CAI_ICACHE]; 1154 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1155 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1156 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1157 1158 /* 1159 * Determine L2 cache/TLB info. 1160 */ 1161 if (lfunc < 0x80000006) { 1162 /* No L2 cache info available. */ 1163 return; 1164 } 1165 1166 x86_cpuid(0x80000006, descs); 1167 1168 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1169 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1170 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1171 cai->cai_linesize = (4 * 1024); 1172 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1173 cai->cai_associativity); 1174 if (cp != NULL) 1175 cai->cai_associativity = cp->cai_associativity; 1176 else 1177 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1178 1179 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1180 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1181 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1182 cai->cai_linesize = largepagesize; 1183 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1184 cai->cai_associativity); 1185 if (cp != NULL) 1186 cai->cai_associativity = cp->cai_associativity; 1187 else 1188 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1189 1190 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1191 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1192 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1193 cai->cai_linesize = (4 * 1024); 1194 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1195 cai->cai_associativity); 1196 if (cp != NULL) 1197 cai->cai_associativity = cp->cai_associativity; 1198 else 1199 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1200 1201 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1202 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1203 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1204 cai->cai_linesize = largepagesize; 1205 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1206 cai->cai_associativity); 1207 if (cp != NULL) 1208 cai->cai_associativity = cp->cai_associativity; 1209 else 1210 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1211 1212 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1213 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1214 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1215 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1216 1217 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1218 cai->cai_associativity); 1219 if (cp != NULL) 1220 cai->cai_associativity = cp->cai_associativity; 1221 else 1222 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1223 1224 /* 1225 * Determine L3 cache info on AMD Family 10h and newer processors 1226 */ 1227 if (ci->ci_family >= 0x10) { 1228 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1229 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1230 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1231 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1232 1233 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1234 cai->cai_associativity); 1235 if (cp != NULL) 1236 cai->cai_associativity = cp->cai_associativity; 1237 else 1238 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1239 } 1240 1241 /* 1242 * Determine 1GB TLB info. 1243 */ 1244 if (lfunc < 0x80000019) { 1245 /* No 1GB TLB info available. */ 1246 return; 1247 } 1248 1249 x86_cpuid(0x80000019, descs); 1250 1251 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1252 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1253 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1254 cai->cai_linesize = (1024 * 1024 * 1024); 1255 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1256 cai->cai_associativity); 1257 if (cp != NULL) 1258 cai->cai_associativity = cp->cai_associativity; 1259 else 1260 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1261 1262 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1263 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1264 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1265 cai->cai_linesize = (1024 * 1024 * 1024); 1266 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1267 cai->cai_associativity); 1268 if (cp != NULL) 1269 cai->cai_associativity = cp->cai_associativity; 1270 else 1271 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1272 1273 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1274 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1275 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1276 cai->cai_linesize = (1024 * 1024 * 1024); 1277 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1278 cai->cai_associativity); 1279 if (cp != NULL) 1280 cai->cai_associativity = cp->cai_associativity; 1281 else 1282 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1283 1284 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1285 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1286 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1287 cai->cai_linesize = (1024 * 1024 * 1024); 1288 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1289 cai->cai_associativity); 1290 if (cp != NULL) 1291 cai->cai_associativity = cp->cai_associativity; 1292 else 1293 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1294 } 1295 1296 static void 1297 via_cpu_cacheinfo(struct cpu_info *ci) 1298 { 1299 struct x86_cache_info *cai; 1300 int stepping; 1301 u_int descs[4]; 1302 u_int lfunc; 1303 1304 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1305 1306 /* 1307 * Determine the largest extended function value. 1308 */ 1309 x86_cpuid(0x80000000, descs); 1310 lfunc = descs[0]; 1311 1312 /* 1313 * Determine L1 cache/TLB info. 1314 */ 1315 if (lfunc < 0x80000005) { 1316 /* No L1 cache info available. */ 1317 return; 1318 } 1319 1320 x86_cpuid(0x80000005, descs); 1321 1322 cai = &ci->ci_cinfo[CAI_ITLB]; 1323 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1324 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1325 cai->cai_linesize = (4 * 1024); 1326 1327 cai = &ci->ci_cinfo[CAI_DTLB]; 1328 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1329 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1330 cai->cai_linesize = (4 * 1024); 1331 1332 cai = &ci->ci_cinfo[CAI_DCACHE]; 1333 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1334 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1335 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1336 if (ci->ci_model == 9 && stepping == 8) { 1337 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1338 cai->cai_associativity = 2; 1339 } 1340 1341 cai = &ci->ci_cinfo[CAI_ICACHE]; 1342 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1343 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1344 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1345 if (ci->ci_model == 9 && stepping == 8) { 1346 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1347 cai->cai_associativity = 2; 1348 } 1349 1350 /* 1351 * Determine L2 cache/TLB info. 1352 */ 1353 if (lfunc < 0x80000006) { 1354 /* No L2 cache info available. */ 1355 return; 1356 } 1357 1358 x86_cpuid(0x80000006, descs); 1359 1360 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1361 if (ci->ci_model >= 9) { 1362 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1363 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1364 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1365 } else { 1366 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1367 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1368 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1369 } 1370 } 1371 1372 static void 1373 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1374 { 1375 u_int descs[4]; 1376 1377 x86_cpuid(0x80860007, descs); 1378 *frequency = descs[0]; 1379 *voltage = descs[1]; 1380 *percentage = descs[2]; 1381 } 1382 1383 static void 1384 transmeta_cpu_info(struct cpu_info *ci) 1385 { 1386 u_int descs[4], nreg; 1387 u_int frequency, voltage, percentage; 1388 1389 x86_cpuid(0x80860000, descs); 1390 nreg = descs[0]; 1391 if (nreg >= 0x80860001) { 1392 x86_cpuid(0x80860001, descs); 1393 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1394 (descs[1] >> 24) & 0xff, 1395 (descs[1] >> 16) & 0xff, 1396 (descs[1] >> 8) & 0xff, 1397 descs[1] & 0xff); 1398 } 1399 if (nreg >= 0x80860002) { 1400 x86_cpuid(0x80860002, descs); 1401 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1402 (descs[1] >> 24) & 0xff, 1403 (descs[1] >> 16) & 0xff, 1404 (descs[1] >> 8) & 0xff, 1405 descs[1] & 0xff, 1406 descs[2]); 1407 } 1408 if (nreg >= 0x80860006) { 1409 union { 1410 char text[65]; 1411 u_int descs[4][4]; 1412 } info; 1413 int i; 1414 1415 for (i=0; i<4; i++) { 1416 x86_cpuid(0x80860003 + i, info.descs[i]); 1417 } 1418 info.text[64] = '\0'; 1419 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1420 } 1421 1422 if (nreg >= 0x80860007) { 1423 tmx86_get_longrun_status(&frequency, 1424 &voltage, &percentage); 1425 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1426 frequency, voltage, percentage); 1427 } 1428 } 1429 1430 static void 1431 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1432 { 1433 u_int descs[4]; 1434 int i; 1435 uint32_t brand[12]; 1436 1437 memset(ci, 0, sizeof(*ci)); 1438 ci->ci_dev = cpuname; 1439 1440 ci->ci_cpu_type = x86_identify(); 1441 if (ci->ci_cpu_type >= 0) { 1442 /* Old pre-cpuid instruction cpu */ 1443 ci->ci_cpuid_level = -1; 1444 return; 1445 } 1446 1447 /* 1448 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1449 * function. 1450 */ 1451 1452 /* 1453 * Fn0000_0000: 1454 * - Save cpuid max level. 1455 * - Save vendor string. 1456 */ 1457 x86_cpuid(0, descs); 1458 ci->ci_cpuid_level = descs[0]; 1459 /* Save vendor string */ 1460 ci->ci_vendor[0] = descs[1]; 1461 ci->ci_vendor[2] = descs[2]; 1462 ci->ci_vendor[1] = descs[3]; 1463 ci->ci_vendor[3] = 0; 1464 1465 /* 1466 * Fn8000_0000: 1467 * - Get cpuid extended function's max level. 1468 */ 1469 x86_cpuid(0x80000000, descs); 1470 if (descs[0] >= 0x80000000) 1471 ci->ci_cpuid_extlevel = descs[0]; 1472 else { 1473 /* Set lower value than 0x80000000 */ 1474 ci->ci_cpuid_extlevel = 0; 1475 } 1476 1477 /* 1478 * Fn8000_000[2-4]: 1479 * - Save brand string. 1480 */ 1481 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1482 x86_cpuid(0x80000002, brand); 1483 x86_cpuid(0x80000003, brand + 4); 1484 x86_cpuid(0x80000004, brand + 8); 1485 for (i = 0; i < 48; i++) 1486 if (((char *) brand)[i] != ' ') 1487 break; 1488 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1489 } 1490 1491 if (ci->ci_cpuid_level < 1) 1492 return; 1493 1494 /* 1495 * Fn0000_0001: 1496 * - Get CPU family, model and stepping (from eax). 1497 * - Initial local APIC ID and brand ID (from ebx) 1498 * - CPUID2 (from ecx) 1499 * - CPUID (from edx) 1500 */ 1501 x86_cpuid(1, descs); 1502 ci->ci_signature = descs[0]; 1503 1504 /* Extract full family/model values */ 1505 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1506 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1507 1508 /* Brand is low order 8 bits of ebx */ 1509 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1510 /* Initial local APIC ID */ 1511 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1512 1513 ci->ci_feat_val[1] = descs[2]; 1514 ci->ci_feat_val[0] = descs[3]; 1515 1516 if (ci->ci_cpuid_level < 3) 1517 return; 1518 1519 /* 1520 * If the processor serial number misfeature is present and supported, 1521 * extract it here. 1522 */ 1523 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1524 ci->ci_cpu_serial[0] = ci->ci_signature; 1525 x86_cpuid(3, descs); 1526 ci->ci_cpu_serial[2] = descs[2]; 1527 ci->ci_cpu_serial[1] = descs[3]; 1528 } 1529 1530 if (ci->ci_cpuid_level < 0x7) 1531 return; 1532 1533 x86_cpuid(7, descs); 1534 ci->ci_feat_val[5] = descs[1]; 1535 ci->ci_feat_val[6] = descs[2]; 1536 1537 if (ci->ci_cpuid_level < 0xd) 1538 return; 1539 1540 /* Get support XCR0 bits */ 1541 x86_cpuid2(0xd, 0, descs); 1542 ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */ 1543 ci->ci_cur_xsave = descs[1]; 1544 ci->ci_max_xsave = descs[2]; 1545 1546 /* Additional flags (eg xsaveopt support) */ 1547 x86_cpuid2(0xd, 1, descs); 1548 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1549 } 1550 1551 static void 1552 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1553 { 1554 uint32_t descs[4]; 1555 char hv_sig[13]; 1556 char *p; 1557 const char *hv_name; 1558 int i; 1559 1560 /* 1561 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1562 * http://lkml.org/lkml/2008/10/1/246 1563 * 1564 * KB1009458: Mechanisms to determine if software is running in 1565 * a VMware virtual machine 1566 * http://kb.vmware.com/kb/1009458 1567 */ 1568 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1569 x86_cpuid(0x40000000, descs); 1570 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1571 memcpy(p, &descs[i], sizeof(descs[i])); 1572 *p = '\0'; 1573 /* 1574 * HV vendor ID string 1575 * ------------+-------------- 1576 * KVM "KVMKVMKVM" 1577 * Microsoft "Microsoft Hv" 1578 * VMware "VMwareVMware" 1579 * Xen "XenVMMXenVMM" 1580 */ 1581 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1582 hv_name = "KVM"; 1583 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1584 hv_name = "Hyper-V"; 1585 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1586 hv_name = "VMware"; 1587 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1588 hv_name = "Xen"; 1589 else 1590 hv_name = "unknown"; 1591 1592 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1593 } 1594 } 1595 1596 static void 1597 cpu_probe_features(struct cpu_info *ci) 1598 { 1599 const struct cpu_cpuid_nameclass *cpup = NULL; 1600 unsigned int i; 1601 1602 if (ci->ci_cpuid_level < 1) 1603 return; 1604 1605 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1606 if (!strncmp((char *)ci->ci_vendor, 1607 i386_cpuid_cpus[i].cpu_id, 12)) { 1608 cpup = &i386_cpuid_cpus[i]; 1609 break; 1610 } 1611 } 1612 1613 if (cpup == NULL) 1614 return; 1615 1616 i = ci->ci_family - CPU_MINFAMILY; 1617 1618 if (i >= __arraycount(cpup->cpu_family)) 1619 i = __arraycount(cpup->cpu_family) - 1; 1620 1621 if (cpup->cpu_family[i].cpu_probe == NULL) 1622 return; 1623 1624 (*cpup->cpu_family[i].cpu_probe)(ci); 1625 } 1626 1627 static void 1628 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1629 { 1630 char buf[32 * 16]; 1631 char *bp; 1632 1633 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1634 1635 if (val == 0 || fmt == NULL) 1636 return; 1637 1638 snprintb_m(buf, sizeof(buf), fmt, val, 1639 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1640 bp = buf; 1641 while (*bp != '\0') { 1642 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1643 bp += strlen(bp) + 1; 1644 } 1645 } 1646 1647 static void 1648 identifycpu_cpuids(struct cpu_info *ci) 1649 { 1650 const char *cpuname = ci->ci_dev; 1651 u_int lp_max = 1; /* logical processors per package */ 1652 u_int smt_max; /* smt per core */ 1653 u_int core_max = 1; /* core per package */ 1654 u_int smt_bits, core_bits; 1655 uint32_t descs[4]; 1656 1657 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1658 ci->ci_packageid = ci->ci_initapicid; 1659 ci->ci_coreid = 0; 1660 ci->ci_smtid = 0; 1661 if (cpu_vendor != CPUVENDOR_INTEL) { 1662 return; 1663 } 1664 1665 /* 1666 * 253668.pdf 7.10.2 1667 */ 1668 1669 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1670 x86_cpuid(1, descs); 1671 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1672 } 1673 if (ci->ci_cpuid_level >= 4) { 1674 x86_cpuid2(4, 0, descs); 1675 core_max = (descs[0] >> 26) + 1; 1676 } 1677 assert(lp_max >= core_max); 1678 smt_max = lp_max / core_max; 1679 smt_bits = ilog2(smt_max - 1) + 1; 1680 core_bits = ilog2(core_max - 1) + 1; 1681 if (smt_bits + core_bits) { 1682 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1683 } 1684 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1685 ci->ci_packageid); 1686 if (core_bits) { 1687 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1688 1689 ci->ci_coreid = 1690 __SHIFTOUT(ci->ci_initapicid, core_mask); 1691 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1692 } 1693 if (smt_bits) { 1694 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1695 1696 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1697 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1698 } 1699 } 1700 1701 void 1702 identifycpu(int fd, const char *cpuname) 1703 { 1704 const char *name = "", *modifier, *vendorname, *brand = ""; 1705 int class = CPUCLASS_386; 1706 unsigned int i; 1707 int modif, family; 1708 const struct cpu_cpuid_nameclass *cpup = NULL; 1709 const struct cpu_cpuid_family *cpufam; 1710 struct cpu_info *ci, cistore; 1711 u_int descs[4]; 1712 size_t sz; 1713 struct cpu_ucode_version ucode; 1714 union { 1715 struct cpu_ucode_version_amd amd; 1716 struct cpu_ucode_version_intel1 intel1; 1717 } ucvers; 1718 1719 ci = &cistore; 1720 cpu_probe_base_features(ci, cpuname); 1721 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1722 ci->ci_cpuid_level); 1723 if (verbose) { 1724 int bf; 1725 1726 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1727 x86_cpuid(bf, descs); 1728 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1729 bf, descs[0], descs[1], descs[2], descs[3]); 1730 } 1731 } 1732 if (ci->ci_cpuid_extlevel >= 0x80000000) 1733 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1734 ci->ci_cpuid_extlevel); 1735 if (verbose) { 1736 unsigned int ef; 1737 1738 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1739 x86_cpuid(ef, descs); 1740 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1741 ef, descs[0], descs[1], descs[2], descs[3]); 1742 } 1743 } 1744 1745 cpu_probe_hv_features(ci, cpuname); 1746 cpu_probe_features(ci); 1747 1748 if (ci->ci_cpu_type >= 0) { 1749 /* Old pre-cpuid instruction cpu */ 1750 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1751 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1752 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1753 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1754 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1755 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1756 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1757 modifier = ""; 1758 } else { 1759 /* CPU which support cpuid instruction */ 1760 modif = (ci->ci_signature >> 12) & 0x3; 1761 family = ci->ci_family; 1762 if (family < CPU_MINFAMILY) 1763 errx(1, "identifycpu: strange family value"); 1764 if (family > CPU_MAXFAMILY) 1765 family = CPU_MAXFAMILY; 1766 1767 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1768 if (!strncmp((char *)ci->ci_vendor, 1769 i386_cpuid_cpus[i].cpu_id, 12)) { 1770 cpup = &i386_cpuid_cpus[i]; 1771 break; 1772 } 1773 } 1774 1775 if (cpup == NULL) { 1776 cpu_vendor = CPUVENDOR_UNKNOWN; 1777 if (ci->ci_vendor[0] != '\0') 1778 vendorname = (char *)&ci->ci_vendor[0]; 1779 else 1780 vendorname = "Unknown"; 1781 class = family - 3; 1782 modifier = ""; 1783 name = ""; 1784 ci->ci_info = NULL; 1785 } else { 1786 cpu_vendor = cpup->cpu_vendor; 1787 vendorname = cpup->cpu_vendorname; 1788 modifier = modifiers[modif]; 1789 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1790 name = cpufam->cpu_models[ci->ci_model]; 1791 if (name == NULL || *name == '\0') 1792 name = cpufam->cpu_model_default; 1793 class = cpufam->cpu_class; 1794 ci->ci_info = cpufam->cpu_info; 1795 1796 if (cpu_vendor == CPUVENDOR_INTEL) { 1797 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1798 const char *tmp; 1799 tmp = intel_family6_name(ci); 1800 if (tmp != NULL) 1801 name = tmp; 1802 } 1803 if (ci->ci_family == 15 && 1804 ci->ci_brand_id < 1805 __arraycount(i386_intel_brand) && 1806 i386_intel_brand[ci->ci_brand_id]) 1807 name = 1808 i386_intel_brand[ci->ci_brand_id]; 1809 } 1810 1811 if (cpu_vendor == CPUVENDOR_AMD) { 1812 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1813 if (ci->ci_brand_id == 1) 1814 /* 1815 * It's Duron. We override the 1816 * name, since it might have 1817 * been misidentified as Athlon. 1818 */ 1819 name = 1820 amd_brand[ci->ci_brand_id]; 1821 else 1822 brand = amd_brand_name; 1823 } 1824 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1825 == 0xf) { 1826 /* Identify AMD64 CPU names. */ 1827 const char *tmp; 1828 tmp = amd_amd64_name(ci); 1829 if (tmp != NULL) 1830 name = tmp; 1831 } 1832 } 1833 1834 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1835 vendorname = "VIA"; 1836 } 1837 } 1838 1839 ci->ci_cpu_class = class; 1840 1841 sz = sizeof(ci->ci_tsc_freq); 1842 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1843 sz = sizeof(use_pae); 1844 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1845 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1846 1847 /* 1848 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1849 * we try to determine from the family/model values. 1850 */ 1851 if (*cpu_brand_string != '\0') 1852 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1853 1854 aprint_normal("%s: %s", cpuname, vendorname); 1855 if (*modifier) 1856 aprint_normal(" %s", modifier); 1857 if (*name) 1858 aprint_normal(" %s", name); 1859 if (*brand) 1860 aprint_normal(" %s", brand); 1861 aprint_normal(" (%s-class)", classnames[class]); 1862 1863 if (ci->ci_tsc_freq != 0) 1864 aprint_normal(", %ju.%02ju MHz", 1865 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1866 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1867 aprint_normal("\n"); 1868 1869 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1870 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1871 if (ci->ci_signature != 0) 1872 aprint_normal(" (id %#x)", ci->ci_signature); 1873 aprint_normal("\n"); 1874 1875 if (ci->ci_info) 1876 (*ci->ci_info)(ci); 1877 1878 /* 1879 * display CPU feature flags 1880 */ 1881 1882 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1883 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1884 1885 /* These next two are actually common definitions! */ 1886 print_bits(cpuname, "features2", 1887 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1888 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1889 print_bits(cpuname, "features3", 1890 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1891 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1892 1893 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1894 ci->ci_feat_val[4]); 1895 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 1896 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 1897 ci->ci_feat_val[5]); 1898 if (cpu_vendor == CPUVENDOR_INTEL) 1899 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 1900 ci->ci_feat_val[6]); 1901 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]); 1902 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1903 ci->ci_feat_val[8]); 1904 1905 if (ci->ci_max_xsave != 0) { 1906 aprint_normal("%s: xsave area size: current %d, maximum %d", 1907 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1908 aprint_normal(", xgetbv %sabled\n", 1909 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1910 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1911 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1912 x86_xgetbv()); 1913 } 1914 1915 x86_print_cache_and_tlb_info(ci); 1916 1917 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1918 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1919 cpuname, 1920 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1921 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1922 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1923 } 1924 1925 if (ci->ci_cpu_class == CPUCLASS_386) 1926 errx(1, "NetBSD requires an 80486 or later processor"); 1927 1928 if (ci->ci_cpu_type == CPU_486DLC) { 1929 #ifndef CYRIX_CACHE_WORKS 1930 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1931 #else 1932 #ifndef CYRIX_CACHE_REALLY_WORKS 1933 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1934 #else 1935 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1936 #endif 1937 #endif 1938 } 1939 1940 /* 1941 * Everything past this point requires a Pentium or later. 1942 */ 1943 if (ci->ci_cpuid_level < 0) 1944 return; 1945 1946 identifycpu_cpuids(ci); 1947 1948 #ifdef INTEL_CORETEMP 1949 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1950 coretemp_register(ci); 1951 #endif 1952 1953 if (cpu_vendor == CPUVENDOR_AMD) { 1954 uint32_t data[4]; 1955 1956 x86_cpuid(0x80000000, data); 1957 if (data[0] >= 0x80000007) 1958 powernow_probe(ci); 1959 1960 if ((data[0] >= 0x8000000a) 1961 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1962 x86_cpuid(0x8000000a, data); 1963 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1964 data[0] & 0xf); 1965 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1966 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1967 data[3]); 1968 } 1969 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1970 uint32_t data[4]; 1971 int32_t bi_index; 1972 1973 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 1974 x86_cpuid(bi_index, data); 1975 switch (bi_index) { 1976 case 6: 1977 print_bits(cpuname, "DSPM-eax", 1978 CPUID_DSPM_FLAGS, data[0]); 1979 print_bits(cpuname, "DSPM-ecx", 1980 CPUID_DSPM_FLAGS1, data[2]); 1981 break; 1982 case 7: 1983 aprint_verbose("%s: SEF highest subleaf %08x\n", 1984 cpuname, data[0]); 1985 break; 1986 #if 0 1987 default: 1988 aprint_verbose("%s: basic %08x-eax %08x\n", 1989 cpuname, bi_index, data[0]); 1990 aprint_verbose("%s: basic %08x-ebx %08x\n", 1991 cpuname, bi_index, data[1]); 1992 aprint_verbose("%s: basic %08x-ecx %08x\n", 1993 cpuname, bi_index, data[2]); 1994 aprint_verbose("%s: basic %08x-edx %08x\n", 1995 cpuname, bi_index, data[3]); 1996 break; 1997 #endif 1998 } 1999 } 2000 } 2001 2002 #ifdef INTEL_ONDEMAND_CLOCKMOD 2003 clockmod_init(); 2004 #endif 2005 2006 if (cpu_vendor == CPUVENDOR_AMD) 2007 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2008 else if (cpu_vendor == CPUVENDOR_INTEL) 2009 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2010 else 2011 return; 2012 2013 ucode.data = &ucvers; 2014 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2015 #ifdef __i386__ 2016 struct cpu_ucode_version_64 ucode_64; 2017 if (errno != ENOTTY) 2018 return; 2019 /* Try the 64 bit ioctl */ 2020 memset(&ucode_64, 0, sizeof ucode_64); 2021 ucode_64.data = &ucvers; 2022 ucode_64.loader_version = ucode.loader_version; 2023 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2024 return; 2025 #else 2026 return; 2027 #endif 2028 } 2029 2030 if (cpu_vendor == CPUVENDOR_AMD) 2031 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2032 else if (cpu_vendor == CPUVENDOR_INTEL) 2033 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2034 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2035 } 2036 2037 static const struct x86_cache_info * 2038 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2039 { 2040 int i; 2041 2042 for (i = 0; cai[i].cai_desc != 0; i++) { 2043 if (cai[i].cai_desc == desc) 2044 return (&cai[i]); 2045 } 2046 2047 return (NULL); 2048 } 2049 2050 static const char * 2051 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2052 const char *sep) 2053 { 2054 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2055 char human_num[HUMAN_BUFSIZE]; 2056 2057 if (cai->cai_totalsize == 0) 2058 return sep; 2059 2060 if (sep == NULL) 2061 aprint_verbose_dev(ci->ci_dev, ""); 2062 else 2063 aprint_verbose("%s", sep); 2064 if (name != NULL) 2065 aprint_verbose("%s ", name); 2066 2067 if (cai->cai_string != NULL) { 2068 aprint_verbose("%s ", cai->cai_string); 2069 } else { 2070 (void)humanize_number(human_num, sizeof(human_num), 2071 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2072 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2073 } 2074 switch (cai->cai_associativity) { 2075 case 0: 2076 aprint_verbose("disabled"); 2077 break; 2078 case 1: 2079 aprint_verbose("direct-mapped"); 2080 break; 2081 case 0xff: 2082 aprint_verbose("fully associative"); 2083 break; 2084 default: 2085 aprint_verbose("%d-way", cai->cai_associativity); 2086 break; 2087 } 2088 return ", "; 2089 } 2090 2091 static const char * 2092 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2093 const char *sep) 2094 { 2095 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2096 char human_num[HUMAN_BUFSIZE]; 2097 2098 if (cai->cai_totalsize == 0) 2099 return sep; 2100 2101 if (sep == NULL) 2102 aprint_verbose_dev(ci->ci_dev, ""); 2103 else 2104 aprint_verbose("%s", sep); 2105 if (name != NULL) 2106 aprint_verbose("%s ", name); 2107 2108 if (cai->cai_string != NULL) { 2109 aprint_verbose("%s", cai->cai_string); 2110 } else { 2111 (void)humanize_number(human_num, sizeof(human_num), 2112 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2113 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2114 human_num); 2115 switch (cai->cai_associativity) { 2116 case 0: 2117 aprint_verbose("disabled"); 2118 break; 2119 case 1: 2120 aprint_verbose("direct-mapped"); 2121 break; 2122 case 0xff: 2123 aprint_verbose("fully associative"); 2124 break; 2125 default: 2126 aprint_verbose("%d-way", cai->cai_associativity); 2127 break; 2128 } 2129 } 2130 return ", "; 2131 } 2132 2133 static void 2134 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2135 { 2136 const char *sep = NULL; 2137 2138 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2139 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2140 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2141 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2142 if (sep != NULL) 2143 aprint_verbose("\n"); 2144 } 2145 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2146 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2147 if (sep != NULL) 2148 aprint_verbose("\n"); 2149 } 2150 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2151 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2152 if (sep != NULL) 2153 aprint_verbose("\n"); 2154 } 2155 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2156 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2157 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2158 if (sep != NULL) 2159 aprint_verbose("\n"); 2160 } 2161 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2162 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2163 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2164 if (sep != NULL) 2165 aprint_verbose("\n"); 2166 } 2167 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2168 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2169 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2170 if (sep != NULL) 2171 aprint_verbose("\n"); 2172 } 2173 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2174 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2175 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2176 if (sep != NULL) 2177 aprint_verbose("\n"); 2178 } 2179 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2180 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2181 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2182 if (sep != NULL) 2183 aprint_verbose("\n"); 2184 } 2185 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2186 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2187 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2188 if (sep != NULL) 2189 aprint_verbose("\n"); 2190 } 2191 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2192 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2193 NULL); 2194 if (sep != NULL) 2195 aprint_verbose("\n"); 2196 } 2197 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2198 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2199 NULL); 2200 if (sep != NULL) 2201 aprint_verbose("\n"); 2202 } 2203 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2204 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2205 NULL); 2206 if (sep != NULL) 2207 aprint_verbose("\n"); 2208 } 2209 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2210 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2211 NULL); 2212 if (sep != NULL) 2213 aprint_verbose("\n"); 2214 } 2215 } 2216 2217 static void 2218 powernow_probe(struct cpu_info *ci) 2219 { 2220 uint32_t regs[4]; 2221 char buf[256]; 2222 2223 x86_cpuid(0x80000007, regs); 2224 2225 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2226 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2227 buf); 2228 } 2229 2230 int 2231 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2232 { 2233 struct cpu_info ci; 2234 int loader_version, res; 2235 struct cpu_ucode_version versreq; 2236 2237 cpu_probe_base_features(&ci, "unknown"); 2238 2239 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2240 loader_version = CPU_UCODE_LOADER_AMD; 2241 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2242 loader_version = CPU_UCODE_LOADER_INTEL1; 2243 else 2244 return -1; 2245 2246 /* check whether the kernel understands this loader version */ 2247 versreq.loader_version = loader_version; 2248 versreq.data = 0; 2249 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2250 if (res) 2251 return -1; 2252 2253 switch (loader_version) { 2254 case CPU_UCODE_LOADER_AMD: 2255 if (uc->cpu_nr != -1) { 2256 /* printf? */ 2257 return -1; 2258 } 2259 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2260 break; 2261 case CPU_UCODE_LOADER_INTEL1: 2262 if (uc->cpu_nr == -1) 2263 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2264 else 2265 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2266 break; 2267 default: /* can't happen */ 2268 return -1; 2269 } 2270 uc->loader_version = loader_version; 2271 return 0; 2272 } 2273
Indexes created Sat Sep 27 14:09:57 GMT 2025