i386.c revision 1.81
1 /* $NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.81 2018/03/05 05:50:37 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[9]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] XCR0 bits (d:0 %eax) 110 * [8] xsave flags (d:1 %eax) 111 */ 112 uint32_t ci_cpu_class; /* CPU class */ 113 uint32_t ci_brand_id; /* Intel brand id */ 114 uint32_t ci_vendor[4]; /* vendor string */ 115 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 116 uint64_t ci_tsc_freq; /* cpu cycles/second */ 117 uint8_t ci_packageid; 118 uint8_t ci_coreid; 119 uint8_t ci_smtid; 120 uint32_t ci_initapicid; 121 122 uint32_t ci_cur_xsave; 123 uint32_t ci_max_xsave; 124 125 struct x86_cache_info ci_cinfo[CAI_COUNT]; 126 void (*ci_info)(struct cpu_info *); 127 }; 128 129 struct cpu_nocpuid_nameclass { 130 int cpu_vendor; 131 const char *cpu_vendorname; 132 const char *cpu_name; 133 int cpu_class; 134 void (*cpu_setup)(struct cpu_info *); 135 void (*cpu_cacheinfo)(struct cpu_info *); 136 void (*cpu_info)(struct cpu_info *); 137 }; 138 139 struct cpu_cpuid_nameclass { 140 const char *cpu_id; 141 int cpu_vendor; 142 const char *cpu_vendorname; 143 struct cpu_cpuid_family { 144 int cpu_class; 145 const char *cpu_models[256]; 146 const char *cpu_model_default; 147 void (*cpu_setup)(struct cpu_info *); 148 void (*cpu_probe)(struct cpu_info *); 149 void (*cpu_info)(struct cpu_info *); 150 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 151 }; 152 153 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 154 155 /* 156 * Map Brand ID from cpuid instruction to brand name. 157 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 158 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 159 * Architectures Software Developer's Manual, Volume 2A". 160 */ 161 static const char * const i386_intel_brand[] = { 162 "", /* Unsupported */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "", /* 0x05: Reserved */ 168 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Celeron", /* Intel (R) Celeron (TM) processor */ 173 "Xeon", /* Intel (R) Xeon (TM) processor */ 174 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 175 "", /* 0x0d: Reserved */ 176 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 177 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 178 "", /* 0x10: Reserved */ 179 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 180 "Celeron M", /* Intel (R) Celeron (R) M processor */ 181 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 182 "Celeron", /* Intel (R) Celeron (R) processor */ 183 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 184 "Pentium M", /* Intel (R) Pentium (R) M processor */ 185 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 186 }; 187 188 /* 189 * AMD processors don't have Brand IDs, so we need these names for probe. 190 */ 191 static const char * const amd_brand[] = { 192 "", 193 "Duron", /* AMD Duron(tm) */ 194 "MP", /* AMD Athlon(tm) MP */ 195 "XP", /* AMD Athlon(tm) XP */ 196 "4" /* AMD Athlon(tm) 4 */ 197 }; 198 199 static int cpu_vendor; 200 static char cpu_brand_string[49]; 201 static char amd_brand_name[48]; 202 static int use_pae, largepagesize; 203 204 /* Setup functions */ 205 static void disable_tsc(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 /* Brand/Model name functions */ 210 static const char *intel_family6_name(struct cpu_info *); 211 static const char *amd_amd64_name(struct cpu_info *); 212 /* Probe functions */ 213 static void amd_family6_probe(struct cpu_info *); 214 static void powernow_probe(struct cpu_info *); 215 static void intel_family_new_probe(struct cpu_info *); 216 static void via_cpu_probe(struct cpu_info *); 217 /* (Cache) Info functions */ 218 static void intel_cpu_cacheinfo(struct cpu_info *); 219 static void amd_cpu_cacheinfo(struct cpu_info *); 220 static void via_cpu_cacheinfo(struct cpu_info *); 221 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 222 static void transmeta_cpu_info(struct cpu_info *); 223 /* Common functions */ 224 static void cpu_probe_base_features(struct cpu_info *, const char *); 225 static void cpu_probe_hv_features(struct cpu_info *, const char *); 226 static void cpu_probe_features(struct cpu_info *); 227 static void print_bits(const char *, const char *, const char *, uint32_t); 228 static void identifycpu_cpuids(struct cpu_info *); 229 static const struct x86_cache_info *cache_info_lookup( 230 const struct x86_cache_info *, uint8_t); 231 static const char *print_cache_config(struct cpu_info *, int, const char *, 232 const char *); 233 static const char *print_tlb_config(struct cpu_info *, int, const char *, 234 const char *); 235 static void x86_print_cache_and_tlb_info(struct cpu_info *); 236 237 /* 238 * Note: these are just the ones that may not have a cpuid instruction. 239 * We deal with the rest in a different way. 240 */ 241 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 242 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386SX */ 244 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386 */ 246 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486SX */ 248 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486 */ 250 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486DLC */ 252 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_6x86 */ 254 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 255 NULL, NULL, NULL }, /* CPU_NX586 */ 256 }; 257 258 const char *classnames[] = { 259 "386", 260 "486", 261 "586", 262 "686" 263 }; 264 265 const char *modifiers[] = { 266 "", 267 "OverDrive", 268 "Dual", 269 "" 270 }; 271 272 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 273 { 274 /* 275 * For Intel processors, check Chapter 35Model-specific 276 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 277 * Software Developer's Manual, Volume 3C". 278 */ 279 "GenuineIntel", 280 CPUVENDOR_INTEL, 281 "Intel", 282 /* Family 4 */ 283 { { 284 CPUCLASS_486, 285 { 286 "486DX", "486DX", "486SX", "486DX2", "486SL", 287 "486SX2", 0, "486DX2 W/B Enhanced", 288 "486DX4", 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "486", /* Default */ 291 NULL, 292 NULL, 293 intel_cpu_cacheinfo, 294 }, 295 /* Family 5 */ 296 { 297 CPUCLASS_586, 298 { 299 "Pentium (P5 A-step)", "Pentium (P5)", 300 "Pentium (P54C)", "Pentium (P24T)", 301 "Pentium/MMX", "Pentium", 0, 302 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 303 "Quark X1000", 0, 0, 0, 0, 0, 0, 304 }, 305 "Pentium", /* Default */ 306 NULL, 307 NULL, 308 intel_cpu_cacheinfo, 309 }, 310 /* Family 6 */ 311 { 312 CPUCLASS_686, 313 { 314 [0x00] = "Pentium Pro (A-step)", 315 [0x01] = "Pentium Pro", 316 [0x03] = "Pentium II (Klamath)", 317 [0x04] = "Pentium Pro", 318 [0x05] = "Pentium II/Celeron (Deschutes)", 319 [0x06] = "Celeron (Mendocino)", 320 [0x07] = "Pentium III (Katmai)", 321 [0x08] = "Pentium III (Coppermine)", 322 [0x09] = "Pentium M (Banias)", 323 [0x0a] = "Pentium III Xeon (Cascades)", 324 [0x0b] = "Pentium III (Tualatin)", 325 [0x0d] = "Pentium M (Dothan)", 326 [0x0e] = "Pentium Core Duo, Core solo", 327 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 328 "Core 2 Quad 6xxx, " 329 "Core 2 Extreme 6xxx, " 330 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 331 "and Pentium DC", 332 [0x15] = "EP80579 Integrated Processor", 333 [0x16] = "Celeron (45nm)", 334 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 335 "Core 2 Quad 8xxx and 9xxx", 336 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 337 "(Nehalem)", 338 [0x1c] = "45nm Atom Family", 339 [0x1d] = "XeonMP 74xx (Nehalem)", 340 [0x1e] = "Core i7 and i5", 341 [0x1f] = "Core i7 and i5", 342 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x26] = "Atom Family", 344 [0x27] = "Atom Family", 345 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 346 "i3 2xxx", 347 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 348 [0x2d] = "Xeon E5 Sandy Bridge family, " 349 "Core i7-39xx Extreme", 350 [0x2e] = "Xeon 75xx & 65xx", 351 [0x2f] = "Xeon E7 family", 352 [0x35] = "Atom Family", 353 [0x36] = "Atom S1000", 354 [0x37] = "Atom E3000, Z3[67]00", 355 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 356 "Ivy Bridge", 357 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 360 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 361 "Core i7-49xx Extreme", 362 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 363 "Core i7-59xx Extreme", 364 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 369 [0x4a] = "Atom Z3400", 370 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 371 [0x4d] = "Atom C2000", 372 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 373 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 374 [0x55] = "Xeon Scalable (Skylake)", 375 [0x56] = "Xeon D-1500 (Broadwell)", 376 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 377 [0x5a] = "Atom E3500", 378 [0x5c] = "Atom (Goldmont)", 379 [0x5d] = "Atom X3-C3000 (Silvermont)", 380 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 381 [0x5f] = "Atom (Goldmont, Denverton)", 382 [0x66] = "Future Core (Cannon Lake)", 383 [0x7a] = "Atom (Goldmont Plus)", 384 [0x85] = "Future Xeon Phi (Knights Mill)", 385 [0x8e] = "7th gen Core (Kaby Lake)", 386 [0x9e] = "7th gen Core (Kaby Lake)", 387 }, 388 "Pentium Pro, II or III", /* Default */ 389 NULL, 390 intel_family_new_probe, 391 intel_cpu_cacheinfo, 392 }, 393 /* Family > 6 */ 394 { 395 CPUCLASS_686, 396 { 397 0, 0, 0, 0, 0, 0, 0, 0, 398 0, 0, 0, 0, 0, 0, 0, 0, 399 }, 400 "Pentium 4", /* Default */ 401 NULL, 402 intel_family_new_probe, 403 intel_cpu_cacheinfo, 404 } } 405 }, 406 { 407 "AuthenticAMD", 408 CPUVENDOR_AMD, 409 "AMD", 410 /* Family 4 */ 411 { { 412 CPUCLASS_486, 413 { 414 0, 0, 0, "Am486DX2 W/T", 415 0, 0, 0, "Am486DX2 W/B", 416 "Am486DX4 W/T or Am5x86 W/T 150", 417 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 418 0, 0, "Am5x86 W/T 133/160", 419 "Am5x86 W/B 133/160", 420 }, 421 "Am486 or Am5x86", /* Default */ 422 NULL, 423 NULL, 424 NULL, 425 }, 426 /* Family 5 */ 427 { 428 CPUCLASS_586, 429 { 430 "K5", "K5", "K5", "K5", 0, 0, "K6", 431 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 432 "K6-2+/III+", 0, 0, 433 }, 434 "K5 or K6", /* Default */ 435 amd_family5_setup, 436 NULL, 437 amd_cpu_cacheinfo, 438 }, 439 /* Family 6 */ 440 { 441 CPUCLASS_686, 442 { 443 0, "Athlon Model 1", "Athlon Model 2", 444 "Duron", "Athlon Model 4 (Thunderbird)", 445 0, "Athlon", "Duron", "Athlon", 0, 446 "Athlon", 0, 0, 0, 0, 0, 447 }, 448 "K7 (Athlon)", /* Default */ 449 NULL, 450 amd_family6_probe, 451 amd_cpu_cacheinfo, 452 }, 453 /* Family > 6 */ 454 { 455 CPUCLASS_686, 456 { 457 0, 0, 0, 0, 0, 0, 0, 0, 458 0, 0, 0, 0, 0, 0, 0, 0, 459 }, 460 "Unknown K8 (Athlon)", /* Default */ 461 NULL, 462 amd_family6_probe, 463 amd_cpu_cacheinfo, 464 } } 465 }, 466 { 467 "CyrixInstead", 468 CPUVENDOR_CYRIX, 469 "Cyrix", 470 /* Family 4 */ 471 { { 472 CPUCLASS_486, 473 { 474 0, 0, 0, 475 "MediaGX", 476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 477 }, 478 "486", /* Default */ 479 cyrix6x86_cpu_setup, /* XXX ?? */ 480 NULL, 481 NULL, 482 }, 483 /* Family 5 */ 484 { 485 CPUCLASS_586, 486 { 487 0, 0, "6x86", 0, 488 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 490 }, 491 "6x86", /* Default */ 492 cyrix6x86_cpu_setup, 493 NULL, 494 NULL, 495 }, 496 /* Family 6 */ 497 { 498 CPUCLASS_686, 499 { 500 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 502 }, 503 "6x86MX", /* Default */ 504 cyrix6x86_cpu_setup, 505 NULL, 506 NULL, 507 }, 508 /* Family > 6 */ 509 { 510 CPUCLASS_686, 511 { 512 0, 0, 0, 0, 0, 0, 0, 0, 513 0, 0, 0, 0, 0, 0, 0, 0, 514 }, 515 "Unknown 6x86MX", /* Default */ 516 NULL, 517 NULL, 518 NULL, 519 } } 520 }, 521 { /* MediaGX is now owned by National Semiconductor */ 522 "Geode by NSC", 523 CPUVENDOR_CYRIX, /* XXX */ 524 "National Semiconductor", 525 /* Family 4, NSC never had any of these */ 526 { { 527 CPUCLASS_486, 528 { 529 0, 0, 0, 0, 0, 0, 0, 0, 530 0, 0, 0, 0, 0, 0, 0, 0, 531 }, 532 "486 compatible", /* Default */ 533 NULL, 534 NULL, 535 NULL, 536 }, 537 /* Family 5: Geode family, formerly MediaGX */ 538 { 539 CPUCLASS_586, 540 { 541 0, 0, 0, 0, 542 "Geode GX1", 543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 544 }, 545 "Geode", /* Default */ 546 cyrix6x86_cpu_setup, 547 NULL, 548 amd_cpu_cacheinfo, 549 }, 550 /* Family 6, not yet available from NSC */ 551 { 552 CPUCLASS_686, 553 { 554 0, 0, 0, 0, 0, 0, 0, 0, 555 0, 0, 0, 0, 0, 0, 0, 0, 556 }, 557 "Pentium Pro compatible", /* Default */ 558 NULL, 559 NULL, 560 NULL, 561 }, 562 /* Family > 6, not yet available from NSC */ 563 { 564 CPUCLASS_686, 565 { 566 0, 0, 0, 0, 0, 0, 0, 0, 567 0, 0, 0, 0, 0, 0, 0, 0, 568 }, 569 "Pentium Pro compatible", /* Default */ 570 NULL, 571 NULL, 572 NULL, 573 } } 574 }, 575 { 576 "CentaurHauls", 577 CPUVENDOR_IDT, 578 "IDT", 579 /* Family 4, IDT never had any of these */ 580 { { 581 CPUCLASS_486, 582 { 583 0, 0, 0, 0, 0, 0, 0, 0, 584 0, 0, 0, 0, 0, 0, 0, 0, 585 }, 586 "486 compatible", /* Default */ 587 NULL, 588 NULL, 589 NULL, 590 }, 591 /* Family 5 */ 592 { 593 CPUCLASS_586, 594 { 595 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 596 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 597 }, 598 "WinChip", /* Default */ 599 winchip_cpu_setup, 600 NULL, 601 NULL, 602 }, 603 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 604 { 605 CPUCLASS_686, 606 { 607 0, 0, 0, 0, 0, 0, "C3 Samuel", 608 "C3 Samuel 2/Ezra", "C3 Ezra-T", 609 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 610 0, "VIA Nano", 611 }, 612 "Unknown VIA/IDT", /* Default */ 613 NULL, 614 via_cpu_probe, 615 via_cpu_cacheinfo, 616 }, 617 /* Family > 6, not yet available from VIA */ 618 { 619 CPUCLASS_686, 620 { 621 0, 0, 0, 0, 0, 0, 0, 0, 622 0, 0, 0, 0, 0, 0, 0, 0, 623 }, 624 "Pentium Pro compatible", /* Default */ 625 NULL, 626 NULL, 627 NULL, 628 } } 629 }, 630 { 631 "GenuineTMx86", 632 CPUVENDOR_TRANSMETA, 633 "Transmeta", 634 /* Family 4, Transmeta never had any of these */ 635 { { 636 CPUCLASS_486, 637 { 638 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 640 }, 641 "486 compatible", /* Default */ 642 NULL, 643 NULL, 644 NULL, 645 }, 646 /* Family 5 */ 647 { 648 CPUCLASS_586, 649 { 650 0, 0, 0, 0, 0, 0, 0, 0, 651 0, 0, 0, 0, 0, 0, 0, 0, 652 }, 653 "Crusoe", /* Default */ 654 NULL, 655 NULL, 656 transmeta_cpu_info, 657 }, 658 /* Family 6, not yet available from Transmeta */ 659 { 660 CPUCLASS_686, 661 { 662 0, 0, 0, 0, 0, 0, 0, 0, 663 0, 0, 0, 0, 0, 0, 0, 0, 664 }, 665 "Pentium Pro compatible", /* Default */ 666 NULL, 667 NULL, 668 NULL, 669 }, 670 /* Family > 6, not yet available from Transmeta */ 671 { 672 CPUCLASS_686, 673 { 674 0, 0, 0, 0, 0, 0, 0, 0, 675 0, 0, 0, 0, 0, 0, 0, 0, 676 }, 677 "Pentium Pro compatible", /* Default */ 678 NULL, 679 NULL, 680 NULL, 681 } } 682 } 683 }; 684 685 /* 686 * disable the TSC such that we don't use the TSC in microtime(9) 687 * because some CPUs got the implementation wrong. 688 */ 689 static void 690 disable_tsc(struct cpu_info *ci) 691 { 692 if (ci->ci_feat_val[0] & CPUID_TSC) { 693 ci->ci_feat_val[0] &= ~CPUID_TSC; 694 aprint_error("WARNING: broken TSC disabled\n"); 695 } 696 } 697 698 static void 699 amd_family5_setup(struct cpu_info *ci) 700 { 701 702 switch (ci->ci_model) { 703 case 0: /* AMD-K5 Model 0 */ 704 /* 705 * According to the AMD Processor Recognition App Note, 706 * the AMD-K5 Model 0 uses the wrong bit to indicate 707 * support for global PTEs, instead using bit 9 (APIC) 708 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 709 */ 710 if (ci->ci_feat_val[0] & CPUID_APIC) 711 ci->ci_feat_val[0] = 712 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 713 /* 714 * XXX But pmap_pg_g is already initialized -- need to kick 715 * XXX the pmap somehow. How does the MP branch do this? 716 */ 717 break; 718 } 719 } 720 721 static void 722 cyrix6x86_cpu_setup(struct cpu_info *ci) 723 { 724 725 /* 726 * Do not disable the TSC on the Geode GX, it's reported to 727 * work fine. 728 */ 729 if (ci->ci_signature != 0x552) 730 disable_tsc(ci); 731 } 732 733 static void 734 winchip_cpu_setup(struct cpu_info *ci) 735 { 736 switch (ci->ci_model) { 737 case 4: /* WinChip C6 */ 738 disable_tsc(ci); 739 } 740 } 741 742 743 static const char * 744 intel_family6_name(struct cpu_info *ci) 745 { 746 const char *ret = NULL; 747 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 748 749 if (ci->ci_model == 5) { 750 switch (l2cache) { 751 case 0: 752 case 128 * 1024: 753 ret = "Celeron (Covington)"; 754 break; 755 case 256 * 1024: 756 ret = "Mobile Pentium II (Dixon)"; 757 break; 758 case 512 * 1024: 759 ret = "Pentium II"; 760 break; 761 case 1 * 1024 * 1024: 762 case 2 * 1024 * 1024: 763 ret = "Pentium II Xeon"; 764 break; 765 } 766 } else if (ci->ci_model == 6) { 767 switch (l2cache) { 768 case 256 * 1024: 769 case 512 * 1024: 770 ret = "Mobile Pentium II"; 771 break; 772 } 773 } else if (ci->ci_model == 7) { 774 switch (l2cache) { 775 case 512 * 1024: 776 ret = "Pentium III"; 777 break; 778 case 1 * 1024 * 1024: 779 case 2 * 1024 * 1024: 780 ret = "Pentium III Xeon"; 781 break; 782 } 783 } else if (ci->ci_model >= 8) { 784 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 785 switch (ci->ci_brand_id) { 786 case 0x3: 787 if (ci->ci_signature == 0x6B1) 788 ret = "Celeron"; 789 break; 790 case 0x8: 791 if (ci->ci_signature >= 0xF13) 792 ret = "genuine processor"; 793 break; 794 case 0xB: 795 if (ci->ci_signature >= 0xF13) 796 ret = "Xeon MP"; 797 break; 798 case 0xE: 799 if (ci->ci_signature < 0xF13) 800 ret = "Xeon"; 801 break; 802 } 803 if (ret == NULL) 804 ret = i386_intel_brand[ci->ci_brand_id]; 805 } 806 } 807 808 return ret; 809 } 810 811 /* 812 * Identify AMD64 CPU names from cpuid. 813 * 814 * Based on: 815 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 816 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 817 * "Revision Guide for AMD NPT Family 0Fh Processors" 818 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 819 * and other miscellaneous reports. 820 * 821 * This is all rather pointless, these are cross 'brand' since the raw 822 * silicon is shared. 823 */ 824 static const char * 825 amd_amd64_name(struct cpu_info *ci) 826 { 827 static char family_str[32]; 828 829 /* Only called if family >= 15 */ 830 831 switch (ci->ci_family) { 832 case 15: 833 switch (ci->ci_model) { 834 case 0x21: /* rev JH-E1/E6 */ 835 case 0x41: /* rev JH-F2 */ 836 return "Dual-Core Opteron"; 837 case 0x23: /* rev JH-E6 (Toledo) */ 838 return "Dual-Core Opteron or Athlon 64 X2"; 839 case 0x43: /* rev JH-F2 (Windsor) */ 840 return "Athlon 64 FX or Athlon 64 X2"; 841 case 0x24: /* rev SH-E5 (Lancaster?) */ 842 return "Mobile Athlon 64 or Turion 64"; 843 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 844 return "Opteron or Athlon 64 FX"; 845 case 0x15: /* rev SH-D0 */ 846 case 0x25: /* rev SH-E4 */ 847 return "Opteron"; 848 case 0x27: /* rev DH-E4, SH-E4 */ 849 return "Athlon 64 or Athlon 64 FX or Opteron"; 850 case 0x48: /* rev BH-F2 */ 851 return "Turion 64 X2"; 852 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 853 case 0x07: /* rev SH-CG (ClawHammer) */ 854 case 0x0b: /* rev CH-CG */ 855 case 0x14: /* rev SH-D0 */ 856 case 0x17: /* rev SH-D0 */ 857 case 0x1b: /* rev CH-D0 */ 858 return "Athlon 64"; 859 case 0x2b: /* rev BH-E4 (Manchester) */ 860 case 0x4b: /* rev BH-F2 (Windsor) */ 861 return "Athlon 64 X2"; 862 case 0x6b: /* rev BH-G1 (Brisbane) */ 863 return "Athlon X2 or Athlon 64 X2"; 864 case 0x08: /* rev CH-CG */ 865 case 0x0c: /* rev DH-CG (Newcastle) */ 866 case 0x0e: /* rev DH-CG (Newcastle?) */ 867 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 868 case 0x18: /* rev CH-D0 */ 869 case 0x1c: /* rev DH-D0 (Winchester) */ 870 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 871 case 0x2c: /* rev DH-E3/E6 */ 872 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 873 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 874 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 875 case 0x6f: /* rev DH-G1 */ 876 return "Athlon 64 or Sempron"; 877 default: 878 break; 879 } 880 return "Unknown AMD64 CPU"; 881 882 #if 0 883 case 16: 884 return "Family 10h"; 885 case 17: 886 return "Family 11h"; 887 case 18: 888 return "Family 12h"; 889 case 19: 890 return "Family 14h"; 891 case 20: 892 return "Family 15h"; 893 #endif 894 895 default: 896 break; 897 } 898 899 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 900 return family_str; 901 } 902 903 static void 904 intel_family_new_probe(struct cpu_info *ci) 905 { 906 uint32_t descs[4]; 907 908 x86_cpuid(0x80000000, descs); 909 910 /* 911 * Determine extended feature flags. 912 */ 913 if (descs[0] >= 0x80000001) { 914 x86_cpuid(0x80000001, descs); 915 ci->ci_feat_val[2] |= descs[3]; 916 ci->ci_feat_val[3] |= descs[2]; 917 } 918 } 919 920 static void 921 via_cpu_probe(struct cpu_info *ci) 922 { 923 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 924 u_int descs[4]; 925 u_int lfunc; 926 927 /* 928 * Determine the largest extended function value. 929 */ 930 x86_cpuid(0x80000000, descs); 931 lfunc = descs[0]; 932 933 /* 934 * Determine the extended feature flags. 935 */ 936 if (lfunc >= 0x80000001) { 937 x86_cpuid(0x80000001, descs); 938 ci->ci_feat_val[2] |= descs[3]; 939 } 940 941 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 942 return; 943 944 /* Nehemiah or Esther */ 945 x86_cpuid(0xc0000000, descs); 946 lfunc = descs[0]; 947 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 948 return; 949 950 x86_cpuid(0xc0000001, descs); 951 lfunc = descs[3]; 952 ci->ci_feat_val[4] = lfunc; 953 } 954 955 static void 956 amd_family6_probe(struct cpu_info *ci) 957 { 958 uint32_t descs[4]; 959 char *p; 960 size_t i; 961 962 x86_cpuid(0x80000000, descs); 963 964 /* 965 * Determine the extended feature flags. 966 */ 967 if (descs[0] >= 0x80000001) { 968 x86_cpuid(0x80000001, descs); 969 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 970 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 971 } 972 973 if (*cpu_brand_string == '\0') 974 return; 975 976 for (i = 1; i < __arraycount(amd_brand); i++) 977 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 978 ci->ci_brand_id = i; 979 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 980 break; 981 } 982 } 983 984 static void 985 intel_cpu_cacheinfo(struct cpu_info *ci) 986 { 987 const struct x86_cache_info *cai; 988 u_int descs[4]; 989 int iterations, i, j; 990 int type, level; 991 int ways, partitions, linesize, sets; 992 int caitype = -1; 993 int totalsize; 994 uint8_t desc; 995 996 /* Return if the cpu is old pre-cpuid instruction cpu */ 997 if (ci->ci_cpu_type >= 0) 998 return; 999 1000 if (ci->ci_cpuid_level < 2) 1001 return; 1002 1003 /* 1004 * Parse the cache info from `cpuid leaf 2', if we have it. 1005 * XXX This is kinda ugly, but hey, so is the architecture... 1006 */ 1007 x86_cpuid(2, descs); 1008 iterations = descs[0] & 0xff; 1009 while (iterations-- > 0) { 1010 for (i = 0; i < 4; i++) { 1011 if (descs[i] & 0x80000000) 1012 continue; 1013 for (j = 0; j < 4; j++) { 1014 /* 1015 * The least significant byte in EAX 1016 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1017 * it should be ignored. 1018 */ 1019 if (i == 0 && j == 0) 1020 continue; 1021 desc = (descs[i] >> (j * 8)) & 0xff; 1022 if (desc == 0) 1023 continue; 1024 cai = cache_info_lookup(intel_cpuid_cache_info, 1025 desc); 1026 if (cai != NULL) 1027 ci->ci_cinfo[cai->cai_index] = *cai; 1028 else if ((verbose != 0) && (desc != 0xff) 1029 && (desc != 0xfe)) 1030 aprint_error_dev(ci->ci_dev, "error:" 1031 " Unknown cacheinfo desc %02x\n", 1032 desc); 1033 } 1034 } 1035 x86_cpuid(2, descs); 1036 } 1037 1038 if (ci->ci_cpuid_level < 4) 1039 return; 1040 1041 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1042 for (i = 0; ; i++) { 1043 x86_cpuid2(4, i, descs); 1044 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1045 if (type == CPUID_DCP_CACHETYPE_N) 1046 break; 1047 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1048 switch (level) { 1049 case 1: 1050 if (type == CPUID_DCP_CACHETYPE_I) 1051 caitype = CAI_ICACHE; 1052 else if (type == CPUID_DCP_CACHETYPE_D) 1053 caitype = CAI_DCACHE; 1054 else 1055 caitype = -1; 1056 break; 1057 case 2: 1058 if (type == CPUID_DCP_CACHETYPE_U) 1059 caitype = CAI_L2CACHE; 1060 else 1061 caitype = -1; 1062 break; 1063 case 3: 1064 if (type == CPUID_DCP_CACHETYPE_U) 1065 caitype = CAI_L3CACHE; 1066 else 1067 caitype = -1; 1068 break; 1069 default: 1070 caitype = -1; 1071 break; 1072 } 1073 if (caitype == -1) { 1074 aprint_error_dev(ci->ci_dev, 1075 "error: unknown cache level&type (%d & %d)\n", 1076 level, type); 1077 continue; 1078 } 1079 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1080 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1081 + 1; 1082 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1083 + 1; 1084 sets = descs[2] + 1; 1085 totalsize = ways * partitions * linesize * sets; 1086 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1087 ci->ci_cinfo[caitype].cai_associativity = ways; 1088 ci->ci_cinfo[caitype].cai_linesize = linesize; 1089 } 1090 1091 if (ci->ci_cpuid_level < 0x18) 1092 return; 1093 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1094 x86_cpuid(0x18, descs); 1095 iterations = descs[0]; 1096 for (i = 0; i <= iterations; i++) { 1097 x86_cpuid2(0x18, i, descs); 1098 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1099 if (type == CPUID_DATP_TCTYPE_N) 1100 continue; 1101 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1102 switch (level) { 1103 case 1: 1104 if (type == CPUID_DATP_TCTYPE_I) 1105 caitype = CAI_ITLB; /* XXX or ITLB2? */ 1106 else if (type == CPUID_DATP_TCTYPE_D) 1107 caitype = CAI_DTLB; 1108 else 1109 caitype = -1; 1110 break; 1111 case 2: 1112 if (type == CPUID_DATP_TCTYPE_I) 1113 caitype = CAI_L2_ITLB; 1114 else if (type == CPUID_DATP_TCTYPE_D) 1115 caitype = CAI_L2_DTLB; 1116 else if (type == CPUID_DATP_TCTYPE_U) 1117 caitype = CAI_L2_STLB; 1118 else 1119 caitype = -1; 1120 break; 1121 case 3: 1122 /* XXX need work for L3 TLB */ 1123 caitype = CAI_L3CACHE; 1124 break; 1125 default: 1126 caitype = -1; 1127 break; 1128 } 1129 if (caitype == -1) { 1130 aprint_error_dev(ci->ci_dev, 1131 "error: unknown TLB level&type (%d & %d)\n", 1132 level, type); 1133 continue; 1134 } 1135 switch (__SHIFTOUT(descs[1], CPUID_DATP_PGSIZE)) { 1136 case CPUID_DATP_PGSIZE_4KB: 1137 linesize = 4 * 1024; 1138 break; 1139 case CPUID_DATP_PGSIZE_2MB: 1140 linesize = 2 * 1024 * 1024; 1141 break; 1142 case CPUID_DATP_PGSIZE_4MB: 1143 linesize = 4 * 1024 * 1024; 1144 break; 1145 case CPUID_DATP_PGSIZE_1GB: 1146 linesize = 1024 * 1024 * 1024; 1147 break; 1148 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1149 aprint_error_dev(ci->ci_dev, 1150 "WARINING: Currently 2M/4M info can't print correctly\n"); 1151 linesize = 4 * 1024 * 1024; 1152 break; 1153 default: 1154 aprint_error_dev(ci->ci_dev, 1155 "error: Unknown size combination\n"); 1156 linesize = 4 * 1024; 1157 break; 1158 } 1159 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1160 sets = descs[2]; 1161 ci->ci_cinfo[caitype].cai_totalsize = sets; /* entries */ 1162 ci->ci_cinfo[caitype].cai_associativity = ways; 1163 ci->ci_cinfo[caitype].cai_linesize = linesize; /* page size */ 1164 } 1165 } 1166 1167 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1168 AMD_L2CACHE_INFO; 1169 1170 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1171 AMD_L3CACHE_INFO; 1172 1173 static void 1174 amd_cpu_cacheinfo(struct cpu_info *ci) 1175 { 1176 const struct x86_cache_info *cp; 1177 struct x86_cache_info *cai; 1178 u_int descs[4]; 1179 u_int lfunc; 1180 1181 /* 1182 * K5 model 0 has none of this info. 1183 */ 1184 if (ci->ci_family == 5 && ci->ci_model == 0) 1185 return; 1186 1187 /* 1188 * Determine the largest extended function value. 1189 */ 1190 x86_cpuid(0x80000000, descs); 1191 lfunc = descs[0]; 1192 1193 /* 1194 * Determine L1 cache/TLB info. 1195 */ 1196 if (lfunc < 0x80000005) { 1197 /* No L1 cache info available. */ 1198 return; 1199 } 1200 1201 x86_cpuid(0x80000005, descs); 1202 1203 /* 1204 * K6-III and higher have large page TLBs. 1205 */ 1206 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1207 cai = &ci->ci_cinfo[CAI_ITLB2]; 1208 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1209 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1210 cai->cai_linesize = largepagesize; 1211 1212 cai = &ci->ci_cinfo[CAI_DTLB2]; 1213 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1214 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1215 cai->cai_linesize = largepagesize; 1216 } 1217 1218 cai = &ci->ci_cinfo[CAI_ITLB]; 1219 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1220 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1221 cai->cai_linesize = (4 * 1024); 1222 1223 cai = &ci->ci_cinfo[CAI_DTLB]; 1224 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1225 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1226 cai->cai_linesize = (4 * 1024); 1227 1228 cai = &ci->ci_cinfo[CAI_DCACHE]; 1229 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1230 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1231 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1232 1233 cai = &ci->ci_cinfo[CAI_ICACHE]; 1234 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1235 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1236 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1237 1238 /* 1239 * Determine L2 cache/TLB info. 1240 */ 1241 if (lfunc < 0x80000006) { 1242 /* No L2 cache info available. */ 1243 return; 1244 } 1245 1246 x86_cpuid(0x80000006, descs); 1247 1248 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1249 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1250 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1251 cai->cai_linesize = (4 * 1024); 1252 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1253 cai->cai_associativity); 1254 if (cp != NULL) 1255 cai->cai_associativity = cp->cai_associativity; 1256 else 1257 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1258 1259 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1260 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1261 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1262 cai->cai_linesize = largepagesize; 1263 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1264 cai->cai_associativity); 1265 if (cp != NULL) 1266 cai->cai_associativity = cp->cai_associativity; 1267 else 1268 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1269 1270 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1271 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1272 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1273 cai->cai_linesize = (4 * 1024); 1274 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1275 cai->cai_associativity); 1276 if (cp != NULL) 1277 cai->cai_associativity = cp->cai_associativity; 1278 else 1279 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1280 1281 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1282 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1283 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1284 cai->cai_linesize = largepagesize; 1285 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1286 cai->cai_associativity); 1287 if (cp != NULL) 1288 cai->cai_associativity = cp->cai_associativity; 1289 else 1290 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1291 1292 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1293 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1294 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1295 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1296 1297 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1298 cai->cai_associativity); 1299 if (cp != NULL) 1300 cai->cai_associativity = cp->cai_associativity; 1301 else 1302 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1303 1304 /* 1305 * Determine L3 cache info on AMD Family 10h and newer processors 1306 */ 1307 if (ci->ci_family >= 0x10) { 1308 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1309 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1310 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1311 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1312 1313 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1314 cai->cai_associativity); 1315 if (cp != NULL) 1316 cai->cai_associativity = cp->cai_associativity; 1317 else 1318 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1319 } 1320 1321 /* 1322 * Determine 1GB TLB info. 1323 */ 1324 if (lfunc < 0x80000019) { 1325 /* No 1GB TLB info available. */ 1326 return; 1327 } 1328 1329 x86_cpuid(0x80000019, descs); 1330 1331 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1332 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1333 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1334 cai->cai_linesize = (1024 * 1024 * 1024); 1335 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1336 cai->cai_associativity); 1337 if (cp != NULL) 1338 cai->cai_associativity = cp->cai_associativity; 1339 else 1340 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1341 1342 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1343 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1344 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1345 cai->cai_linesize = (1024 * 1024 * 1024); 1346 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1347 cai->cai_associativity); 1348 if (cp != NULL) 1349 cai->cai_associativity = cp->cai_associativity; 1350 else 1351 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1352 1353 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1354 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1355 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1356 cai->cai_linesize = (1024 * 1024 * 1024); 1357 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1358 cai->cai_associativity); 1359 if (cp != NULL) 1360 cai->cai_associativity = cp->cai_associativity; 1361 else 1362 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1363 1364 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1365 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1366 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1367 cai->cai_linesize = (1024 * 1024 * 1024); 1368 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1369 cai->cai_associativity); 1370 if (cp != NULL) 1371 cai->cai_associativity = cp->cai_associativity; 1372 else 1373 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1374 } 1375 1376 static void 1377 via_cpu_cacheinfo(struct cpu_info *ci) 1378 { 1379 struct x86_cache_info *cai; 1380 int stepping; 1381 u_int descs[4]; 1382 u_int lfunc; 1383 1384 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1385 1386 /* 1387 * Determine the largest extended function value. 1388 */ 1389 x86_cpuid(0x80000000, descs); 1390 lfunc = descs[0]; 1391 1392 /* 1393 * Determine L1 cache/TLB info. 1394 */ 1395 if (lfunc < 0x80000005) { 1396 /* No L1 cache info available. */ 1397 return; 1398 } 1399 1400 x86_cpuid(0x80000005, descs); 1401 1402 cai = &ci->ci_cinfo[CAI_ITLB]; 1403 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1404 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1405 cai->cai_linesize = (4 * 1024); 1406 1407 cai = &ci->ci_cinfo[CAI_DTLB]; 1408 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1409 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1410 cai->cai_linesize = (4 * 1024); 1411 1412 cai = &ci->ci_cinfo[CAI_DCACHE]; 1413 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1414 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1415 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1416 if (ci->ci_model == 9 && stepping == 8) { 1417 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1418 cai->cai_associativity = 2; 1419 } 1420 1421 cai = &ci->ci_cinfo[CAI_ICACHE]; 1422 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1423 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1424 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1425 if (ci->ci_model == 9 && stepping == 8) { 1426 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1427 cai->cai_associativity = 2; 1428 } 1429 1430 /* 1431 * Determine L2 cache/TLB info. 1432 */ 1433 if (lfunc < 0x80000006) { 1434 /* No L2 cache info available. */ 1435 return; 1436 } 1437 1438 x86_cpuid(0x80000006, descs); 1439 1440 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1441 if (ci->ci_model >= 9) { 1442 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1443 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1444 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1445 } else { 1446 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1447 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1448 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1449 } 1450 } 1451 1452 static void 1453 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1454 { 1455 u_int descs[4]; 1456 1457 x86_cpuid(0x80860007, descs); 1458 *frequency = descs[0]; 1459 *voltage = descs[1]; 1460 *percentage = descs[2]; 1461 } 1462 1463 static void 1464 transmeta_cpu_info(struct cpu_info *ci) 1465 { 1466 u_int descs[4], nreg; 1467 u_int frequency, voltage, percentage; 1468 1469 x86_cpuid(0x80860000, descs); 1470 nreg = descs[0]; 1471 if (nreg >= 0x80860001) { 1472 x86_cpuid(0x80860001, descs); 1473 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1474 (descs[1] >> 24) & 0xff, 1475 (descs[1] >> 16) & 0xff, 1476 (descs[1] >> 8) & 0xff, 1477 descs[1] & 0xff); 1478 } 1479 if (nreg >= 0x80860002) { 1480 x86_cpuid(0x80860002, descs); 1481 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1482 (descs[1] >> 24) & 0xff, 1483 (descs[1] >> 16) & 0xff, 1484 (descs[1] >> 8) & 0xff, 1485 descs[1] & 0xff, 1486 descs[2]); 1487 } 1488 if (nreg >= 0x80860006) { 1489 union { 1490 char text[65]; 1491 u_int descs[4][4]; 1492 } info; 1493 int i; 1494 1495 for (i=0; i<4; i++) { 1496 x86_cpuid(0x80860003 + i, info.descs[i]); 1497 } 1498 info.text[64] = '\0'; 1499 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1500 } 1501 1502 if (nreg >= 0x80860007) { 1503 tmx86_get_longrun_status(&frequency, 1504 &voltage, &percentage); 1505 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1506 frequency, voltage, percentage); 1507 } 1508 } 1509 1510 static void 1511 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1512 { 1513 u_int descs[4]; 1514 int i; 1515 uint32_t brand[12]; 1516 1517 memset(ci, 0, sizeof(*ci)); 1518 ci->ci_dev = cpuname; 1519 1520 ci->ci_cpu_type = x86_identify(); 1521 if (ci->ci_cpu_type >= 0) { 1522 /* Old pre-cpuid instruction cpu */ 1523 ci->ci_cpuid_level = -1; 1524 return; 1525 } 1526 1527 /* 1528 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1529 * function. 1530 */ 1531 1532 /* 1533 * Fn0000_0000: 1534 * - Save cpuid max level. 1535 * - Save vendor string. 1536 */ 1537 x86_cpuid(0, descs); 1538 ci->ci_cpuid_level = descs[0]; 1539 /* Save vendor string */ 1540 ci->ci_vendor[0] = descs[1]; 1541 ci->ci_vendor[2] = descs[2]; 1542 ci->ci_vendor[1] = descs[3]; 1543 ci->ci_vendor[3] = 0; 1544 1545 /* 1546 * Fn8000_0000: 1547 * - Get cpuid extended function's max level. 1548 */ 1549 x86_cpuid(0x80000000, descs); 1550 if (descs[0] >= 0x80000000) 1551 ci->ci_cpuid_extlevel = descs[0]; 1552 else { 1553 /* Set lower value than 0x80000000 */ 1554 ci->ci_cpuid_extlevel = 0; 1555 } 1556 1557 /* 1558 * Fn8000_000[2-4]: 1559 * - Save brand string. 1560 */ 1561 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1562 x86_cpuid(0x80000002, brand); 1563 x86_cpuid(0x80000003, brand + 4); 1564 x86_cpuid(0x80000004, brand + 8); 1565 for (i = 0; i < 48; i++) 1566 if (((char *) brand)[i] != ' ') 1567 break; 1568 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1569 } 1570 1571 if (ci->ci_cpuid_level < 1) 1572 return; 1573 1574 /* 1575 * Fn0000_0001: 1576 * - Get CPU family, model and stepping (from eax). 1577 * - Initial local APIC ID and brand ID (from ebx) 1578 * - CPUID2 (from ecx) 1579 * - CPUID (from edx) 1580 */ 1581 x86_cpuid(1, descs); 1582 ci->ci_signature = descs[0]; 1583 1584 /* Extract full family/model values */ 1585 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1586 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1587 1588 /* Brand is low order 8 bits of ebx */ 1589 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1590 /* Initial local APIC ID */ 1591 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1592 1593 ci->ci_feat_val[1] = descs[2]; 1594 ci->ci_feat_val[0] = descs[3]; 1595 1596 if (ci->ci_cpuid_level < 3) 1597 return; 1598 1599 /* 1600 * If the processor serial number misfeature is present and supported, 1601 * extract it here. 1602 */ 1603 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1604 ci->ci_cpu_serial[0] = ci->ci_signature; 1605 x86_cpuid(3, descs); 1606 ci->ci_cpu_serial[2] = descs[2]; 1607 ci->ci_cpu_serial[1] = descs[3]; 1608 } 1609 1610 if (ci->ci_cpuid_level < 0x7) 1611 return; 1612 1613 x86_cpuid(7, descs); 1614 ci->ci_feat_val[5] = descs[1]; 1615 ci->ci_feat_val[6] = descs[2]; 1616 1617 if (ci->ci_cpuid_level < 0xd) 1618 return; 1619 1620 /* Get support XCR0 bits */ 1621 x86_cpuid2(0xd, 0, descs); 1622 ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */ 1623 ci->ci_cur_xsave = descs[1]; 1624 ci->ci_max_xsave = descs[2]; 1625 1626 /* Additional flags (eg xsaveopt support) */ 1627 x86_cpuid2(0xd, 1, descs); 1628 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1629 } 1630 1631 static void 1632 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1633 { 1634 uint32_t descs[4]; 1635 char hv_sig[13]; 1636 char *p; 1637 const char *hv_name; 1638 int i; 1639 1640 /* 1641 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1642 * http://lkml.org/lkml/2008/10/1/246 1643 * 1644 * KB1009458: Mechanisms to determine if software is running in 1645 * a VMware virtual machine 1646 * http://kb.vmware.com/kb/1009458 1647 */ 1648 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1649 x86_cpuid(0x40000000, descs); 1650 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1651 memcpy(p, &descs[i], sizeof(descs[i])); 1652 *p = '\0'; 1653 /* 1654 * HV vendor ID string 1655 * ------------+-------------- 1656 * KVM "KVMKVMKVM" 1657 * Microsoft "Microsoft Hv" 1658 * VMware "VMwareVMware" 1659 * Xen "XenVMMXenVMM" 1660 */ 1661 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1662 hv_name = "KVM"; 1663 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1664 hv_name = "Hyper-V"; 1665 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1666 hv_name = "VMware"; 1667 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1668 hv_name = "Xen"; 1669 else 1670 hv_name = "unknown"; 1671 1672 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1673 } 1674 } 1675 1676 static void 1677 cpu_probe_features(struct cpu_info *ci) 1678 { 1679 const struct cpu_cpuid_nameclass *cpup = NULL; 1680 unsigned int i; 1681 1682 if (ci->ci_cpuid_level < 1) 1683 return; 1684 1685 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1686 if (!strncmp((char *)ci->ci_vendor, 1687 i386_cpuid_cpus[i].cpu_id, 12)) { 1688 cpup = &i386_cpuid_cpus[i]; 1689 break; 1690 } 1691 } 1692 1693 if (cpup == NULL) 1694 return; 1695 1696 i = ci->ci_family - CPU_MINFAMILY; 1697 1698 if (i >= __arraycount(cpup->cpu_family)) 1699 i = __arraycount(cpup->cpu_family) - 1; 1700 1701 if (cpup->cpu_family[i].cpu_probe == NULL) 1702 return; 1703 1704 (*cpup->cpu_family[i].cpu_probe)(ci); 1705 } 1706 1707 static void 1708 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1709 { 1710 char buf[32 * 16]; 1711 char *bp; 1712 1713 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1714 1715 if (val == 0 || fmt == NULL) 1716 return; 1717 1718 snprintb_m(buf, sizeof(buf), fmt, val, 1719 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1720 bp = buf; 1721 while (*bp != '\0') { 1722 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1723 bp += strlen(bp) + 1; 1724 } 1725 } 1726 1727 static void 1728 identifycpu_cpuids(struct cpu_info *ci) 1729 { 1730 const char *cpuname = ci->ci_dev; 1731 u_int lp_max = 1; /* logical processors per package */ 1732 u_int smt_max; /* smt per core */ 1733 u_int core_max = 1; /* core per package */ 1734 u_int smt_bits, core_bits; 1735 uint32_t descs[4]; 1736 1737 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1738 ci->ci_packageid = ci->ci_initapicid; 1739 ci->ci_coreid = 0; 1740 ci->ci_smtid = 0; 1741 if (cpu_vendor != CPUVENDOR_INTEL) { 1742 return; 1743 } 1744 1745 /* 1746 * 253668.pdf 7.10.2 1747 */ 1748 1749 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1750 x86_cpuid(1, descs); 1751 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1752 } 1753 if (ci->ci_cpuid_level >= 4) { 1754 x86_cpuid2(4, 0, descs); 1755 core_max = (descs[0] >> 26) + 1; 1756 } 1757 assert(lp_max >= core_max); 1758 smt_max = lp_max / core_max; 1759 smt_bits = ilog2(smt_max - 1) + 1; 1760 core_bits = ilog2(core_max - 1) + 1; 1761 if (smt_bits + core_bits) { 1762 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1763 } 1764 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1765 ci->ci_packageid); 1766 if (core_bits) { 1767 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1768 1769 ci->ci_coreid = 1770 __SHIFTOUT(ci->ci_initapicid, core_mask); 1771 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1772 } 1773 if (smt_bits) { 1774 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1775 1776 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1777 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1778 } 1779 } 1780 1781 void 1782 identifycpu(int fd, const char *cpuname) 1783 { 1784 const char *name = "", *modifier, *vendorname, *brand = ""; 1785 int class = CPUCLASS_386; 1786 unsigned int i; 1787 int modif, family; 1788 const struct cpu_cpuid_nameclass *cpup = NULL; 1789 const struct cpu_cpuid_family *cpufam; 1790 struct cpu_info *ci, cistore; 1791 u_int descs[4]; 1792 size_t sz; 1793 struct cpu_ucode_version ucode; 1794 union { 1795 struct cpu_ucode_version_amd amd; 1796 struct cpu_ucode_version_intel1 intel1; 1797 } ucvers; 1798 1799 ci = &cistore; 1800 cpu_probe_base_features(ci, cpuname); 1801 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1802 ci->ci_cpuid_level); 1803 if (verbose) { 1804 int bf; 1805 1806 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1807 x86_cpuid(bf, descs); 1808 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1809 bf, descs[0], descs[1], descs[2], descs[3]); 1810 } 1811 } 1812 if (ci->ci_cpuid_extlevel >= 0x80000000) 1813 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1814 ci->ci_cpuid_extlevel); 1815 if (verbose) { 1816 unsigned int ef; 1817 1818 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1819 x86_cpuid(ef, descs); 1820 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1821 ef, descs[0], descs[1], descs[2], descs[3]); 1822 } 1823 } 1824 1825 cpu_probe_hv_features(ci, cpuname); 1826 cpu_probe_features(ci); 1827 1828 if (ci->ci_cpu_type >= 0) { 1829 /* Old pre-cpuid instruction cpu */ 1830 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1831 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1832 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1833 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1834 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1835 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1836 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1837 modifier = ""; 1838 } else { 1839 /* CPU which support cpuid instruction */ 1840 modif = (ci->ci_signature >> 12) & 0x3; 1841 family = ci->ci_family; 1842 if (family < CPU_MINFAMILY) 1843 errx(1, "identifycpu: strange family value"); 1844 if (family > CPU_MAXFAMILY) 1845 family = CPU_MAXFAMILY; 1846 1847 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1848 if (!strncmp((char *)ci->ci_vendor, 1849 i386_cpuid_cpus[i].cpu_id, 12)) { 1850 cpup = &i386_cpuid_cpus[i]; 1851 break; 1852 } 1853 } 1854 1855 if (cpup == NULL) { 1856 cpu_vendor = CPUVENDOR_UNKNOWN; 1857 if (ci->ci_vendor[0] != '\0') 1858 vendorname = (char *)&ci->ci_vendor[0]; 1859 else 1860 vendorname = "Unknown"; 1861 class = family - 3; 1862 modifier = ""; 1863 name = ""; 1864 ci->ci_info = NULL; 1865 } else { 1866 cpu_vendor = cpup->cpu_vendor; 1867 vendorname = cpup->cpu_vendorname; 1868 modifier = modifiers[modif]; 1869 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1870 name = cpufam->cpu_models[ci->ci_model]; 1871 if (name == NULL || *name == '\0') 1872 name = cpufam->cpu_model_default; 1873 class = cpufam->cpu_class; 1874 ci->ci_info = cpufam->cpu_info; 1875 1876 if (cpu_vendor == CPUVENDOR_INTEL) { 1877 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1878 const char *tmp; 1879 tmp = intel_family6_name(ci); 1880 if (tmp != NULL) 1881 name = tmp; 1882 } 1883 if (ci->ci_family == 15 && 1884 ci->ci_brand_id < 1885 __arraycount(i386_intel_brand) && 1886 i386_intel_brand[ci->ci_brand_id]) 1887 name = 1888 i386_intel_brand[ci->ci_brand_id]; 1889 } 1890 1891 if (cpu_vendor == CPUVENDOR_AMD) { 1892 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1893 if (ci->ci_brand_id == 1) 1894 /* 1895 * It's Duron. We override the 1896 * name, since it might have 1897 * been misidentified as Athlon. 1898 */ 1899 name = 1900 amd_brand[ci->ci_brand_id]; 1901 else 1902 brand = amd_brand_name; 1903 } 1904 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1905 == 0xf) { 1906 /* Identify AMD64 CPU names. */ 1907 const char *tmp; 1908 tmp = amd_amd64_name(ci); 1909 if (tmp != NULL) 1910 name = tmp; 1911 } 1912 } 1913 1914 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1915 vendorname = "VIA"; 1916 } 1917 } 1918 1919 ci->ci_cpu_class = class; 1920 1921 sz = sizeof(ci->ci_tsc_freq); 1922 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1923 sz = sizeof(use_pae); 1924 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1925 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1926 1927 /* 1928 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1929 * we try to determine from the family/model values. 1930 */ 1931 if (*cpu_brand_string != '\0') 1932 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1933 1934 aprint_normal("%s: %s", cpuname, vendorname); 1935 if (*modifier) 1936 aprint_normal(" %s", modifier); 1937 if (*name) 1938 aprint_normal(" %s", name); 1939 if (*brand) 1940 aprint_normal(" %s", brand); 1941 aprint_normal(" (%s-class)", classnames[class]); 1942 1943 if (ci->ci_tsc_freq != 0) 1944 aprint_normal(", %ju.%02ju MHz", 1945 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1946 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1947 aprint_normal("\n"); 1948 1949 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1950 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1951 if (ci->ci_signature != 0) 1952 aprint_normal(" (id %#x)", ci->ci_signature); 1953 aprint_normal("\n"); 1954 1955 if (ci->ci_info) 1956 (*ci->ci_info)(ci); 1957 1958 /* 1959 * display CPU feature flags 1960 */ 1961 1962 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1963 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1964 1965 /* These next two are actually common definitions! */ 1966 print_bits(cpuname, "features2", 1967 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1968 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1969 print_bits(cpuname, "features3", 1970 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1971 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1972 1973 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1974 ci->ci_feat_val[4]); 1975 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 1976 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 1977 ci->ci_feat_val[5]); 1978 if (cpu_vendor == CPUVENDOR_INTEL) 1979 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 1980 ci->ci_feat_val[6]); 1981 1982 if ((cpu_vendor == CPUVENDOR_INTEL) && (ci->ci_cpuid_level >= 7)) { 1983 x86_cpuid(7, descs); 1984 print_bits(cpuname, "SEF edx", CPUID_SEF_FLAGS2, descs[3]); 1985 } 1986 1987 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]); 1988 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1989 ci->ci_feat_val[8]); 1990 1991 if (ci->ci_max_xsave != 0) { 1992 aprint_normal("%s: xsave area size: current %d, maximum %d", 1993 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1994 aprint_normal(", xgetbv %sabled\n", 1995 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1996 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1997 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1998 x86_xgetbv()); 1999 } 2000 2001 x86_print_cache_and_tlb_info(ci); 2002 2003 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2004 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2005 cpuname, 2006 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2007 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2008 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2009 } 2010 2011 if (ci->ci_cpu_class == CPUCLASS_386) 2012 errx(1, "NetBSD requires an 80486 or later processor"); 2013 2014 if (ci->ci_cpu_type == CPU_486DLC) { 2015 #ifndef CYRIX_CACHE_WORKS 2016 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2017 #else 2018 #ifndef CYRIX_CACHE_REALLY_WORKS 2019 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2020 #else 2021 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2022 #endif 2023 #endif 2024 } 2025 2026 /* 2027 * Everything past this point requires a Pentium or later. 2028 */ 2029 if (ci->ci_cpuid_level < 0) 2030 return; 2031 2032 identifycpu_cpuids(ci); 2033 2034 #ifdef INTEL_CORETEMP 2035 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 2036 coretemp_register(ci); 2037 #endif 2038 2039 if (cpu_vendor == CPUVENDOR_AMD) { 2040 uint32_t data[4]; 2041 2042 x86_cpuid(0x80000000, data); 2043 if (data[0] >= 0x80000007) 2044 powernow_probe(ci); 2045 2046 if ((data[0] >= 0x8000000a) 2047 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2048 x86_cpuid(0x8000000a, data); 2049 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2050 data[0] & 0xf); 2051 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 2052 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 2053 data[3]); 2054 } 2055 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2056 uint32_t data[4]; 2057 int32_t bi_index; 2058 2059 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2060 x86_cpuid(bi_index, data); 2061 switch (bi_index) { 2062 case 6: 2063 print_bits(cpuname, "DSPM-eax", 2064 CPUID_DSPM_FLAGS, data[0]); 2065 print_bits(cpuname, "DSPM-ecx", 2066 CPUID_DSPM_FLAGS1, data[2]); 2067 break; 2068 case 7: 2069 aprint_verbose("%s: SEF highest subleaf %08x\n", 2070 cpuname, data[0]); 2071 break; 2072 #if 0 2073 default: 2074 aprint_verbose("%s: basic %08x-eax %08x\n", 2075 cpuname, bi_index, data[0]); 2076 aprint_verbose("%s: basic %08x-ebx %08x\n", 2077 cpuname, bi_index, data[1]); 2078 aprint_verbose("%s: basic %08x-ecx %08x\n", 2079 cpuname, bi_index, data[2]); 2080 aprint_verbose("%s: basic %08x-edx %08x\n", 2081 cpuname, bi_index, data[3]); 2082 break; 2083 #endif 2084 } 2085 } 2086 } 2087 2088 #ifdef INTEL_ONDEMAND_CLOCKMOD 2089 clockmod_init(); 2090 #endif 2091 2092 if (cpu_vendor == CPUVENDOR_AMD) 2093 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2094 else if (cpu_vendor == CPUVENDOR_INTEL) 2095 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2096 else 2097 return; 2098 2099 ucode.data = &ucvers; 2100 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2101 #ifdef __i386__ 2102 struct cpu_ucode_version_64 ucode_64; 2103 if (errno != ENOTTY) 2104 return; 2105 /* Try the 64 bit ioctl */ 2106 memset(&ucode_64, 0, sizeof ucode_64); 2107 ucode_64.data = &ucvers; 2108 ucode_64.loader_version = ucode.loader_version; 2109 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2110 return; 2111 #else 2112 return; 2113 #endif 2114 } 2115 2116 if (cpu_vendor == CPUVENDOR_AMD) 2117 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2118 else if (cpu_vendor == CPUVENDOR_INTEL) 2119 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2120 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2121 } 2122 2123 static const struct x86_cache_info * 2124 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2125 { 2126 int i; 2127 2128 for (i = 0; cai[i].cai_desc != 0; i++) { 2129 if (cai[i].cai_desc == desc) 2130 return (&cai[i]); 2131 } 2132 2133 return (NULL); 2134 } 2135 2136 static const char * 2137 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2138 const char *sep) 2139 { 2140 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2141 char human_num[HUMAN_BUFSIZE]; 2142 2143 if (cai->cai_totalsize == 0) 2144 return sep; 2145 2146 if (sep == NULL) 2147 aprint_verbose_dev(ci->ci_dev, ""); 2148 else 2149 aprint_verbose("%s", sep); 2150 if (name != NULL) 2151 aprint_verbose("%s ", name); 2152 2153 if (cai->cai_string != NULL) { 2154 aprint_verbose("%s ", cai->cai_string); 2155 } else { 2156 (void)humanize_number(human_num, sizeof(human_num), 2157 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2158 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2159 } 2160 switch (cai->cai_associativity) { 2161 case 0: 2162 aprint_verbose("disabled"); 2163 break; 2164 case 1: 2165 aprint_verbose("direct-mapped"); 2166 break; 2167 case 0xff: 2168 aprint_verbose("fully associative"); 2169 break; 2170 default: 2171 aprint_verbose("%d-way", cai->cai_associativity); 2172 break; 2173 } 2174 return ", "; 2175 } 2176 2177 static const char * 2178 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2179 const char *sep) 2180 { 2181 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2182 char human_num[HUMAN_BUFSIZE]; 2183 2184 if (cai->cai_totalsize == 0) 2185 return sep; 2186 2187 if (sep == NULL) 2188 aprint_verbose_dev(ci->ci_dev, ""); 2189 else 2190 aprint_verbose("%s", sep); 2191 if (name != NULL) 2192 aprint_verbose("%s ", name); 2193 2194 if (cai->cai_string != NULL) { 2195 aprint_verbose("%s", cai->cai_string); 2196 } else { 2197 (void)humanize_number(human_num, sizeof(human_num), 2198 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2199 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2200 human_num); 2201 switch (cai->cai_associativity) { 2202 case 0: 2203 aprint_verbose("disabled"); 2204 break; 2205 case 1: 2206 aprint_verbose("direct-mapped"); 2207 break; 2208 case 0xff: 2209 aprint_verbose("fully associative"); 2210 break; 2211 default: 2212 aprint_verbose("%d-way", cai->cai_associativity); 2213 break; 2214 } 2215 } 2216 return ", "; 2217 } 2218 2219 static void 2220 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2221 { 2222 const char *sep = NULL; 2223 2224 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2225 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2226 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2227 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2228 if (sep != NULL) 2229 aprint_verbose("\n"); 2230 } 2231 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2232 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2233 if (sep != NULL) 2234 aprint_verbose("\n"); 2235 } 2236 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2237 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2238 if (sep != NULL) 2239 aprint_verbose("\n"); 2240 } 2241 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2242 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2243 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2244 if (sep != NULL) 2245 aprint_verbose("\n"); 2246 } 2247 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2248 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2249 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2250 if (sep != NULL) 2251 aprint_verbose("\n"); 2252 } 2253 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2254 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2255 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2256 if (sep != NULL) 2257 aprint_verbose("\n"); 2258 } 2259 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2260 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2261 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2262 if (sep != NULL) 2263 aprint_verbose("\n"); 2264 } 2265 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2266 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2267 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2268 if (sep != NULL) 2269 aprint_verbose("\n"); 2270 } 2271 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2272 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2273 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2274 if (sep != NULL) 2275 aprint_verbose("\n"); 2276 } 2277 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2278 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2279 NULL); 2280 if (sep != NULL) 2281 aprint_verbose("\n"); 2282 } 2283 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2284 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2285 NULL); 2286 if (sep != NULL) 2287 aprint_verbose("\n"); 2288 } 2289 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2290 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2291 NULL); 2292 if (sep != NULL) 2293 aprint_verbose("\n"); 2294 } 2295 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2296 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2297 NULL); 2298 if (sep != NULL) 2299 aprint_verbose("\n"); 2300 } 2301 } 2302 2303 static void 2304 powernow_probe(struct cpu_info *ci) 2305 { 2306 uint32_t regs[4]; 2307 char buf[256]; 2308 2309 x86_cpuid(0x80000007, regs); 2310 2311 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2312 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2313 buf); 2314 } 2315 2316 bool 2317 identifycpu_bind(void) 2318 { 2319 2320 return true; 2321 } 2322 2323 int 2324 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2325 { 2326 struct cpu_info ci; 2327 int loader_version, res; 2328 struct cpu_ucode_version versreq; 2329 2330 cpu_probe_base_features(&ci, "unknown"); 2331 2332 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2333 loader_version = CPU_UCODE_LOADER_AMD; 2334 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2335 loader_version = CPU_UCODE_LOADER_INTEL1; 2336 else 2337 return -1; 2338 2339 /* check whether the kernel understands this loader version */ 2340 versreq.loader_version = loader_version; 2341 versreq.data = 0; 2342 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2343 if (res) 2344 return -1; 2345 2346 switch (loader_version) { 2347 case CPU_UCODE_LOADER_AMD: 2348 if (uc->cpu_nr != -1) { 2349 /* printf? */ 2350 return -1; 2351 } 2352 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2353 break; 2354 case CPU_UCODE_LOADER_INTEL1: 2355 if (uc->cpu_nr == -1) 2356 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2357 else 2358 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2359 break; 2360 default: /* can't happen */ 2361 return -1; 2362 } 2363 uc->loader_version = loader_version; 2364 return 0; 2365 } 2366
Indexes created Sun Sep 28 16:09:52 GMT 2025