i386.c revision 1.82
1 /* $NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.82 2018/03/05 10:54:05 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[9]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] XCR0 bits (d:0 %eax) 110 * [8] xsave flags (d:1 %eax) 111 */ 112 uint32_t ci_cpu_class; /* CPU class */ 113 uint32_t ci_brand_id; /* Intel brand id */ 114 uint32_t ci_vendor[4]; /* vendor string */ 115 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 116 uint64_t ci_tsc_freq; /* cpu cycles/second */ 117 uint8_t ci_packageid; 118 uint8_t ci_coreid; 119 uint8_t ci_smtid; 120 uint32_t ci_initapicid; 121 122 uint32_t ci_cur_xsave; 123 uint32_t ci_max_xsave; 124 125 struct x86_cache_info ci_cinfo[CAI_COUNT]; 126 void (*ci_info)(struct cpu_info *); 127 }; 128 129 struct cpu_nocpuid_nameclass { 130 int cpu_vendor; 131 const char *cpu_vendorname; 132 const char *cpu_name; 133 int cpu_class; 134 void (*cpu_setup)(struct cpu_info *); 135 void (*cpu_cacheinfo)(struct cpu_info *); 136 void (*cpu_info)(struct cpu_info *); 137 }; 138 139 struct cpu_cpuid_nameclass { 140 const char *cpu_id; 141 int cpu_vendor; 142 const char *cpu_vendorname; 143 struct cpu_cpuid_family { 144 int cpu_class; 145 const char *cpu_models[256]; 146 const char *cpu_model_default; 147 void (*cpu_setup)(struct cpu_info *); 148 void (*cpu_probe)(struct cpu_info *); 149 void (*cpu_info)(struct cpu_info *); 150 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 151 }; 152 153 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 154 155 /* 156 * Map Brand ID from cpuid instruction to brand name. 157 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 158 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 159 * Architectures Software Developer's Manual, Volume 2A". 160 */ 161 static const char * const i386_intel_brand[] = { 162 "", /* Unsupported */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Pentium III", /* Intel (R) Pentium (R) III processor */ 165 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "", /* 0x05: Reserved */ 168 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Celeron", /* Intel (R) Celeron (TM) processor */ 173 "Xeon", /* Intel (R) Xeon (TM) processor */ 174 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 175 "", /* 0x0d: Reserved */ 176 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 177 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 178 "", /* 0x10: Reserved */ 179 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 180 "Celeron M", /* Intel (R) Celeron (R) M processor */ 181 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 182 "Celeron", /* Intel (R) Celeron (R) processor */ 183 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 184 "Pentium M", /* Intel (R) Pentium (R) M processor */ 185 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 186 }; 187 188 /* 189 * AMD processors don't have Brand IDs, so we need these names for probe. 190 */ 191 static const char * const amd_brand[] = { 192 "", 193 "Duron", /* AMD Duron(tm) */ 194 "MP", /* AMD Athlon(tm) MP */ 195 "XP", /* AMD Athlon(tm) XP */ 196 "4" /* AMD Athlon(tm) 4 */ 197 }; 198 199 static int cpu_vendor; 200 static char cpu_brand_string[49]; 201 static char amd_brand_name[48]; 202 static int use_pae, largepagesize; 203 204 /* Setup functions */ 205 static void disable_tsc(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 /* Brand/Model name functions */ 210 static const char *intel_family6_name(struct cpu_info *); 211 static const char *amd_amd64_name(struct cpu_info *); 212 /* Probe functions */ 213 static void amd_family6_probe(struct cpu_info *); 214 static void powernow_probe(struct cpu_info *); 215 static void intel_family_new_probe(struct cpu_info *); 216 static void via_cpu_probe(struct cpu_info *); 217 /* (Cache) Info functions */ 218 static void intel_cpu_cacheinfo(struct cpu_info *); 219 static void amd_cpu_cacheinfo(struct cpu_info *); 220 static void via_cpu_cacheinfo(struct cpu_info *); 221 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 222 static void transmeta_cpu_info(struct cpu_info *); 223 /* Common functions */ 224 static void cpu_probe_base_features(struct cpu_info *, const char *); 225 static void cpu_probe_hv_features(struct cpu_info *, const char *); 226 static void cpu_probe_features(struct cpu_info *); 227 static void print_bits(const char *, const char *, const char *, uint32_t); 228 static void identifycpu_cpuids(struct cpu_info *); 229 static const struct x86_cache_info *cache_info_lookup( 230 const struct x86_cache_info *, uint8_t); 231 static const char *print_cache_config(struct cpu_info *, int, const char *, 232 const char *); 233 static const char *print_tlb_config(struct cpu_info *, int, const char *, 234 const char *); 235 static void x86_print_cache_and_tlb_info(struct cpu_info *); 236 237 /* 238 * Note: these are just the ones that may not have a cpuid instruction. 239 * We deal with the rest in a different way. 240 */ 241 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 242 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 243 NULL, NULL, NULL }, /* CPU_386SX */ 244 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386 */ 246 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 247 NULL, NULL, NULL }, /* CPU_486SX */ 248 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486 */ 250 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486DLC */ 252 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_6x86 */ 254 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 255 NULL, NULL, NULL }, /* CPU_NX586 */ 256 }; 257 258 const char *classnames[] = { 259 "386", 260 "486", 261 "586", 262 "686" 263 }; 264 265 const char *modifiers[] = { 266 "", 267 "OverDrive", 268 "Dual", 269 "" 270 }; 271 272 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 273 { 274 /* 275 * For Intel processors, check Chapter 35Model-specific 276 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 277 * Software Developer's Manual, Volume 3C". 278 */ 279 "GenuineIntel", 280 CPUVENDOR_INTEL, 281 "Intel", 282 /* Family 4 */ 283 { { 284 CPUCLASS_486, 285 { 286 "486DX", "486DX", "486SX", "486DX2", "486SL", 287 "486SX2", 0, "486DX2 W/B Enhanced", 288 "486DX4", 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "486", /* Default */ 291 NULL, 292 NULL, 293 intel_cpu_cacheinfo, 294 }, 295 /* Family 5 */ 296 { 297 CPUCLASS_586, 298 { 299 "Pentium (P5 A-step)", "Pentium (P5)", 300 "Pentium (P54C)", "Pentium (P24T)", 301 "Pentium/MMX", "Pentium", 0, 302 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 303 "Quark X1000", 0, 0, 0, 0, 0, 0, 304 }, 305 "Pentium", /* Default */ 306 NULL, 307 NULL, 308 intel_cpu_cacheinfo, 309 }, 310 /* Family 6 */ 311 { 312 CPUCLASS_686, 313 { 314 [0x00] = "Pentium Pro (A-step)", 315 [0x01] = "Pentium Pro", 316 [0x03] = "Pentium II (Klamath)", 317 [0x04] = "Pentium Pro", 318 [0x05] = "Pentium II/Celeron (Deschutes)", 319 [0x06] = "Celeron (Mendocino)", 320 [0x07] = "Pentium III (Katmai)", 321 [0x08] = "Pentium III (Coppermine)", 322 [0x09] = "Pentium M (Banias)", 323 [0x0a] = "Pentium III Xeon (Cascades)", 324 [0x0b] = "Pentium III (Tualatin)", 325 [0x0d] = "Pentium M (Dothan)", 326 [0x0e] = "Pentium Core Duo, Core solo", 327 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 328 "Core 2 Quad 6xxx, " 329 "Core 2 Extreme 6xxx, " 330 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 331 "and Pentium DC", 332 [0x15] = "EP80579 Integrated Processor", 333 [0x16] = "Celeron (45nm)", 334 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 335 "Core 2 Quad 8xxx and 9xxx", 336 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 337 "(Nehalem)", 338 [0x1c] = "45nm Atom Family", 339 [0x1d] = "XeonMP 74xx (Nehalem)", 340 [0x1e] = "Core i7 and i5", 341 [0x1f] = "Core i7 and i5", 342 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 343 [0x26] = "Atom Family", 344 [0x27] = "Atom Family", 345 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 346 "i3 2xxx", 347 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 348 [0x2d] = "Xeon E5 Sandy Bridge family, " 349 "Core i7-39xx Extreme", 350 [0x2e] = "Xeon 75xx & 65xx", 351 [0x2f] = "Xeon E7 family", 352 [0x35] = "Atom Family", 353 [0x36] = "Atom S1000", 354 [0x37] = "Atom E3000, Z3[67]00", 355 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 356 "Ivy Bridge", 357 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 358 "(Haswell)", 359 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 360 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 361 "Core i7-49xx Extreme", 362 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 363 "Core i7-59xx Extreme", 364 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 365 "(Haswell)", 366 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 369 [0x4a] = "Atom Z3400", 370 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 371 [0x4d] = "Atom C2000", 372 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 373 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 374 [0x55] = "Xeon Scalable (Skylake)", 375 [0x56] = "Xeon D-1500 (Broadwell)", 376 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 377 [0x5a] = "Atom E3500", 378 [0x5c] = "Atom (Goldmont)", 379 [0x5d] = "Atom X3-C3000 (Silvermont)", 380 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 381 [0x5f] = "Atom (Goldmont, Denverton)", 382 [0x66] = "Future Core (Cannon Lake)", 383 [0x7a] = "Atom (Goldmont Plus)", 384 [0x85] = "Future Xeon Phi (Knights Mill)", 385 [0x8e] = "7th gen Core (Kaby Lake)", 386 [0x9e] = "7th gen Core (Kaby Lake)", 387 }, 388 "Pentium Pro, II or III", /* Default */ 389 NULL, 390 intel_family_new_probe, 391 intel_cpu_cacheinfo, 392 }, 393 /* Family > 6 */ 394 { 395 CPUCLASS_686, 396 { 397 0, 0, 0, 0, 0, 0, 0, 0, 398 0, 0, 0, 0, 0, 0, 0, 0, 399 }, 400 "Pentium 4", /* Default */ 401 NULL, 402 intel_family_new_probe, 403 intel_cpu_cacheinfo, 404 } } 405 }, 406 { 407 "AuthenticAMD", 408 CPUVENDOR_AMD, 409 "AMD", 410 /* Family 4 */ 411 { { 412 CPUCLASS_486, 413 { 414 0, 0, 0, "Am486DX2 W/T", 415 0, 0, 0, "Am486DX2 W/B", 416 "Am486DX4 W/T or Am5x86 W/T 150", 417 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 418 0, 0, "Am5x86 W/T 133/160", 419 "Am5x86 W/B 133/160", 420 }, 421 "Am486 or Am5x86", /* Default */ 422 NULL, 423 NULL, 424 NULL, 425 }, 426 /* Family 5 */ 427 { 428 CPUCLASS_586, 429 { 430 "K5", "K5", "K5", "K5", 0, 0, "K6", 431 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 432 "K6-2+/III+", 0, 0, 433 }, 434 "K5 or K6", /* Default */ 435 amd_family5_setup, 436 NULL, 437 amd_cpu_cacheinfo, 438 }, 439 /* Family 6 */ 440 { 441 CPUCLASS_686, 442 { 443 0, "Athlon Model 1", "Athlon Model 2", 444 "Duron", "Athlon Model 4 (Thunderbird)", 445 0, "Athlon", "Duron", "Athlon", 0, 446 "Athlon", 0, 0, 0, 0, 0, 447 }, 448 "K7 (Athlon)", /* Default */ 449 NULL, 450 amd_family6_probe, 451 amd_cpu_cacheinfo, 452 }, 453 /* Family > 6 */ 454 { 455 CPUCLASS_686, 456 { 457 0, 0, 0, 0, 0, 0, 0, 0, 458 0, 0, 0, 0, 0, 0, 0, 0, 459 }, 460 "Unknown K8 (Athlon)", /* Default */ 461 NULL, 462 amd_family6_probe, 463 amd_cpu_cacheinfo, 464 } } 465 }, 466 { 467 "CyrixInstead", 468 CPUVENDOR_CYRIX, 469 "Cyrix", 470 /* Family 4 */ 471 { { 472 CPUCLASS_486, 473 { 474 0, 0, 0, 475 "MediaGX", 476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 477 }, 478 "486", /* Default */ 479 cyrix6x86_cpu_setup, /* XXX ?? */ 480 NULL, 481 NULL, 482 }, 483 /* Family 5 */ 484 { 485 CPUCLASS_586, 486 { 487 0, 0, "6x86", 0, 488 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 490 }, 491 "6x86", /* Default */ 492 cyrix6x86_cpu_setup, 493 NULL, 494 NULL, 495 }, 496 /* Family 6 */ 497 { 498 CPUCLASS_686, 499 { 500 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 502 }, 503 "6x86MX", /* Default */ 504 cyrix6x86_cpu_setup, 505 NULL, 506 NULL, 507 }, 508 /* Family > 6 */ 509 { 510 CPUCLASS_686, 511 { 512 0, 0, 0, 0, 0, 0, 0, 0, 513 0, 0, 0, 0, 0, 0, 0, 0, 514 }, 515 "Unknown 6x86MX", /* Default */ 516 NULL, 517 NULL, 518 NULL, 519 } } 520 }, 521 { /* MediaGX is now owned by National Semiconductor */ 522 "Geode by NSC", 523 CPUVENDOR_CYRIX, /* XXX */ 524 "National Semiconductor", 525 /* Family 4, NSC never had any of these */ 526 { { 527 CPUCLASS_486, 528 { 529 0, 0, 0, 0, 0, 0, 0, 0, 530 0, 0, 0, 0, 0, 0, 0, 0, 531 }, 532 "486 compatible", /* Default */ 533 NULL, 534 NULL, 535 NULL, 536 }, 537 /* Family 5: Geode family, formerly MediaGX */ 538 { 539 CPUCLASS_586, 540 { 541 0, 0, 0, 0, 542 "Geode GX1", 543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 544 }, 545 "Geode", /* Default */ 546 cyrix6x86_cpu_setup, 547 NULL, 548 amd_cpu_cacheinfo, 549 }, 550 /* Family 6, not yet available from NSC */ 551 { 552 CPUCLASS_686, 553 { 554 0, 0, 0, 0, 0, 0, 0, 0, 555 0, 0, 0, 0, 0, 0, 0, 0, 556 }, 557 "Pentium Pro compatible", /* Default */ 558 NULL, 559 NULL, 560 NULL, 561 }, 562 /* Family > 6, not yet available from NSC */ 563 { 564 CPUCLASS_686, 565 { 566 0, 0, 0, 0, 0, 0, 0, 0, 567 0, 0, 0, 0, 0, 0, 0, 0, 568 }, 569 "Pentium Pro compatible", /* Default */ 570 NULL, 571 NULL, 572 NULL, 573 } } 574 }, 575 { 576 "CentaurHauls", 577 CPUVENDOR_IDT, 578 "IDT", 579 /* Family 4, IDT never had any of these */ 580 { { 581 CPUCLASS_486, 582 { 583 0, 0, 0, 0, 0, 0, 0, 0, 584 0, 0, 0, 0, 0, 0, 0, 0, 585 }, 586 "486 compatible", /* Default */ 587 NULL, 588 NULL, 589 NULL, 590 }, 591 /* Family 5 */ 592 { 593 CPUCLASS_586, 594 { 595 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 596 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 597 }, 598 "WinChip", /* Default */ 599 winchip_cpu_setup, 600 NULL, 601 NULL, 602 }, 603 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 604 { 605 CPUCLASS_686, 606 { 607 0, 0, 0, 0, 0, 0, "C3 Samuel", 608 "C3 Samuel 2/Ezra", "C3 Ezra-T", 609 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 610 0, "VIA Nano", 611 }, 612 "Unknown VIA/IDT", /* Default */ 613 NULL, 614 via_cpu_probe, 615 via_cpu_cacheinfo, 616 }, 617 /* Family > 6, not yet available from VIA */ 618 { 619 CPUCLASS_686, 620 { 621 0, 0, 0, 0, 0, 0, 0, 0, 622 0, 0, 0, 0, 0, 0, 0, 0, 623 }, 624 "Pentium Pro compatible", /* Default */ 625 NULL, 626 NULL, 627 NULL, 628 } } 629 }, 630 { 631 "GenuineTMx86", 632 CPUVENDOR_TRANSMETA, 633 "Transmeta", 634 /* Family 4, Transmeta never had any of these */ 635 { { 636 CPUCLASS_486, 637 { 638 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 640 }, 641 "486 compatible", /* Default */ 642 NULL, 643 NULL, 644 NULL, 645 }, 646 /* Family 5 */ 647 { 648 CPUCLASS_586, 649 { 650 0, 0, 0, 0, 0, 0, 0, 0, 651 0, 0, 0, 0, 0, 0, 0, 0, 652 }, 653 "Crusoe", /* Default */ 654 NULL, 655 NULL, 656 transmeta_cpu_info, 657 }, 658 /* Family 6, not yet available from Transmeta */ 659 { 660 CPUCLASS_686, 661 { 662 0, 0, 0, 0, 0, 0, 0, 0, 663 0, 0, 0, 0, 0, 0, 0, 0, 664 }, 665 "Pentium Pro compatible", /* Default */ 666 NULL, 667 NULL, 668 NULL, 669 }, 670 /* Family > 6, not yet available from Transmeta */ 671 { 672 CPUCLASS_686, 673 { 674 0, 0, 0, 0, 0, 0, 0, 0, 675 0, 0, 0, 0, 0, 0, 0, 0, 676 }, 677 "Pentium Pro compatible", /* Default */ 678 NULL, 679 NULL, 680 NULL, 681 } } 682 } 683 }; 684 685 /* 686 * disable the TSC such that we don't use the TSC in microtime(9) 687 * because some CPUs got the implementation wrong. 688 */ 689 static void 690 disable_tsc(struct cpu_info *ci) 691 { 692 if (ci->ci_feat_val[0] & CPUID_TSC) { 693 ci->ci_feat_val[0] &= ~CPUID_TSC; 694 aprint_error("WARNING: broken TSC disabled\n"); 695 } 696 } 697 698 static void 699 amd_family5_setup(struct cpu_info *ci) 700 { 701 702 switch (ci->ci_model) { 703 case 0: /* AMD-K5 Model 0 */ 704 /* 705 * According to the AMD Processor Recognition App Note, 706 * the AMD-K5 Model 0 uses the wrong bit to indicate 707 * support for global PTEs, instead using bit 9 (APIC) 708 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 709 */ 710 if (ci->ci_feat_val[0] & CPUID_APIC) 711 ci->ci_feat_val[0] = 712 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 713 /* 714 * XXX But pmap_pg_g is already initialized -- need to kick 715 * XXX the pmap somehow. How does the MP branch do this? 716 */ 717 break; 718 } 719 } 720 721 static void 722 cyrix6x86_cpu_setup(struct cpu_info *ci) 723 { 724 725 /* 726 * Do not disable the TSC on the Geode GX, it's reported to 727 * work fine. 728 */ 729 if (ci->ci_signature != 0x552) 730 disable_tsc(ci); 731 } 732 733 static void 734 winchip_cpu_setup(struct cpu_info *ci) 735 { 736 switch (ci->ci_model) { 737 case 4: /* WinChip C6 */ 738 disable_tsc(ci); 739 } 740 } 741 742 743 static const char * 744 intel_family6_name(struct cpu_info *ci) 745 { 746 const char *ret = NULL; 747 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 748 749 if (ci->ci_model == 5) { 750 switch (l2cache) { 751 case 0: 752 case 128 * 1024: 753 ret = "Celeron (Covington)"; 754 break; 755 case 256 * 1024: 756 ret = "Mobile Pentium II (Dixon)"; 757 break; 758 case 512 * 1024: 759 ret = "Pentium II"; 760 break; 761 case 1 * 1024 * 1024: 762 case 2 * 1024 * 1024: 763 ret = "Pentium II Xeon"; 764 break; 765 } 766 } else if (ci->ci_model == 6) { 767 switch (l2cache) { 768 case 256 * 1024: 769 case 512 * 1024: 770 ret = "Mobile Pentium II"; 771 break; 772 } 773 } else if (ci->ci_model == 7) { 774 switch (l2cache) { 775 case 512 * 1024: 776 ret = "Pentium III"; 777 break; 778 case 1 * 1024 * 1024: 779 case 2 * 1024 * 1024: 780 ret = "Pentium III Xeon"; 781 break; 782 } 783 } else if (ci->ci_model >= 8) { 784 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 785 switch (ci->ci_brand_id) { 786 case 0x3: 787 if (ci->ci_signature == 0x6B1) 788 ret = "Celeron"; 789 break; 790 case 0x8: 791 if (ci->ci_signature >= 0xF13) 792 ret = "genuine processor"; 793 break; 794 case 0xB: 795 if (ci->ci_signature >= 0xF13) 796 ret = "Xeon MP"; 797 break; 798 case 0xE: 799 if (ci->ci_signature < 0xF13) 800 ret = "Xeon"; 801 break; 802 } 803 if (ret == NULL) 804 ret = i386_intel_brand[ci->ci_brand_id]; 805 } 806 } 807 808 return ret; 809 } 810 811 /* 812 * Identify AMD64 CPU names from cpuid. 813 * 814 * Based on: 815 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 816 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 817 * "Revision Guide for AMD NPT Family 0Fh Processors" 818 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 819 * and other miscellaneous reports. 820 * 821 * This is all rather pointless, these are cross 'brand' since the raw 822 * silicon is shared. 823 */ 824 static const char * 825 amd_amd64_name(struct cpu_info *ci) 826 { 827 static char family_str[32]; 828 829 /* Only called if family >= 15 */ 830 831 switch (ci->ci_family) { 832 case 15: 833 switch (ci->ci_model) { 834 case 0x21: /* rev JH-E1/E6 */ 835 case 0x41: /* rev JH-F2 */ 836 return "Dual-Core Opteron"; 837 case 0x23: /* rev JH-E6 (Toledo) */ 838 return "Dual-Core Opteron or Athlon 64 X2"; 839 case 0x43: /* rev JH-F2 (Windsor) */ 840 return "Athlon 64 FX or Athlon 64 X2"; 841 case 0x24: /* rev SH-E5 (Lancaster?) */ 842 return "Mobile Athlon 64 or Turion 64"; 843 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 844 return "Opteron or Athlon 64 FX"; 845 case 0x15: /* rev SH-D0 */ 846 case 0x25: /* rev SH-E4 */ 847 return "Opteron"; 848 case 0x27: /* rev DH-E4, SH-E4 */ 849 return "Athlon 64 or Athlon 64 FX or Opteron"; 850 case 0x48: /* rev BH-F2 */ 851 return "Turion 64 X2"; 852 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 853 case 0x07: /* rev SH-CG (ClawHammer) */ 854 case 0x0b: /* rev CH-CG */ 855 case 0x14: /* rev SH-D0 */ 856 case 0x17: /* rev SH-D0 */ 857 case 0x1b: /* rev CH-D0 */ 858 return "Athlon 64"; 859 case 0x2b: /* rev BH-E4 (Manchester) */ 860 case 0x4b: /* rev BH-F2 (Windsor) */ 861 return "Athlon 64 X2"; 862 case 0x6b: /* rev BH-G1 (Brisbane) */ 863 return "Athlon X2 or Athlon 64 X2"; 864 case 0x08: /* rev CH-CG */ 865 case 0x0c: /* rev DH-CG (Newcastle) */ 866 case 0x0e: /* rev DH-CG (Newcastle?) */ 867 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 868 case 0x18: /* rev CH-D0 */ 869 case 0x1c: /* rev DH-D0 (Winchester) */ 870 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 871 case 0x2c: /* rev DH-E3/E6 */ 872 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 873 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 874 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 875 case 0x6f: /* rev DH-G1 */ 876 return "Athlon 64 or Sempron"; 877 default: 878 break; 879 } 880 return "Unknown AMD64 CPU"; 881 882 #if 0 883 case 16: 884 return "Family 10h"; 885 case 17: 886 return "Family 11h"; 887 case 18: 888 return "Family 12h"; 889 case 19: 890 return "Family 14h"; 891 case 20: 892 return "Family 15h"; 893 #endif 894 895 default: 896 break; 897 } 898 899 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 900 return family_str; 901 } 902 903 static void 904 intel_family_new_probe(struct cpu_info *ci) 905 { 906 uint32_t descs[4]; 907 908 x86_cpuid(0x80000000, descs); 909 910 /* 911 * Determine extended feature flags. 912 */ 913 if (descs[0] >= 0x80000001) { 914 x86_cpuid(0x80000001, descs); 915 ci->ci_feat_val[2] |= descs[3]; 916 ci->ci_feat_val[3] |= descs[2]; 917 } 918 } 919 920 static void 921 via_cpu_probe(struct cpu_info *ci) 922 { 923 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 924 u_int descs[4]; 925 u_int lfunc; 926 927 /* 928 * Determine the largest extended function value. 929 */ 930 x86_cpuid(0x80000000, descs); 931 lfunc = descs[0]; 932 933 /* 934 * Determine the extended feature flags. 935 */ 936 if (lfunc >= 0x80000001) { 937 x86_cpuid(0x80000001, descs); 938 ci->ci_feat_val[2] |= descs[3]; 939 } 940 941 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 942 return; 943 944 /* Nehemiah or Esther */ 945 x86_cpuid(0xc0000000, descs); 946 lfunc = descs[0]; 947 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 948 return; 949 950 x86_cpuid(0xc0000001, descs); 951 lfunc = descs[3]; 952 ci->ci_feat_val[4] = lfunc; 953 } 954 955 static void 956 amd_family6_probe(struct cpu_info *ci) 957 { 958 uint32_t descs[4]; 959 char *p; 960 size_t i; 961 962 x86_cpuid(0x80000000, descs); 963 964 /* 965 * Determine the extended feature flags. 966 */ 967 if (descs[0] >= 0x80000001) { 968 x86_cpuid(0x80000001, descs); 969 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 970 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 971 } 972 973 if (*cpu_brand_string == '\0') 974 return; 975 976 for (i = 1; i < __arraycount(amd_brand); i++) 977 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 978 ci->ci_brand_id = i; 979 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 980 break; 981 } 982 } 983 984 static void 985 intel_cpu_cacheinfo(struct cpu_info *ci) 986 { 987 const struct x86_cache_info *cai; 988 u_int descs[4]; 989 int iterations, i, j; 990 int type, level; 991 int ways, partitions, linesize, sets; 992 int caitype = -1; 993 int totalsize; 994 uint8_t desc; 995 996 /* Return if the cpu is old pre-cpuid instruction cpu */ 997 if (ci->ci_cpu_type >= 0) 998 return; 999 1000 if (ci->ci_cpuid_level < 2) 1001 return; 1002 1003 /* 1004 * Parse the cache info from `cpuid leaf 2', if we have it. 1005 * XXX This is kinda ugly, but hey, so is the architecture... 1006 */ 1007 x86_cpuid(2, descs); 1008 iterations = descs[0] & 0xff; 1009 while (iterations-- > 0) { 1010 for (i = 0; i < 4; i++) { 1011 if (descs[i] & 0x80000000) 1012 continue; 1013 for (j = 0; j < 4; j++) { 1014 /* 1015 * The least significant byte in EAX 1016 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1017 * it should be ignored. 1018 */ 1019 if (i == 0 && j == 0) 1020 continue; 1021 desc = (descs[i] >> (j * 8)) & 0xff; 1022 if (desc == 0) 1023 continue; 1024 cai = cache_info_lookup(intel_cpuid_cache_info, 1025 desc); 1026 if (cai != NULL) 1027 ci->ci_cinfo[cai->cai_index] = *cai; 1028 else if ((verbose != 0) && (desc != 0xff) 1029 && (desc != 0xfe)) 1030 aprint_error_dev(ci->ci_dev, "error:" 1031 " Unknown cacheinfo desc %02x\n", 1032 desc); 1033 } 1034 } 1035 x86_cpuid(2, descs); 1036 } 1037 1038 if (ci->ci_cpuid_level < 4) 1039 return; 1040 1041 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1042 for (i = 0; ; i++) { 1043 x86_cpuid2(4, i, descs); 1044 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1045 if (type == CPUID_DCP_CACHETYPE_N) 1046 break; 1047 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1048 switch (level) { 1049 case 1: 1050 if (type == CPUID_DCP_CACHETYPE_I) 1051 caitype = CAI_ICACHE; 1052 else if (type == CPUID_DCP_CACHETYPE_D) 1053 caitype = CAI_DCACHE; 1054 else 1055 caitype = -1; 1056 break; 1057 case 2: 1058 if (type == CPUID_DCP_CACHETYPE_U) 1059 caitype = CAI_L2CACHE; 1060 else 1061 caitype = -1; 1062 break; 1063 case 3: 1064 if (type == CPUID_DCP_CACHETYPE_U) 1065 caitype = CAI_L3CACHE; 1066 else 1067 caitype = -1; 1068 break; 1069 default: 1070 caitype = -1; 1071 break; 1072 } 1073 if (caitype == -1) { 1074 aprint_error_dev(ci->ci_dev, 1075 "error: unknown cache level&type (%d & %d)\n", 1076 level, type); 1077 continue; 1078 } 1079 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1080 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1081 + 1; 1082 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1083 + 1; 1084 sets = descs[2] + 1; 1085 totalsize = ways * partitions * linesize * sets; 1086 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1087 ci->ci_cinfo[caitype].cai_associativity = ways; 1088 ci->ci_cinfo[caitype].cai_linesize = linesize; 1089 } 1090 1091 if (ci->ci_cpuid_level < 0x18) 1092 return; 1093 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1094 x86_cpuid(0x18, descs); 1095 iterations = descs[0]; 1096 for (i = 0; i <= iterations; i++) { 1097 bool full; 1098 1099 x86_cpuid2(0x18, i, descs); 1100 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1101 if (type == CPUID_DATP_TCTYPE_N) 1102 continue; 1103 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1104 switch (level) { 1105 case 1: 1106 if (type == CPUID_DATP_TCTYPE_I) 1107 caitype = CAI_ITLB; /* XXX or ITLB2? */ 1108 else if (type == CPUID_DATP_TCTYPE_D) 1109 caitype = CAI_DTLB; 1110 else 1111 caitype = -1; 1112 break; 1113 case 2: 1114 if (type == CPUID_DATP_TCTYPE_I) 1115 caitype = CAI_L2_ITLB; 1116 else if (type == CPUID_DATP_TCTYPE_D) 1117 caitype = CAI_L2_DTLB; 1118 else if (type == CPUID_DATP_TCTYPE_U) 1119 caitype = CAI_L2_STLB; 1120 else 1121 caitype = -1; 1122 break; 1123 case 3: 1124 /* XXX need work for L3 TLB */ 1125 caitype = CAI_L3CACHE; 1126 break; 1127 default: 1128 caitype = -1; 1129 break; 1130 } 1131 if (caitype == -1) { 1132 aprint_error_dev(ci->ci_dev, 1133 "error: unknown TLB level&type (%d & %d)\n", 1134 level, type); 1135 continue; 1136 } 1137 switch (__SHIFTOUT(descs[1], CPUID_DATP_PGSIZE)) { 1138 case CPUID_DATP_PGSIZE_4KB: 1139 linesize = 4 * 1024; 1140 break; 1141 case CPUID_DATP_PGSIZE_2MB: 1142 linesize = 2 * 1024 * 1024; 1143 break; 1144 case CPUID_DATP_PGSIZE_4MB: 1145 linesize = 4 * 1024 * 1024; 1146 break; 1147 case CPUID_DATP_PGSIZE_1GB: 1148 linesize = 1024 * 1024 * 1024; 1149 break; 1150 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1151 aprint_error_dev(ci->ci_dev, 1152 "WARINING: Currently 2M/4M info can't print correctly\n"); 1153 linesize = 4 * 1024 * 1024; 1154 break; 1155 default: 1156 aprint_error_dev(ci->ci_dev, 1157 "error: Unknown size combination\n"); 1158 linesize = 4 * 1024; 1159 break; 1160 } 1161 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1162 sets = descs[2]; 1163 full = descs[3] & CPUID_DATP_FULLASSOC; 1164 ci->ci_cinfo[caitype].cai_totalsize 1165 = ways * sets; /* entries */ 1166 ci->ci_cinfo[caitype].cai_associativity 1167 = full ? 0xff : ways; 1168 ci->ci_cinfo[caitype].cai_linesize = linesize; /* page size */ 1169 } 1170 } 1171 1172 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1173 AMD_L2CACHE_INFO; 1174 1175 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1176 AMD_L3CACHE_INFO; 1177 1178 static void 1179 amd_cpu_cacheinfo(struct cpu_info *ci) 1180 { 1181 const struct x86_cache_info *cp; 1182 struct x86_cache_info *cai; 1183 u_int descs[4]; 1184 u_int lfunc; 1185 1186 /* 1187 * K5 model 0 has none of this info. 1188 */ 1189 if (ci->ci_family == 5 && ci->ci_model == 0) 1190 return; 1191 1192 /* 1193 * Determine the largest extended function value. 1194 */ 1195 x86_cpuid(0x80000000, descs); 1196 lfunc = descs[0]; 1197 1198 /* 1199 * Determine L1 cache/TLB info. 1200 */ 1201 if (lfunc < 0x80000005) { 1202 /* No L1 cache info available. */ 1203 return; 1204 } 1205 1206 x86_cpuid(0x80000005, descs); 1207 1208 /* 1209 * K6-III and higher have large page TLBs. 1210 */ 1211 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1212 cai = &ci->ci_cinfo[CAI_ITLB2]; 1213 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1214 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1215 cai->cai_linesize = largepagesize; 1216 1217 cai = &ci->ci_cinfo[CAI_DTLB2]; 1218 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1219 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1220 cai->cai_linesize = largepagesize; 1221 } 1222 1223 cai = &ci->ci_cinfo[CAI_ITLB]; 1224 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1225 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1226 cai->cai_linesize = (4 * 1024); 1227 1228 cai = &ci->ci_cinfo[CAI_DTLB]; 1229 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1230 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1231 cai->cai_linesize = (4 * 1024); 1232 1233 cai = &ci->ci_cinfo[CAI_DCACHE]; 1234 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1235 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1236 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1237 1238 cai = &ci->ci_cinfo[CAI_ICACHE]; 1239 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1240 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1241 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1242 1243 /* 1244 * Determine L2 cache/TLB info. 1245 */ 1246 if (lfunc < 0x80000006) { 1247 /* No L2 cache info available. */ 1248 return; 1249 } 1250 1251 x86_cpuid(0x80000006, descs); 1252 1253 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1254 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1255 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1256 cai->cai_linesize = (4 * 1024); 1257 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1258 cai->cai_associativity); 1259 if (cp != NULL) 1260 cai->cai_associativity = cp->cai_associativity; 1261 else 1262 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1263 1264 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1265 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1266 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1267 cai->cai_linesize = largepagesize; 1268 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1269 cai->cai_associativity); 1270 if (cp != NULL) 1271 cai->cai_associativity = cp->cai_associativity; 1272 else 1273 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1274 1275 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1276 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1277 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1278 cai->cai_linesize = (4 * 1024); 1279 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1280 cai->cai_associativity); 1281 if (cp != NULL) 1282 cai->cai_associativity = cp->cai_associativity; 1283 else 1284 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1285 1286 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1287 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1288 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1289 cai->cai_linesize = largepagesize; 1290 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1291 cai->cai_associativity); 1292 if (cp != NULL) 1293 cai->cai_associativity = cp->cai_associativity; 1294 else 1295 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1296 1297 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1298 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1299 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1300 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1301 1302 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1303 cai->cai_associativity); 1304 if (cp != NULL) 1305 cai->cai_associativity = cp->cai_associativity; 1306 else 1307 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1308 1309 /* 1310 * Determine L3 cache info on AMD Family 10h and newer processors 1311 */ 1312 if (ci->ci_family >= 0x10) { 1313 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1314 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1315 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1316 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1317 1318 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1319 cai->cai_associativity); 1320 if (cp != NULL) 1321 cai->cai_associativity = cp->cai_associativity; 1322 else 1323 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1324 } 1325 1326 /* 1327 * Determine 1GB TLB info. 1328 */ 1329 if (lfunc < 0x80000019) { 1330 /* No 1GB TLB info available. */ 1331 return; 1332 } 1333 1334 x86_cpuid(0x80000019, descs); 1335 1336 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1337 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1338 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1339 cai->cai_linesize = (1024 * 1024 * 1024); 1340 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1341 cai->cai_associativity); 1342 if (cp != NULL) 1343 cai->cai_associativity = cp->cai_associativity; 1344 else 1345 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1346 1347 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1348 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1349 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1350 cai->cai_linesize = (1024 * 1024 * 1024); 1351 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1352 cai->cai_associativity); 1353 if (cp != NULL) 1354 cai->cai_associativity = cp->cai_associativity; 1355 else 1356 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1357 1358 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1359 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1360 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1361 cai->cai_linesize = (1024 * 1024 * 1024); 1362 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1363 cai->cai_associativity); 1364 if (cp != NULL) 1365 cai->cai_associativity = cp->cai_associativity; 1366 else 1367 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1368 1369 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1370 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1371 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1372 cai->cai_linesize = (1024 * 1024 * 1024); 1373 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1374 cai->cai_associativity); 1375 if (cp != NULL) 1376 cai->cai_associativity = cp->cai_associativity; 1377 else 1378 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1379 } 1380 1381 static void 1382 via_cpu_cacheinfo(struct cpu_info *ci) 1383 { 1384 struct x86_cache_info *cai; 1385 int stepping; 1386 u_int descs[4]; 1387 u_int lfunc; 1388 1389 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1390 1391 /* 1392 * Determine the largest extended function value. 1393 */ 1394 x86_cpuid(0x80000000, descs); 1395 lfunc = descs[0]; 1396 1397 /* 1398 * Determine L1 cache/TLB info. 1399 */ 1400 if (lfunc < 0x80000005) { 1401 /* No L1 cache info available. */ 1402 return; 1403 } 1404 1405 x86_cpuid(0x80000005, descs); 1406 1407 cai = &ci->ci_cinfo[CAI_ITLB]; 1408 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1409 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1410 cai->cai_linesize = (4 * 1024); 1411 1412 cai = &ci->ci_cinfo[CAI_DTLB]; 1413 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1414 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1415 cai->cai_linesize = (4 * 1024); 1416 1417 cai = &ci->ci_cinfo[CAI_DCACHE]; 1418 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1419 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1420 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1421 if (ci->ci_model == 9 && stepping == 8) { 1422 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1423 cai->cai_associativity = 2; 1424 } 1425 1426 cai = &ci->ci_cinfo[CAI_ICACHE]; 1427 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1428 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1429 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1430 if (ci->ci_model == 9 && stepping == 8) { 1431 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1432 cai->cai_associativity = 2; 1433 } 1434 1435 /* 1436 * Determine L2 cache/TLB info. 1437 */ 1438 if (lfunc < 0x80000006) { 1439 /* No L2 cache info available. */ 1440 return; 1441 } 1442 1443 x86_cpuid(0x80000006, descs); 1444 1445 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1446 if (ci->ci_model >= 9) { 1447 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1448 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1449 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1450 } else { 1451 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1452 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1453 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1454 } 1455 } 1456 1457 static void 1458 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1459 { 1460 u_int descs[4]; 1461 1462 x86_cpuid(0x80860007, descs); 1463 *frequency = descs[0]; 1464 *voltage = descs[1]; 1465 *percentage = descs[2]; 1466 } 1467 1468 static void 1469 transmeta_cpu_info(struct cpu_info *ci) 1470 { 1471 u_int descs[4], nreg; 1472 u_int frequency, voltage, percentage; 1473 1474 x86_cpuid(0x80860000, descs); 1475 nreg = descs[0]; 1476 if (nreg >= 0x80860001) { 1477 x86_cpuid(0x80860001, descs); 1478 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1479 (descs[1] >> 24) & 0xff, 1480 (descs[1] >> 16) & 0xff, 1481 (descs[1] >> 8) & 0xff, 1482 descs[1] & 0xff); 1483 } 1484 if (nreg >= 0x80860002) { 1485 x86_cpuid(0x80860002, descs); 1486 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1487 (descs[1] >> 24) & 0xff, 1488 (descs[1] >> 16) & 0xff, 1489 (descs[1] >> 8) & 0xff, 1490 descs[1] & 0xff, 1491 descs[2]); 1492 } 1493 if (nreg >= 0x80860006) { 1494 union { 1495 char text[65]; 1496 u_int descs[4][4]; 1497 } info; 1498 int i; 1499 1500 for (i=0; i<4; i++) { 1501 x86_cpuid(0x80860003 + i, info.descs[i]); 1502 } 1503 info.text[64] = '\0'; 1504 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1505 } 1506 1507 if (nreg >= 0x80860007) { 1508 tmx86_get_longrun_status(&frequency, 1509 &voltage, &percentage); 1510 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1511 frequency, voltage, percentage); 1512 } 1513 } 1514 1515 static void 1516 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1517 { 1518 u_int descs[4]; 1519 int i; 1520 uint32_t brand[12]; 1521 1522 memset(ci, 0, sizeof(*ci)); 1523 ci->ci_dev = cpuname; 1524 1525 ci->ci_cpu_type = x86_identify(); 1526 if (ci->ci_cpu_type >= 0) { 1527 /* Old pre-cpuid instruction cpu */ 1528 ci->ci_cpuid_level = -1; 1529 return; 1530 } 1531 1532 /* 1533 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1534 * function. 1535 */ 1536 1537 /* 1538 * Fn0000_0000: 1539 * - Save cpuid max level. 1540 * - Save vendor string. 1541 */ 1542 x86_cpuid(0, descs); 1543 ci->ci_cpuid_level = descs[0]; 1544 /* Save vendor string */ 1545 ci->ci_vendor[0] = descs[1]; 1546 ci->ci_vendor[2] = descs[2]; 1547 ci->ci_vendor[1] = descs[3]; 1548 ci->ci_vendor[3] = 0; 1549 1550 /* 1551 * Fn8000_0000: 1552 * - Get cpuid extended function's max level. 1553 */ 1554 x86_cpuid(0x80000000, descs); 1555 if (descs[0] >= 0x80000000) 1556 ci->ci_cpuid_extlevel = descs[0]; 1557 else { 1558 /* Set lower value than 0x80000000 */ 1559 ci->ci_cpuid_extlevel = 0; 1560 } 1561 1562 /* 1563 * Fn8000_000[2-4]: 1564 * - Save brand string. 1565 */ 1566 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1567 x86_cpuid(0x80000002, brand); 1568 x86_cpuid(0x80000003, brand + 4); 1569 x86_cpuid(0x80000004, brand + 8); 1570 for (i = 0; i < 48; i++) 1571 if (((char *) brand)[i] != ' ') 1572 break; 1573 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1574 } 1575 1576 if (ci->ci_cpuid_level < 1) 1577 return; 1578 1579 /* 1580 * Fn0000_0001: 1581 * - Get CPU family, model and stepping (from eax). 1582 * - Initial local APIC ID and brand ID (from ebx) 1583 * - CPUID2 (from ecx) 1584 * - CPUID (from edx) 1585 */ 1586 x86_cpuid(1, descs); 1587 ci->ci_signature = descs[0]; 1588 1589 /* Extract full family/model values */ 1590 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1591 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1592 1593 /* Brand is low order 8 bits of ebx */ 1594 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1595 /* Initial local APIC ID */ 1596 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1597 1598 ci->ci_feat_val[1] = descs[2]; 1599 ci->ci_feat_val[0] = descs[3]; 1600 1601 if (ci->ci_cpuid_level < 3) 1602 return; 1603 1604 /* 1605 * If the processor serial number misfeature is present and supported, 1606 * extract it here. 1607 */ 1608 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1609 ci->ci_cpu_serial[0] = ci->ci_signature; 1610 x86_cpuid(3, descs); 1611 ci->ci_cpu_serial[2] = descs[2]; 1612 ci->ci_cpu_serial[1] = descs[3]; 1613 } 1614 1615 if (ci->ci_cpuid_level < 0x7) 1616 return; 1617 1618 x86_cpuid(7, descs); 1619 ci->ci_feat_val[5] = descs[1]; 1620 ci->ci_feat_val[6] = descs[2]; 1621 1622 if (ci->ci_cpuid_level < 0xd) 1623 return; 1624 1625 /* Get support XCR0 bits */ 1626 x86_cpuid2(0xd, 0, descs); 1627 ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */ 1628 ci->ci_cur_xsave = descs[1]; 1629 ci->ci_max_xsave = descs[2]; 1630 1631 /* Additional flags (eg xsaveopt support) */ 1632 x86_cpuid2(0xd, 1, descs); 1633 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1634 } 1635 1636 static void 1637 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1638 { 1639 uint32_t descs[4]; 1640 char hv_sig[13]; 1641 char *p; 1642 const char *hv_name; 1643 int i; 1644 1645 /* 1646 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1647 * http://lkml.org/lkml/2008/10/1/246 1648 * 1649 * KB1009458: Mechanisms to determine if software is running in 1650 * a VMware virtual machine 1651 * http://kb.vmware.com/kb/1009458 1652 */ 1653 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1654 x86_cpuid(0x40000000, descs); 1655 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1656 memcpy(p, &descs[i], sizeof(descs[i])); 1657 *p = '\0'; 1658 /* 1659 * HV vendor ID string 1660 * ------------+-------------- 1661 * KVM "KVMKVMKVM" 1662 * Microsoft "Microsoft Hv" 1663 * VMware "VMwareVMware" 1664 * Xen "XenVMMXenVMM" 1665 */ 1666 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1667 hv_name = "KVM"; 1668 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1669 hv_name = "Hyper-V"; 1670 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1671 hv_name = "VMware"; 1672 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1673 hv_name = "Xen"; 1674 else 1675 hv_name = "unknown"; 1676 1677 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1678 } 1679 } 1680 1681 static void 1682 cpu_probe_features(struct cpu_info *ci) 1683 { 1684 const struct cpu_cpuid_nameclass *cpup = NULL; 1685 unsigned int i; 1686 1687 if (ci->ci_cpuid_level < 1) 1688 return; 1689 1690 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1691 if (!strncmp((char *)ci->ci_vendor, 1692 i386_cpuid_cpus[i].cpu_id, 12)) { 1693 cpup = &i386_cpuid_cpus[i]; 1694 break; 1695 } 1696 } 1697 1698 if (cpup == NULL) 1699 return; 1700 1701 i = ci->ci_family - CPU_MINFAMILY; 1702 1703 if (i >= __arraycount(cpup->cpu_family)) 1704 i = __arraycount(cpup->cpu_family) - 1; 1705 1706 if (cpup->cpu_family[i].cpu_probe == NULL) 1707 return; 1708 1709 (*cpup->cpu_family[i].cpu_probe)(ci); 1710 } 1711 1712 static void 1713 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1714 { 1715 char buf[32 * 16]; 1716 char *bp; 1717 1718 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1719 1720 if (val == 0 || fmt == NULL) 1721 return; 1722 1723 snprintb_m(buf, sizeof(buf), fmt, val, 1724 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1725 bp = buf; 1726 while (*bp != '\0') { 1727 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1728 bp += strlen(bp) + 1; 1729 } 1730 } 1731 1732 static void 1733 identifycpu_cpuids(struct cpu_info *ci) 1734 { 1735 const char *cpuname = ci->ci_dev; 1736 u_int lp_max = 1; /* logical processors per package */ 1737 u_int smt_max; /* smt per core */ 1738 u_int core_max = 1; /* core per package */ 1739 u_int smt_bits, core_bits; 1740 uint32_t descs[4]; 1741 1742 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1743 ci->ci_packageid = ci->ci_initapicid; 1744 ci->ci_coreid = 0; 1745 ci->ci_smtid = 0; 1746 if (cpu_vendor != CPUVENDOR_INTEL) { 1747 return; 1748 } 1749 1750 /* 1751 * 253668.pdf 7.10.2 1752 */ 1753 1754 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1755 x86_cpuid(1, descs); 1756 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1757 } 1758 if (ci->ci_cpuid_level >= 4) { 1759 x86_cpuid2(4, 0, descs); 1760 core_max = (descs[0] >> 26) + 1; 1761 } 1762 assert(lp_max >= core_max); 1763 smt_max = lp_max / core_max; 1764 smt_bits = ilog2(smt_max - 1) + 1; 1765 core_bits = ilog2(core_max - 1) + 1; 1766 if (smt_bits + core_bits) { 1767 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1768 } 1769 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1770 ci->ci_packageid); 1771 if (core_bits) { 1772 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1773 1774 ci->ci_coreid = 1775 __SHIFTOUT(ci->ci_initapicid, core_mask); 1776 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1777 } 1778 if (smt_bits) { 1779 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 1780 1781 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 1782 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1783 } 1784 } 1785 1786 void 1787 identifycpu(int fd, const char *cpuname) 1788 { 1789 const char *name = "", *modifier, *vendorname, *brand = ""; 1790 int class = CPUCLASS_386; 1791 unsigned int i; 1792 int modif, family; 1793 const struct cpu_cpuid_nameclass *cpup = NULL; 1794 const struct cpu_cpuid_family *cpufam; 1795 struct cpu_info *ci, cistore; 1796 u_int descs[4]; 1797 size_t sz; 1798 struct cpu_ucode_version ucode; 1799 union { 1800 struct cpu_ucode_version_amd amd; 1801 struct cpu_ucode_version_intel1 intel1; 1802 } ucvers; 1803 1804 ci = &cistore; 1805 cpu_probe_base_features(ci, cpuname); 1806 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1807 ci->ci_cpuid_level); 1808 if (verbose) { 1809 int bf; 1810 1811 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1812 x86_cpuid(bf, descs); 1813 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1814 bf, descs[0], descs[1], descs[2], descs[3]); 1815 } 1816 } 1817 if (ci->ci_cpuid_extlevel >= 0x80000000) 1818 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1819 ci->ci_cpuid_extlevel); 1820 if (verbose) { 1821 unsigned int ef; 1822 1823 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1824 x86_cpuid(ef, descs); 1825 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1826 ef, descs[0], descs[1], descs[2], descs[3]); 1827 } 1828 } 1829 1830 cpu_probe_hv_features(ci, cpuname); 1831 cpu_probe_features(ci); 1832 1833 if (ci->ci_cpu_type >= 0) { 1834 /* Old pre-cpuid instruction cpu */ 1835 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1836 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1837 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1838 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1839 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1840 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1841 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1842 modifier = ""; 1843 } else { 1844 /* CPU which support cpuid instruction */ 1845 modif = (ci->ci_signature >> 12) & 0x3; 1846 family = ci->ci_family; 1847 if (family < CPU_MINFAMILY) 1848 errx(1, "identifycpu: strange family value"); 1849 if (family > CPU_MAXFAMILY) 1850 family = CPU_MAXFAMILY; 1851 1852 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1853 if (!strncmp((char *)ci->ci_vendor, 1854 i386_cpuid_cpus[i].cpu_id, 12)) { 1855 cpup = &i386_cpuid_cpus[i]; 1856 break; 1857 } 1858 } 1859 1860 if (cpup == NULL) { 1861 cpu_vendor = CPUVENDOR_UNKNOWN; 1862 if (ci->ci_vendor[0] != '\0') 1863 vendorname = (char *)&ci->ci_vendor[0]; 1864 else 1865 vendorname = "Unknown"; 1866 class = family - 3; 1867 modifier = ""; 1868 name = ""; 1869 ci->ci_info = NULL; 1870 } else { 1871 cpu_vendor = cpup->cpu_vendor; 1872 vendorname = cpup->cpu_vendorname; 1873 modifier = modifiers[modif]; 1874 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1875 name = cpufam->cpu_models[ci->ci_model]; 1876 if (name == NULL || *name == '\0') 1877 name = cpufam->cpu_model_default; 1878 class = cpufam->cpu_class; 1879 ci->ci_info = cpufam->cpu_info; 1880 1881 if (cpu_vendor == CPUVENDOR_INTEL) { 1882 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1883 const char *tmp; 1884 tmp = intel_family6_name(ci); 1885 if (tmp != NULL) 1886 name = tmp; 1887 } 1888 if (ci->ci_family == 15 && 1889 ci->ci_brand_id < 1890 __arraycount(i386_intel_brand) && 1891 i386_intel_brand[ci->ci_brand_id]) 1892 name = 1893 i386_intel_brand[ci->ci_brand_id]; 1894 } 1895 1896 if (cpu_vendor == CPUVENDOR_AMD) { 1897 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1898 if (ci->ci_brand_id == 1) 1899 /* 1900 * It's Duron. We override the 1901 * name, since it might have 1902 * been misidentified as Athlon. 1903 */ 1904 name = 1905 amd_brand[ci->ci_brand_id]; 1906 else 1907 brand = amd_brand_name; 1908 } 1909 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 1910 == 0xf) { 1911 /* Identify AMD64 CPU names. */ 1912 const char *tmp; 1913 tmp = amd_amd64_name(ci); 1914 if (tmp != NULL) 1915 name = tmp; 1916 } 1917 } 1918 1919 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1920 vendorname = "VIA"; 1921 } 1922 } 1923 1924 ci->ci_cpu_class = class; 1925 1926 sz = sizeof(ci->ci_tsc_freq); 1927 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1928 sz = sizeof(use_pae); 1929 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1930 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1931 1932 /* 1933 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1934 * we try to determine from the family/model values. 1935 */ 1936 if (*cpu_brand_string != '\0') 1937 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1938 1939 aprint_normal("%s: %s", cpuname, vendorname); 1940 if (*modifier) 1941 aprint_normal(" %s", modifier); 1942 if (*name) 1943 aprint_normal(" %s", name); 1944 if (*brand) 1945 aprint_normal(" %s", brand); 1946 aprint_normal(" (%s-class)", classnames[class]); 1947 1948 if (ci->ci_tsc_freq != 0) 1949 aprint_normal(", %ju.%02ju MHz", 1950 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1951 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1952 aprint_normal("\n"); 1953 1954 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1955 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 1956 if (ci->ci_signature != 0) 1957 aprint_normal(" (id %#x)", ci->ci_signature); 1958 aprint_normal("\n"); 1959 1960 if (ci->ci_info) 1961 (*ci->ci_info)(ci); 1962 1963 /* 1964 * display CPU feature flags 1965 */ 1966 1967 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1968 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1969 1970 /* These next two are actually common definitions! */ 1971 print_bits(cpuname, "features2", 1972 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1973 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1974 print_bits(cpuname, "features3", 1975 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1976 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1977 1978 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1979 ci->ci_feat_val[4]); 1980 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 1981 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 1982 ci->ci_feat_val[5]); 1983 if (cpu_vendor == CPUVENDOR_INTEL) 1984 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 1985 ci->ci_feat_val[6]); 1986 1987 if ((cpu_vendor == CPUVENDOR_INTEL) && (ci->ci_cpuid_level >= 7)) { 1988 x86_cpuid(7, descs); 1989 print_bits(cpuname, "SEF edx", CPUID_SEF_FLAGS2, descs[3]); 1990 } 1991 1992 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]); 1993 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1994 ci->ci_feat_val[8]); 1995 1996 if (ci->ci_max_xsave != 0) { 1997 aprint_normal("%s: xsave area size: current %d, maximum %d", 1998 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1999 aprint_normal(", xgetbv %sabled\n", 2000 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2001 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2002 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2003 x86_xgetbv()); 2004 } 2005 2006 x86_print_cache_and_tlb_info(ci); 2007 2008 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2009 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2010 cpuname, 2011 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2012 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2013 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2014 } 2015 2016 if (ci->ci_cpu_class == CPUCLASS_386) 2017 errx(1, "NetBSD requires an 80486 or later processor"); 2018 2019 if (ci->ci_cpu_type == CPU_486DLC) { 2020 #ifndef CYRIX_CACHE_WORKS 2021 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2022 #else 2023 #ifndef CYRIX_CACHE_REALLY_WORKS 2024 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2025 #else 2026 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2027 #endif 2028 #endif 2029 } 2030 2031 /* 2032 * Everything past this point requires a Pentium or later. 2033 */ 2034 if (ci->ci_cpuid_level < 0) 2035 return; 2036 2037 identifycpu_cpuids(ci); 2038 2039 #ifdef INTEL_CORETEMP 2040 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 2041 coretemp_register(ci); 2042 #endif 2043 2044 if (cpu_vendor == CPUVENDOR_AMD) { 2045 uint32_t data[4]; 2046 2047 x86_cpuid(0x80000000, data); 2048 if (data[0] >= 0x80000007) 2049 powernow_probe(ci); 2050 2051 if ((data[0] >= 0x8000000a) 2052 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2053 x86_cpuid(0x8000000a, data); 2054 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2055 data[0] & 0xf); 2056 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 2057 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 2058 data[3]); 2059 } 2060 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2061 uint32_t data[4]; 2062 int32_t bi_index; 2063 2064 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2065 x86_cpuid(bi_index, data); 2066 switch (bi_index) { 2067 case 6: 2068 print_bits(cpuname, "DSPM-eax", 2069 CPUID_DSPM_FLAGS, data[0]); 2070 print_bits(cpuname, "DSPM-ecx", 2071 CPUID_DSPM_FLAGS1, data[2]); 2072 break; 2073 case 7: 2074 aprint_verbose("%s: SEF highest subleaf %08x\n", 2075 cpuname, data[0]); 2076 break; 2077 #if 0 2078 default: 2079 aprint_verbose("%s: basic %08x-eax %08x\n", 2080 cpuname, bi_index, data[0]); 2081 aprint_verbose("%s: basic %08x-ebx %08x\n", 2082 cpuname, bi_index, data[1]); 2083 aprint_verbose("%s: basic %08x-ecx %08x\n", 2084 cpuname, bi_index, data[2]); 2085 aprint_verbose("%s: basic %08x-edx %08x\n", 2086 cpuname, bi_index, data[3]); 2087 break; 2088 #endif 2089 } 2090 } 2091 } 2092 2093 #ifdef INTEL_ONDEMAND_CLOCKMOD 2094 clockmod_init(); 2095 #endif 2096 2097 if (cpu_vendor == CPUVENDOR_AMD) 2098 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2099 else if (cpu_vendor == CPUVENDOR_INTEL) 2100 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2101 else 2102 return; 2103 2104 ucode.data = &ucvers; 2105 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2106 #ifdef __i386__ 2107 struct cpu_ucode_version_64 ucode_64; 2108 if (errno != ENOTTY) 2109 return; 2110 /* Try the 64 bit ioctl */ 2111 memset(&ucode_64, 0, sizeof ucode_64); 2112 ucode_64.data = &ucvers; 2113 ucode_64.loader_version = ucode.loader_version; 2114 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2115 return; 2116 #else 2117 return; 2118 #endif 2119 } 2120 2121 if (cpu_vendor == CPUVENDOR_AMD) 2122 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2123 else if (cpu_vendor == CPUVENDOR_INTEL) 2124 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2125 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2126 } 2127 2128 static const struct x86_cache_info * 2129 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2130 { 2131 int i; 2132 2133 for (i = 0; cai[i].cai_desc != 0; i++) { 2134 if (cai[i].cai_desc == desc) 2135 return (&cai[i]); 2136 } 2137 2138 return (NULL); 2139 } 2140 2141 static const char * 2142 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2143 const char *sep) 2144 { 2145 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2146 char human_num[HUMAN_BUFSIZE]; 2147 2148 if (cai->cai_totalsize == 0) 2149 return sep; 2150 2151 if (sep == NULL) 2152 aprint_verbose_dev(ci->ci_dev, ""); 2153 else 2154 aprint_verbose("%s", sep); 2155 if (name != NULL) 2156 aprint_verbose("%s ", name); 2157 2158 if (cai->cai_string != NULL) { 2159 aprint_verbose("%s ", cai->cai_string); 2160 } else { 2161 (void)humanize_number(human_num, sizeof(human_num), 2162 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2163 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2164 } 2165 switch (cai->cai_associativity) { 2166 case 0: 2167 aprint_verbose("disabled"); 2168 break; 2169 case 1: 2170 aprint_verbose("direct-mapped"); 2171 break; 2172 case 0xff: 2173 aprint_verbose("fully associative"); 2174 break; 2175 default: 2176 aprint_verbose("%d-way", cai->cai_associativity); 2177 break; 2178 } 2179 return ", "; 2180 } 2181 2182 static const char * 2183 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2184 const char *sep) 2185 { 2186 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2187 char human_num[HUMAN_BUFSIZE]; 2188 2189 if (cai->cai_totalsize == 0) 2190 return sep; 2191 2192 if (sep == NULL) 2193 aprint_verbose_dev(ci->ci_dev, ""); 2194 else 2195 aprint_verbose("%s", sep); 2196 if (name != NULL) 2197 aprint_verbose("%s ", name); 2198 2199 if (cai->cai_string != NULL) { 2200 aprint_verbose("%s", cai->cai_string); 2201 } else { 2202 (void)humanize_number(human_num, sizeof(human_num), 2203 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2204 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2205 human_num); 2206 switch (cai->cai_associativity) { 2207 case 0: 2208 aprint_verbose("disabled"); 2209 break; 2210 case 1: 2211 aprint_verbose("direct-mapped"); 2212 break; 2213 case 0xff: 2214 aprint_verbose("fully associative"); 2215 break; 2216 default: 2217 aprint_verbose("%d-way", cai->cai_associativity); 2218 break; 2219 } 2220 } 2221 return ", "; 2222 } 2223 2224 static void 2225 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2226 { 2227 const char *sep = NULL; 2228 2229 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2230 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2231 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2232 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2233 if (sep != NULL) 2234 aprint_verbose("\n"); 2235 } 2236 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2237 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2238 if (sep != NULL) 2239 aprint_verbose("\n"); 2240 } 2241 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2242 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2243 if (sep != NULL) 2244 aprint_verbose("\n"); 2245 } 2246 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2247 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2248 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2249 if (sep != NULL) 2250 aprint_verbose("\n"); 2251 } 2252 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2253 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2254 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2255 if (sep != NULL) 2256 aprint_verbose("\n"); 2257 } 2258 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2259 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2260 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2261 if (sep != NULL) 2262 aprint_verbose("\n"); 2263 } 2264 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2265 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2266 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2267 if (sep != NULL) 2268 aprint_verbose("\n"); 2269 } 2270 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2271 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2272 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2273 if (sep != NULL) 2274 aprint_verbose("\n"); 2275 } 2276 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2277 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2278 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2279 if (sep != NULL) 2280 aprint_verbose("\n"); 2281 } 2282 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2283 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2284 NULL); 2285 if (sep != NULL) 2286 aprint_verbose("\n"); 2287 } 2288 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2289 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2290 NULL); 2291 if (sep != NULL) 2292 aprint_verbose("\n"); 2293 } 2294 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2295 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2296 NULL); 2297 if (sep != NULL) 2298 aprint_verbose("\n"); 2299 } 2300 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2301 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2302 NULL); 2303 if (sep != NULL) 2304 aprint_verbose("\n"); 2305 } 2306 } 2307 2308 static void 2309 powernow_probe(struct cpu_info *ci) 2310 { 2311 uint32_t regs[4]; 2312 char buf[256]; 2313 2314 x86_cpuid(0x80000007, regs); 2315 2316 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2317 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2318 buf); 2319 } 2320 2321 bool 2322 identifycpu_bind(void) 2323 { 2324 2325 return true; 2326 } 2327 2328 int 2329 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2330 { 2331 struct cpu_info ci; 2332 int loader_version, res; 2333 struct cpu_ucode_version versreq; 2334 2335 cpu_probe_base_features(&ci, "unknown"); 2336 2337 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2338 loader_version = CPU_UCODE_LOADER_AMD; 2339 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2340 loader_version = CPU_UCODE_LOADER_INTEL1; 2341 else 2342 return -1; 2343 2344 /* check whether the kernel understands this loader version */ 2345 versreq.loader_version = loader_version; 2346 versreq.data = 0; 2347 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2348 if (res) 2349 return -1; 2350 2351 switch (loader_version) { 2352 case CPU_UCODE_LOADER_AMD: 2353 if (uc->cpu_nr != -1) { 2354 /* printf? */ 2355 return -1; 2356 } 2357 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2358 break; 2359 case CPU_UCODE_LOADER_INTEL1: 2360 if (uc->cpu_nr == -1) 2361 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2362 else 2363 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2364 break; 2365 default: /* can't happen */ 2366 return -1; 2367 } 2368 uc->loader_version = loader_version; 2369 return 0; 2370 } 2371
Indexes created Thu Oct 23 22:10:10 GMT 2025