i386.c revision 1.82.2.6
1 /* $NetBSD: i386.c,v 1.82.2.6 2019/01/18 08:51:02 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.82.2.6 2019/01/18 08:51:02 pgoyette Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] structure ext. feat. %edx 110 * [8] XCR0 bits (d:0 %eax) 111 * [9] xsave flags (d:1 %eax) 112 */ 113 uint32_t ci_cpu_class; /* CPU class */ 114 uint32_t ci_brand_id; /* Intel brand id */ 115 uint32_t ci_vendor[4]; /* vendor string */ 116 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 117 uint64_t ci_tsc_freq; /* cpu cycles/second */ 118 uint8_t ci_packageid; 119 uint8_t ci_coreid; 120 uint8_t ci_smtid; 121 uint32_t ci_initapicid; 122 123 uint32_t ci_cur_xsave; 124 uint32_t ci_max_xsave; 125 126 struct x86_cache_info ci_cinfo[CAI_COUNT]; 127 void (*ci_info)(struct cpu_info *); 128 }; 129 130 struct cpu_nocpuid_nameclass { 131 int cpu_vendor; 132 const char *cpu_vendorname; 133 const char *cpu_name; 134 int cpu_class; 135 void (*cpu_setup)(struct cpu_info *); 136 void (*cpu_cacheinfo)(struct cpu_info *); 137 void (*cpu_info)(struct cpu_info *); 138 }; 139 140 struct cpu_cpuid_nameclass { 141 const char *cpu_id; 142 int cpu_vendor; 143 const char *cpu_vendorname; 144 struct cpu_cpuid_family { 145 int cpu_class; 146 const char *cpu_models[256]; 147 const char *cpu_model_default; 148 void (*cpu_setup)(struct cpu_info *); 149 void (*cpu_probe)(struct cpu_info *); 150 void (*cpu_info)(struct cpu_info *); 151 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 152 }; 153 154 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 155 156 /* 157 * Map Brand ID from cpuid instruction to brand name. 158 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 159 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 160 * Architectures Software Developer's Manual, Volume 2A". 161 */ 162 static const char * const i386_intel_brand[] = { 163 "", /* Unsupported */ 164 "Celeron", /* Intel (R) Celeron (TM) processor */ 165 "Pentium III", /* Intel (R) Pentium (R) III processor */ 166 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 167 "Pentium III", /* Intel (R) Pentium (R) III processor */ 168 "", /* 0x05: Reserved */ 169 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 170 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 173 "Celeron", /* Intel (R) Celeron (TM) processor */ 174 "Xeon", /* Intel (R) Xeon (TM) processor */ 175 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 176 "", /* 0x0d: Reserved */ 177 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "", /* 0x10: Reserved */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Celeron M", /* Intel (R) Celeron (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 "Celeron", /* Intel (R) Celeron (R) processor */ 184 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 185 "Pentium M", /* Intel (R) Pentium (R) M processor */ 186 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 187 }; 188 189 /* 190 * AMD processors don't have Brand IDs, so we need these names for probe. 191 */ 192 static const char * const amd_brand[] = { 193 "", 194 "Duron", /* AMD Duron(tm) */ 195 "MP", /* AMD Athlon(tm) MP */ 196 "XP", /* AMD Athlon(tm) XP */ 197 "4" /* AMD Athlon(tm) 4 */ 198 }; 199 200 static int cpu_vendor; 201 static char cpu_brand_string[49]; 202 static char amd_brand_name[48]; 203 static int use_pae, largepagesize; 204 205 /* Setup functions */ 206 static void disable_tsc(struct cpu_info *); 207 static void amd_family5_setup(struct cpu_info *); 208 static void cyrix6x86_cpu_setup(struct cpu_info *); 209 static void winchip_cpu_setup(struct cpu_info *); 210 /* Brand/Model name functions */ 211 static const char *intel_family6_name(struct cpu_info *); 212 static const char *amd_amd64_name(struct cpu_info *); 213 /* Probe functions */ 214 static void amd_family6_probe(struct cpu_info *); 215 static void powernow_probe(struct cpu_info *); 216 static void intel_family_new_probe(struct cpu_info *); 217 static void via_cpu_probe(struct cpu_info *); 218 /* (Cache) Info functions */ 219 static void intel_cpu_cacheinfo(struct cpu_info *); 220 static void amd_cpu_cacheinfo(struct cpu_info *); 221 static void via_cpu_cacheinfo(struct cpu_info *); 222 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 223 static void transmeta_cpu_info(struct cpu_info *); 224 /* Common functions */ 225 static void cpu_probe_base_features(struct cpu_info *, const char *); 226 static void cpu_probe_hv_features(struct cpu_info *, const char *); 227 static void cpu_probe_features(struct cpu_info *); 228 static void print_bits(const char *, const char *, const char *, uint32_t); 229 static void identifycpu_cpuids(struct cpu_info *); 230 static const struct x86_cache_info *cache_info_lookup( 231 const struct x86_cache_info *, uint8_t); 232 static const char *print_cache_config(struct cpu_info *, int, const char *, 233 const char *); 234 static const char *print_tlb_config(struct cpu_info *, int, const char *, 235 const char *); 236 static void x86_print_cache_and_tlb_info(struct cpu_info *); 237 238 /* 239 * Note: these are just the ones that may not have a cpuid instruction. 240 * We deal with the rest in a different way. 241 */ 242 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 243 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 244 NULL, NULL, NULL }, /* CPU_386SX */ 245 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 246 NULL, NULL, NULL }, /* CPU_386 */ 247 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486SX */ 249 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_486 */ 251 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 252 NULL, NULL, NULL }, /* CPU_486DLC */ 253 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 254 NULL, NULL, NULL }, /* CPU_6x86 */ 255 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 256 NULL, NULL, NULL }, /* CPU_NX586 */ 257 }; 258 259 const char *classnames[] = { 260 "386", 261 "486", 262 "586", 263 "686" 264 }; 265 266 const char *modifiers[] = { 267 "", 268 "OverDrive", 269 "Dual", 270 "" 271 }; 272 273 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 274 { 275 /* 276 * For Intel processors, check Chapter 35Model-specific 277 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 278 * Software Developer's Manual, Volume 3C". 279 */ 280 "GenuineIntel", 281 CPUVENDOR_INTEL, 282 "Intel", 283 /* Family 4 */ 284 { { 285 CPUCLASS_486, 286 { 287 "486DX", "486DX", "486SX", "486DX2", "486SL", 288 "486SX2", 0, "486DX2 W/B Enhanced", 289 "486DX4", 0, 0, 0, 0, 0, 0, 0, 290 }, 291 "486", /* Default */ 292 NULL, 293 NULL, 294 intel_cpu_cacheinfo, 295 }, 296 /* Family 5 */ 297 { 298 CPUCLASS_586, 299 { 300 "Pentium (P5 A-step)", "Pentium (P5)", 301 "Pentium (P54C)", "Pentium (P24T)", 302 "Pentium/MMX", "Pentium", 0, 303 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 304 "Quark X1000", 0, 0, 0, 0, 0, 0, 305 }, 306 "Pentium", /* Default */ 307 NULL, 308 NULL, 309 intel_cpu_cacheinfo, 310 }, 311 /* Family 6 */ 312 { 313 CPUCLASS_686, 314 { 315 [0x00] = "Pentium Pro (A-step)", 316 [0x01] = "Pentium Pro", 317 [0x03] = "Pentium II (Klamath)", 318 [0x04] = "Pentium Pro", 319 [0x05] = "Pentium II/Celeron (Deschutes)", 320 [0x06] = "Celeron (Mendocino)", 321 [0x07] = "Pentium III (Katmai)", 322 [0x08] = "Pentium III (Coppermine)", 323 [0x09] = "Pentium M (Banias)", 324 [0x0a] = "Pentium III Xeon (Cascades)", 325 [0x0b] = "Pentium III (Tualatin)", 326 [0x0d] = "Pentium M (Dothan)", 327 [0x0e] = "Pentium Core Duo, Core solo", 328 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 329 "Core 2 Quad 6xxx, " 330 "Core 2 Extreme 6xxx, " 331 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 332 "and Pentium DC", 333 [0x15] = "EP80579 Integrated Processor", 334 [0x16] = "Celeron (45nm)", 335 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 336 "Core 2 Quad 8xxx and 9xxx", 337 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 338 "(Nehalem)", 339 [0x1c] = "45nm Atom Family", 340 [0x1d] = "XeonMP 74xx (Nehalem)", 341 [0x1e] = "Core i7 and i5", 342 [0x1f] = "Core i7 and i5", 343 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 344 [0x26] = "Atom Family", 345 [0x27] = "Atom Family", 346 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 347 "i3 2xxx", 348 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 349 [0x2d] = "Xeon E5 Sandy Bridge family, " 350 "Core i7-39xx Extreme", 351 [0x2e] = "Xeon 75xx & 65xx", 352 [0x2f] = "Xeon E7 family", 353 [0x35] = "Atom Family", 354 [0x36] = "Atom S1000", 355 [0x37] = "Atom E3000, Z3[67]00", 356 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 357 "Ivy Bridge", 358 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 359 "(Haswell)", 360 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 361 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 362 "Core i7-49xx Extreme", 363 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 364 "Core i7-59xx Extreme", 365 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 366 "(Haswell)", 367 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 368 "(Haswell)", 369 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 370 [0x4a] = "Atom Z3400", 371 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 372 [0x4d] = "Atom C2000", 373 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 374 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 375 [0x55] = "Xeon Scalable (Skylake)", 376 [0x56] = "Xeon D-1500 (Broadwell)", 377 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 378 [0x5a] = "Atom E3500", 379 [0x5c] = "Atom (Goldmont)", 380 [0x5d] = "Atom X3-C3000 (Silvermont)", 381 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 382 [0x5f] = "Atom (Goldmont, Denverton)", 383 [0x66] = "Future Core (Cannon Lake)", 384 [0x7a] = "Atom (Goldmont Plus)", 385 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 386 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 387 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 388 }, 389 "Pentium Pro, II or III", /* Default */ 390 NULL, 391 intel_family_new_probe, 392 intel_cpu_cacheinfo, 393 }, 394 /* Family > 6 */ 395 { 396 CPUCLASS_686, 397 { 398 0, 0, 0, 0, 0, 0, 0, 0, 399 0, 0, 0, 0, 0, 0, 0, 0, 400 }, 401 "Pentium 4", /* Default */ 402 NULL, 403 intel_family_new_probe, 404 intel_cpu_cacheinfo, 405 } } 406 }, 407 { 408 "AuthenticAMD", 409 CPUVENDOR_AMD, 410 "AMD", 411 /* Family 4 */ 412 { { 413 CPUCLASS_486, 414 { 415 0, 0, 0, "Am486DX2 W/T", 416 0, 0, 0, "Am486DX2 W/B", 417 "Am486DX4 W/T or Am5x86 W/T 150", 418 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 419 0, 0, "Am5x86 W/T 133/160", 420 "Am5x86 W/B 133/160", 421 }, 422 "Am486 or Am5x86", /* Default */ 423 NULL, 424 NULL, 425 NULL, 426 }, 427 /* Family 5 */ 428 { 429 CPUCLASS_586, 430 { 431 "K5", "K5", "K5", "K5", 0, 0, "K6", 432 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 433 "K6-2+/III+", 0, 0, 434 }, 435 "K5 or K6", /* Default */ 436 amd_family5_setup, 437 NULL, 438 amd_cpu_cacheinfo, 439 }, 440 /* Family 6 */ 441 { 442 CPUCLASS_686, 443 { 444 0, "Athlon Model 1", "Athlon Model 2", 445 "Duron", "Athlon Model 4 (Thunderbird)", 446 0, "Athlon", "Duron", "Athlon", 0, 447 "Athlon", 0, 0, 0, 0, 0, 448 }, 449 "K7 (Athlon)", /* Default */ 450 NULL, 451 amd_family6_probe, 452 amd_cpu_cacheinfo, 453 }, 454 /* Family > 6 */ 455 { 456 CPUCLASS_686, 457 { 458 0, 0, 0, 0, 0, 0, 0, 0, 459 0, 0, 0, 0, 0, 0, 0, 0, 460 }, 461 "Unknown K8 (Athlon)", /* Default */ 462 NULL, 463 amd_family6_probe, 464 amd_cpu_cacheinfo, 465 } } 466 }, 467 { 468 "CyrixInstead", 469 CPUVENDOR_CYRIX, 470 "Cyrix", 471 /* Family 4 */ 472 { { 473 CPUCLASS_486, 474 { 475 0, 0, 0, 476 "MediaGX", 477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 478 }, 479 "486", /* Default */ 480 cyrix6x86_cpu_setup, /* XXX ?? */ 481 NULL, 482 NULL, 483 }, 484 /* Family 5 */ 485 { 486 CPUCLASS_586, 487 { 488 0, 0, "6x86", 0, 489 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 491 }, 492 "6x86", /* Default */ 493 cyrix6x86_cpu_setup, 494 NULL, 495 NULL, 496 }, 497 /* Family 6 */ 498 { 499 CPUCLASS_686, 500 { 501 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 502 0, 0, 0, 0, 0, 0, 0, 0, 503 }, 504 "6x86MX", /* Default */ 505 cyrix6x86_cpu_setup, 506 NULL, 507 NULL, 508 }, 509 /* Family > 6 */ 510 { 511 CPUCLASS_686, 512 { 513 0, 0, 0, 0, 0, 0, 0, 0, 514 0, 0, 0, 0, 0, 0, 0, 0, 515 }, 516 "Unknown 6x86MX", /* Default */ 517 NULL, 518 NULL, 519 NULL, 520 } } 521 }, 522 { /* MediaGX is now owned by National Semiconductor */ 523 "Geode by NSC", 524 CPUVENDOR_CYRIX, /* XXX */ 525 "National Semiconductor", 526 /* Family 4, NSC never had any of these */ 527 { { 528 CPUCLASS_486, 529 { 530 0, 0, 0, 0, 0, 0, 0, 0, 531 0, 0, 0, 0, 0, 0, 0, 0, 532 }, 533 "486 compatible", /* Default */ 534 NULL, 535 NULL, 536 NULL, 537 }, 538 /* Family 5: Geode family, formerly MediaGX */ 539 { 540 CPUCLASS_586, 541 { 542 0, 0, 0, 0, 543 "Geode GX1", 544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 545 }, 546 "Geode", /* Default */ 547 cyrix6x86_cpu_setup, 548 NULL, 549 amd_cpu_cacheinfo, 550 }, 551 /* Family 6, not yet available from NSC */ 552 { 553 CPUCLASS_686, 554 { 555 0, 0, 0, 0, 0, 0, 0, 0, 556 0, 0, 0, 0, 0, 0, 0, 0, 557 }, 558 "Pentium Pro compatible", /* Default */ 559 NULL, 560 NULL, 561 NULL, 562 }, 563 /* Family > 6, not yet available from NSC */ 564 { 565 CPUCLASS_686, 566 { 567 0, 0, 0, 0, 0, 0, 0, 0, 568 0, 0, 0, 0, 0, 0, 0, 0, 569 }, 570 "Pentium Pro compatible", /* Default */ 571 NULL, 572 NULL, 573 NULL, 574 } } 575 }, 576 { 577 "CentaurHauls", 578 CPUVENDOR_IDT, 579 "IDT", 580 /* Family 4, IDT never had any of these */ 581 { { 582 CPUCLASS_486, 583 { 584 0, 0, 0, 0, 0, 0, 0, 0, 585 0, 0, 0, 0, 0, 0, 0, 0, 586 }, 587 "486 compatible", /* Default */ 588 NULL, 589 NULL, 590 NULL, 591 }, 592 /* Family 5 */ 593 { 594 CPUCLASS_586, 595 { 596 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 597 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 598 }, 599 "WinChip", /* Default */ 600 winchip_cpu_setup, 601 NULL, 602 NULL, 603 }, 604 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 605 { 606 CPUCLASS_686, 607 { 608 0, 0, 0, 0, 0, 0, "C3 Samuel", 609 "C3 Samuel 2/Ezra", "C3 Ezra-T", 610 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 611 0, "VIA Nano", 612 }, 613 "Unknown VIA/IDT", /* Default */ 614 NULL, 615 via_cpu_probe, 616 via_cpu_cacheinfo, 617 }, 618 /* Family > 6, not yet available from VIA */ 619 { 620 CPUCLASS_686, 621 { 622 0, 0, 0, 0, 0, 0, 0, 0, 623 0, 0, 0, 0, 0, 0, 0, 0, 624 }, 625 "Pentium Pro compatible", /* Default */ 626 NULL, 627 NULL, 628 NULL, 629 } } 630 }, 631 { 632 "GenuineTMx86", 633 CPUVENDOR_TRANSMETA, 634 "Transmeta", 635 /* Family 4, Transmeta never had any of these */ 636 { { 637 CPUCLASS_486, 638 { 639 0, 0, 0, 0, 0, 0, 0, 0, 640 0, 0, 0, 0, 0, 0, 0, 0, 641 }, 642 "486 compatible", /* Default */ 643 NULL, 644 NULL, 645 NULL, 646 }, 647 /* Family 5 */ 648 { 649 CPUCLASS_586, 650 { 651 0, 0, 0, 0, 0, 0, 0, 0, 652 0, 0, 0, 0, 0, 0, 0, 0, 653 }, 654 "Crusoe", /* Default */ 655 NULL, 656 NULL, 657 transmeta_cpu_info, 658 }, 659 /* Family 6, not yet available from Transmeta */ 660 { 661 CPUCLASS_686, 662 { 663 0, 0, 0, 0, 0, 0, 0, 0, 664 0, 0, 0, 0, 0, 0, 0, 0, 665 }, 666 "Pentium Pro compatible", /* Default */ 667 NULL, 668 NULL, 669 NULL, 670 }, 671 /* Family > 6, not yet available from Transmeta */ 672 { 673 CPUCLASS_686, 674 { 675 0, 0, 0, 0, 0, 0, 0, 0, 676 0, 0, 0, 0, 0, 0, 0, 0, 677 }, 678 "Pentium Pro compatible", /* Default */ 679 NULL, 680 NULL, 681 NULL, 682 } } 683 } 684 }; 685 686 /* 687 * disable the TSC such that we don't use the TSC in microtime(9) 688 * because some CPUs got the implementation wrong. 689 */ 690 static void 691 disable_tsc(struct cpu_info *ci) 692 { 693 if (ci->ci_feat_val[0] & CPUID_TSC) { 694 ci->ci_feat_val[0] &= ~CPUID_TSC; 695 aprint_error("WARNING: broken TSC disabled\n"); 696 } 697 } 698 699 static void 700 amd_family5_setup(struct cpu_info *ci) 701 { 702 703 switch (ci->ci_model) { 704 case 0: /* AMD-K5 Model 0 */ 705 /* 706 * According to the AMD Processor Recognition App Note, 707 * the AMD-K5 Model 0 uses the wrong bit to indicate 708 * support for global PTEs, instead using bit 9 (APIC) 709 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 710 */ 711 if (ci->ci_feat_val[0] & CPUID_APIC) 712 ci->ci_feat_val[0] = 713 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 714 /* 715 * XXX But pmap_pg_g is already initialized -- need to kick 716 * XXX the pmap somehow. How does the MP branch do this? 717 */ 718 break; 719 } 720 } 721 722 static void 723 cyrix6x86_cpu_setup(struct cpu_info *ci) 724 { 725 726 /* 727 * Do not disable the TSC on the Geode GX, it's reported to 728 * work fine. 729 */ 730 if (ci->ci_signature != 0x552) 731 disable_tsc(ci); 732 } 733 734 static void 735 winchip_cpu_setup(struct cpu_info *ci) 736 { 737 switch (ci->ci_model) { 738 case 4: /* WinChip C6 */ 739 disable_tsc(ci); 740 } 741 } 742 743 744 static const char * 745 intel_family6_name(struct cpu_info *ci) 746 { 747 const char *ret = NULL; 748 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 749 750 if (ci->ci_model == 5) { 751 switch (l2cache) { 752 case 0: 753 case 128 * 1024: 754 ret = "Celeron (Covington)"; 755 break; 756 case 256 * 1024: 757 ret = "Mobile Pentium II (Dixon)"; 758 break; 759 case 512 * 1024: 760 ret = "Pentium II"; 761 break; 762 case 1 * 1024 * 1024: 763 case 2 * 1024 * 1024: 764 ret = "Pentium II Xeon"; 765 break; 766 } 767 } else if (ci->ci_model == 6) { 768 switch (l2cache) { 769 case 256 * 1024: 770 case 512 * 1024: 771 ret = "Mobile Pentium II"; 772 break; 773 } 774 } else if (ci->ci_model == 7) { 775 switch (l2cache) { 776 case 512 * 1024: 777 ret = "Pentium III"; 778 break; 779 case 1 * 1024 * 1024: 780 case 2 * 1024 * 1024: 781 ret = "Pentium III Xeon"; 782 break; 783 } 784 } else if (ci->ci_model >= 8) { 785 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 786 switch (ci->ci_brand_id) { 787 case 0x3: 788 if (ci->ci_signature == 0x6B1) 789 ret = "Celeron"; 790 break; 791 case 0x8: 792 if (ci->ci_signature >= 0xF13) 793 ret = "genuine processor"; 794 break; 795 case 0xB: 796 if (ci->ci_signature >= 0xF13) 797 ret = "Xeon MP"; 798 break; 799 case 0xE: 800 if (ci->ci_signature < 0xF13) 801 ret = "Xeon"; 802 break; 803 } 804 if (ret == NULL) 805 ret = i386_intel_brand[ci->ci_brand_id]; 806 } 807 } 808 809 return ret; 810 } 811 812 /* 813 * Identify AMD64 CPU names from cpuid. 814 * 815 * Based on: 816 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 817 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 818 * "Revision Guide for AMD NPT Family 0Fh Processors" 819 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 820 * and other miscellaneous reports. 821 * 822 * This is all rather pointless, these are cross 'brand' since the raw 823 * silicon is shared. 824 */ 825 static const char * 826 amd_amd64_name(struct cpu_info *ci) 827 { 828 static char family_str[32]; 829 830 /* Only called if family >= 15 */ 831 832 switch (ci->ci_family) { 833 case 15: 834 switch (ci->ci_model) { 835 case 0x21: /* rev JH-E1/E6 */ 836 case 0x41: /* rev JH-F2 */ 837 return "Dual-Core Opteron"; 838 case 0x23: /* rev JH-E6 (Toledo) */ 839 return "Dual-Core Opteron or Athlon 64 X2"; 840 case 0x43: /* rev JH-F2 (Windsor) */ 841 return "Athlon 64 FX or Athlon 64 X2"; 842 case 0x24: /* rev SH-E5 (Lancaster?) */ 843 return "Mobile Athlon 64 or Turion 64"; 844 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 845 return "Opteron or Athlon 64 FX"; 846 case 0x15: /* rev SH-D0 */ 847 case 0x25: /* rev SH-E4 */ 848 return "Opteron"; 849 case 0x27: /* rev DH-E4, SH-E4 */ 850 return "Athlon 64 or Athlon 64 FX or Opteron"; 851 case 0x48: /* rev BH-F2 */ 852 return "Turion 64 X2"; 853 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 854 case 0x07: /* rev SH-CG (ClawHammer) */ 855 case 0x0b: /* rev CH-CG */ 856 case 0x14: /* rev SH-D0 */ 857 case 0x17: /* rev SH-D0 */ 858 case 0x1b: /* rev CH-D0 */ 859 return "Athlon 64"; 860 case 0x2b: /* rev BH-E4 (Manchester) */ 861 case 0x4b: /* rev BH-F2 (Windsor) */ 862 return "Athlon 64 X2"; 863 case 0x6b: /* rev BH-G1 (Brisbane) */ 864 return "Athlon X2 or Athlon 64 X2"; 865 case 0x08: /* rev CH-CG */ 866 case 0x0c: /* rev DH-CG (Newcastle) */ 867 case 0x0e: /* rev DH-CG (Newcastle?) */ 868 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 869 case 0x18: /* rev CH-D0 */ 870 case 0x1c: /* rev DH-D0 (Winchester) */ 871 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 872 case 0x2c: /* rev DH-E3/E6 */ 873 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 874 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 875 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 876 case 0x6f: /* rev DH-G1 */ 877 return "Athlon 64 or Sempron"; 878 default: 879 break; 880 } 881 return "Unknown AMD64 CPU"; 882 883 #if 0 884 case 16: 885 return "Family 10h"; 886 case 17: 887 return "Family 11h"; 888 case 18: 889 return "Family 12h"; 890 case 19: 891 return "Family 14h"; 892 case 20: 893 return "Family 15h"; 894 #endif 895 896 default: 897 break; 898 } 899 900 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 901 return family_str; 902 } 903 904 static void 905 intel_family_new_probe(struct cpu_info *ci) 906 { 907 uint32_t descs[4]; 908 909 x86_cpuid(0x80000000, descs); 910 911 /* 912 * Determine extended feature flags. 913 */ 914 if (descs[0] >= 0x80000001) { 915 x86_cpuid(0x80000001, descs); 916 ci->ci_feat_val[2] |= descs[3]; 917 ci->ci_feat_val[3] |= descs[2]; 918 } 919 } 920 921 static void 922 via_cpu_probe(struct cpu_info *ci) 923 { 924 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 925 u_int descs[4]; 926 u_int lfunc; 927 928 /* 929 * Determine the largest extended function value. 930 */ 931 x86_cpuid(0x80000000, descs); 932 lfunc = descs[0]; 933 934 /* 935 * Determine the extended feature flags. 936 */ 937 if (lfunc >= 0x80000001) { 938 x86_cpuid(0x80000001, descs); 939 ci->ci_feat_val[2] |= descs[3]; 940 } 941 942 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 943 return; 944 945 /* Nehemiah or Esther */ 946 x86_cpuid(0xc0000000, descs); 947 lfunc = descs[0]; 948 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 949 return; 950 951 x86_cpuid(0xc0000001, descs); 952 lfunc = descs[3]; 953 ci->ci_feat_val[4] = lfunc; 954 } 955 956 static void 957 amd_family6_probe(struct cpu_info *ci) 958 { 959 uint32_t descs[4]; 960 char *p; 961 size_t i; 962 963 x86_cpuid(0x80000000, descs); 964 965 /* 966 * Determine the extended feature flags. 967 */ 968 if (descs[0] >= 0x80000001) { 969 x86_cpuid(0x80000001, descs); 970 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 971 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 972 } 973 974 if (*cpu_brand_string == '\0') 975 return; 976 977 for (i = 1; i < __arraycount(amd_brand); i++) 978 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 979 ci->ci_brand_id = i; 980 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 981 break; 982 } 983 } 984 985 static void 986 intel_cpu_cacheinfo(struct cpu_info *ci) 987 { 988 const struct x86_cache_info *cai; 989 u_int descs[4]; 990 int iterations, i, j; 991 int type, level; 992 int ways, partitions, linesize, sets; 993 int caitype = -1; 994 int totalsize; 995 uint8_t desc; 996 997 /* Return if the cpu is old pre-cpuid instruction cpu */ 998 if (ci->ci_cpu_type >= 0) 999 return; 1000 1001 if (ci->ci_cpuid_level < 2) 1002 return; 1003 1004 /* 1005 * Parse the cache info from `cpuid leaf 2', if we have it. 1006 * XXX This is kinda ugly, but hey, so is the architecture... 1007 */ 1008 x86_cpuid(2, descs); 1009 iterations = descs[0] & 0xff; 1010 while (iterations-- > 0) { 1011 for (i = 0; i < 4; i++) { 1012 if (descs[i] & 0x80000000) 1013 continue; 1014 for (j = 0; j < 4; j++) { 1015 /* 1016 * The least significant byte in EAX 1017 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1018 * it should be ignored. 1019 */ 1020 if (i == 0 && j == 0) 1021 continue; 1022 desc = (descs[i] >> (j * 8)) & 0xff; 1023 if (desc == 0) 1024 continue; 1025 cai = cache_info_lookup(intel_cpuid_cache_info, 1026 desc); 1027 if (cai != NULL) 1028 ci->ci_cinfo[cai->cai_index] = *cai; 1029 else if ((verbose != 0) && (desc != 0xff) 1030 && (desc != 0xfe)) 1031 aprint_error_dev(ci->ci_dev, "error:" 1032 " Unknown cacheinfo desc %02x\n", 1033 desc); 1034 } 1035 } 1036 x86_cpuid(2, descs); 1037 } 1038 1039 if (ci->ci_cpuid_level < 4) 1040 return; 1041 1042 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1043 for (i = 0; ; i++) { 1044 x86_cpuid2(4, i, descs); 1045 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1046 if (type == CPUID_DCP_CACHETYPE_N) 1047 break; 1048 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1049 switch (level) { 1050 case 1: 1051 if (type == CPUID_DCP_CACHETYPE_I) 1052 caitype = CAI_ICACHE; 1053 else if (type == CPUID_DCP_CACHETYPE_D) 1054 caitype = CAI_DCACHE; 1055 else 1056 caitype = -1; 1057 break; 1058 case 2: 1059 if (type == CPUID_DCP_CACHETYPE_U) 1060 caitype = CAI_L2CACHE; 1061 else 1062 caitype = -1; 1063 break; 1064 case 3: 1065 if (type == CPUID_DCP_CACHETYPE_U) 1066 caitype = CAI_L3CACHE; 1067 else 1068 caitype = -1; 1069 break; 1070 default: 1071 caitype = -1; 1072 break; 1073 } 1074 if (caitype == -1) { 1075 aprint_error_dev(ci->ci_dev, 1076 "error: unknown cache level&type (%d & %d)\n", 1077 level, type); 1078 continue; 1079 } 1080 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1081 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1082 + 1; 1083 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1084 + 1; 1085 sets = descs[2] + 1; 1086 totalsize = ways * partitions * linesize * sets; 1087 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1088 ci->ci_cinfo[caitype].cai_associativity = ways; 1089 ci->ci_cinfo[caitype].cai_linesize = linesize; 1090 } 1091 1092 if (ci->ci_cpuid_level < 0x18) 1093 return; 1094 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1095 x86_cpuid(0x18, descs); 1096 iterations = descs[0]; 1097 for (i = 0; i <= iterations; i++) { 1098 uint32_t pgsize; 1099 bool full; 1100 1101 x86_cpuid2(0x18, i, descs); 1102 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1103 if (type == CPUID_DATP_TCTYPE_N) 1104 continue; 1105 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1106 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1107 switch (level) { 1108 case 1: 1109 if (type == CPUID_DATP_TCTYPE_I) { 1110 switch (pgsize) { 1111 case CPUID_DATP_PGSIZE_4KB: 1112 caitype = CAI_ITLB; 1113 break; 1114 case CPUID_DATP_PGSIZE_2MB 1115 | CPUID_DATP_PGSIZE_4MB: 1116 caitype = CAI_ITLB2; 1117 break; 1118 case CPUID_DATP_PGSIZE_1GB: 1119 caitype = CAI_L1_1GBITLB; 1120 break; 1121 default: 1122 aprint_error_dev(ci->ci_dev, 1123 "error: unknown ITLB size (%d)\n", 1124 pgsize); 1125 caitype = CAI_ITLB; 1126 break; 1127 } 1128 } else if (type == CPUID_DATP_TCTYPE_D) { 1129 switch (pgsize) { 1130 case CPUID_DATP_PGSIZE_4KB: 1131 caitype = CAI_DTLB; 1132 break; 1133 case CPUID_DATP_PGSIZE_2MB 1134 | CPUID_DATP_PGSIZE_4MB: 1135 caitype = CAI_DTLB2; 1136 break; 1137 case CPUID_DATP_PGSIZE_1GB: 1138 caitype = CAI_L1_1GBDTLB; 1139 break; 1140 default: 1141 aprint_error_dev(ci->ci_dev, 1142 "error: unknown DTLB size (%d)\n", 1143 pgsize); 1144 caitype = CAI_DTLB; 1145 break; 1146 } 1147 } else 1148 caitype = -1; 1149 break; 1150 case 2: 1151 if (type == CPUID_DATP_TCTYPE_I) 1152 caitype = CAI_L2_ITLB; 1153 else if (type == CPUID_DATP_TCTYPE_D) 1154 caitype = CAI_L2_DTLB; 1155 else if (type == CPUID_DATP_TCTYPE_U) { 1156 switch (pgsize) { 1157 case CPUID_DATP_PGSIZE_4KB: 1158 caitype = CAI_L2_STLB; 1159 break; 1160 case CPUID_DATP_PGSIZE_4KB 1161 | CPUID_DATP_PGSIZE_2MB: 1162 caitype = CAI_L2_STLB2; 1163 break; 1164 case CPUID_DATP_PGSIZE_2MB 1165 | CPUID_DATP_PGSIZE_4MB: 1166 caitype = CAI_L2_STLB3; 1167 break; 1168 default: 1169 aprint_error_dev(ci->ci_dev, 1170 "error: unknown L2 STLB size (%d)\n", 1171 pgsize); 1172 caitype = CAI_DTLB; 1173 break; 1174 } 1175 } else 1176 caitype = -1; 1177 break; 1178 case 3: 1179 /* XXX need work for L3 TLB */ 1180 caitype = CAI_L3CACHE; 1181 break; 1182 default: 1183 caitype = -1; 1184 break; 1185 } 1186 if (caitype == -1) { 1187 aprint_error_dev(ci->ci_dev, 1188 "error: unknown TLB level&type (%d & %d)\n", 1189 level, type); 1190 continue; 1191 } 1192 switch (pgsize) { 1193 case CPUID_DATP_PGSIZE_4KB: 1194 linesize = 4 * 1024; 1195 break; 1196 case CPUID_DATP_PGSIZE_2MB: 1197 linesize = 2 * 1024 * 1024; 1198 break; 1199 case CPUID_DATP_PGSIZE_4MB: 1200 linesize = 4 * 1024 * 1024; 1201 break; 1202 case CPUID_DATP_PGSIZE_1GB: 1203 linesize = 1024 * 1024 * 1024; 1204 break; 1205 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1206 aprint_error_dev(ci->ci_dev, 1207 "WARINING: Currently 2M/4M info can't print correctly\n"); 1208 linesize = 4 * 1024 * 1024; 1209 break; 1210 default: 1211 aprint_error_dev(ci->ci_dev, 1212 "error: Unknown size combination\n"); 1213 linesize = 4 * 1024; 1214 break; 1215 } 1216 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1217 sets = descs[2]; 1218 full = descs[3] & CPUID_DATP_FULLASSOC; 1219 ci->ci_cinfo[caitype].cai_totalsize 1220 = ways * sets; /* entries */ 1221 ci->ci_cinfo[caitype].cai_associativity 1222 = full ? 0xff : ways; 1223 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1224 } 1225 } 1226 1227 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1228 AMD_L2CACHE_INFO; 1229 1230 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1231 AMD_L3CACHE_INFO; 1232 1233 static void 1234 amd_cpu_cacheinfo(struct cpu_info *ci) 1235 { 1236 const struct x86_cache_info *cp; 1237 struct x86_cache_info *cai; 1238 u_int descs[4]; 1239 u_int lfunc; 1240 1241 /* 1242 * K5 model 0 has none of this info. 1243 */ 1244 if (ci->ci_family == 5 && ci->ci_model == 0) 1245 return; 1246 1247 /* 1248 * Determine the largest extended function value. 1249 */ 1250 x86_cpuid(0x80000000, descs); 1251 lfunc = descs[0]; 1252 1253 /* 1254 * Determine L1 cache/TLB info. 1255 */ 1256 if (lfunc < 0x80000005) { 1257 /* No L1 cache info available. */ 1258 return; 1259 } 1260 1261 x86_cpuid(0x80000005, descs); 1262 1263 /* 1264 * K6-III and higher have large page TLBs. 1265 */ 1266 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1267 cai = &ci->ci_cinfo[CAI_ITLB2]; 1268 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1269 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1270 cai->cai_linesize = largepagesize; 1271 1272 cai = &ci->ci_cinfo[CAI_DTLB2]; 1273 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1274 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1275 cai->cai_linesize = largepagesize; 1276 } 1277 1278 cai = &ci->ci_cinfo[CAI_ITLB]; 1279 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1280 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1281 cai->cai_linesize = (4 * 1024); 1282 1283 cai = &ci->ci_cinfo[CAI_DTLB]; 1284 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1285 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1286 cai->cai_linesize = (4 * 1024); 1287 1288 cai = &ci->ci_cinfo[CAI_DCACHE]; 1289 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1290 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1291 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1292 1293 cai = &ci->ci_cinfo[CAI_ICACHE]; 1294 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1295 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1296 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1297 1298 /* 1299 * Determine L2 cache/TLB info. 1300 */ 1301 if (lfunc < 0x80000006) { 1302 /* No L2 cache info available. */ 1303 return; 1304 } 1305 1306 x86_cpuid(0x80000006, descs); 1307 1308 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1309 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1310 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1311 cai->cai_linesize = (4 * 1024); 1312 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1313 cai->cai_associativity); 1314 if (cp != NULL) 1315 cai->cai_associativity = cp->cai_associativity; 1316 else 1317 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1318 1319 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1320 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1321 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1322 cai->cai_linesize = largepagesize; 1323 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1324 cai->cai_associativity); 1325 if (cp != NULL) 1326 cai->cai_associativity = cp->cai_associativity; 1327 else 1328 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1329 1330 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1331 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1332 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1333 cai->cai_linesize = (4 * 1024); 1334 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1335 cai->cai_associativity); 1336 if (cp != NULL) 1337 cai->cai_associativity = cp->cai_associativity; 1338 else 1339 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1340 1341 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1342 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1343 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1344 cai->cai_linesize = largepagesize; 1345 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1346 cai->cai_associativity); 1347 if (cp != NULL) 1348 cai->cai_associativity = cp->cai_associativity; 1349 else 1350 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1351 1352 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1353 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1354 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1355 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1356 1357 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1358 cai->cai_associativity); 1359 if (cp != NULL) 1360 cai->cai_associativity = cp->cai_associativity; 1361 else 1362 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1363 1364 /* 1365 * Determine L3 cache info on AMD Family 10h and newer processors 1366 */ 1367 if (ci->ci_family >= 0x10) { 1368 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1369 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1370 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1371 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1372 1373 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1374 cai->cai_associativity); 1375 if (cp != NULL) 1376 cai->cai_associativity = cp->cai_associativity; 1377 else 1378 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1379 } 1380 1381 /* 1382 * Determine 1GB TLB info. 1383 */ 1384 if (lfunc < 0x80000019) { 1385 /* No 1GB TLB info available. */ 1386 return; 1387 } 1388 1389 x86_cpuid(0x80000019, descs); 1390 1391 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1392 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1393 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1394 cai->cai_linesize = (1024 * 1024 * 1024); 1395 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1396 cai->cai_associativity); 1397 if (cp != NULL) 1398 cai->cai_associativity = cp->cai_associativity; 1399 else 1400 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1401 1402 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1403 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1404 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1405 cai->cai_linesize = (1024 * 1024 * 1024); 1406 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1407 cai->cai_associativity); 1408 if (cp != NULL) 1409 cai->cai_associativity = cp->cai_associativity; 1410 else 1411 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1412 1413 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1414 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1415 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1416 cai->cai_linesize = (1024 * 1024 * 1024); 1417 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1418 cai->cai_associativity); 1419 if (cp != NULL) 1420 cai->cai_associativity = cp->cai_associativity; 1421 else 1422 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1423 1424 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1425 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1426 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1427 cai->cai_linesize = (1024 * 1024 * 1024); 1428 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1429 cai->cai_associativity); 1430 if (cp != NULL) 1431 cai->cai_associativity = cp->cai_associativity; 1432 else 1433 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1434 } 1435 1436 static void 1437 via_cpu_cacheinfo(struct cpu_info *ci) 1438 { 1439 struct x86_cache_info *cai; 1440 int stepping; 1441 u_int descs[4]; 1442 u_int lfunc; 1443 1444 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1445 1446 /* 1447 * Determine the largest extended function value. 1448 */ 1449 x86_cpuid(0x80000000, descs); 1450 lfunc = descs[0]; 1451 1452 /* 1453 * Determine L1 cache/TLB info. 1454 */ 1455 if (lfunc < 0x80000005) { 1456 /* No L1 cache info available. */ 1457 return; 1458 } 1459 1460 x86_cpuid(0x80000005, descs); 1461 1462 cai = &ci->ci_cinfo[CAI_ITLB]; 1463 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1464 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1465 cai->cai_linesize = (4 * 1024); 1466 1467 cai = &ci->ci_cinfo[CAI_DTLB]; 1468 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1469 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1470 cai->cai_linesize = (4 * 1024); 1471 1472 cai = &ci->ci_cinfo[CAI_DCACHE]; 1473 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1474 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1475 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1476 if (ci->ci_model == 9 && stepping == 8) { 1477 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1478 cai->cai_associativity = 2; 1479 } 1480 1481 cai = &ci->ci_cinfo[CAI_ICACHE]; 1482 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1483 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1484 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1485 if (ci->ci_model == 9 && stepping == 8) { 1486 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1487 cai->cai_associativity = 2; 1488 } 1489 1490 /* 1491 * Determine L2 cache/TLB info. 1492 */ 1493 if (lfunc < 0x80000006) { 1494 /* No L2 cache info available. */ 1495 return; 1496 } 1497 1498 x86_cpuid(0x80000006, descs); 1499 1500 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1501 if (ci->ci_model >= 9) { 1502 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1503 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1504 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1505 } else { 1506 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1507 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1508 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1509 } 1510 } 1511 1512 static void 1513 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1514 { 1515 u_int descs[4]; 1516 1517 x86_cpuid(0x80860007, descs); 1518 *frequency = descs[0]; 1519 *voltage = descs[1]; 1520 *percentage = descs[2]; 1521 } 1522 1523 static void 1524 transmeta_cpu_info(struct cpu_info *ci) 1525 { 1526 u_int descs[4], nreg; 1527 u_int frequency, voltage, percentage; 1528 1529 x86_cpuid(0x80860000, descs); 1530 nreg = descs[0]; 1531 if (nreg >= 0x80860001) { 1532 x86_cpuid(0x80860001, descs); 1533 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1534 (descs[1] >> 24) & 0xff, 1535 (descs[1] >> 16) & 0xff, 1536 (descs[1] >> 8) & 0xff, 1537 descs[1] & 0xff); 1538 } 1539 if (nreg >= 0x80860002) { 1540 x86_cpuid(0x80860002, descs); 1541 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1542 (descs[1] >> 24) & 0xff, 1543 (descs[1] >> 16) & 0xff, 1544 (descs[1] >> 8) & 0xff, 1545 descs[1] & 0xff, 1546 descs[2]); 1547 } 1548 if (nreg >= 0x80860006) { 1549 union { 1550 char text[65]; 1551 u_int descs[4][4]; 1552 } info; 1553 int i; 1554 1555 for (i=0; i<4; i++) { 1556 x86_cpuid(0x80860003 + i, info.descs[i]); 1557 } 1558 info.text[64] = '\0'; 1559 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1560 } 1561 1562 if (nreg >= 0x80860007) { 1563 tmx86_get_longrun_status(&frequency, 1564 &voltage, &percentage); 1565 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1566 frequency, voltage, percentage); 1567 } 1568 } 1569 1570 static void 1571 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1572 { 1573 u_int descs[4]; 1574 int i; 1575 uint32_t brand[12]; 1576 1577 memset(ci, 0, sizeof(*ci)); 1578 ci->ci_dev = cpuname; 1579 1580 ci->ci_cpu_type = x86_identify(); 1581 if (ci->ci_cpu_type >= 0) { 1582 /* Old pre-cpuid instruction cpu */ 1583 ci->ci_cpuid_level = -1; 1584 return; 1585 } 1586 1587 /* 1588 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1589 * function. 1590 */ 1591 1592 /* 1593 * Fn0000_0000: 1594 * - Save cpuid max level. 1595 * - Save vendor string. 1596 */ 1597 x86_cpuid(0, descs); 1598 ci->ci_cpuid_level = descs[0]; 1599 /* Save vendor string */ 1600 ci->ci_vendor[0] = descs[1]; 1601 ci->ci_vendor[2] = descs[2]; 1602 ci->ci_vendor[1] = descs[3]; 1603 ci->ci_vendor[3] = 0; 1604 1605 /* 1606 * Fn8000_0000: 1607 * - Get cpuid extended function's max level. 1608 */ 1609 x86_cpuid(0x80000000, descs); 1610 if (descs[0] >= 0x80000000) 1611 ci->ci_cpuid_extlevel = descs[0]; 1612 else { 1613 /* Set lower value than 0x80000000 */ 1614 ci->ci_cpuid_extlevel = 0; 1615 } 1616 1617 /* 1618 * Fn8000_000[2-4]: 1619 * - Save brand string. 1620 */ 1621 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1622 x86_cpuid(0x80000002, brand); 1623 x86_cpuid(0x80000003, brand + 4); 1624 x86_cpuid(0x80000004, brand + 8); 1625 for (i = 0; i < 48; i++) 1626 if (((char *) brand)[i] != ' ') 1627 break; 1628 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1629 } 1630 1631 if (ci->ci_cpuid_level < 1) 1632 return; 1633 1634 /* 1635 * Fn0000_0001: 1636 * - Get CPU family, model and stepping (from eax). 1637 * - Initial local APIC ID and brand ID (from ebx) 1638 * - CPUID2 (from ecx) 1639 * - CPUID (from edx) 1640 */ 1641 x86_cpuid(1, descs); 1642 ci->ci_signature = descs[0]; 1643 1644 /* Extract full family/model values */ 1645 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1646 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1647 1648 /* Brand is low order 8 bits of ebx */ 1649 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1650 /* Initial local APIC ID */ 1651 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1652 1653 ci->ci_feat_val[1] = descs[2]; 1654 ci->ci_feat_val[0] = descs[3]; 1655 1656 if (ci->ci_cpuid_level < 3) 1657 return; 1658 1659 /* 1660 * If the processor serial number misfeature is present and supported, 1661 * extract it here. 1662 */ 1663 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1664 ci->ci_cpu_serial[0] = ci->ci_signature; 1665 x86_cpuid(3, descs); 1666 ci->ci_cpu_serial[2] = descs[2]; 1667 ci->ci_cpu_serial[1] = descs[3]; 1668 } 1669 1670 if (ci->ci_cpuid_level < 0x7) 1671 return; 1672 1673 x86_cpuid(7, descs); 1674 ci->ci_feat_val[5] = descs[1]; 1675 ci->ci_feat_val[6] = descs[2]; 1676 ci->ci_feat_val[7] = descs[3]; 1677 1678 if (ci->ci_cpuid_level < 0xd) 1679 return; 1680 1681 /* Get support XCR0 bits */ 1682 x86_cpuid2(0xd, 0, descs); 1683 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1684 ci->ci_cur_xsave = descs[1]; 1685 ci->ci_max_xsave = descs[2]; 1686 1687 /* Additional flags (eg xsaveopt support) */ 1688 x86_cpuid2(0xd, 1, descs); 1689 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1690 } 1691 1692 static void 1693 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1694 { 1695 uint32_t descs[4]; 1696 char hv_sig[13]; 1697 char *p; 1698 const char *hv_name; 1699 int i; 1700 1701 /* 1702 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1703 * http://lkml.org/lkml/2008/10/1/246 1704 * 1705 * KB1009458: Mechanisms to determine if software is running in 1706 * a VMware virtual machine 1707 * http://kb.vmware.com/kb/1009458 1708 */ 1709 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1710 x86_cpuid(0x40000000, descs); 1711 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1712 memcpy(p, &descs[i], sizeof(descs[i])); 1713 *p = '\0'; 1714 /* 1715 * HV vendor ID string 1716 * ------------+-------------- 1717 * KVM "KVMKVMKVM" 1718 * Microsoft "Microsoft Hv" 1719 * VMware "VMwareVMware" 1720 * Xen "XenVMMXenVMM" 1721 * NetBSD "___ NVMM ___" 1722 */ 1723 if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1724 hv_name = "KVM"; 1725 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1726 hv_name = "Hyper-V"; 1727 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1728 hv_name = "VMware"; 1729 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1730 hv_name = "Xen"; 1731 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1732 hv_name = "NVMM"; 1733 else 1734 hv_name = "unknown"; 1735 1736 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1737 } 1738 } 1739 1740 static void 1741 cpu_probe_features(struct cpu_info *ci) 1742 { 1743 const struct cpu_cpuid_nameclass *cpup = NULL; 1744 unsigned int i; 1745 1746 if (ci->ci_cpuid_level < 1) 1747 return; 1748 1749 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1750 if (!strncmp((char *)ci->ci_vendor, 1751 i386_cpuid_cpus[i].cpu_id, 12)) { 1752 cpup = &i386_cpuid_cpus[i]; 1753 break; 1754 } 1755 } 1756 1757 if (cpup == NULL) 1758 return; 1759 1760 i = ci->ci_family - CPU_MINFAMILY; 1761 1762 if (i >= __arraycount(cpup->cpu_family)) 1763 i = __arraycount(cpup->cpu_family) - 1; 1764 1765 if (cpup->cpu_family[i].cpu_probe == NULL) 1766 return; 1767 1768 (*cpup->cpu_family[i].cpu_probe)(ci); 1769 } 1770 1771 static void 1772 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1773 { 1774 char buf[32 * 16]; 1775 char *bp; 1776 1777 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1778 1779 if (val == 0 || fmt == NULL) 1780 return; 1781 1782 snprintb_m(buf, sizeof(buf), fmt, val, 1783 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1784 bp = buf; 1785 while (*bp != '\0') { 1786 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1787 bp += strlen(bp) + 1; 1788 } 1789 } 1790 1791 static void 1792 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1793 { 1794 u_int lp_max = 1; /* logical processors per package */ 1795 u_int smt_max; /* smt per core */ 1796 u_int core_max = 1; /* core per package */ 1797 u_int smt_bits, core_bits; 1798 uint32_t descs[4]; 1799 1800 /* 1801 * 253668.pdf 7.10.2 1802 */ 1803 1804 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1805 x86_cpuid(1, descs); 1806 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1807 } 1808 x86_cpuid2(4, 0, descs); 1809 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1810 1811 assert(lp_max >= core_max); 1812 smt_max = lp_max / core_max; 1813 smt_bits = ilog2(smt_max - 1) + 1; 1814 core_bits = ilog2(core_max - 1) + 1; 1815 1816 if (smt_bits + core_bits) 1817 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1818 1819 if (core_bits) 1820 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1821 __BITS(smt_bits, smt_bits + core_bits - 1)); 1822 1823 if (smt_bits) 1824 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1825 __BITS((int)0, (int)(smt_bits - 1))); 1826 } 1827 1828 static void 1829 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1830 { 1831 const char *cpuname = ci->ci_dev; 1832 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1833 uint32_t descs[4]; 1834 int i; 1835 1836 x86_cpuid(0x0b, descs); 1837 if (descs[1] == 0) { 1838 identifycpu_cpuids_intel_0x04(ci); 1839 return; 1840 } 1841 1842 for (i = 0; ; i++) { 1843 unsigned int shiftnum, lvltype; 1844 x86_cpuid2(0x0b, i, descs); 1845 1846 /* On invalid level, (EAX and) EBX return 0 */ 1847 if (descs[1] == 0) 1848 break; 1849 1850 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1851 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1852 switch (lvltype) { 1853 case CPUID_TOP_LVLTYPE_SMT: 1854 core_shift = shiftnum; 1855 break; 1856 case CPUID_TOP_LVLTYPE_CORE: 1857 pkg_shift = shiftnum; 1858 break; 1859 case CPUID_TOP_LVLTYPE_INVAL: 1860 aprint_verbose("%s: Invalid level type\n", cpuname); 1861 break; 1862 default: 1863 aprint_verbose("%s: Unknown level type(%d) \n", 1864 cpuname, lvltype); 1865 break; 1866 } 1867 } 1868 1869 assert(pkg_shift >= core_shift); 1870 smt_bits = core_shift; 1871 core_bits = pkg_shift - core_shift; 1872 1873 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1874 1875 if (core_bits) 1876 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1877 __BITS(core_shift, pkg_shift - 1)); 1878 1879 if (smt_bits) 1880 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1881 __BITS((int)0, core_shift - 1)); 1882 } 1883 1884 static void 1885 identifycpu_cpuids_intel(struct cpu_info *ci) 1886 { 1887 const char *cpuname = ci->ci_dev; 1888 1889 if (ci->ci_cpuid_level >= 0x0b) 1890 identifycpu_cpuids_intel_0x0b(ci); 1891 else if (ci->ci_cpuid_level >= 4) 1892 identifycpu_cpuids_intel_0x04(ci); 1893 1894 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1895 ci->ci_packageid); 1896 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1897 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1898 } 1899 1900 static void 1901 identifycpu_cpuids(struct cpu_info *ci) 1902 { 1903 const char *cpuname = ci->ci_dev; 1904 1905 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1906 ci->ci_packageid = ci->ci_initapicid; 1907 ci->ci_coreid = 0; 1908 ci->ci_smtid = 0; 1909 1910 if (cpu_vendor == CPUVENDOR_INTEL) 1911 identifycpu_cpuids_intel(ci); 1912 } 1913 1914 void 1915 identifycpu(int fd, const char *cpuname) 1916 { 1917 const char *name = "", *modifier, *vendorname, *brand = ""; 1918 int class = CPUCLASS_386; 1919 unsigned int i; 1920 int modif, family; 1921 const struct cpu_cpuid_nameclass *cpup = NULL; 1922 const struct cpu_cpuid_family *cpufam; 1923 struct cpu_info *ci, cistore; 1924 u_int descs[4]; 1925 size_t sz; 1926 struct cpu_ucode_version ucode; 1927 union { 1928 struct cpu_ucode_version_amd amd; 1929 struct cpu_ucode_version_intel1 intel1; 1930 } ucvers; 1931 1932 ci = &cistore; 1933 cpu_probe_base_features(ci, cpuname); 1934 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1935 ci->ci_cpuid_level); 1936 if (verbose) { 1937 int bf; 1938 1939 for (bf = 0; bf <= ci->ci_cpuid_level; bf++) { 1940 x86_cpuid(bf, descs); 1941 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1942 bf, descs[0], descs[1], descs[2], descs[3]); 1943 } 1944 } 1945 if (ci->ci_cpuid_extlevel >= 0x80000000) 1946 aprint_verbose("%s: highest extended info %08x\n", cpuname, 1947 ci->ci_cpuid_extlevel); 1948 if (verbose) { 1949 unsigned int ef; 1950 1951 for (ef = 0x80000000; ef <= ci->ci_cpuid_extlevel; ef++) { 1952 x86_cpuid(ef, descs); 1953 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1954 ef, descs[0], descs[1], descs[2], descs[3]); 1955 } 1956 } 1957 1958 cpu_probe_hv_features(ci, cpuname); 1959 cpu_probe_features(ci); 1960 1961 if (ci->ci_cpu_type >= 0) { 1962 /* Old pre-cpuid instruction cpu */ 1963 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1964 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1965 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1966 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1967 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1968 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1969 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1970 modifier = ""; 1971 } else { 1972 /* CPU which support cpuid instruction */ 1973 modif = (ci->ci_signature >> 12) & 0x3; 1974 family = ci->ci_family; 1975 if (family < CPU_MINFAMILY) 1976 errx(1, "identifycpu: strange family value"); 1977 if (family > CPU_MAXFAMILY) 1978 family = CPU_MAXFAMILY; 1979 1980 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1981 if (!strncmp((char *)ci->ci_vendor, 1982 i386_cpuid_cpus[i].cpu_id, 12)) { 1983 cpup = &i386_cpuid_cpus[i]; 1984 break; 1985 } 1986 } 1987 1988 if (cpup == NULL) { 1989 cpu_vendor = CPUVENDOR_UNKNOWN; 1990 if (ci->ci_vendor[0] != '\0') 1991 vendorname = (char *)&ci->ci_vendor[0]; 1992 else 1993 vendorname = "Unknown"; 1994 class = family - 3; 1995 modifier = ""; 1996 name = ""; 1997 ci->ci_info = NULL; 1998 } else { 1999 cpu_vendor = cpup->cpu_vendor; 2000 vendorname = cpup->cpu_vendorname; 2001 modifier = modifiers[modif]; 2002 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2003 name = cpufam->cpu_models[ci->ci_model]; 2004 if (name == NULL || *name == '\0') 2005 name = cpufam->cpu_model_default; 2006 class = cpufam->cpu_class; 2007 ci->ci_info = cpufam->cpu_info; 2008 2009 if (cpu_vendor == CPUVENDOR_INTEL) { 2010 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2011 const char *tmp; 2012 tmp = intel_family6_name(ci); 2013 if (tmp != NULL) 2014 name = tmp; 2015 } 2016 if (ci->ci_family == 15 && 2017 ci->ci_brand_id < 2018 __arraycount(i386_intel_brand) && 2019 i386_intel_brand[ci->ci_brand_id]) 2020 name = 2021 i386_intel_brand[ci->ci_brand_id]; 2022 } 2023 2024 if (cpu_vendor == CPUVENDOR_AMD) { 2025 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2026 if (ci->ci_brand_id == 1) 2027 /* 2028 * It's Duron. We override the 2029 * name, since it might have 2030 * been misidentified as Athlon. 2031 */ 2032 name = 2033 amd_brand[ci->ci_brand_id]; 2034 else 2035 brand = amd_brand_name; 2036 } 2037 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2038 == 0xf) { 2039 /* Identify AMD64 CPU names. */ 2040 const char *tmp; 2041 tmp = amd_amd64_name(ci); 2042 if (tmp != NULL) 2043 name = tmp; 2044 } 2045 } 2046 2047 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2048 vendorname = "VIA"; 2049 } 2050 } 2051 2052 ci->ci_cpu_class = class; 2053 2054 sz = sizeof(ci->ci_tsc_freq); 2055 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2056 sz = sizeof(use_pae); 2057 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2058 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2059 2060 /* 2061 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2062 * we try to determine from the family/model values. 2063 */ 2064 if (*cpu_brand_string != '\0') 2065 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2066 2067 aprint_normal("%s: %s", cpuname, vendorname); 2068 if (*modifier) 2069 aprint_normal(" %s", modifier); 2070 if (*name) 2071 aprint_normal(" %s", name); 2072 if (*brand) 2073 aprint_normal(" %s", brand); 2074 aprint_normal(" (%s-class)", classnames[class]); 2075 2076 if (ci->ci_tsc_freq != 0) 2077 aprint_normal(", %ju.%02ju MHz", 2078 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2079 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2080 aprint_normal("\n"); 2081 2082 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2083 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2084 if (ci->ci_signature != 0) 2085 aprint_normal(" (id %#x)", ci->ci_signature); 2086 aprint_normal("\n"); 2087 2088 if (ci->ci_info) 2089 (*ci->ci_info)(ci); 2090 2091 /* 2092 * display CPU feature flags 2093 */ 2094 2095 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2096 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2097 2098 /* These next two are actually common definitions! */ 2099 print_bits(cpuname, "features2", 2100 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2101 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2102 print_bits(cpuname, "features3", 2103 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2104 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2105 2106 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2107 ci->ci_feat_val[4]); 2108 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2109 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2110 ci->ci_feat_val[5]); 2111 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2112 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2113 ci->ci_feat_val[6]); 2114 2115 if (cpu_vendor == CPUVENDOR_INTEL) 2116 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2117 ci->ci_feat_val[7]); 2118 2119 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2120 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2121 ci->ci_feat_val[9]); 2122 2123 if (ci->ci_max_xsave != 0) { 2124 aprint_normal("%s: xsave area size: current %d, maximum %d", 2125 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2126 aprint_normal(", xgetbv %sabled\n", 2127 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2128 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2129 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2130 x86_xgetbv()); 2131 } 2132 2133 x86_print_cache_and_tlb_info(ci); 2134 2135 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2136 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2137 cpuname, 2138 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2139 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2140 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2141 } 2142 2143 if (ci->ci_cpu_class == CPUCLASS_386) 2144 errx(1, "NetBSD requires an 80486 or later processor"); 2145 2146 if (ci->ci_cpu_type == CPU_486DLC) { 2147 #ifndef CYRIX_CACHE_WORKS 2148 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2149 #else 2150 #ifndef CYRIX_CACHE_REALLY_WORKS 2151 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2152 #else 2153 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2154 #endif 2155 #endif 2156 } 2157 2158 /* 2159 * Everything past this point requires a Pentium or later. 2160 */ 2161 if (ci->ci_cpuid_level < 0) 2162 return; 2163 2164 identifycpu_cpuids(ci); 2165 2166 if ((ci->ci_cpuid_level >= 5) 2167 && ((cpu_vendor == CPUVENDOR_INTEL) 2168 || (cpu_vendor == CPUVENDOR_AMD))) { 2169 uint16_t lmin, lmax; 2170 x86_cpuid(5, descs); 2171 2172 print_bits(cpuname, "MONITOR/MWAIT extensions", 2173 CPUID_MON_FLAGS, descs[2]); 2174 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2175 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2176 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2177 if (lmin != lmax) 2178 aprint_normal("-%hu", lmax); 2179 aprint_normal("\n"); 2180 2181 for (i = 0; i <= 7; i++) { 2182 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2183 2184 if (num != 0) 2185 aprint_normal("%s: C%u substates %u\n", 2186 cpuname, i, num); 2187 } 2188 } 2189 if ((ci->ci_cpuid_level >= 6) 2190 && ((cpu_vendor == CPUVENDOR_INTEL) 2191 || (cpu_vendor == CPUVENDOR_AMD))) { 2192 x86_cpuid(6, descs); 2193 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2194 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2195 } 2196 if ((ci->ci_cpuid_level >= 7) 2197 && ((cpu_vendor == CPUVENDOR_INTEL) 2198 || (cpu_vendor == CPUVENDOR_AMD))) { 2199 x86_cpuid(7, descs); 2200 aprint_verbose("%s: SEF highest subleaf %08x\n", 2201 cpuname, descs[0]); 2202 } 2203 2204 if (cpu_vendor == CPUVENDOR_AMD) { 2205 x86_cpuid(0x80000000, descs); 2206 if (descs[0] >= 0x80000007) 2207 powernow_probe(ci); 2208 2209 if ((descs[0] >= 0x8000000a) 2210 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2211 x86_cpuid(0x8000000a, descs); 2212 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2213 descs[0] & 0xf); 2214 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2215 descs[1]); 2216 print_bits(cpuname, "SVM features", 2217 CPUID_AMD_SVM_FLAGS, descs[3]); 2218 } 2219 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2220 int32_t bi_index; 2221 2222 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2223 x86_cpuid(bi_index, descs); 2224 switch (bi_index) { 2225 case 0x0a: 2226 print_bits(cpuname, "Perfmon-eax", 2227 CPUID_PERF_FLAGS0, descs[0]); 2228 print_bits(cpuname, "Perfmon-ebx", 2229 CPUID_PERF_FLAGS1, descs[1]); 2230 print_bits(cpuname, "Perfmon-edx", 2231 CPUID_PERF_FLAGS3, descs[3]); 2232 break; 2233 default: 2234 #if 0 2235 aprint_verbose("%s: basic %08x-eax %08x\n", 2236 cpuname, bi_index, descs[0]); 2237 aprint_verbose("%s: basic %08x-ebx %08x\n", 2238 cpuname, bi_index, descs[1]); 2239 aprint_verbose("%s: basic %08x-ecx %08x\n", 2240 cpuname, bi_index, descs[2]); 2241 aprint_verbose("%s: basic %08x-edx %08x\n", 2242 cpuname, bi_index, descs[3]); 2243 #endif 2244 break; 2245 } 2246 } 2247 } 2248 2249 #ifdef INTEL_ONDEMAND_CLOCKMOD 2250 clockmod_init(); 2251 #endif 2252 2253 if (cpu_vendor == CPUVENDOR_AMD) 2254 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2255 else if (cpu_vendor == CPUVENDOR_INTEL) 2256 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2257 else 2258 return; 2259 2260 ucode.data = &ucvers; 2261 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2262 #ifdef __i386__ 2263 struct cpu_ucode_version_64 ucode_64; 2264 if (errno != ENOTTY) 2265 return; 2266 /* Try the 64 bit ioctl */ 2267 memset(&ucode_64, 0, sizeof ucode_64); 2268 ucode_64.data = &ucvers; 2269 ucode_64.loader_version = ucode.loader_version; 2270 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2271 return; 2272 #else 2273 return; 2274 #endif 2275 } 2276 2277 if (cpu_vendor == CPUVENDOR_AMD) 2278 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2279 else if (cpu_vendor == CPUVENDOR_INTEL) 2280 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2281 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2282 } 2283 2284 static const struct x86_cache_info * 2285 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2286 { 2287 int i; 2288 2289 for (i = 0; cai[i].cai_desc != 0; i++) { 2290 if (cai[i].cai_desc == desc) 2291 return (&cai[i]); 2292 } 2293 2294 return (NULL); 2295 } 2296 2297 static const char * 2298 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2299 const char *sep) 2300 { 2301 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2302 char human_num[HUMAN_BUFSIZE]; 2303 2304 if (cai->cai_totalsize == 0) 2305 return sep; 2306 2307 if (sep == NULL) 2308 aprint_verbose_dev(ci->ci_dev, ""); 2309 else 2310 aprint_verbose("%s", sep); 2311 if (name != NULL) 2312 aprint_verbose("%s ", name); 2313 2314 if (cai->cai_string != NULL) { 2315 aprint_verbose("%s ", cai->cai_string); 2316 } else { 2317 (void)humanize_number(human_num, sizeof(human_num), 2318 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2319 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2320 } 2321 switch (cai->cai_associativity) { 2322 case 0: 2323 aprint_verbose("disabled"); 2324 break; 2325 case 1: 2326 aprint_verbose("direct-mapped"); 2327 break; 2328 case 0xff: 2329 aprint_verbose("fully associative"); 2330 break; 2331 default: 2332 aprint_verbose("%d-way", cai->cai_associativity); 2333 break; 2334 } 2335 return ", "; 2336 } 2337 2338 static const char * 2339 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2340 const char *sep) 2341 { 2342 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2343 char human_num[HUMAN_BUFSIZE]; 2344 2345 if (cai->cai_totalsize == 0) 2346 return sep; 2347 2348 if (sep == NULL) 2349 aprint_verbose_dev(ci->ci_dev, ""); 2350 else 2351 aprint_verbose("%s", sep); 2352 if (name != NULL) 2353 aprint_verbose("%s ", name); 2354 2355 if (cai->cai_string != NULL) { 2356 aprint_verbose("%s", cai->cai_string); 2357 } else { 2358 (void)humanize_number(human_num, sizeof(human_num), 2359 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2360 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2361 human_num); 2362 switch (cai->cai_associativity) { 2363 case 0: 2364 aprint_verbose("disabled"); 2365 break; 2366 case 1: 2367 aprint_verbose("direct-mapped"); 2368 break; 2369 case 0xff: 2370 aprint_verbose("fully associative"); 2371 break; 2372 default: 2373 aprint_verbose("%d-way", cai->cai_associativity); 2374 break; 2375 } 2376 } 2377 return ", "; 2378 } 2379 2380 static void 2381 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2382 { 2383 const char *sep = NULL; 2384 2385 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2386 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2387 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2388 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2389 if (sep != NULL) 2390 aprint_verbose("\n"); 2391 } 2392 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2393 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2394 if (sep != NULL) 2395 aprint_verbose("\n"); 2396 } 2397 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2398 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2399 if (sep != NULL) 2400 aprint_verbose("\n"); 2401 } 2402 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2403 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2404 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2405 if (sep != NULL) 2406 aprint_verbose("\n"); 2407 } 2408 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2409 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2410 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2411 if (sep != NULL) 2412 aprint_verbose("\n"); 2413 } 2414 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2415 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2416 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2417 if (sep != NULL) 2418 aprint_verbose("\n"); 2419 } 2420 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2421 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2422 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2423 if (sep != NULL) 2424 aprint_verbose("\n"); 2425 } 2426 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2427 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2428 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2429 if (sep != NULL) 2430 aprint_verbose("\n"); 2431 } 2432 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2433 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2434 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2435 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2436 if (sep != NULL) 2437 aprint_verbose("\n"); 2438 } 2439 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2440 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2441 NULL); 2442 if (sep != NULL) 2443 aprint_verbose("\n"); 2444 } 2445 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2446 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2447 NULL); 2448 if (sep != NULL) 2449 aprint_verbose("\n"); 2450 } 2451 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2452 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2453 NULL); 2454 if (sep != NULL) 2455 aprint_verbose("\n"); 2456 } 2457 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2458 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2459 NULL); 2460 if (sep != NULL) 2461 aprint_verbose("\n"); 2462 } 2463 } 2464 2465 static void 2466 powernow_probe(struct cpu_info *ci) 2467 { 2468 uint32_t regs[4]; 2469 char buf[256]; 2470 2471 x86_cpuid(0x80000007, regs); 2472 2473 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2474 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2475 buf); 2476 } 2477 2478 bool 2479 identifycpu_bind(void) 2480 { 2481 2482 return true; 2483 } 2484 2485 int 2486 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2487 { 2488 struct cpu_info ci; 2489 int loader_version, res; 2490 struct cpu_ucode_version versreq; 2491 2492 cpu_probe_base_features(&ci, "unknown"); 2493 2494 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2495 loader_version = CPU_UCODE_LOADER_AMD; 2496 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2497 loader_version = CPU_UCODE_LOADER_INTEL1; 2498 else 2499 return -1; 2500 2501 /* check whether the kernel understands this loader version */ 2502 versreq.loader_version = loader_version; 2503 versreq.data = 0; 2504 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2505 if (res) 2506 return -1; 2507 2508 switch (loader_version) { 2509 case CPU_UCODE_LOADER_AMD: 2510 if (uc->cpu_nr != -1) { 2511 /* printf? */ 2512 return -1; 2513 } 2514 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2515 break; 2516 case CPU_UCODE_LOADER_INTEL1: 2517 if (uc->cpu_nr == -1) 2518 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2519 else 2520 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2521 break; 2522 default: /* can't happen */ 2523 return -1; 2524 } 2525 uc->loader_version = loader_version; 2526 return 0; 2527 } 2528
Indexes created Thu Oct 23 22:10:10 GMT 2025