i386.c revision 1.85.2.3
1 /* $NetBSD: i386.c,v 1.85.2.3 2020/04/21 18:42:47 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.85.2.3 2020/04/21 18:42:47 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t); 182 static void intel_cpu_cacheinfo(struct cpu_info *); 183 static void amd_cpu_cacheinfo(struct cpu_info *); 184 static void via_cpu_cacheinfo(struct cpu_info *); 185 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 186 static void transmeta_cpu_info(struct cpu_info *); 187 /* Common functions */ 188 static void cpu_probe_base_features(struct cpu_info *, const char *); 189 static void cpu_probe_hv_features(struct cpu_info *, const char *); 190 static void cpu_probe_features(struct cpu_info *); 191 static void print_bits(const char *, const char *, const char *, uint32_t); 192 static void identifycpu_cpuids(struct cpu_info *); 193 static const struct x86_cache_info *cache_info_lookup( 194 const struct x86_cache_info *, uint8_t); 195 static const char *print_cache_config(struct cpu_info *, int, const char *, 196 const char *); 197 static const char *print_tlb_config(struct cpu_info *, int, const char *, 198 const char *); 199 static void x86_print_cache_and_tlb_info(struct cpu_info *); 200 201 /* 202 * Note: these are just the ones that may not have a cpuid instruction. 203 * We deal with the rest in a different way. 204 */ 205 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 206 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 207 NULL, NULL, NULL }, /* CPU_386SX */ 208 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 209 NULL, NULL, NULL }, /* CPU_386 */ 210 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 211 NULL, NULL, NULL }, /* CPU_486SX */ 212 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 213 NULL, NULL, NULL }, /* CPU_486 */ 214 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 215 NULL, NULL, NULL }, /* CPU_486DLC */ 216 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 217 NULL, NULL, NULL }, /* CPU_6x86 */ 218 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_NX586 */ 220 }; 221 222 const char *classnames[] = { 223 "386", 224 "486", 225 "586", 226 "686" 227 }; 228 229 const char *modifiers[] = { 230 "", 231 "OverDrive", 232 "Dual", 233 "" 234 }; 235 236 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 237 { 238 /* 239 * For Intel processors, check Chapter 35Model-specific 240 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 241 * Software Developer's Manual, Volume 3C". 242 */ 243 "GenuineIntel", 244 CPUVENDOR_INTEL, 245 "Intel", 246 /* Family 4 */ 247 { { 248 CPUCLASS_486, 249 { 250 "486DX", "486DX", "486SX", "486DX2", "486SL", 251 "486SX2", 0, "486DX2 W/B Enhanced", 252 "486DX4", 0, 0, 0, 0, 0, 0, 0, 253 }, 254 "486", /* Default */ 255 NULL, 256 NULL, 257 intel_cpu_cacheinfo, 258 }, 259 /* Family 5 */ 260 { 261 CPUCLASS_586, 262 { 263 "Pentium (P5 A-step)", "Pentium (P5)", 264 "Pentium (P54C)", "Pentium (P24T)", 265 "Pentium/MMX", "Pentium", 0, 266 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 267 "Quark X1000", 0, 0, 0, 0, 0, 0, 268 }, 269 "Pentium", /* Default */ 270 NULL, 271 NULL, 272 intel_cpu_cacheinfo, 273 }, 274 /* Family 6 */ 275 { 276 CPUCLASS_686, 277 { 278 [0x00] = "Pentium Pro (A-step)", 279 [0x01] = "Pentium Pro", 280 [0x03] = "Pentium II (Klamath)", 281 [0x04] = "Pentium Pro", 282 [0x05] = "Pentium II/Celeron (Deschutes)", 283 [0x06] = "Celeron (Mendocino)", 284 [0x07] = "Pentium III (Katmai)", 285 [0x08] = "Pentium III (Coppermine)", 286 [0x09] = "Pentium M (Banias)", 287 [0x0a] = "Pentium III Xeon (Cascades)", 288 [0x0b] = "Pentium III (Tualatin)", 289 [0x0d] = "Pentium M (Dothan)", 290 [0x0e] = "Pentium Core Duo, Core solo", 291 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 292 "Core 2 Quad 6xxx, " 293 "Core 2 Extreme 6xxx, " 294 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 295 "and Pentium DC", 296 [0x15] = "EP80579 Integrated Processor", 297 [0x16] = "Celeron (45nm)", 298 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 299 "Core 2 Quad 8xxx and 9xxx", 300 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 301 "(Nehalem)", 302 [0x1c] = "45nm Atom Family", 303 [0x1d] = "XeonMP 74xx (Nehalem)", 304 [0x1e] = "Core i7 and i5", 305 [0x1f] = "Core i7 and i5", 306 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 307 [0x26] = "Atom Family", 308 [0x27] = "Atom Family", 309 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 310 "i3 2xxx", 311 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 312 [0x2d] = "Xeon E5 Sandy Bridge family, " 313 "Core i7-39xx Extreme", 314 [0x2e] = "Xeon 75xx & 65xx", 315 [0x2f] = "Xeon E7 family", 316 [0x35] = "Atom Family", 317 [0x36] = "Atom S1000", 318 [0x37] = "Atom E3000, Z3[67]00", 319 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 320 "Ivy Bridge", 321 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 322 "(Haswell)", 323 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 324 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 325 "Core i7-49xx Extreme", 326 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 327 "Core i7-59xx Extreme", 328 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 329 "(Haswell)", 330 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 331 "(Haswell)", 332 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 333 [0x4a] = "Atom Z3400", 334 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 335 [0x4d] = "Atom C2000", 336 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 337 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 338 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 339 [0x56] = "Xeon D-1500 (Broadwell)", 340 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 341 [0x5a] = "Atom E3500", 342 [0x5c] = "Atom (Goldmont)", 343 [0x5d] = "Atom X3-C3000 (Silvermont)", 344 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 345 [0x5f] = "Atom (Goldmont, Denverton)", 346 [0x66] = "8th gen Core i3 (Cannon Lake)", 347 [0x6a] = "Future Xeon (Ice Lake)", 348 [0x6c] = "Future Xeon (Ice Lake)", 349 [0x7a] = "Atom (Goldmont Plus)", 350 [0x7d] = "10th gen Core (Ice Lake)", 351 [0x7e] = "10th gen Core (Ice Lake)", 352 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 353 [0x86] = "Atom (Tremont)", 354 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 355 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 356 }, 357 "Pentium Pro, II or III", /* Default */ 358 NULL, 359 intel_family_new_probe, 360 intel_cpu_cacheinfo, 361 }, 362 /* Family > 6 */ 363 { 364 CPUCLASS_686, 365 { 366 0, 0, 0, 0, 0, 0, 0, 0, 367 0, 0, 0, 0, 0, 0, 0, 0, 368 }, 369 "Pentium 4", /* Default */ 370 NULL, 371 intel_family_new_probe, 372 intel_cpu_cacheinfo, 373 } } 374 }, 375 { 376 "AuthenticAMD", 377 CPUVENDOR_AMD, 378 "AMD", 379 /* Family 4 */ 380 { { 381 CPUCLASS_486, 382 { 383 0, 0, 0, "Am486DX2 W/T", 384 0, 0, 0, "Am486DX2 W/B", 385 "Am486DX4 W/T or Am5x86 W/T 150", 386 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 387 0, 0, "Am5x86 W/T 133/160", 388 "Am5x86 W/B 133/160", 389 }, 390 "Am486 or Am5x86", /* Default */ 391 NULL, 392 NULL, 393 NULL, 394 }, 395 /* Family 5 */ 396 { 397 CPUCLASS_586, 398 { 399 "K5", "K5", "K5", "K5", 0, 0, "K6", 400 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 401 "K6-2+/III+", 0, 0, 402 }, 403 "K5 or K6", /* Default */ 404 amd_family5_setup, 405 NULL, 406 amd_cpu_cacheinfo, 407 }, 408 /* Family 6 */ 409 { 410 CPUCLASS_686, 411 { 412 0, "Athlon Model 1", "Athlon Model 2", 413 "Duron", "Athlon Model 4 (Thunderbird)", 414 0, "Athlon", "Duron", "Athlon", 0, 415 "Athlon", 0, 0, 0, 0, 0, 416 }, 417 "K7 (Athlon)", /* Default */ 418 NULL, 419 amd_family6_probe, 420 amd_cpu_cacheinfo, 421 }, 422 /* Family > 6 */ 423 { 424 CPUCLASS_686, 425 { 426 0, 0, 0, 0, 0, 0, 0, 0, 427 0, 0, 0, 0, 0, 0, 0, 0, 428 }, 429 "Unknown K8 (Athlon)", /* Default */ 430 NULL, 431 amd_family6_probe, 432 amd_cpu_cacheinfo, 433 } } 434 }, 435 { 436 "CyrixInstead", 437 CPUVENDOR_CYRIX, 438 "Cyrix", 439 /* Family 4 */ 440 { { 441 CPUCLASS_486, 442 { 443 0, 0, 0, 444 "MediaGX", 445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 446 }, 447 "486", /* Default */ 448 cyrix6x86_cpu_setup, /* XXX ?? */ 449 NULL, 450 NULL, 451 }, 452 /* Family 5 */ 453 { 454 CPUCLASS_586, 455 { 456 0, 0, "6x86", 0, 457 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 459 }, 460 "6x86", /* Default */ 461 cyrix6x86_cpu_setup, 462 NULL, 463 NULL, 464 }, 465 /* Family 6 */ 466 { 467 CPUCLASS_686, 468 { 469 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 470 0, 0, 0, 0, 0, 0, 0, 0, 471 }, 472 "6x86MX", /* Default */ 473 cyrix6x86_cpu_setup, 474 NULL, 475 NULL, 476 }, 477 /* Family > 6 */ 478 { 479 CPUCLASS_686, 480 { 481 0, 0, 0, 0, 0, 0, 0, 0, 482 0, 0, 0, 0, 0, 0, 0, 0, 483 }, 484 "Unknown 6x86MX", /* Default */ 485 NULL, 486 NULL, 487 NULL, 488 } } 489 }, 490 { /* MediaGX is now owned by National Semiconductor */ 491 "Geode by NSC", 492 CPUVENDOR_CYRIX, /* XXX */ 493 "National Semiconductor", 494 /* Family 4, NSC never had any of these */ 495 { { 496 CPUCLASS_486, 497 { 498 0, 0, 0, 0, 0, 0, 0, 0, 499 0, 0, 0, 0, 0, 0, 0, 0, 500 }, 501 "486 compatible", /* Default */ 502 NULL, 503 NULL, 504 NULL, 505 }, 506 /* Family 5: Geode family, formerly MediaGX */ 507 { 508 CPUCLASS_586, 509 { 510 0, 0, 0, 0, 511 "Geode GX1", 512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 513 }, 514 "Geode", /* Default */ 515 cyrix6x86_cpu_setup, 516 NULL, 517 amd_cpu_cacheinfo, 518 }, 519 /* Family 6, not yet available from NSC */ 520 { 521 CPUCLASS_686, 522 { 523 0, 0, 0, 0, 0, 0, 0, 0, 524 0, 0, 0, 0, 0, 0, 0, 0, 525 }, 526 "Pentium Pro compatible", /* Default */ 527 NULL, 528 NULL, 529 NULL, 530 }, 531 /* Family > 6, not yet available from NSC */ 532 { 533 CPUCLASS_686, 534 { 535 0, 0, 0, 0, 0, 0, 0, 0, 536 0, 0, 0, 0, 0, 0, 0, 0, 537 }, 538 "Pentium Pro compatible", /* Default */ 539 NULL, 540 NULL, 541 NULL, 542 } } 543 }, 544 { 545 "CentaurHauls", 546 CPUVENDOR_IDT, 547 "IDT", 548 /* Family 4, IDT never had any of these */ 549 { { 550 CPUCLASS_486, 551 { 552 0, 0, 0, 0, 0, 0, 0, 0, 553 0, 0, 0, 0, 0, 0, 0, 0, 554 }, 555 "486 compatible", /* Default */ 556 NULL, 557 NULL, 558 NULL, 559 }, 560 /* Family 5 */ 561 { 562 CPUCLASS_586, 563 { 564 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 565 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 566 }, 567 "WinChip", /* Default */ 568 winchip_cpu_setup, 569 NULL, 570 NULL, 571 }, 572 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 573 { 574 CPUCLASS_686, 575 { 576 0, 0, 0, 0, 0, 0, "C3 Samuel", 577 "C3 Samuel 2/Ezra", "C3 Ezra-T", 578 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 579 0, "VIA Nano", 580 }, 581 "Unknown VIA/IDT", /* Default */ 582 NULL, 583 via_cpu_probe, 584 via_cpu_cacheinfo, 585 }, 586 /* Family > 6, not yet available from VIA */ 587 { 588 CPUCLASS_686, 589 { 590 0, 0, 0, 0, 0, 0, 0, 0, 591 0, 0, 0, 0, 0, 0, 0, 0, 592 }, 593 "Pentium Pro compatible", /* Default */ 594 NULL, 595 NULL, 596 NULL, 597 } } 598 }, 599 { 600 "GenuineTMx86", 601 CPUVENDOR_TRANSMETA, 602 "Transmeta", 603 /* Family 4, Transmeta never had any of these */ 604 { { 605 CPUCLASS_486, 606 { 607 0, 0, 0, 0, 0, 0, 0, 0, 608 0, 0, 0, 0, 0, 0, 0, 0, 609 }, 610 "486 compatible", /* Default */ 611 NULL, 612 NULL, 613 NULL, 614 }, 615 /* Family 5 */ 616 { 617 CPUCLASS_586, 618 { 619 0, 0, 0, 0, 0, 0, 0, 0, 620 0, 0, 0, 0, 0, 0, 0, 0, 621 }, 622 "Crusoe", /* Default */ 623 NULL, 624 NULL, 625 transmeta_cpu_info, 626 }, 627 /* Family 6, not yet available from Transmeta */ 628 { 629 CPUCLASS_686, 630 { 631 0, 0, 0, 0, 0, 0, 0, 0, 632 0, 0, 0, 0, 0, 0, 0, 0, 633 }, 634 "Pentium Pro compatible", /* Default */ 635 NULL, 636 NULL, 637 NULL, 638 }, 639 /* Family > 6, not yet available from Transmeta */ 640 { 641 CPUCLASS_686, 642 { 643 0, 0, 0, 0, 0, 0, 0, 0, 644 0, 0, 0, 0, 0, 0, 0, 0, 645 }, 646 "Pentium Pro compatible", /* Default */ 647 NULL, 648 NULL, 649 NULL, 650 } } 651 } 652 }; 653 654 /* 655 * disable the TSC such that we don't use the TSC in microtime(9) 656 * because some CPUs got the implementation wrong. 657 */ 658 static void 659 disable_tsc(struct cpu_info *ci) 660 { 661 if (ci->ci_feat_val[0] & CPUID_TSC) { 662 ci->ci_feat_val[0] &= ~CPUID_TSC; 663 aprint_error("WARNING: broken TSC disabled\n"); 664 } 665 } 666 667 static void 668 amd_family5_setup(struct cpu_info *ci) 669 { 670 671 switch (ci->ci_model) { 672 case 0: /* AMD-K5 Model 0 */ 673 /* 674 * According to the AMD Processor Recognition App Note, 675 * the AMD-K5 Model 0 uses the wrong bit to indicate 676 * support for global PTEs, instead using bit 9 (APIC) 677 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 678 */ 679 if (ci->ci_feat_val[0] & CPUID_APIC) 680 ci->ci_feat_val[0] = 681 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 682 /* 683 * XXX But pmap_pg_g is already initialized -- need to kick 684 * XXX the pmap somehow. How does the MP branch do this? 685 */ 686 break; 687 } 688 } 689 690 static void 691 cyrix6x86_cpu_setup(struct cpu_info *ci) 692 { 693 694 /* 695 * Do not disable the TSC on the Geode GX, it's reported to 696 * work fine. 697 */ 698 if (ci->ci_signature != 0x552) 699 disable_tsc(ci); 700 } 701 702 static void 703 winchip_cpu_setup(struct cpu_info *ci) 704 { 705 switch (ci->ci_model) { 706 case 4: /* WinChip C6 */ 707 disable_tsc(ci); 708 } 709 } 710 711 712 static const char * 713 intel_family6_name(struct cpu_info *ci) 714 { 715 const char *ret = NULL; 716 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 717 718 if (ci->ci_model == 5) { 719 switch (l2cache) { 720 case 0: 721 case 128 * 1024: 722 ret = "Celeron (Covington)"; 723 break; 724 case 256 * 1024: 725 ret = "Mobile Pentium II (Dixon)"; 726 break; 727 case 512 * 1024: 728 ret = "Pentium II"; 729 break; 730 case 1 * 1024 * 1024: 731 case 2 * 1024 * 1024: 732 ret = "Pentium II Xeon"; 733 break; 734 } 735 } else if (ci->ci_model == 6) { 736 switch (l2cache) { 737 case 256 * 1024: 738 case 512 * 1024: 739 ret = "Mobile Pentium II"; 740 break; 741 } 742 } else if (ci->ci_model == 7) { 743 switch (l2cache) { 744 case 512 * 1024: 745 ret = "Pentium III"; 746 break; 747 case 1 * 1024 * 1024: 748 case 2 * 1024 * 1024: 749 ret = "Pentium III Xeon"; 750 break; 751 } 752 } else if (ci->ci_model >= 8) { 753 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 754 switch (ci->ci_brand_id) { 755 case 0x3: 756 if (ci->ci_signature == 0x6B1) 757 ret = "Celeron"; 758 break; 759 case 0x8: 760 if (ci->ci_signature >= 0xF13) 761 ret = "genuine processor"; 762 break; 763 case 0xB: 764 if (ci->ci_signature >= 0xF13) 765 ret = "Xeon MP"; 766 break; 767 case 0xE: 768 if (ci->ci_signature < 0xF13) 769 ret = "Xeon"; 770 break; 771 } 772 if (ret == NULL) 773 ret = i386_intel_brand[ci->ci_brand_id]; 774 } 775 } 776 777 return ret; 778 } 779 780 /* 781 * Identify AMD64 CPU names from cpuid. 782 * 783 * Based on: 784 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 785 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 786 * "Revision Guide for AMD NPT Family 0Fh Processors" 787 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 788 * and other miscellaneous reports. 789 * 790 * This is all rather pointless, these are cross 'brand' since the raw 791 * silicon is shared. 792 */ 793 static const char * 794 amd_amd64_name(struct cpu_info *ci) 795 { 796 static char family_str[32]; 797 798 /* Only called if family >= 15 */ 799 800 switch (ci->ci_family) { 801 case 15: 802 switch (ci->ci_model) { 803 case 0x21: /* rev JH-E1/E6 */ 804 case 0x41: /* rev JH-F2 */ 805 return "Dual-Core Opteron"; 806 case 0x23: /* rev JH-E6 (Toledo) */ 807 return "Dual-Core Opteron or Athlon 64 X2"; 808 case 0x43: /* rev JH-F2 (Windsor) */ 809 return "Athlon 64 FX or Athlon 64 X2"; 810 case 0x24: /* rev SH-E5 (Lancaster?) */ 811 return "Mobile Athlon 64 or Turion 64"; 812 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 813 return "Opteron or Athlon 64 FX"; 814 case 0x15: /* rev SH-D0 */ 815 case 0x25: /* rev SH-E4 */ 816 return "Opteron"; 817 case 0x27: /* rev DH-E4, SH-E4 */ 818 return "Athlon 64 or Athlon 64 FX or Opteron"; 819 case 0x48: /* rev BH-F2 */ 820 return "Turion 64 X2"; 821 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 822 case 0x07: /* rev SH-CG (ClawHammer) */ 823 case 0x0b: /* rev CH-CG */ 824 case 0x14: /* rev SH-D0 */ 825 case 0x17: /* rev SH-D0 */ 826 case 0x1b: /* rev CH-D0 */ 827 return "Athlon 64"; 828 case 0x2b: /* rev BH-E4 (Manchester) */ 829 case 0x4b: /* rev BH-F2 (Windsor) */ 830 return "Athlon 64 X2"; 831 case 0x6b: /* rev BH-G1 (Brisbane) */ 832 return "Athlon X2 or Athlon 64 X2"; 833 case 0x08: /* rev CH-CG */ 834 case 0x0c: /* rev DH-CG (Newcastle) */ 835 case 0x0e: /* rev DH-CG (Newcastle?) */ 836 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 837 case 0x18: /* rev CH-D0 */ 838 case 0x1c: /* rev DH-D0 (Winchester) */ 839 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 840 case 0x2c: /* rev DH-E3/E6 */ 841 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 842 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 843 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 844 case 0x6f: /* rev DH-G1 */ 845 return "Athlon 64 or Sempron"; 846 default: 847 break; 848 } 849 return "Unknown AMD64 CPU"; 850 851 #if 0 852 case 16: 853 return "Family 10h"; 854 case 17: 855 return "Family 11h"; 856 case 18: 857 return "Family 12h"; 858 case 19: 859 return "Family 14h"; 860 case 20: 861 return "Family 15h"; 862 #endif 863 864 default: 865 break; 866 } 867 868 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 869 return family_str; 870 } 871 872 static void 873 intel_family_new_probe(struct cpu_info *ci) 874 { 875 uint32_t descs[4]; 876 877 x86_cpuid(0x80000000, descs); 878 879 /* 880 * Determine extended feature flags. 881 */ 882 if (descs[0] >= 0x80000001) { 883 x86_cpuid(0x80000001, descs); 884 ci->ci_feat_val[2] |= descs[3]; 885 ci->ci_feat_val[3] |= descs[2]; 886 } 887 } 888 889 static void 890 via_cpu_probe(struct cpu_info *ci) 891 { 892 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 893 u_int descs[4]; 894 u_int lfunc; 895 896 /* 897 * Determine the largest extended function value. 898 */ 899 x86_cpuid(0x80000000, descs); 900 lfunc = descs[0]; 901 902 /* 903 * Determine the extended feature flags. 904 */ 905 if (lfunc >= 0x80000001) { 906 x86_cpuid(0x80000001, descs); 907 ci->ci_feat_val[2] |= descs[3]; 908 } 909 910 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 911 return; 912 913 /* Nehemiah or Esther */ 914 x86_cpuid(0xc0000000, descs); 915 lfunc = descs[0]; 916 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 917 return; 918 919 x86_cpuid(0xc0000001, descs); 920 lfunc = descs[3]; 921 ci->ci_feat_val[4] = lfunc; 922 } 923 924 static void 925 amd_family6_probe(struct cpu_info *ci) 926 { 927 uint32_t descs[4]; 928 char *p; 929 size_t i; 930 931 x86_cpuid(0x80000000, descs); 932 933 /* 934 * Determine the extended feature flags. 935 */ 936 if (descs[0] >= 0x80000001) { 937 x86_cpuid(0x80000001, descs); 938 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 939 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 940 } 941 942 if (*cpu_brand_string == '\0') 943 return; 944 945 for (i = 1; i < __arraycount(amd_brand); i++) 946 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 947 ci->ci_brand_id = i; 948 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 949 break; 950 } 951 } 952 953 /* 954 * Get cache info from one of the following: 955 * Intel Deterministic Cache Parameter Leaf (0x04) 956 * AMD Cache Topology Information Leaf (0x8000001d) 957 */ 958 static void 959 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 960 { 961 u_int descs[4]; 962 int type, level, ways, partitions, linesize, sets, totalsize; 963 int caitype = -1; 964 int i; 965 966 for (i = 0; ; i++) { 967 x86_cpuid2(leaf, i, descs); 968 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 969 if (type == CPUID_DCP_CACHETYPE_N) 970 break; 971 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 972 switch (level) { 973 case 1: 974 if (type == CPUID_DCP_CACHETYPE_I) 975 caitype = CAI_ICACHE; 976 else if (type == CPUID_DCP_CACHETYPE_D) 977 caitype = CAI_DCACHE; 978 else 979 caitype = -1; 980 break; 981 case 2: 982 if (type == CPUID_DCP_CACHETYPE_U) 983 caitype = CAI_L2CACHE; 984 else 985 caitype = -1; 986 break; 987 case 3: 988 if (type == CPUID_DCP_CACHETYPE_U) 989 caitype = CAI_L3CACHE; 990 else 991 caitype = -1; 992 break; 993 default: 994 caitype = -1; 995 break; 996 } 997 if (caitype == -1) { 998 aprint_error_dev(ci->ci_dev, 999 "error: unknown cache level&type (%d & %d)\n", 1000 level, type); 1001 continue; 1002 } 1003 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1004 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1005 + 1; 1006 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1007 + 1; 1008 sets = descs[2] + 1; 1009 totalsize = ways * partitions * linesize * sets; 1010 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1011 ci->ci_cinfo[caitype].cai_associativity = ways; 1012 ci->ci_cinfo[caitype].cai_linesize = linesize; 1013 } 1014 } 1015 1016 static void 1017 intel_cpu_cacheinfo(struct cpu_info *ci) 1018 { 1019 const struct x86_cache_info *cai; 1020 u_int descs[4]; 1021 int iterations, i, j; 1022 int type, level, ways, linesize, sets; 1023 int caitype = -1; 1024 uint8_t desc; 1025 1026 /* Return if the cpu is old pre-cpuid instruction cpu */ 1027 if (ci->ci_cpu_type >= 0) 1028 return; 1029 1030 if (ci->ci_max_cpuid < 2) 1031 return; 1032 1033 /* 1034 * Parse the cache info from `cpuid leaf 2', if we have it. 1035 * XXX This is kinda ugly, but hey, so is the architecture... 1036 */ 1037 x86_cpuid(2, descs); 1038 iterations = descs[0] & 0xff; 1039 while (iterations-- > 0) { 1040 for (i = 0; i < 4; i++) { 1041 if (descs[i] & 0x80000000) 1042 continue; 1043 for (j = 0; j < 4; j++) { 1044 /* 1045 * The least significant byte in EAX 1046 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1047 * it should be ignored. 1048 */ 1049 if (i == 0 && j == 0) 1050 continue; 1051 desc = (descs[i] >> (j * 8)) & 0xff; 1052 if (desc == 0) 1053 continue; 1054 cai = cache_info_lookup(intel_cpuid_cache_info, 1055 desc); 1056 if (cai != NULL) 1057 ci->ci_cinfo[cai->cai_index] = *cai; 1058 else if ((verbose != 0) && (desc != 0xff) 1059 && (desc != 0xfe)) 1060 aprint_error_dev(ci->ci_dev, "error:" 1061 " Unknown cacheinfo desc %02x\n", 1062 desc); 1063 } 1064 } 1065 x86_cpuid(2, descs); 1066 } 1067 1068 if (ci->ci_max_cpuid < 4) 1069 return; 1070 1071 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1072 cpu_dcp_cacheinfo(ci, 4); 1073 1074 if (ci->ci_max_cpuid < 0x18) 1075 return; 1076 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1077 x86_cpuid(0x18, descs); 1078 iterations = descs[0]; 1079 for (i = 0; i <= iterations; i++) { 1080 uint32_t pgsize; 1081 bool full; 1082 1083 x86_cpuid2(0x18, i, descs); 1084 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1085 if (type == CPUID_DATP_TCTYPE_N) 1086 continue; 1087 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1088 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1089 switch (level) { 1090 case 1: 1091 if (type == CPUID_DATP_TCTYPE_I) { 1092 switch (pgsize) { 1093 case CPUID_DATP_PGSIZE_4KB: 1094 caitype = CAI_ITLB; 1095 break; 1096 case CPUID_DATP_PGSIZE_2MB 1097 | CPUID_DATP_PGSIZE_4MB: 1098 caitype = CAI_ITLB2; 1099 break; 1100 case CPUID_DATP_PGSIZE_1GB: 1101 caitype = CAI_L1_1GBITLB; 1102 break; 1103 default: 1104 aprint_error_dev(ci->ci_dev, 1105 "error: unknown ITLB size (%d)\n", 1106 pgsize); 1107 caitype = CAI_ITLB; 1108 break; 1109 } 1110 } else if (type == CPUID_DATP_TCTYPE_D) { 1111 switch (pgsize) { 1112 case CPUID_DATP_PGSIZE_4KB: 1113 caitype = CAI_DTLB; 1114 break; 1115 case CPUID_DATP_PGSIZE_2MB 1116 | CPUID_DATP_PGSIZE_4MB: 1117 caitype = CAI_DTLB2; 1118 break; 1119 case CPUID_DATP_PGSIZE_1GB: 1120 caitype = CAI_L1_1GBDTLB; 1121 break; 1122 default: 1123 aprint_error_dev(ci->ci_dev, 1124 "error: unknown DTLB size (%d)\n", 1125 pgsize); 1126 caitype = CAI_DTLB; 1127 break; 1128 } 1129 } else 1130 caitype = -1; 1131 break; 1132 case 2: 1133 if (type == CPUID_DATP_TCTYPE_I) 1134 caitype = CAI_L2_ITLB; 1135 else if (type == CPUID_DATP_TCTYPE_D) 1136 caitype = CAI_L2_DTLB; 1137 else if (type == CPUID_DATP_TCTYPE_U) { 1138 switch (pgsize) { 1139 case CPUID_DATP_PGSIZE_4KB: 1140 caitype = CAI_L2_STLB; 1141 break; 1142 case CPUID_DATP_PGSIZE_4KB 1143 | CPUID_DATP_PGSIZE_2MB: 1144 caitype = CAI_L2_STLB2; 1145 break; 1146 case CPUID_DATP_PGSIZE_2MB 1147 | CPUID_DATP_PGSIZE_4MB: 1148 caitype = CAI_L2_STLB3; 1149 break; 1150 default: 1151 aprint_error_dev(ci->ci_dev, 1152 "error: unknown L2 STLB size (%d)\n", 1153 pgsize); 1154 caitype = CAI_DTLB; 1155 break; 1156 } 1157 } else 1158 caitype = -1; 1159 break; 1160 case 3: 1161 /* XXX need work for L3 TLB */ 1162 caitype = CAI_L3CACHE; 1163 break; 1164 default: 1165 caitype = -1; 1166 break; 1167 } 1168 if (caitype == -1) { 1169 aprint_error_dev(ci->ci_dev, 1170 "error: unknown TLB level&type (%d & %d)\n", 1171 level, type); 1172 continue; 1173 } 1174 switch (pgsize) { 1175 case CPUID_DATP_PGSIZE_4KB: 1176 linesize = 4 * 1024; 1177 break; 1178 case CPUID_DATP_PGSIZE_2MB: 1179 linesize = 2 * 1024 * 1024; 1180 break; 1181 case CPUID_DATP_PGSIZE_4MB: 1182 linesize = 4 * 1024 * 1024; 1183 break; 1184 case CPUID_DATP_PGSIZE_1GB: 1185 linesize = 1024 * 1024 * 1024; 1186 break; 1187 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1188 aprint_error_dev(ci->ci_dev, 1189 "WARINING: Currently 2M/4M info can't print correctly\n"); 1190 linesize = 4 * 1024 * 1024; 1191 break; 1192 default: 1193 aprint_error_dev(ci->ci_dev, 1194 "error: Unknown size combination\n"); 1195 linesize = 4 * 1024; 1196 break; 1197 } 1198 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1199 sets = descs[2]; 1200 full = descs[3] & CPUID_DATP_FULLASSOC; 1201 ci->ci_cinfo[caitype].cai_totalsize 1202 = ways * sets; /* entries */ 1203 ci->ci_cinfo[caitype].cai_associativity 1204 = full ? 0xff : ways; 1205 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1206 } 1207 } 1208 1209 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1210 AMD_L2L3CACHE_INFO; 1211 1212 static void 1213 amd_cpu_cacheinfo(struct cpu_info *ci) 1214 { 1215 const struct x86_cache_info *cp; 1216 struct x86_cache_info *cai; 1217 u_int descs[4]; 1218 u_int lfunc; 1219 1220 /* K5 model 0 has none of this info. */ 1221 if (ci->ci_family == 5 && ci->ci_model == 0) 1222 return; 1223 1224 /* Determine the largest extended function value. */ 1225 x86_cpuid(0x80000000, descs); 1226 lfunc = descs[0]; 1227 1228 if (lfunc < 0x80000005) 1229 return; 1230 1231 /* Determine L1 cache/TLB info. */ 1232 x86_cpuid(0x80000005, descs); 1233 1234 /* K6-III and higher have large page TLBs. */ 1235 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1236 cai = &ci->ci_cinfo[CAI_ITLB2]; 1237 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1238 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1239 cai->cai_linesize = largepagesize; 1240 1241 cai = &ci->ci_cinfo[CAI_DTLB2]; 1242 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1243 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1244 cai->cai_linesize = largepagesize; 1245 } 1246 1247 cai = &ci->ci_cinfo[CAI_ITLB]; 1248 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1249 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1250 cai->cai_linesize = (4 * 1024); 1251 1252 cai = &ci->ci_cinfo[CAI_DTLB]; 1253 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1254 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1255 cai->cai_linesize = (4 * 1024); 1256 1257 cai = &ci->ci_cinfo[CAI_DCACHE]; 1258 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1259 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1260 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1261 1262 cai = &ci->ci_cinfo[CAI_ICACHE]; 1263 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1264 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1265 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1266 1267 if (lfunc < 0x80000006) 1268 return; 1269 1270 /* Determine L2 cache/TLB info. */ 1271 x86_cpuid(0x80000006, descs); 1272 1273 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1274 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1275 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1276 cai->cai_linesize = (4 * 1024); 1277 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1278 cai->cai_associativity); 1279 if (cp != NULL) 1280 cai->cai_associativity = cp->cai_associativity; 1281 else 1282 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1283 1284 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1285 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1286 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1287 cai->cai_linesize = largepagesize; 1288 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1289 cai->cai_associativity); 1290 if (cp != NULL) 1291 cai->cai_associativity = cp->cai_associativity; 1292 else 1293 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1294 1295 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1296 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1297 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1298 cai->cai_linesize = (4 * 1024); 1299 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1300 cai->cai_associativity); 1301 if (cp != NULL) 1302 cai->cai_associativity = cp->cai_associativity; 1303 else 1304 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1305 1306 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1307 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1308 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1309 cai->cai_linesize = largepagesize; 1310 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1311 cai->cai_associativity); 1312 if (cp != NULL) 1313 cai->cai_associativity = cp->cai_associativity; 1314 else 1315 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1316 1317 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1318 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1319 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1320 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1321 1322 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1323 cai->cai_associativity); 1324 if (cp != NULL) 1325 cai->cai_associativity = cp->cai_associativity; 1326 else 1327 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1328 1329 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1330 if (ci->ci_family >= 0x10) { 1331 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1332 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1333 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1334 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1335 1336 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1337 cai->cai_associativity); 1338 if (cp != NULL) 1339 cai->cai_associativity = cp->cai_associativity; 1340 else 1341 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1342 } 1343 1344 if (lfunc < 0x80000019) 1345 return; 1346 1347 /* Determine 1GB TLB info. */ 1348 x86_cpuid(0x80000019, descs); 1349 1350 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1351 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1352 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1353 cai->cai_linesize = (1024 * 1024 * 1024); 1354 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1355 cai->cai_associativity); 1356 if (cp != NULL) 1357 cai->cai_associativity = cp->cai_associativity; 1358 else 1359 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1360 1361 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1362 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1363 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1364 cai->cai_linesize = (1024 * 1024 * 1024); 1365 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1366 cai->cai_associativity); 1367 if (cp != NULL) 1368 cai->cai_associativity = cp->cai_associativity; 1369 else 1370 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1371 1372 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1373 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1374 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1375 cai->cai_linesize = (1024 * 1024 * 1024); 1376 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1377 cai->cai_associativity); 1378 if (cp != NULL) 1379 cai->cai_associativity = cp->cai_associativity; 1380 else 1381 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1382 1383 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1384 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1385 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1386 cai->cai_linesize = (1024 * 1024 * 1024); 1387 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1388 cai->cai_associativity); 1389 if (cp != NULL) 1390 cai->cai_associativity = cp->cai_associativity; 1391 else 1392 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1393 1394 if (lfunc < 0x8000001d) 1395 return; 1396 1397 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1398 cpu_dcp_cacheinfo(ci, 0x8000001d); 1399 } 1400 1401 static void 1402 via_cpu_cacheinfo(struct cpu_info *ci) 1403 { 1404 struct x86_cache_info *cai; 1405 int stepping; 1406 u_int descs[4]; 1407 u_int lfunc; 1408 1409 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1410 1411 /* 1412 * Determine the largest extended function value. 1413 */ 1414 x86_cpuid(0x80000000, descs); 1415 lfunc = descs[0]; 1416 1417 /* 1418 * Determine L1 cache/TLB info. 1419 */ 1420 if (lfunc < 0x80000005) { 1421 /* No L1 cache info available. */ 1422 return; 1423 } 1424 1425 x86_cpuid(0x80000005, descs); 1426 1427 cai = &ci->ci_cinfo[CAI_ITLB]; 1428 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1429 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1430 cai->cai_linesize = (4 * 1024); 1431 1432 cai = &ci->ci_cinfo[CAI_DTLB]; 1433 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1434 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1435 cai->cai_linesize = (4 * 1024); 1436 1437 cai = &ci->ci_cinfo[CAI_DCACHE]; 1438 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1439 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1440 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1441 if (ci->ci_model == 9 && stepping == 8) { 1442 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1443 cai->cai_associativity = 2; 1444 } 1445 1446 cai = &ci->ci_cinfo[CAI_ICACHE]; 1447 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1448 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1449 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1450 if (ci->ci_model == 9 && stepping == 8) { 1451 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1452 cai->cai_associativity = 2; 1453 } 1454 1455 /* 1456 * Determine L2 cache/TLB info. 1457 */ 1458 if (lfunc < 0x80000006) { 1459 /* No L2 cache info available. */ 1460 return; 1461 } 1462 1463 x86_cpuid(0x80000006, descs); 1464 1465 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1466 if (ci->ci_model >= 9) { 1467 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1468 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1469 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1470 } else { 1471 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1472 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1473 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1474 } 1475 } 1476 1477 static void 1478 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1479 { 1480 u_int descs[4]; 1481 1482 x86_cpuid(0x80860007, descs); 1483 *frequency = descs[0]; 1484 *voltage = descs[1]; 1485 *percentage = descs[2]; 1486 } 1487 1488 static void 1489 transmeta_cpu_info(struct cpu_info *ci) 1490 { 1491 u_int descs[4], nreg; 1492 u_int frequency, voltage, percentage; 1493 1494 x86_cpuid(0x80860000, descs); 1495 nreg = descs[0]; 1496 if (nreg >= 0x80860001) { 1497 x86_cpuid(0x80860001, descs); 1498 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1499 (descs[1] >> 24) & 0xff, 1500 (descs[1] >> 16) & 0xff, 1501 (descs[1] >> 8) & 0xff, 1502 descs[1] & 0xff); 1503 } 1504 if (nreg >= 0x80860002) { 1505 x86_cpuid(0x80860002, descs); 1506 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1507 (descs[1] >> 24) & 0xff, 1508 (descs[1] >> 16) & 0xff, 1509 (descs[1] >> 8) & 0xff, 1510 descs[1] & 0xff, 1511 descs[2]); 1512 } 1513 if (nreg >= 0x80860006) { 1514 union { 1515 char text[65]; 1516 u_int descs[4][4]; 1517 } info; 1518 int i; 1519 1520 for (i=0; i<4; i++) { 1521 x86_cpuid(0x80860003 + i, info.descs[i]); 1522 } 1523 info.text[64] = '\0'; 1524 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1525 } 1526 1527 if (nreg >= 0x80860007) { 1528 tmx86_get_longrun_status(&frequency, 1529 &voltage, &percentage); 1530 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1531 frequency, voltage, percentage); 1532 } 1533 } 1534 1535 static void 1536 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1537 { 1538 u_int descs[4]; 1539 int i; 1540 uint32_t brand[12]; 1541 1542 memset(ci, 0, sizeof(*ci)); 1543 ci->ci_dev = cpuname; 1544 1545 ci->ci_cpu_type = x86_identify(); 1546 if (ci->ci_cpu_type >= 0) { 1547 /* Old pre-cpuid instruction cpu */ 1548 ci->ci_max_cpuid = -1; 1549 return; 1550 } 1551 1552 /* 1553 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1554 * function. 1555 */ 1556 1557 /* 1558 * Fn0000_0000: 1559 * - Save cpuid max level. 1560 * - Save vendor string. 1561 */ 1562 x86_cpuid(0, descs); 1563 ci->ci_max_cpuid = descs[0]; 1564 /* Save vendor string */ 1565 ci->ci_vendor[0] = descs[1]; 1566 ci->ci_vendor[2] = descs[2]; 1567 ci->ci_vendor[1] = descs[3]; 1568 ci->ci_vendor[3] = 0; 1569 1570 /* 1571 * Fn8000_0000: 1572 * - Get cpuid extended function's max level. 1573 */ 1574 x86_cpuid(0x80000000, descs); 1575 if (descs[0] >= 0x80000000) 1576 ci->ci_max_ext_cpuid = descs[0]; 1577 else { 1578 /* Set lower value than 0x80000000 */ 1579 ci->ci_max_ext_cpuid = 0; 1580 } 1581 1582 /* 1583 * Fn8000_000[2-4]: 1584 * - Save brand string. 1585 */ 1586 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1587 x86_cpuid(0x80000002, brand); 1588 x86_cpuid(0x80000003, brand + 4); 1589 x86_cpuid(0x80000004, brand + 8); 1590 for (i = 0; i < 48; i++) 1591 if (((char *) brand)[i] != ' ') 1592 break; 1593 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1594 } 1595 1596 if (ci->ci_max_cpuid < 1) 1597 return; 1598 1599 /* 1600 * Fn0000_0001: 1601 * - Get CPU family, model and stepping (from eax). 1602 * - Initial local APIC ID and brand ID (from ebx) 1603 * - CPUID2 (from ecx) 1604 * - CPUID (from edx) 1605 */ 1606 x86_cpuid(1, descs); 1607 ci->ci_signature = descs[0]; 1608 1609 /* Extract full family/model values */ 1610 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1611 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1612 1613 /* Brand is low order 8 bits of ebx */ 1614 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1615 /* Initial local APIC ID */ 1616 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1617 1618 ci->ci_feat_val[1] = descs[2]; 1619 ci->ci_feat_val[0] = descs[3]; 1620 1621 if (ci->ci_max_cpuid < 3) 1622 return; 1623 1624 /* 1625 * If the processor serial number misfeature is present and supported, 1626 * extract it here. 1627 */ 1628 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1629 ci->ci_cpu_serial[0] = ci->ci_signature; 1630 x86_cpuid(3, descs); 1631 ci->ci_cpu_serial[2] = descs[2]; 1632 ci->ci_cpu_serial[1] = descs[3]; 1633 } 1634 1635 if (ci->ci_max_cpuid < 0x7) 1636 return; 1637 1638 x86_cpuid(7, descs); 1639 ci->ci_feat_val[5] = descs[1]; 1640 ci->ci_feat_val[6] = descs[2]; 1641 ci->ci_feat_val[7] = descs[3]; 1642 1643 if (ci->ci_max_cpuid < 0xd) 1644 return; 1645 1646 /* Get support XCR0 bits */ 1647 x86_cpuid2(0xd, 0, descs); 1648 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1649 ci->ci_cur_xsave = descs[1]; 1650 ci->ci_max_xsave = descs[2]; 1651 1652 /* Additional flags (eg xsaveopt support) */ 1653 x86_cpuid2(0xd, 1, descs); 1654 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1655 } 1656 1657 static void 1658 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1659 { 1660 uint32_t descs[4]; 1661 char hv_sig[13]; 1662 char *p; 1663 const char *hv_name; 1664 int i; 1665 1666 /* 1667 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1668 * http://lkml.org/lkml/2008/10/1/246 1669 * 1670 * KB1009458: Mechanisms to determine if software is running in 1671 * a VMware virtual machine 1672 * http://kb.vmware.com/kb/1009458 1673 */ 1674 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1675 x86_cpuid(0x40000000, descs); 1676 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1677 memcpy(p, &descs[i], sizeof(descs[i])); 1678 *p = '\0'; 1679 /* 1680 * HV vendor ID string 1681 * ------------+-------------- 1682 * HAXM "HAXMHAXMHAXM" 1683 * KVM "KVMKVMKVM" 1684 * Microsoft "Microsoft Hv" 1685 * QEMU(TCG) "TCGTCGTCGTCG" 1686 * VMware "VMwareVMware" 1687 * Xen "XenVMMXenVMM" 1688 * NetBSD "___ NVMM ___" 1689 */ 1690 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1691 hv_name = "HAXM"; 1692 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1693 hv_name = "KVM"; 1694 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1695 hv_name = "Hyper-V"; 1696 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1697 hv_name = "QEMU(TCG)"; 1698 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1699 hv_name = "VMware"; 1700 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1701 hv_name = "Xen"; 1702 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1703 hv_name = "NVMM"; 1704 else 1705 hv_name = "unknown"; 1706 1707 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1708 } 1709 } 1710 1711 static void 1712 cpu_probe_features(struct cpu_info *ci) 1713 { 1714 const struct cpu_cpuid_nameclass *cpup = NULL; 1715 unsigned int i; 1716 1717 if (ci->ci_max_cpuid < 1) 1718 return; 1719 1720 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1721 if (!strncmp((char *)ci->ci_vendor, 1722 i386_cpuid_cpus[i].cpu_id, 12)) { 1723 cpup = &i386_cpuid_cpus[i]; 1724 break; 1725 } 1726 } 1727 1728 if (cpup == NULL) 1729 return; 1730 1731 i = ci->ci_family - CPU_MINFAMILY; 1732 1733 if (i >= __arraycount(cpup->cpu_family)) 1734 i = __arraycount(cpup->cpu_family) - 1; 1735 1736 if (cpup->cpu_family[i].cpu_probe == NULL) 1737 return; 1738 1739 (*cpup->cpu_family[i].cpu_probe)(ci); 1740 } 1741 1742 static void 1743 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1744 { 1745 char buf[32 * 16]; 1746 char *bp; 1747 1748 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1749 1750 if (val == 0 || fmt == NULL) 1751 return; 1752 1753 snprintb_m(buf, sizeof(buf), fmt, val, 1754 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1755 bp = buf; 1756 while (*bp != '\0') { 1757 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1758 bp += strlen(bp) + 1; 1759 } 1760 } 1761 1762 static void 1763 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1764 const char *blockname) 1765 { 1766 uint32_t descs[4]; 1767 uint32_t leaf; 1768 1769 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1770 leafend); 1771 1772 if (verbose) { 1773 for (leaf = leafstart; leaf <= leafend; leaf++) { 1774 x86_cpuid(leaf, descs); 1775 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1776 leaf, descs[0], descs[1], descs[2], descs[3]); 1777 } 1778 } 1779 } 1780 1781 static void 1782 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1783 { 1784 u_int lp_max = 1; /* logical processors per package */ 1785 u_int smt_max; /* smt per core */ 1786 u_int core_max = 1; /* core per package */ 1787 u_int smt_bits, core_bits; 1788 uint32_t descs[4]; 1789 1790 /* 1791 * 253668.pdf 7.10.2 1792 */ 1793 1794 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1795 x86_cpuid(1, descs); 1796 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1797 } 1798 x86_cpuid2(4, 0, descs); 1799 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1800 1801 assert(lp_max >= core_max); 1802 smt_max = lp_max / core_max; 1803 smt_bits = ilog2(smt_max - 1) + 1; 1804 core_bits = ilog2(core_max - 1) + 1; 1805 1806 if (smt_bits + core_bits) 1807 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1808 1809 if (core_bits) 1810 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1811 __BITS(smt_bits, smt_bits + core_bits - 1)); 1812 1813 if (smt_bits) 1814 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1815 __BITS((int)0, (int)(smt_bits - 1))); 1816 } 1817 1818 static void 1819 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1820 { 1821 const char *cpuname = ci->ci_dev; 1822 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1823 uint32_t descs[4]; 1824 int i; 1825 1826 x86_cpuid(0x0b, descs); 1827 if (descs[1] == 0) { 1828 identifycpu_cpuids_intel_0x04(ci); 1829 return; 1830 } 1831 1832 for (i = 0; ; i++) { 1833 unsigned int shiftnum, lvltype; 1834 x86_cpuid2(0x0b, i, descs); 1835 1836 /* On invalid level, (EAX and) EBX return 0 */ 1837 if (descs[1] == 0) 1838 break; 1839 1840 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1841 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1842 switch (lvltype) { 1843 case CPUID_TOP_LVLTYPE_SMT: 1844 core_shift = shiftnum; 1845 break; 1846 case CPUID_TOP_LVLTYPE_CORE: 1847 pkg_shift = shiftnum; 1848 break; 1849 case CPUID_TOP_LVLTYPE_INVAL: 1850 aprint_verbose("%s: Invalid level type\n", cpuname); 1851 break; 1852 default: 1853 aprint_verbose("%s: Unknown level type(%d) \n", 1854 cpuname, lvltype); 1855 break; 1856 } 1857 } 1858 1859 assert(pkg_shift >= core_shift); 1860 smt_bits = core_shift; 1861 core_bits = pkg_shift - core_shift; 1862 1863 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1864 1865 if (core_bits) 1866 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1867 __BITS(core_shift, pkg_shift - 1)); 1868 1869 if (smt_bits) 1870 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1871 __BITS((int)0, core_shift - 1)); 1872 } 1873 1874 static void 1875 identifycpu_cpuids_intel(struct cpu_info *ci) 1876 { 1877 const char *cpuname = ci->ci_dev; 1878 1879 if (ci->ci_max_cpuid >= 0x0b) 1880 identifycpu_cpuids_intel_0x0b(ci); 1881 else if (ci->ci_max_cpuid >= 4) 1882 identifycpu_cpuids_intel_0x04(ci); 1883 1884 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1885 ci->ci_packageid); 1886 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1887 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1888 } 1889 1890 static void 1891 identifycpu_cpuids_amd(struct cpu_info *ci) 1892 { 1893 const char *cpuname = ci->ci_dev; 1894 u_int lp_max, core_max; 1895 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1896 uint32_t descs[4]; 1897 1898 apic_id = ci->ci_initapicid; 1899 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1900 1901 if (cpu_family < 0xf) 1902 return; 1903 1904 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1905 x86_cpuid(1, descs); 1906 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1907 1908 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1909 x86_cpuid(0x8000008, descs); 1910 core_max = (descs[2] & 0xff) + 1; 1911 n = (descs[2] >> 12) & 0x0f; 1912 if (n != 0) 1913 core_bits = n; 1914 } 1915 } else { 1916 lp_max = 1; 1917 } 1918 core_max = lp_max; 1919 1920 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1921 if (core_bits == 0) 1922 core_bits = ilog2(core_max - 1) + 1; 1923 1924 #if 0 /* MSRs need kernel mode */ 1925 if (cpu_family < 0x11) { 1926 const uint64_t reg = rdmsr(MSR_NB_CFG); 1927 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1928 const u_int node_id = apic_id & __BITS(0, 2); 1929 apic_id = (cpu_family == 0xf) ? 1930 (apic_id >> core_bits) | (node_id << core_bits) : 1931 (apic_id >> 5) | (node_id << 2); 1932 } 1933 } 1934 #endif 1935 1936 if (cpu_family == 0x17) { 1937 x86_cpuid(0x8000001e, descs); 1938 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1939 smt_bits = ilog2(threads); 1940 core_bits -= smt_bits; 1941 } 1942 1943 if (smt_bits + core_bits) { 1944 if (smt_bits + core_bits < 32) 1945 ci->ci_packageid = 0; 1946 } 1947 if (core_bits) { 1948 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1949 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1950 } 1951 if (smt_bits) { 1952 u_int smt_mask = __BITS(0, smt_bits - 1); 1953 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1954 } 1955 1956 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1957 ci->ci_packageid); 1958 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1959 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1960 } 1961 1962 static void 1963 identifycpu_cpuids(struct cpu_info *ci) 1964 { 1965 const char *cpuname = ci->ci_dev; 1966 1967 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1968 ci->ci_packageid = ci->ci_initapicid; 1969 ci->ci_coreid = 0; 1970 ci->ci_smtid = 0; 1971 1972 if (cpu_vendor == CPUVENDOR_INTEL) 1973 identifycpu_cpuids_intel(ci); 1974 else if (cpu_vendor == CPUVENDOR_AMD) 1975 identifycpu_cpuids_amd(ci); 1976 } 1977 1978 void 1979 identifycpu(int fd, const char *cpuname) 1980 { 1981 const char *name = "", *modifier, *vendorname, *brand = ""; 1982 int class = CPUCLASS_386; 1983 unsigned int i; 1984 int modif, family; 1985 const struct cpu_cpuid_nameclass *cpup = NULL; 1986 const struct cpu_cpuid_family *cpufam; 1987 struct cpu_info *ci, cistore; 1988 u_int descs[4]; 1989 size_t sz; 1990 struct cpu_ucode_version ucode; 1991 union { 1992 struct cpu_ucode_version_amd amd; 1993 struct cpu_ucode_version_intel1 intel1; 1994 } ucvers; 1995 1996 ci = &cistore; 1997 cpu_probe_base_features(ci, cpuname); 1998 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1999 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2000 x86_cpuid(0x40000000, descs); 2001 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2002 } 2003 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 2004 2005 cpu_probe_hv_features(ci, cpuname); 2006 cpu_probe_features(ci); 2007 2008 if (ci->ci_cpu_type >= 0) { 2009 /* Old pre-cpuid instruction cpu */ 2010 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2011 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2012 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2013 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2014 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2015 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2016 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2017 modifier = ""; 2018 } else { 2019 /* CPU which support cpuid instruction */ 2020 modif = (ci->ci_signature >> 12) & 0x3; 2021 family = ci->ci_family; 2022 if (family < CPU_MINFAMILY) 2023 errx(1, "identifycpu: strange family value"); 2024 if (family > CPU_MAXFAMILY) 2025 family = CPU_MAXFAMILY; 2026 2027 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2028 if (!strncmp((char *)ci->ci_vendor, 2029 i386_cpuid_cpus[i].cpu_id, 12)) { 2030 cpup = &i386_cpuid_cpus[i]; 2031 break; 2032 } 2033 } 2034 2035 if (cpup == NULL) { 2036 cpu_vendor = CPUVENDOR_UNKNOWN; 2037 if (ci->ci_vendor[0] != '\0') 2038 vendorname = (char *)&ci->ci_vendor[0]; 2039 else 2040 vendorname = "Unknown"; 2041 class = family - 3; 2042 modifier = ""; 2043 name = ""; 2044 ci->ci_info = NULL; 2045 } else { 2046 cpu_vendor = cpup->cpu_vendor; 2047 vendorname = cpup->cpu_vendorname; 2048 modifier = modifiers[modif]; 2049 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2050 name = cpufam->cpu_models[ci->ci_model]; 2051 if (name == NULL || *name == '\0') 2052 name = cpufam->cpu_model_default; 2053 class = cpufam->cpu_class; 2054 ci->ci_info = cpufam->cpu_info; 2055 2056 if (cpu_vendor == CPUVENDOR_INTEL) { 2057 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2058 const char *tmp; 2059 tmp = intel_family6_name(ci); 2060 if (tmp != NULL) 2061 name = tmp; 2062 } 2063 if (ci->ci_family == 15 && 2064 ci->ci_brand_id < 2065 __arraycount(i386_intel_brand) && 2066 i386_intel_brand[ci->ci_brand_id]) 2067 name = 2068 i386_intel_brand[ci->ci_brand_id]; 2069 } 2070 2071 if (cpu_vendor == CPUVENDOR_AMD) { 2072 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2073 if (ci->ci_brand_id == 1) 2074 /* 2075 * It's Duron. We override the 2076 * name, since it might have 2077 * been misidentified as Athlon. 2078 */ 2079 name = 2080 amd_brand[ci->ci_brand_id]; 2081 else 2082 brand = amd_brand_name; 2083 } 2084 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2085 == 0xf) { 2086 /* Identify AMD64 CPU names. */ 2087 const char *tmp; 2088 tmp = amd_amd64_name(ci); 2089 if (tmp != NULL) 2090 name = tmp; 2091 } 2092 } 2093 2094 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2095 vendorname = "VIA"; 2096 } 2097 } 2098 2099 ci->ci_cpu_class = class; 2100 2101 sz = sizeof(ci->ci_tsc_freq); 2102 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2103 sz = sizeof(use_pae); 2104 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2105 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2106 2107 /* 2108 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2109 * we try to determine from the family/model values. 2110 */ 2111 if (*cpu_brand_string != '\0') 2112 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2113 2114 aprint_normal("%s: %s", cpuname, vendorname); 2115 if (*modifier) 2116 aprint_normal(" %s", modifier); 2117 if (*name) 2118 aprint_normal(" %s", name); 2119 if (*brand) 2120 aprint_normal(" %s", brand); 2121 aprint_normal(" (%s-class)", classnames[class]); 2122 2123 if (ci->ci_tsc_freq != 0) 2124 aprint_normal(", %ju.%02ju MHz", 2125 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2126 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2127 aprint_normal("\n"); 2128 2129 (void)cpu_tsc_freq_cpuid(ci); 2130 2131 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2132 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2133 if (ci->ci_signature != 0) 2134 aprint_normal(" (id %#x)", ci->ci_signature); 2135 aprint_normal("\n"); 2136 2137 if (ci->ci_info) 2138 (*ci->ci_info)(ci); 2139 2140 /* 2141 * display CPU feature flags 2142 */ 2143 2144 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2145 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2146 2147 /* These next two are actually common definitions! */ 2148 print_bits(cpuname, "features2", 2149 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2150 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2151 print_bits(cpuname, "features3", 2152 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2153 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2154 2155 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2156 ci->ci_feat_val[4]); 2157 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2158 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2159 ci->ci_feat_val[5]); 2160 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2161 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2162 ci->ci_feat_val[6]); 2163 2164 if (cpu_vendor == CPUVENDOR_INTEL) 2165 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2166 ci->ci_feat_val[7]); 2167 2168 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2169 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2170 ci->ci_feat_val[9]); 2171 2172 if (ci->ci_max_xsave != 0) { 2173 aprint_normal("%s: xsave area size: current %d, maximum %d", 2174 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2175 aprint_normal(", xgetbv %sabled\n", 2176 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2177 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2178 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2179 x86_xgetbv()); 2180 } 2181 2182 x86_print_cache_and_tlb_info(ci); 2183 2184 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2185 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2186 cpuname, 2187 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2188 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2189 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2190 } 2191 2192 if (ci->ci_cpu_class == CPUCLASS_386) 2193 errx(1, "NetBSD requires an 80486 or later processor"); 2194 2195 if (ci->ci_cpu_type == CPU_486DLC) { 2196 #ifndef CYRIX_CACHE_WORKS 2197 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2198 #else 2199 #ifndef CYRIX_CACHE_REALLY_WORKS 2200 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2201 #else 2202 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2203 #endif 2204 #endif 2205 } 2206 2207 /* 2208 * Everything past this point requires a Pentium or later. 2209 */ 2210 if (ci->ci_max_cpuid < 0) 2211 return; 2212 2213 identifycpu_cpuids(ci); 2214 2215 if ((ci->ci_max_cpuid >= 5) 2216 && ((cpu_vendor == CPUVENDOR_INTEL) 2217 || (cpu_vendor == CPUVENDOR_AMD))) { 2218 uint16_t lmin, lmax; 2219 x86_cpuid(5, descs); 2220 2221 print_bits(cpuname, "MONITOR/MWAIT extensions", 2222 CPUID_MON_FLAGS, descs[2]); 2223 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2224 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2225 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2226 if (lmin != lmax) 2227 aprint_normal("-%hu", lmax); 2228 aprint_normal("\n"); 2229 2230 for (i = 0; i <= 7; i++) { 2231 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2232 2233 if (num != 0) 2234 aprint_normal("%s: C%u substates %u\n", 2235 cpuname, i, num); 2236 } 2237 } 2238 if ((ci->ci_max_cpuid >= 6) 2239 && ((cpu_vendor == CPUVENDOR_INTEL) 2240 || (cpu_vendor == CPUVENDOR_AMD))) { 2241 x86_cpuid(6, descs); 2242 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2243 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2244 } 2245 if ((ci->ci_max_cpuid >= 7) 2246 && ((cpu_vendor == CPUVENDOR_INTEL) 2247 || (cpu_vendor == CPUVENDOR_AMD))) { 2248 x86_cpuid(7, descs); 2249 aprint_verbose("%s: SEF highest subleaf %08x\n", 2250 cpuname, descs[0]); 2251 } 2252 2253 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2254 if (ci->ci_max_ext_cpuid >= 0x80000007) 2255 powernow_probe(ci); 2256 2257 if (cpu_vendor == CPUVENDOR_AMD) { 2258 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2259 x86_cpuid(0x80000008, descs); 2260 print_bits(cpuname, "AMD Extended features", 2261 CPUID_CAPEX_FLAGS, descs[1]); 2262 } 2263 2264 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2265 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2266 x86_cpuid(0x8000000a, descs); 2267 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2268 descs[0] & 0xf); 2269 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2270 descs[1]); 2271 print_bits(cpuname, "SVM features", 2272 CPUID_AMD_SVM_FLAGS, descs[3]); 2273 } 2274 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2275 x86_cpuid(0x8000001f, descs); 2276 print_bits(cpuname, "Encrypted Memory features", 2277 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2278 } 2279 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2280 int32_t bi_index; 2281 2282 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2283 x86_cpuid(bi_index, descs); 2284 switch (bi_index) { 2285 case 0x0a: 2286 print_bits(cpuname, "Perfmon-eax", 2287 CPUID_PERF_FLAGS0, descs[0]); 2288 print_bits(cpuname, "Perfmon-ebx", 2289 CPUID_PERF_FLAGS1, descs[1]); 2290 print_bits(cpuname, "Perfmon-edx", 2291 CPUID_PERF_FLAGS3, descs[3]); 2292 break; 2293 default: 2294 #if 0 2295 aprint_verbose("%s: basic %08x-eax %08x\n", 2296 cpuname, bi_index, descs[0]); 2297 aprint_verbose("%s: basic %08x-ebx %08x\n", 2298 cpuname, bi_index, descs[1]); 2299 aprint_verbose("%s: basic %08x-ecx %08x\n", 2300 cpuname, bi_index, descs[2]); 2301 aprint_verbose("%s: basic %08x-edx %08x\n", 2302 cpuname, bi_index, descs[3]); 2303 #endif 2304 break; 2305 } 2306 } 2307 } 2308 2309 #ifdef INTEL_ONDEMAND_CLOCKMOD 2310 clockmod_init(); 2311 #endif 2312 2313 if (cpu_vendor == CPUVENDOR_AMD) 2314 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2315 else if (cpu_vendor == CPUVENDOR_INTEL) 2316 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2317 else 2318 return; 2319 2320 ucode.data = &ucvers; 2321 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2322 #ifdef __i386__ 2323 struct cpu_ucode_version_64 ucode_64; 2324 if (errno != ENOTTY) 2325 return; 2326 /* Try the 64 bit ioctl */ 2327 memset(&ucode_64, 0, sizeof ucode_64); 2328 ucode_64.data = &ucvers; 2329 ucode_64.loader_version = ucode.loader_version; 2330 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2331 return; 2332 #else 2333 return; 2334 #endif 2335 } 2336 2337 if (cpu_vendor == CPUVENDOR_AMD) 2338 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2339 else if (cpu_vendor == CPUVENDOR_INTEL) 2340 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2341 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2342 } 2343 2344 static const struct x86_cache_info * 2345 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2346 { 2347 int i; 2348 2349 for (i = 0; cai[i].cai_desc != 0; i++) { 2350 if (cai[i].cai_desc == desc) 2351 return (&cai[i]); 2352 } 2353 2354 return (NULL); 2355 } 2356 2357 static const char * 2358 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2359 const char *sep) 2360 { 2361 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2362 char human_num[HUMAN_BUFSIZE]; 2363 2364 if (cai->cai_totalsize == 0) 2365 return sep; 2366 2367 if (sep == NULL) 2368 aprint_verbose_dev(ci->ci_dev, ""); 2369 else 2370 aprint_verbose("%s", sep); 2371 if (name != NULL) 2372 aprint_verbose("%s ", name); 2373 2374 if (cai->cai_string != NULL) { 2375 aprint_verbose("%s ", cai->cai_string); 2376 } else { 2377 (void)humanize_number(human_num, sizeof(human_num), 2378 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2379 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2380 } 2381 switch (cai->cai_associativity) { 2382 case 0: 2383 aprint_verbose("disabled"); 2384 break; 2385 case 1: 2386 aprint_verbose("direct-mapped"); 2387 break; 2388 case 0xff: 2389 aprint_verbose("fully associative"); 2390 break; 2391 default: 2392 aprint_verbose("%d-way", cai->cai_associativity); 2393 break; 2394 } 2395 return ", "; 2396 } 2397 2398 static const char * 2399 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2400 const char *sep) 2401 { 2402 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2403 char human_num[HUMAN_BUFSIZE]; 2404 2405 if (cai->cai_totalsize == 0) 2406 return sep; 2407 2408 if (sep == NULL) 2409 aprint_verbose_dev(ci->ci_dev, ""); 2410 else 2411 aprint_verbose("%s", sep); 2412 if (name != NULL) 2413 aprint_verbose("%s ", name); 2414 2415 if (cai->cai_string != NULL) { 2416 aprint_verbose("%s", cai->cai_string); 2417 } else { 2418 (void)humanize_number(human_num, sizeof(human_num), 2419 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2420 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2421 human_num); 2422 switch (cai->cai_associativity) { 2423 case 0: 2424 aprint_verbose("disabled"); 2425 break; 2426 case 1: 2427 aprint_verbose("direct-mapped"); 2428 break; 2429 case 0xff: 2430 aprint_verbose("fully associative"); 2431 break; 2432 default: 2433 aprint_verbose("%d-way", cai->cai_associativity); 2434 break; 2435 } 2436 } 2437 return ", "; 2438 } 2439 2440 static void 2441 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2442 { 2443 const char *sep = NULL; 2444 2445 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2446 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2447 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2448 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2449 if (sep != NULL) 2450 aprint_verbose("\n"); 2451 } 2452 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2453 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2454 if (sep != NULL) 2455 aprint_verbose("\n"); 2456 } 2457 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2458 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2459 if (sep != NULL) 2460 aprint_verbose("\n"); 2461 } 2462 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2463 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2464 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2465 if (sep != NULL) 2466 aprint_verbose("\n"); 2467 } 2468 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2469 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2470 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2471 if (sep != NULL) 2472 aprint_verbose("\n"); 2473 } 2474 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2475 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2476 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2477 if (sep != NULL) 2478 aprint_verbose("\n"); 2479 } 2480 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2481 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2482 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2483 if (sep != NULL) 2484 aprint_verbose("\n"); 2485 } 2486 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2487 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2488 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2489 if (sep != NULL) 2490 aprint_verbose("\n"); 2491 } 2492 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2493 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2494 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2495 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2496 if (sep != NULL) 2497 aprint_verbose("\n"); 2498 } 2499 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2500 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2501 NULL); 2502 if (sep != NULL) 2503 aprint_verbose("\n"); 2504 } 2505 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2506 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2507 NULL); 2508 if (sep != NULL) 2509 aprint_verbose("\n"); 2510 } 2511 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2512 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2513 NULL); 2514 if (sep != NULL) 2515 aprint_verbose("\n"); 2516 } 2517 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2518 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2519 NULL); 2520 if (sep != NULL) 2521 aprint_verbose("\n"); 2522 } 2523 } 2524 2525 static void 2526 powernow_probe(struct cpu_info *ci) 2527 { 2528 uint32_t regs[4]; 2529 char buf[256]; 2530 2531 x86_cpuid(0x80000007, regs); 2532 2533 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2534 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2535 } 2536 2537 bool 2538 identifycpu_bind(void) 2539 { 2540 2541 return true; 2542 } 2543 2544 int 2545 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2546 { 2547 struct cpu_info ci; 2548 int loader_version, res; 2549 struct cpu_ucode_version versreq; 2550 2551 cpu_probe_base_features(&ci, "unknown"); 2552 2553 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2554 loader_version = CPU_UCODE_LOADER_AMD; 2555 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2556 loader_version = CPU_UCODE_LOADER_INTEL1; 2557 else 2558 return -1; 2559 2560 /* check whether the kernel understands this loader version */ 2561 versreq.loader_version = loader_version; 2562 versreq.data = 0; 2563 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2564 if (res) 2565 return -1; 2566 2567 switch (loader_version) { 2568 case CPU_UCODE_LOADER_AMD: 2569 if (uc->cpu_nr != -1) { 2570 /* printf? */ 2571 return -1; 2572 } 2573 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2574 break; 2575 case CPU_UCODE_LOADER_INTEL1: 2576 if (uc->cpu_nr == -1) 2577 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2578 else 2579 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2580 break; 2581 default: /* can't happen */ 2582 return -1; 2583 } 2584 uc->loader_version = loader_version; 2585 return 0; 2586 } 2587
Indexes created Sat Oct 25 16:10:12 GMT 2025