i386.c revision 1.95
1 /* $NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.95 2019/03/24 04:43:54 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] structure ext. feat. %edx 110 * [8] XCR0 bits (d:0 %eax) 111 * [9] xsave flags (d:1 %eax) 112 */ 113 uint32_t ci_cpu_class; /* CPU class */ 114 uint32_t ci_brand_id; /* Intel brand id */ 115 uint32_t ci_vendor[4]; /* vendor string */ 116 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 117 uint64_t ci_tsc_freq; /* cpu cycles/second */ 118 uint8_t ci_packageid; 119 uint8_t ci_coreid; 120 uint8_t ci_smtid; 121 uint32_t ci_initapicid; 122 123 uint32_t ci_cur_xsave; 124 uint32_t ci_max_xsave; 125 126 struct x86_cache_info ci_cinfo[CAI_COUNT]; 127 void (*ci_info)(struct cpu_info *); 128 }; 129 130 struct cpu_nocpuid_nameclass { 131 int cpu_vendor; 132 const char *cpu_vendorname; 133 const char *cpu_name; 134 int cpu_class; 135 void (*cpu_setup)(struct cpu_info *); 136 void (*cpu_cacheinfo)(struct cpu_info *); 137 void (*cpu_info)(struct cpu_info *); 138 }; 139 140 struct cpu_cpuid_nameclass { 141 const char *cpu_id; 142 int cpu_vendor; 143 const char *cpu_vendorname; 144 struct cpu_cpuid_family { 145 int cpu_class; 146 const char *cpu_models[256]; 147 const char *cpu_model_default; 148 void (*cpu_setup)(struct cpu_info *); 149 void (*cpu_probe)(struct cpu_info *); 150 void (*cpu_info)(struct cpu_info *); 151 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 152 }; 153 154 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 155 156 /* 157 * Map Brand ID from cpuid instruction to brand name. 158 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 159 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 160 * Architectures Software Developer's Manual, Volume 2A". 161 */ 162 static const char * const i386_intel_brand[] = { 163 "", /* Unsupported */ 164 "Celeron", /* Intel (R) Celeron (TM) processor */ 165 "Pentium III", /* Intel (R) Pentium (R) III processor */ 166 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 167 "Pentium III", /* Intel (R) Pentium (R) III processor */ 168 "", /* 0x05: Reserved */ 169 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 170 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 171 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 172 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 173 "Celeron", /* Intel (R) Celeron (TM) processor */ 174 "Xeon", /* Intel (R) Xeon (TM) processor */ 175 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 176 "", /* 0x0d: Reserved */ 177 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "", /* 0x10: Reserved */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Celeron M", /* Intel (R) Celeron (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 "Celeron", /* Intel (R) Celeron (R) processor */ 184 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 185 "Pentium M", /* Intel (R) Pentium (R) M processor */ 186 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 187 }; 188 189 /* 190 * AMD processors don't have Brand IDs, so we need these names for probe. 191 */ 192 static const char * const amd_brand[] = { 193 "", 194 "Duron", /* AMD Duron(tm) */ 195 "MP", /* AMD Athlon(tm) MP */ 196 "XP", /* AMD Athlon(tm) XP */ 197 "4" /* AMD Athlon(tm) 4 */ 198 }; 199 200 static int cpu_vendor; 201 static char cpu_brand_string[49]; 202 static char amd_brand_name[48]; 203 static int use_pae, largepagesize; 204 205 /* Setup functions */ 206 static void disable_tsc(struct cpu_info *); 207 static void amd_family5_setup(struct cpu_info *); 208 static void cyrix6x86_cpu_setup(struct cpu_info *); 209 static void winchip_cpu_setup(struct cpu_info *); 210 /* Brand/Model name functions */ 211 static const char *intel_family6_name(struct cpu_info *); 212 static const char *amd_amd64_name(struct cpu_info *); 213 /* Probe functions */ 214 static void amd_family6_probe(struct cpu_info *); 215 static void powernow_probe(struct cpu_info *); 216 static void intel_family_new_probe(struct cpu_info *); 217 static void via_cpu_probe(struct cpu_info *); 218 /* (Cache) Info functions */ 219 static void intel_cpu_cacheinfo(struct cpu_info *); 220 static void amd_cpu_cacheinfo(struct cpu_info *); 221 static void via_cpu_cacheinfo(struct cpu_info *); 222 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 223 static void transmeta_cpu_info(struct cpu_info *); 224 /* Common functions */ 225 static void cpu_probe_base_features(struct cpu_info *, const char *); 226 static void cpu_probe_hv_features(struct cpu_info *, const char *); 227 static void cpu_probe_features(struct cpu_info *); 228 static void print_bits(const char *, const char *, const char *, uint32_t); 229 static void identifycpu_cpuids(struct cpu_info *); 230 static const struct x86_cache_info *cache_info_lookup( 231 const struct x86_cache_info *, uint8_t); 232 static const char *print_cache_config(struct cpu_info *, int, const char *, 233 const char *); 234 static const char *print_tlb_config(struct cpu_info *, int, const char *, 235 const char *); 236 static void x86_print_cache_and_tlb_info(struct cpu_info *); 237 238 /* 239 * Note: these are just the ones that may not have a cpuid instruction. 240 * We deal with the rest in a different way. 241 */ 242 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 243 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 244 NULL, NULL, NULL }, /* CPU_386SX */ 245 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 246 NULL, NULL, NULL }, /* CPU_386 */ 247 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 248 NULL, NULL, NULL }, /* CPU_486SX */ 249 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_486 */ 251 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 252 NULL, NULL, NULL }, /* CPU_486DLC */ 253 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 254 NULL, NULL, NULL }, /* CPU_6x86 */ 255 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 256 NULL, NULL, NULL }, /* CPU_NX586 */ 257 }; 258 259 const char *classnames[] = { 260 "386", 261 "486", 262 "586", 263 "686" 264 }; 265 266 const char *modifiers[] = { 267 "", 268 "OverDrive", 269 "Dual", 270 "" 271 }; 272 273 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 274 { 275 /* 276 * For Intel processors, check Chapter 35Model-specific 277 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 278 * Software Developer's Manual, Volume 3C". 279 */ 280 "GenuineIntel", 281 CPUVENDOR_INTEL, 282 "Intel", 283 /* Family 4 */ 284 { { 285 CPUCLASS_486, 286 { 287 "486DX", "486DX", "486SX", "486DX2", "486SL", 288 "486SX2", 0, "486DX2 W/B Enhanced", 289 "486DX4", 0, 0, 0, 0, 0, 0, 0, 290 }, 291 "486", /* Default */ 292 NULL, 293 NULL, 294 intel_cpu_cacheinfo, 295 }, 296 /* Family 5 */ 297 { 298 CPUCLASS_586, 299 { 300 "Pentium (P5 A-step)", "Pentium (P5)", 301 "Pentium (P54C)", "Pentium (P24T)", 302 "Pentium/MMX", "Pentium", 0, 303 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 304 "Quark X1000", 0, 0, 0, 0, 0, 0, 305 }, 306 "Pentium", /* Default */ 307 NULL, 308 NULL, 309 intel_cpu_cacheinfo, 310 }, 311 /* Family 6 */ 312 { 313 CPUCLASS_686, 314 { 315 [0x00] = "Pentium Pro (A-step)", 316 [0x01] = "Pentium Pro", 317 [0x03] = "Pentium II (Klamath)", 318 [0x04] = "Pentium Pro", 319 [0x05] = "Pentium II/Celeron (Deschutes)", 320 [0x06] = "Celeron (Mendocino)", 321 [0x07] = "Pentium III (Katmai)", 322 [0x08] = "Pentium III (Coppermine)", 323 [0x09] = "Pentium M (Banias)", 324 [0x0a] = "Pentium III Xeon (Cascades)", 325 [0x0b] = "Pentium III (Tualatin)", 326 [0x0d] = "Pentium M (Dothan)", 327 [0x0e] = "Pentium Core Duo, Core solo", 328 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 329 "Core 2 Quad 6xxx, " 330 "Core 2 Extreme 6xxx, " 331 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 332 "and Pentium DC", 333 [0x15] = "EP80579 Integrated Processor", 334 [0x16] = "Celeron (45nm)", 335 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 336 "Core 2 Quad 8xxx and 9xxx", 337 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 338 "(Nehalem)", 339 [0x1c] = "45nm Atom Family", 340 [0x1d] = "XeonMP 74xx (Nehalem)", 341 [0x1e] = "Core i7 and i5", 342 [0x1f] = "Core i7 and i5", 343 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 344 [0x26] = "Atom Family", 345 [0x27] = "Atom Family", 346 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 347 "i3 2xxx", 348 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 349 [0x2d] = "Xeon E5 Sandy Bridge family, " 350 "Core i7-39xx Extreme", 351 [0x2e] = "Xeon 75xx & 65xx", 352 [0x2f] = "Xeon E7 family", 353 [0x35] = "Atom Family", 354 [0x36] = "Atom S1000", 355 [0x37] = "Atom E3000, Z3[67]00", 356 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 357 "Ivy Bridge", 358 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 359 "(Haswell)", 360 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 361 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 362 "Core i7-49xx Extreme", 363 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 364 "Core i7-59xx Extreme", 365 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 366 "(Haswell)", 367 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 368 "(Haswell)", 369 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 370 [0x4a] = "Atom Z3400", 371 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 372 [0x4d] = "Atom C2000", 373 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 374 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 375 [0x55] = "Xeon Scalable (Skylake)", 376 [0x56] = "Xeon D-1500 (Broadwell)", 377 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 378 [0x5a] = "Atom E3500", 379 [0x5c] = "Atom (Goldmont)", 380 [0x5d] = "Atom X3-C3000 (Silvermont)", 381 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 382 [0x5f] = "Atom (Goldmont, Denverton)", 383 [0x66] = "Future Core (Cannon Lake)", 384 [0x7a] = "Atom (Goldmont Plus)", 385 [0x7e] = "Future Core (Ice Lake)", 386 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 387 [0x86] = "Atom (Tremont)", 388 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 389 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 390 }, 391 "Pentium Pro, II or III", /* Default */ 392 NULL, 393 intel_family_new_probe, 394 intel_cpu_cacheinfo, 395 }, 396 /* Family > 6 */ 397 { 398 CPUCLASS_686, 399 { 400 0, 0, 0, 0, 0, 0, 0, 0, 401 0, 0, 0, 0, 0, 0, 0, 0, 402 }, 403 "Pentium 4", /* Default */ 404 NULL, 405 intel_family_new_probe, 406 intel_cpu_cacheinfo, 407 } } 408 }, 409 { 410 "AuthenticAMD", 411 CPUVENDOR_AMD, 412 "AMD", 413 /* Family 4 */ 414 { { 415 CPUCLASS_486, 416 { 417 0, 0, 0, "Am486DX2 W/T", 418 0, 0, 0, "Am486DX2 W/B", 419 "Am486DX4 W/T or Am5x86 W/T 150", 420 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 421 0, 0, "Am5x86 W/T 133/160", 422 "Am5x86 W/B 133/160", 423 }, 424 "Am486 or Am5x86", /* Default */ 425 NULL, 426 NULL, 427 NULL, 428 }, 429 /* Family 5 */ 430 { 431 CPUCLASS_586, 432 { 433 "K5", "K5", "K5", "K5", 0, 0, "K6", 434 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 435 "K6-2+/III+", 0, 0, 436 }, 437 "K5 or K6", /* Default */ 438 amd_family5_setup, 439 NULL, 440 amd_cpu_cacheinfo, 441 }, 442 /* Family 6 */ 443 { 444 CPUCLASS_686, 445 { 446 0, "Athlon Model 1", "Athlon Model 2", 447 "Duron", "Athlon Model 4 (Thunderbird)", 448 0, "Athlon", "Duron", "Athlon", 0, 449 "Athlon", 0, 0, 0, 0, 0, 450 }, 451 "K7 (Athlon)", /* Default */ 452 NULL, 453 amd_family6_probe, 454 amd_cpu_cacheinfo, 455 }, 456 /* Family > 6 */ 457 { 458 CPUCLASS_686, 459 { 460 0, 0, 0, 0, 0, 0, 0, 0, 461 0, 0, 0, 0, 0, 0, 0, 0, 462 }, 463 "Unknown K8 (Athlon)", /* Default */ 464 NULL, 465 amd_family6_probe, 466 amd_cpu_cacheinfo, 467 } } 468 }, 469 { 470 "CyrixInstead", 471 CPUVENDOR_CYRIX, 472 "Cyrix", 473 /* Family 4 */ 474 { { 475 CPUCLASS_486, 476 { 477 0, 0, 0, 478 "MediaGX", 479 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 480 }, 481 "486", /* Default */ 482 cyrix6x86_cpu_setup, /* XXX ?? */ 483 NULL, 484 NULL, 485 }, 486 /* Family 5 */ 487 { 488 CPUCLASS_586, 489 { 490 0, 0, "6x86", 0, 491 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 493 }, 494 "6x86", /* Default */ 495 cyrix6x86_cpu_setup, 496 NULL, 497 NULL, 498 }, 499 /* Family 6 */ 500 { 501 CPUCLASS_686, 502 { 503 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 504 0, 0, 0, 0, 0, 0, 0, 0, 505 }, 506 "6x86MX", /* Default */ 507 cyrix6x86_cpu_setup, 508 NULL, 509 NULL, 510 }, 511 /* Family > 6 */ 512 { 513 CPUCLASS_686, 514 { 515 0, 0, 0, 0, 0, 0, 0, 0, 516 0, 0, 0, 0, 0, 0, 0, 0, 517 }, 518 "Unknown 6x86MX", /* Default */ 519 NULL, 520 NULL, 521 NULL, 522 } } 523 }, 524 { /* MediaGX is now owned by National Semiconductor */ 525 "Geode by NSC", 526 CPUVENDOR_CYRIX, /* XXX */ 527 "National Semiconductor", 528 /* Family 4, NSC never had any of these */ 529 { { 530 CPUCLASS_486, 531 { 532 0, 0, 0, 0, 0, 0, 0, 0, 533 0, 0, 0, 0, 0, 0, 0, 0, 534 }, 535 "486 compatible", /* Default */ 536 NULL, 537 NULL, 538 NULL, 539 }, 540 /* Family 5: Geode family, formerly MediaGX */ 541 { 542 CPUCLASS_586, 543 { 544 0, 0, 0, 0, 545 "Geode GX1", 546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 547 }, 548 "Geode", /* Default */ 549 cyrix6x86_cpu_setup, 550 NULL, 551 amd_cpu_cacheinfo, 552 }, 553 /* Family 6, not yet available from NSC */ 554 { 555 CPUCLASS_686, 556 { 557 0, 0, 0, 0, 0, 0, 0, 0, 558 0, 0, 0, 0, 0, 0, 0, 0, 559 }, 560 "Pentium Pro compatible", /* Default */ 561 NULL, 562 NULL, 563 NULL, 564 }, 565 /* Family > 6, not yet available from NSC */ 566 { 567 CPUCLASS_686, 568 { 569 0, 0, 0, 0, 0, 0, 0, 0, 570 0, 0, 0, 0, 0, 0, 0, 0, 571 }, 572 "Pentium Pro compatible", /* Default */ 573 NULL, 574 NULL, 575 NULL, 576 } } 577 }, 578 { 579 "CentaurHauls", 580 CPUVENDOR_IDT, 581 "IDT", 582 /* Family 4, IDT never had any of these */ 583 { { 584 CPUCLASS_486, 585 { 586 0, 0, 0, 0, 0, 0, 0, 0, 587 0, 0, 0, 0, 0, 0, 0, 0, 588 }, 589 "486 compatible", /* Default */ 590 NULL, 591 NULL, 592 NULL, 593 }, 594 /* Family 5 */ 595 { 596 CPUCLASS_586, 597 { 598 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 599 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 600 }, 601 "WinChip", /* Default */ 602 winchip_cpu_setup, 603 NULL, 604 NULL, 605 }, 606 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 607 { 608 CPUCLASS_686, 609 { 610 0, 0, 0, 0, 0, 0, "C3 Samuel", 611 "C3 Samuel 2/Ezra", "C3 Ezra-T", 612 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 613 0, "VIA Nano", 614 }, 615 "Unknown VIA/IDT", /* Default */ 616 NULL, 617 via_cpu_probe, 618 via_cpu_cacheinfo, 619 }, 620 /* Family > 6, not yet available from VIA */ 621 { 622 CPUCLASS_686, 623 { 624 0, 0, 0, 0, 0, 0, 0, 0, 625 0, 0, 0, 0, 0, 0, 0, 0, 626 }, 627 "Pentium Pro compatible", /* Default */ 628 NULL, 629 NULL, 630 NULL, 631 } } 632 }, 633 { 634 "GenuineTMx86", 635 CPUVENDOR_TRANSMETA, 636 "Transmeta", 637 /* Family 4, Transmeta never had any of these */ 638 { { 639 CPUCLASS_486, 640 { 641 0, 0, 0, 0, 0, 0, 0, 0, 642 0, 0, 0, 0, 0, 0, 0, 0, 643 }, 644 "486 compatible", /* Default */ 645 NULL, 646 NULL, 647 NULL, 648 }, 649 /* Family 5 */ 650 { 651 CPUCLASS_586, 652 { 653 0, 0, 0, 0, 0, 0, 0, 0, 654 0, 0, 0, 0, 0, 0, 0, 0, 655 }, 656 "Crusoe", /* Default */ 657 NULL, 658 NULL, 659 transmeta_cpu_info, 660 }, 661 /* Family 6, not yet available from Transmeta */ 662 { 663 CPUCLASS_686, 664 { 665 0, 0, 0, 0, 0, 0, 0, 0, 666 0, 0, 0, 0, 0, 0, 0, 0, 667 }, 668 "Pentium Pro compatible", /* Default */ 669 NULL, 670 NULL, 671 NULL, 672 }, 673 /* Family > 6, not yet available from Transmeta */ 674 { 675 CPUCLASS_686, 676 { 677 0, 0, 0, 0, 0, 0, 0, 0, 678 0, 0, 0, 0, 0, 0, 0, 0, 679 }, 680 "Pentium Pro compatible", /* Default */ 681 NULL, 682 NULL, 683 NULL, 684 } } 685 } 686 }; 687 688 /* 689 * disable the TSC such that we don't use the TSC in microtime(9) 690 * because some CPUs got the implementation wrong. 691 */ 692 static void 693 disable_tsc(struct cpu_info *ci) 694 { 695 if (ci->ci_feat_val[0] & CPUID_TSC) { 696 ci->ci_feat_val[0] &= ~CPUID_TSC; 697 aprint_error("WARNING: broken TSC disabled\n"); 698 } 699 } 700 701 static void 702 amd_family5_setup(struct cpu_info *ci) 703 { 704 705 switch (ci->ci_model) { 706 case 0: /* AMD-K5 Model 0 */ 707 /* 708 * According to the AMD Processor Recognition App Note, 709 * the AMD-K5 Model 0 uses the wrong bit to indicate 710 * support for global PTEs, instead using bit 9 (APIC) 711 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 712 */ 713 if (ci->ci_feat_val[0] & CPUID_APIC) 714 ci->ci_feat_val[0] = 715 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 716 /* 717 * XXX But pmap_pg_g is already initialized -- need to kick 718 * XXX the pmap somehow. How does the MP branch do this? 719 */ 720 break; 721 } 722 } 723 724 static void 725 cyrix6x86_cpu_setup(struct cpu_info *ci) 726 { 727 728 /* 729 * Do not disable the TSC on the Geode GX, it's reported to 730 * work fine. 731 */ 732 if (ci->ci_signature != 0x552) 733 disable_tsc(ci); 734 } 735 736 static void 737 winchip_cpu_setup(struct cpu_info *ci) 738 { 739 switch (ci->ci_model) { 740 case 4: /* WinChip C6 */ 741 disable_tsc(ci); 742 } 743 } 744 745 746 static const char * 747 intel_family6_name(struct cpu_info *ci) 748 { 749 const char *ret = NULL; 750 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 751 752 if (ci->ci_model == 5) { 753 switch (l2cache) { 754 case 0: 755 case 128 * 1024: 756 ret = "Celeron (Covington)"; 757 break; 758 case 256 * 1024: 759 ret = "Mobile Pentium II (Dixon)"; 760 break; 761 case 512 * 1024: 762 ret = "Pentium II"; 763 break; 764 case 1 * 1024 * 1024: 765 case 2 * 1024 * 1024: 766 ret = "Pentium II Xeon"; 767 break; 768 } 769 } else if (ci->ci_model == 6) { 770 switch (l2cache) { 771 case 256 * 1024: 772 case 512 * 1024: 773 ret = "Mobile Pentium II"; 774 break; 775 } 776 } else if (ci->ci_model == 7) { 777 switch (l2cache) { 778 case 512 * 1024: 779 ret = "Pentium III"; 780 break; 781 case 1 * 1024 * 1024: 782 case 2 * 1024 * 1024: 783 ret = "Pentium III Xeon"; 784 break; 785 } 786 } else if (ci->ci_model >= 8) { 787 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 788 switch (ci->ci_brand_id) { 789 case 0x3: 790 if (ci->ci_signature == 0x6B1) 791 ret = "Celeron"; 792 break; 793 case 0x8: 794 if (ci->ci_signature >= 0xF13) 795 ret = "genuine processor"; 796 break; 797 case 0xB: 798 if (ci->ci_signature >= 0xF13) 799 ret = "Xeon MP"; 800 break; 801 case 0xE: 802 if (ci->ci_signature < 0xF13) 803 ret = "Xeon"; 804 break; 805 } 806 if (ret == NULL) 807 ret = i386_intel_brand[ci->ci_brand_id]; 808 } 809 } 810 811 return ret; 812 } 813 814 /* 815 * Identify AMD64 CPU names from cpuid. 816 * 817 * Based on: 818 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 819 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 820 * "Revision Guide for AMD NPT Family 0Fh Processors" 821 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 822 * and other miscellaneous reports. 823 * 824 * This is all rather pointless, these are cross 'brand' since the raw 825 * silicon is shared. 826 */ 827 static const char * 828 amd_amd64_name(struct cpu_info *ci) 829 { 830 static char family_str[32]; 831 832 /* Only called if family >= 15 */ 833 834 switch (ci->ci_family) { 835 case 15: 836 switch (ci->ci_model) { 837 case 0x21: /* rev JH-E1/E6 */ 838 case 0x41: /* rev JH-F2 */ 839 return "Dual-Core Opteron"; 840 case 0x23: /* rev JH-E6 (Toledo) */ 841 return "Dual-Core Opteron or Athlon 64 X2"; 842 case 0x43: /* rev JH-F2 (Windsor) */ 843 return "Athlon 64 FX or Athlon 64 X2"; 844 case 0x24: /* rev SH-E5 (Lancaster?) */ 845 return "Mobile Athlon 64 or Turion 64"; 846 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 847 return "Opteron or Athlon 64 FX"; 848 case 0x15: /* rev SH-D0 */ 849 case 0x25: /* rev SH-E4 */ 850 return "Opteron"; 851 case 0x27: /* rev DH-E4, SH-E4 */ 852 return "Athlon 64 or Athlon 64 FX or Opteron"; 853 case 0x48: /* rev BH-F2 */ 854 return "Turion 64 X2"; 855 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 856 case 0x07: /* rev SH-CG (ClawHammer) */ 857 case 0x0b: /* rev CH-CG */ 858 case 0x14: /* rev SH-D0 */ 859 case 0x17: /* rev SH-D0 */ 860 case 0x1b: /* rev CH-D0 */ 861 return "Athlon 64"; 862 case 0x2b: /* rev BH-E4 (Manchester) */ 863 case 0x4b: /* rev BH-F2 (Windsor) */ 864 return "Athlon 64 X2"; 865 case 0x6b: /* rev BH-G1 (Brisbane) */ 866 return "Athlon X2 or Athlon 64 X2"; 867 case 0x08: /* rev CH-CG */ 868 case 0x0c: /* rev DH-CG (Newcastle) */ 869 case 0x0e: /* rev DH-CG (Newcastle?) */ 870 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 871 case 0x18: /* rev CH-D0 */ 872 case 0x1c: /* rev DH-D0 (Winchester) */ 873 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 874 case 0x2c: /* rev DH-E3/E6 */ 875 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 876 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 877 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 878 case 0x6f: /* rev DH-G1 */ 879 return "Athlon 64 or Sempron"; 880 default: 881 break; 882 } 883 return "Unknown AMD64 CPU"; 884 885 #if 0 886 case 16: 887 return "Family 10h"; 888 case 17: 889 return "Family 11h"; 890 case 18: 891 return "Family 12h"; 892 case 19: 893 return "Family 14h"; 894 case 20: 895 return "Family 15h"; 896 #endif 897 898 default: 899 break; 900 } 901 902 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 903 return family_str; 904 } 905 906 static void 907 intel_family_new_probe(struct cpu_info *ci) 908 { 909 uint32_t descs[4]; 910 911 x86_cpuid(0x80000000, descs); 912 913 /* 914 * Determine extended feature flags. 915 */ 916 if (descs[0] >= 0x80000001) { 917 x86_cpuid(0x80000001, descs); 918 ci->ci_feat_val[2] |= descs[3]; 919 ci->ci_feat_val[3] |= descs[2]; 920 } 921 } 922 923 static void 924 via_cpu_probe(struct cpu_info *ci) 925 { 926 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 927 u_int descs[4]; 928 u_int lfunc; 929 930 /* 931 * Determine the largest extended function value. 932 */ 933 x86_cpuid(0x80000000, descs); 934 lfunc = descs[0]; 935 936 /* 937 * Determine the extended feature flags. 938 */ 939 if (lfunc >= 0x80000001) { 940 x86_cpuid(0x80000001, descs); 941 ci->ci_feat_val[2] |= descs[3]; 942 } 943 944 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 945 return; 946 947 /* Nehemiah or Esther */ 948 x86_cpuid(0xc0000000, descs); 949 lfunc = descs[0]; 950 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 951 return; 952 953 x86_cpuid(0xc0000001, descs); 954 lfunc = descs[3]; 955 ci->ci_feat_val[4] = lfunc; 956 } 957 958 static void 959 amd_family6_probe(struct cpu_info *ci) 960 { 961 uint32_t descs[4]; 962 char *p; 963 size_t i; 964 965 x86_cpuid(0x80000000, descs); 966 967 /* 968 * Determine the extended feature flags. 969 */ 970 if (descs[0] >= 0x80000001) { 971 x86_cpuid(0x80000001, descs); 972 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 973 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 974 } 975 976 if (*cpu_brand_string == '\0') 977 return; 978 979 for (i = 1; i < __arraycount(amd_brand); i++) 980 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 981 ci->ci_brand_id = i; 982 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 983 break; 984 } 985 } 986 987 static void 988 intel_cpu_cacheinfo(struct cpu_info *ci) 989 { 990 const struct x86_cache_info *cai; 991 u_int descs[4]; 992 int iterations, i, j; 993 int type, level; 994 int ways, partitions, linesize, sets; 995 int caitype = -1; 996 int totalsize; 997 uint8_t desc; 998 999 /* Return if the cpu is old pre-cpuid instruction cpu */ 1000 if (ci->ci_cpu_type >= 0) 1001 return; 1002 1003 if (ci->ci_cpuid_level < 2) 1004 return; 1005 1006 /* 1007 * Parse the cache info from `cpuid leaf 2', if we have it. 1008 * XXX This is kinda ugly, but hey, so is the architecture... 1009 */ 1010 x86_cpuid(2, descs); 1011 iterations = descs[0] & 0xff; 1012 while (iterations-- > 0) { 1013 for (i = 0; i < 4; i++) { 1014 if (descs[i] & 0x80000000) 1015 continue; 1016 for (j = 0; j < 4; j++) { 1017 /* 1018 * The least significant byte in EAX 1019 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1020 * it should be ignored. 1021 */ 1022 if (i == 0 && j == 0) 1023 continue; 1024 desc = (descs[i] >> (j * 8)) & 0xff; 1025 if (desc == 0) 1026 continue; 1027 cai = cache_info_lookup(intel_cpuid_cache_info, 1028 desc); 1029 if (cai != NULL) 1030 ci->ci_cinfo[cai->cai_index] = *cai; 1031 else if ((verbose != 0) && (desc != 0xff) 1032 && (desc != 0xfe)) 1033 aprint_error_dev(ci->ci_dev, "error:" 1034 " Unknown cacheinfo desc %02x\n", 1035 desc); 1036 } 1037 } 1038 x86_cpuid(2, descs); 1039 } 1040 1041 if (ci->ci_cpuid_level < 4) 1042 return; 1043 1044 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1045 for (i = 0; ; i++) { 1046 x86_cpuid2(4, i, descs); 1047 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1048 if (type == CPUID_DCP_CACHETYPE_N) 1049 break; 1050 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1051 switch (level) { 1052 case 1: 1053 if (type == CPUID_DCP_CACHETYPE_I) 1054 caitype = CAI_ICACHE; 1055 else if (type == CPUID_DCP_CACHETYPE_D) 1056 caitype = CAI_DCACHE; 1057 else 1058 caitype = -1; 1059 break; 1060 case 2: 1061 if (type == CPUID_DCP_CACHETYPE_U) 1062 caitype = CAI_L2CACHE; 1063 else 1064 caitype = -1; 1065 break; 1066 case 3: 1067 if (type == CPUID_DCP_CACHETYPE_U) 1068 caitype = CAI_L3CACHE; 1069 else 1070 caitype = -1; 1071 break; 1072 default: 1073 caitype = -1; 1074 break; 1075 } 1076 if (caitype == -1) { 1077 aprint_error_dev(ci->ci_dev, 1078 "error: unknown cache level&type (%d & %d)\n", 1079 level, type); 1080 continue; 1081 } 1082 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1083 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1084 + 1; 1085 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1086 + 1; 1087 sets = descs[2] + 1; 1088 totalsize = ways * partitions * linesize * sets; 1089 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1090 ci->ci_cinfo[caitype].cai_associativity = ways; 1091 ci->ci_cinfo[caitype].cai_linesize = linesize; 1092 } 1093 1094 if (ci->ci_cpuid_level < 0x18) 1095 return; 1096 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1097 x86_cpuid(0x18, descs); 1098 iterations = descs[0]; 1099 for (i = 0; i <= iterations; i++) { 1100 uint32_t pgsize; 1101 bool full; 1102 1103 x86_cpuid2(0x18, i, descs); 1104 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1105 if (type == CPUID_DATP_TCTYPE_N) 1106 continue; 1107 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1108 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1109 switch (level) { 1110 case 1: 1111 if (type == CPUID_DATP_TCTYPE_I) { 1112 switch (pgsize) { 1113 case CPUID_DATP_PGSIZE_4KB: 1114 caitype = CAI_ITLB; 1115 break; 1116 case CPUID_DATP_PGSIZE_2MB 1117 | CPUID_DATP_PGSIZE_4MB: 1118 caitype = CAI_ITLB2; 1119 break; 1120 case CPUID_DATP_PGSIZE_1GB: 1121 caitype = CAI_L1_1GBITLB; 1122 break; 1123 default: 1124 aprint_error_dev(ci->ci_dev, 1125 "error: unknown ITLB size (%d)\n", 1126 pgsize); 1127 caitype = CAI_ITLB; 1128 break; 1129 } 1130 } else if (type == CPUID_DATP_TCTYPE_D) { 1131 switch (pgsize) { 1132 case CPUID_DATP_PGSIZE_4KB: 1133 caitype = CAI_DTLB; 1134 break; 1135 case CPUID_DATP_PGSIZE_2MB 1136 | CPUID_DATP_PGSIZE_4MB: 1137 caitype = CAI_DTLB2; 1138 break; 1139 case CPUID_DATP_PGSIZE_1GB: 1140 caitype = CAI_L1_1GBDTLB; 1141 break; 1142 default: 1143 aprint_error_dev(ci->ci_dev, 1144 "error: unknown DTLB size (%d)\n", 1145 pgsize); 1146 caitype = CAI_DTLB; 1147 break; 1148 } 1149 } else 1150 caitype = -1; 1151 break; 1152 case 2: 1153 if (type == CPUID_DATP_TCTYPE_I) 1154 caitype = CAI_L2_ITLB; 1155 else if (type == CPUID_DATP_TCTYPE_D) 1156 caitype = CAI_L2_DTLB; 1157 else if (type == CPUID_DATP_TCTYPE_U) { 1158 switch (pgsize) { 1159 case CPUID_DATP_PGSIZE_4KB: 1160 caitype = CAI_L2_STLB; 1161 break; 1162 case CPUID_DATP_PGSIZE_4KB 1163 | CPUID_DATP_PGSIZE_2MB: 1164 caitype = CAI_L2_STLB2; 1165 break; 1166 case CPUID_DATP_PGSIZE_2MB 1167 | CPUID_DATP_PGSIZE_4MB: 1168 caitype = CAI_L2_STLB3; 1169 break; 1170 default: 1171 aprint_error_dev(ci->ci_dev, 1172 "error: unknown L2 STLB size (%d)\n", 1173 pgsize); 1174 caitype = CAI_DTLB; 1175 break; 1176 } 1177 } else 1178 caitype = -1; 1179 break; 1180 case 3: 1181 /* XXX need work for L3 TLB */ 1182 caitype = CAI_L3CACHE; 1183 break; 1184 default: 1185 caitype = -1; 1186 break; 1187 } 1188 if (caitype == -1) { 1189 aprint_error_dev(ci->ci_dev, 1190 "error: unknown TLB level&type (%d & %d)\n", 1191 level, type); 1192 continue; 1193 } 1194 switch (pgsize) { 1195 case CPUID_DATP_PGSIZE_4KB: 1196 linesize = 4 * 1024; 1197 break; 1198 case CPUID_DATP_PGSIZE_2MB: 1199 linesize = 2 * 1024 * 1024; 1200 break; 1201 case CPUID_DATP_PGSIZE_4MB: 1202 linesize = 4 * 1024 * 1024; 1203 break; 1204 case CPUID_DATP_PGSIZE_1GB: 1205 linesize = 1024 * 1024 * 1024; 1206 break; 1207 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1208 aprint_error_dev(ci->ci_dev, 1209 "WARINING: Currently 2M/4M info can't print correctly\n"); 1210 linesize = 4 * 1024 * 1024; 1211 break; 1212 default: 1213 aprint_error_dev(ci->ci_dev, 1214 "error: Unknown size combination\n"); 1215 linesize = 4 * 1024; 1216 break; 1217 } 1218 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1219 sets = descs[2]; 1220 full = descs[3] & CPUID_DATP_FULLASSOC; 1221 ci->ci_cinfo[caitype].cai_totalsize 1222 = ways * sets; /* entries */ 1223 ci->ci_cinfo[caitype].cai_associativity 1224 = full ? 0xff : ways; 1225 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1226 } 1227 } 1228 1229 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1230 AMD_L2CACHE_INFO; 1231 1232 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1233 AMD_L3CACHE_INFO; 1234 1235 static void 1236 amd_cpu_cacheinfo(struct cpu_info *ci) 1237 { 1238 const struct x86_cache_info *cp; 1239 struct x86_cache_info *cai; 1240 u_int descs[4]; 1241 u_int lfunc; 1242 1243 /* 1244 * K5 model 0 has none of this info. 1245 */ 1246 if (ci->ci_family == 5 && ci->ci_model == 0) 1247 return; 1248 1249 /* 1250 * Determine the largest extended function value. 1251 */ 1252 x86_cpuid(0x80000000, descs); 1253 lfunc = descs[0]; 1254 1255 /* 1256 * Determine L1 cache/TLB info. 1257 */ 1258 if (lfunc < 0x80000005) { 1259 /* No L1 cache info available. */ 1260 return; 1261 } 1262 1263 x86_cpuid(0x80000005, descs); 1264 1265 /* 1266 * K6-III and higher have large page TLBs. 1267 */ 1268 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1269 cai = &ci->ci_cinfo[CAI_ITLB2]; 1270 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1271 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1272 cai->cai_linesize = largepagesize; 1273 1274 cai = &ci->ci_cinfo[CAI_DTLB2]; 1275 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1276 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1277 cai->cai_linesize = largepagesize; 1278 } 1279 1280 cai = &ci->ci_cinfo[CAI_ITLB]; 1281 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1282 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1283 cai->cai_linesize = (4 * 1024); 1284 1285 cai = &ci->ci_cinfo[CAI_DTLB]; 1286 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1287 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1288 cai->cai_linesize = (4 * 1024); 1289 1290 cai = &ci->ci_cinfo[CAI_DCACHE]; 1291 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1292 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1293 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1294 1295 cai = &ci->ci_cinfo[CAI_ICACHE]; 1296 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1297 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1298 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1299 1300 /* 1301 * Determine L2 cache/TLB info. 1302 */ 1303 if (lfunc < 0x80000006) { 1304 /* No L2 cache info available. */ 1305 return; 1306 } 1307 1308 x86_cpuid(0x80000006, descs); 1309 1310 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1311 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1312 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1313 cai->cai_linesize = (4 * 1024); 1314 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1315 cai->cai_associativity); 1316 if (cp != NULL) 1317 cai->cai_associativity = cp->cai_associativity; 1318 else 1319 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1320 1321 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1322 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1323 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1324 cai->cai_linesize = largepagesize; 1325 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1326 cai->cai_associativity); 1327 if (cp != NULL) 1328 cai->cai_associativity = cp->cai_associativity; 1329 else 1330 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1331 1332 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1333 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1334 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1335 cai->cai_linesize = (4 * 1024); 1336 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1337 cai->cai_associativity); 1338 if (cp != NULL) 1339 cai->cai_associativity = cp->cai_associativity; 1340 else 1341 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1342 1343 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1344 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1345 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1346 cai->cai_linesize = largepagesize; 1347 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1348 cai->cai_associativity); 1349 if (cp != NULL) 1350 cai->cai_associativity = cp->cai_associativity; 1351 else 1352 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1353 1354 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1355 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1356 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1357 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1358 1359 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1360 cai->cai_associativity); 1361 if (cp != NULL) 1362 cai->cai_associativity = cp->cai_associativity; 1363 else 1364 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1365 1366 /* 1367 * Determine L3 cache info on AMD Family 10h and newer processors 1368 */ 1369 if (ci->ci_family >= 0x10) { 1370 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1371 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1372 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1373 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1374 1375 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1376 cai->cai_associativity); 1377 if (cp != NULL) 1378 cai->cai_associativity = cp->cai_associativity; 1379 else 1380 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1381 } 1382 1383 /* 1384 * Determine 1GB TLB info. 1385 */ 1386 if (lfunc < 0x80000019) { 1387 /* No 1GB TLB info available. */ 1388 return; 1389 } 1390 1391 x86_cpuid(0x80000019, descs); 1392 1393 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1394 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1395 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1396 cai->cai_linesize = (1024 * 1024 * 1024); 1397 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1398 cai->cai_associativity); 1399 if (cp != NULL) 1400 cai->cai_associativity = cp->cai_associativity; 1401 else 1402 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1403 1404 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1405 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1406 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1407 cai->cai_linesize = (1024 * 1024 * 1024); 1408 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1409 cai->cai_associativity); 1410 if (cp != NULL) 1411 cai->cai_associativity = cp->cai_associativity; 1412 else 1413 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1414 1415 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1416 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1417 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1418 cai->cai_linesize = (1024 * 1024 * 1024); 1419 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1420 cai->cai_associativity); 1421 if (cp != NULL) 1422 cai->cai_associativity = cp->cai_associativity; 1423 else 1424 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1425 1426 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1427 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1428 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1429 cai->cai_linesize = (1024 * 1024 * 1024); 1430 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1431 cai->cai_associativity); 1432 if (cp != NULL) 1433 cai->cai_associativity = cp->cai_associativity; 1434 else 1435 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1436 } 1437 1438 static void 1439 via_cpu_cacheinfo(struct cpu_info *ci) 1440 { 1441 struct x86_cache_info *cai; 1442 int stepping; 1443 u_int descs[4]; 1444 u_int lfunc; 1445 1446 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1447 1448 /* 1449 * Determine the largest extended function value. 1450 */ 1451 x86_cpuid(0x80000000, descs); 1452 lfunc = descs[0]; 1453 1454 /* 1455 * Determine L1 cache/TLB info. 1456 */ 1457 if (lfunc < 0x80000005) { 1458 /* No L1 cache info available. */ 1459 return; 1460 } 1461 1462 x86_cpuid(0x80000005, descs); 1463 1464 cai = &ci->ci_cinfo[CAI_ITLB]; 1465 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1466 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1467 cai->cai_linesize = (4 * 1024); 1468 1469 cai = &ci->ci_cinfo[CAI_DTLB]; 1470 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1471 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1472 cai->cai_linesize = (4 * 1024); 1473 1474 cai = &ci->ci_cinfo[CAI_DCACHE]; 1475 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1476 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1477 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1478 if (ci->ci_model == 9 && stepping == 8) { 1479 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1480 cai->cai_associativity = 2; 1481 } 1482 1483 cai = &ci->ci_cinfo[CAI_ICACHE]; 1484 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1485 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1486 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1487 if (ci->ci_model == 9 && stepping == 8) { 1488 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1489 cai->cai_associativity = 2; 1490 } 1491 1492 /* 1493 * Determine L2 cache/TLB info. 1494 */ 1495 if (lfunc < 0x80000006) { 1496 /* No L2 cache info available. */ 1497 return; 1498 } 1499 1500 x86_cpuid(0x80000006, descs); 1501 1502 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1503 if (ci->ci_model >= 9) { 1504 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1505 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1506 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1507 } else { 1508 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1509 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1510 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1511 } 1512 } 1513 1514 static void 1515 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1516 { 1517 u_int descs[4]; 1518 1519 x86_cpuid(0x80860007, descs); 1520 *frequency = descs[0]; 1521 *voltage = descs[1]; 1522 *percentage = descs[2]; 1523 } 1524 1525 static void 1526 transmeta_cpu_info(struct cpu_info *ci) 1527 { 1528 u_int descs[4], nreg; 1529 u_int frequency, voltage, percentage; 1530 1531 x86_cpuid(0x80860000, descs); 1532 nreg = descs[0]; 1533 if (nreg >= 0x80860001) { 1534 x86_cpuid(0x80860001, descs); 1535 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1536 (descs[1] >> 24) & 0xff, 1537 (descs[1] >> 16) & 0xff, 1538 (descs[1] >> 8) & 0xff, 1539 descs[1] & 0xff); 1540 } 1541 if (nreg >= 0x80860002) { 1542 x86_cpuid(0x80860002, descs); 1543 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1544 (descs[1] >> 24) & 0xff, 1545 (descs[1] >> 16) & 0xff, 1546 (descs[1] >> 8) & 0xff, 1547 descs[1] & 0xff, 1548 descs[2]); 1549 } 1550 if (nreg >= 0x80860006) { 1551 union { 1552 char text[65]; 1553 u_int descs[4][4]; 1554 } info; 1555 int i; 1556 1557 for (i=0; i<4; i++) { 1558 x86_cpuid(0x80860003 + i, info.descs[i]); 1559 } 1560 info.text[64] = '\0'; 1561 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1562 } 1563 1564 if (nreg >= 0x80860007) { 1565 tmx86_get_longrun_status(&frequency, 1566 &voltage, &percentage); 1567 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1568 frequency, voltage, percentage); 1569 } 1570 } 1571 1572 static void 1573 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1574 { 1575 u_int descs[4]; 1576 int i; 1577 uint32_t brand[12]; 1578 1579 memset(ci, 0, sizeof(*ci)); 1580 ci->ci_dev = cpuname; 1581 1582 ci->ci_cpu_type = x86_identify(); 1583 if (ci->ci_cpu_type >= 0) { 1584 /* Old pre-cpuid instruction cpu */ 1585 ci->ci_cpuid_level = -1; 1586 return; 1587 } 1588 1589 /* 1590 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1591 * function. 1592 */ 1593 1594 /* 1595 * Fn0000_0000: 1596 * - Save cpuid max level. 1597 * - Save vendor string. 1598 */ 1599 x86_cpuid(0, descs); 1600 ci->ci_cpuid_level = descs[0]; 1601 /* Save vendor string */ 1602 ci->ci_vendor[0] = descs[1]; 1603 ci->ci_vendor[2] = descs[2]; 1604 ci->ci_vendor[1] = descs[3]; 1605 ci->ci_vendor[3] = 0; 1606 1607 /* 1608 * Fn8000_0000: 1609 * - Get cpuid extended function's max level. 1610 */ 1611 x86_cpuid(0x80000000, descs); 1612 if (descs[0] >= 0x80000000) 1613 ci->ci_cpuid_extlevel = descs[0]; 1614 else { 1615 /* Set lower value than 0x80000000 */ 1616 ci->ci_cpuid_extlevel = 0; 1617 } 1618 1619 /* 1620 * Fn8000_000[2-4]: 1621 * - Save brand string. 1622 */ 1623 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1624 x86_cpuid(0x80000002, brand); 1625 x86_cpuid(0x80000003, brand + 4); 1626 x86_cpuid(0x80000004, brand + 8); 1627 for (i = 0; i < 48; i++) 1628 if (((char *) brand)[i] != ' ') 1629 break; 1630 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1631 } 1632 1633 if (ci->ci_cpuid_level < 1) 1634 return; 1635 1636 /* 1637 * Fn0000_0001: 1638 * - Get CPU family, model and stepping (from eax). 1639 * - Initial local APIC ID and brand ID (from ebx) 1640 * - CPUID2 (from ecx) 1641 * - CPUID (from edx) 1642 */ 1643 x86_cpuid(1, descs); 1644 ci->ci_signature = descs[0]; 1645 1646 /* Extract full family/model values */ 1647 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1648 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1649 1650 /* Brand is low order 8 bits of ebx */ 1651 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1652 /* Initial local APIC ID */ 1653 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1654 1655 ci->ci_feat_val[1] = descs[2]; 1656 ci->ci_feat_val[0] = descs[3]; 1657 1658 if (ci->ci_cpuid_level < 3) 1659 return; 1660 1661 /* 1662 * If the processor serial number misfeature is present and supported, 1663 * extract it here. 1664 */ 1665 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1666 ci->ci_cpu_serial[0] = ci->ci_signature; 1667 x86_cpuid(3, descs); 1668 ci->ci_cpu_serial[2] = descs[2]; 1669 ci->ci_cpu_serial[1] = descs[3]; 1670 } 1671 1672 if (ci->ci_cpuid_level < 0x7) 1673 return; 1674 1675 x86_cpuid(7, descs); 1676 ci->ci_feat_val[5] = descs[1]; 1677 ci->ci_feat_val[6] = descs[2]; 1678 ci->ci_feat_val[7] = descs[3]; 1679 1680 if (ci->ci_cpuid_level < 0xd) 1681 return; 1682 1683 /* Get support XCR0 bits */ 1684 x86_cpuid2(0xd, 0, descs); 1685 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1686 ci->ci_cur_xsave = descs[1]; 1687 ci->ci_max_xsave = descs[2]; 1688 1689 /* Additional flags (eg xsaveopt support) */ 1690 x86_cpuid2(0xd, 1, descs); 1691 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1692 } 1693 1694 static void 1695 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1696 { 1697 uint32_t descs[4]; 1698 char hv_sig[13]; 1699 char *p; 1700 const char *hv_name; 1701 int i; 1702 1703 /* 1704 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1705 * http://lkml.org/lkml/2008/10/1/246 1706 * 1707 * KB1009458: Mechanisms to determine if software is running in 1708 * a VMware virtual machine 1709 * http://kb.vmware.com/kb/1009458 1710 */ 1711 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1712 x86_cpuid(0x40000000, descs); 1713 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1714 memcpy(p, &descs[i], sizeof(descs[i])); 1715 *p = '\0'; 1716 /* 1717 * HV vendor ID string 1718 * ------------+-------------- 1719 * HAXM "HAXMHAXMHAXM" 1720 * KVM "KVMKVMKVM" 1721 * Microsoft "Microsoft Hv" 1722 * QEMU(TCG) "TCGTCGTCGTCG" 1723 * VMware "VMwareVMware" 1724 * Xen "XenVMMXenVMM" 1725 * NetBSD "___ NVMM ___" 1726 */ 1727 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1728 hv_name = "HAXM"; 1729 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1730 hv_name = "KVM"; 1731 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1732 hv_name = "Hyper-V"; 1733 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1734 hv_name = "QEMU(TCG)"; 1735 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1736 hv_name = "VMware"; 1737 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1738 hv_name = "Xen"; 1739 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1740 hv_name = "NVMM"; 1741 else 1742 hv_name = "unknown"; 1743 1744 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1745 } 1746 } 1747 1748 static void 1749 cpu_probe_features(struct cpu_info *ci) 1750 { 1751 const struct cpu_cpuid_nameclass *cpup = NULL; 1752 unsigned int i; 1753 1754 if (ci->ci_cpuid_level < 1) 1755 return; 1756 1757 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1758 if (!strncmp((char *)ci->ci_vendor, 1759 i386_cpuid_cpus[i].cpu_id, 12)) { 1760 cpup = &i386_cpuid_cpus[i]; 1761 break; 1762 } 1763 } 1764 1765 if (cpup == NULL) 1766 return; 1767 1768 i = ci->ci_family - CPU_MINFAMILY; 1769 1770 if (i >= __arraycount(cpup->cpu_family)) 1771 i = __arraycount(cpup->cpu_family) - 1; 1772 1773 if (cpup->cpu_family[i].cpu_probe == NULL) 1774 return; 1775 1776 (*cpup->cpu_family[i].cpu_probe)(ci); 1777 } 1778 1779 static void 1780 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1781 { 1782 char buf[32 * 16]; 1783 char *bp; 1784 1785 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1786 1787 if (val == 0 || fmt == NULL) 1788 return; 1789 1790 snprintb_m(buf, sizeof(buf), fmt, val, 1791 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1792 bp = buf; 1793 while (*bp != '\0') { 1794 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1795 bp += strlen(bp) + 1; 1796 } 1797 } 1798 1799 static void 1800 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1801 const char *blockname) 1802 { 1803 uint32_t descs[4]; 1804 uint32_t leaf; 1805 1806 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1807 leafend); 1808 1809 if (verbose) { 1810 for (leaf = leafstart; leaf <= leafend; leaf++) { 1811 x86_cpuid(leaf, descs); 1812 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1813 leaf, descs[0], descs[1], descs[2], descs[3]); 1814 } 1815 } 1816 } 1817 1818 static void 1819 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1820 { 1821 u_int lp_max = 1; /* logical processors per package */ 1822 u_int smt_max; /* smt per core */ 1823 u_int core_max = 1; /* core per package */ 1824 u_int smt_bits, core_bits; 1825 uint32_t descs[4]; 1826 1827 /* 1828 * 253668.pdf 7.10.2 1829 */ 1830 1831 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1832 x86_cpuid(1, descs); 1833 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1834 } 1835 x86_cpuid2(4, 0, descs); 1836 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1837 1838 assert(lp_max >= core_max); 1839 smt_max = lp_max / core_max; 1840 smt_bits = ilog2(smt_max - 1) + 1; 1841 core_bits = ilog2(core_max - 1) + 1; 1842 1843 if (smt_bits + core_bits) 1844 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1845 1846 if (core_bits) 1847 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1848 __BITS(smt_bits, smt_bits + core_bits - 1)); 1849 1850 if (smt_bits) 1851 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1852 __BITS((int)0, (int)(smt_bits - 1))); 1853 } 1854 1855 static void 1856 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1857 { 1858 const char *cpuname = ci->ci_dev; 1859 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1860 uint32_t descs[4]; 1861 int i; 1862 1863 x86_cpuid(0x0b, descs); 1864 if (descs[1] == 0) { 1865 identifycpu_cpuids_intel_0x04(ci); 1866 return; 1867 } 1868 1869 for (i = 0; ; i++) { 1870 unsigned int shiftnum, lvltype; 1871 x86_cpuid2(0x0b, i, descs); 1872 1873 /* On invalid level, (EAX and) EBX return 0 */ 1874 if (descs[1] == 0) 1875 break; 1876 1877 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1878 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1879 switch (lvltype) { 1880 case CPUID_TOP_LVLTYPE_SMT: 1881 core_shift = shiftnum; 1882 break; 1883 case CPUID_TOP_LVLTYPE_CORE: 1884 pkg_shift = shiftnum; 1885 break; 1886 case CPUID_TOP_LVLTYPE_INVAL: 1887 aprint_verbose("%s: Invalid level type\n", cpuname); 1888 break; 1889 default: 1890 aprint_verbose("%s: Unknown level type(%d) \n", 1891 cpuname, lvltype); 1892 break; 1893 } 1894 } 1895 1896 assert(pkg_shift >= core_shift); 1897 smt_bits = core_shift; 1898 core_bits = pkg_shift - core_shift; 1899 1900 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1901 1902 if (core_bits) 1903 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1904 __BITS(core_shift, pkg_shift - 1)); 1905 1906 if (smt_bits) 1907 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1908 __BITS((int)0, core_shift - 1)); 1909 } 1910 1911 static void 1912 identifycpu_cpuids_intel(struct cpu_info *ci) 1913 { 1914 const char *cpuname = ci->ci_dev; 1915 1916 if (ci->ci_cpuid_level >= 0x0b) 1917 identifycpu_cpuids_intel_0x0b(ci); 1918 else if (ci->ci_cpuid_level >= 4) 1919 identifycpu_cpuids_intel_0x04(ci); 1920 1921 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1922 ci->ci_packageid); 1923 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1924 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1925 } 1926 1927 static void 1928 identifycpu_cpuids(struct cpu_info *ci) 1929 { 1930 const char *cpuname = ci->ci_dev; 1931 1932 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1933 ci->ci_packageid = ci->ci_initapicid; 1934 ci->ci_coreid = 0; 1935 ci->ci_smtid = 0; 1936 1937 if (cpu_vendor == CPUVENDOR_INTEL) 1938 identifycpu_cpuids_intel(ci); 1939 } 1940 1941 void 1942 identifycpu(int fd, const char *cpuname) 1943 { 1944 const char *name = "", *modifier, *vendorname, *brand = ""; 1945 int class = CPUCLASS_386; 1946 unsigned int i; 1947 int modif, family; 1948 const struct cpu_cpuid_nameclass *cpup = NULL; 1949 const struct cpu_cpuid_family *cpufam; 1950 struct cpu_info *ci, cistore; 1951 u_int descs[4]; 1952 size_t sz; 1953 struct cpu_ucode_version ucode; 1954 union { 1955 struct cpu_ucode_version_amd amd; 1956 struct cpu_ucode_version_intel1 intel1; 1957 } ucvers; 1958 1959 ci = &cistore; 1960 cpu_probe_base_features(ci, cpuname); 1961 dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic"); 1962 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1963 x86_cpuid(0x40000000, descs); 1964 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1965 } 1966 dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended"); 1967 1968 cpu_probe_hv_features(ci, cpuname); 1969 cpu_probe_features(ci); 1970 1971 if (ci->ci_cpu_type >= 0) { 1972 /* Old pre-cpuid instruction cpu */ 1973 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1974 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1975 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1976 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1977 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1978 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1979 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1980 modifier = ""; 1981 } else { 1982 /* CPU which support cpuid instruction */ 1983 modif = (ci->ci_signature >> 12) & 0x3; 1984 family = ci->ci_family; 1985 if (family < CPU_MINFAMILY) 1986 errx(1, "identifycpu: strange family value"); 1987 if (family > CPU_MAXFAMILY) 1988 family = CPU_MAXFAMILY; 1989 1990 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1991 if (!strncmp((char *)ci->ci_vendor, 1992 i386_cpuid_cpus[i].cpu_id, 12)) { 1993 cpup = &i386_cpuid_cpus[i]; 1994 break; 1995 } 1996 } 1997 1998 if (cpup == NULL) { 1999 cpu_vendor = CPUVENDOR_UNKNOWN; 2000 if (ci->ci_vendor[0] != '\0') 2001 vendorname = (char *)&ci->ci_vendor[0]; 2002 else 2003 vendorname = "Unknown"; 2004 class = family - 3; 2005 modifier = ""; 2006 name = ""; 2007 ci->ci_info = NULL; 2008 } else { 2009 cpu_vendor = cpup->cpu_vendor; 2010 vendorname = cpup->cpu_vendorname; 2011 modifier = modifiers[modif]; 2012 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2013 name = cpufam->cpu_models[ci->ci_model]; 2014 if (name == NULL || *name == '\0') 2015 name = cpufam->cpu_model_default; 2016 class = cpufam->cpu_class; 2017 ci->ci_info = cpufam->cpu_info; 2018 2019 if (cpu_vendor == CPUVENDOR_INTEL) { 2020 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2021 const char *tmp; 2022 tmp = intel_family6_name(ci); 2023 if (tmp != NULL) 2024 name = tmp; 2025 } 2026 if (ci->ci_family == 15 && 2027 ci->ci_brand_id < 2028 __arraycount(i386_intel_brand) && 2029 i386_intel_brand[ci->ci_brand_id]) 2030 name = 2031 i386_intel_brand[ci->ci_brand_id]; 2032 } 2033 2034 if (cpu_vendor == CPUVENDOR_AMD) { 2035 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2036 if (ci->ci_brand_id == 1) 2037 /* 2038 * It's Duron. We override the 2039 * name, since it might have 2040 * been misidentified as Athlon. 2041 */ 2042 name = 2043 amd_brand[ci->ci_brand_id]; 2044 else 2045 brand = amd_brand_name; 2046 } 2047 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2048 == 0xf) { 2049 /* Identify AMD64 CPU names. */ 2050 const char *tmp; 2051 tmp = amd_amd64_name(ci); 2052 if (tmp != NULL) 2053 name = tmp; 2054 } 2055 } 2056 2057 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2058 vendorname = "VIA"; 2059 } 2060 } 2061 2062 ci->ci_cpu_class = class; 2063 2064 sz = sizeof(ci->ci_tsc_freq); 2065 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2066 sz = sizeof(use_pae); 2067 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2068 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2069 2070 /* 2071 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2072 * we try to determine from the family/model values. 2073 */ 2074 if (*cpu_brand_string != '\0') 2075 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2076 2077 aprint_normal("%s: %s", cpuname, vendorname); 2078 if (*modifier) 2079 aprint_normal(" %s", modifier); 2080 if (*name) 2081 aprint_normal(" %s", name); 2082 if (*brand) 2083 aprint_normal(" %s", brand); 2084 aprint_normal(" (%s-class)", classnames[class]); 2085 2086 if (ci->ci_tsc_freq != 0) 2087 aprint_normal(", %ju.%02ju MHz", 2088 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2089 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2090 aprint_normal("\n"); 2091 2092 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2093 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2094 if (ci->ci_signature != 0) 2095 aprint_normal(" (id %#x)", ci->ci_signature); 2096 aprint_normal("\n"); 2097 2098 if (ci->ci_info) 2099 (*ci->ci_info)(ci); 2100 2101 /* 2102 * display CPU feature flags 2103 */ 2104 2105 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2106 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2107 2108 /* These next two are actually common definitions! */ 2109 print_bits(cpuname, "features2", 2110 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2111 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2112 print_bits(cpuname, "features3", 2113 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2114 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2115 2116 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2117 ci->ci_feat_val[4]); 2118 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2119 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2120 ci->ci_feat_val[5]); 2121 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2122 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2123 ci->ci_feat_val[6]); 2124 2125 if (cpu_vendor == CPUVENDOR_INTEL) 2126 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2127 ci->ci_feat_val[7]); 2128 2129 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2130 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2131 ci->ci_feat_val[9]); 2132 2133 if (ci->ci_max_xsave != 0) { 2134 aprint_normal("%s: xsave area size: current %d, maximum %d", 2135 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2136 aprint_normal(", xgetbv %sabled\n", 2137 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2138 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2139 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2140 x86_xgetbv()); 2141 } 2142 2143 x86_print_cache_and_tlb_info(ci); 2144 2145 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2146 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2147 cpuname, 2148 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2149 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2150 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2151 } 2152 2153 if (ci->ci_cpu_class == CPUCLASS_386) 2154 errx(1, "NetBSD requires an 80486 or later processor"); 2155 2156 if (ci->ci_cpu_type == CPU_486DLC) { 2157 #ifndef CYRIX_CACHE_WORKS 2158 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2159 #else 2160 #ifndef CYRIX_CACHE_REALLY_WORKS 2161 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2162 #else 2163 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2164 #endif 2165 #endif 2166 } 2167 2168 /* 2169 * Everything past this point requires a Pentium or later. 2170 */ 2171 if (ci->ci_cpuid_level < 0) 2172 return; 2173 2174 identifycpu_cpuids(ci); 2175 2176 if ((ci->ci_cpuid_level >= 5) 2177 && ((cpu_vendor == CPUVENDOR_INTEL) 2178 || (cpu_vendor == CPUVENDOR_AMD))) { 2179 uint16_t lmin, lmax; 2180 x86_cpuid(5, descs); 2181 2182 print_bits(cpuname, "MONITOR/MWAIT extensions", 2183 CPUID_MON_FLAGS, descs[2]); 2184 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2185 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2186 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2187 if (lmin != lmax) 2188 aprint_normal("-%hu", lmax); 2189 aprint_normal("\n"); 2190 2191 for (i = 0; i <= 7; i++) { 2192 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2193 2194 if (num != 0) 2195 aprint_normal("%s: C%u substates %u\n", 2196 cpuname, i, num); 2197 } 2198 } 2199 if ((ci->ci_cpuid_level >= 6) 2200 && ((cpu_vendor == CPUVENDOR_INTEL) 2201 || (cpu_vendor == CPUVENDOR_AMD))) { 2202 x86_cpuid(6, descs); 2203 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2204 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2205 } 2206 if ((ci->ci_cpuid_level >= 7) 2207 && ((cpu_vendor == CPUVENDOR_INTEL) 2208 || (cpu_vendor == CPUVENDOR_AMD))) { 2209 x86_cpuid(7, descs); 2210 aprint_verbose("%s: SEF highest subleaf %08x\n", 2211 cpuname, descs[0]); 2212 } 2213 2214 if (cpu_vendor == CPUVENDOR_AMD) { 2215 x86_cpuid(0x80000000, descs); 2216 if (descs[0] >= 0x80000007) 2217 powernow_probe(ci); 2218 2219 if ((descs[0] >= 0x8000000a) 2220 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2221 x86_cpuid(0x8000000a, descs); 2222 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2223 descs[0] & 0xf); 2224 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2225 descs[1]); 2226 print_bits(cpuname, "SVM features", 2227 CPUID_AMD_SVM_FLAGS, descs[3]); 2228 } 2229 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2230 int32_t bi_index; 2231 2232 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2233 x86_cpuid(bi_index, descs); 2234 switch (bi_index) { 2235 case 0x0a: 2236 print_bits(cpuname, "Perfmon-eax", 2237 CPUID_PERF_FLAGS0, descs[0]); 2238 print_bits(cpuname, "Perfmon-ebx", 2239 CPUID_PERF_FLAGS1, descs[1]); 2240 print_bits(cpuname, "Perfmon-edx", 2241 CPUID_PERF_FLAGS3, descs[3]); 2242 break; 2243 default: 2244 #if 0 2245 aprint_verbose("%s: basic %08x-eax %08x\n", 2246 cpuname, bi_index, descs[0]); 2247 aprint_verbose("%s: basic %08x-ebx %08x\n", 2248 cpuname, bi_index, descs[1]); 2249 aprint_verbose("%s: basic %08x-ecx %08x\n", 2250 cpuname, bi_index, descs[2]); 2251 aprint_verbose("%s: basic %08x-edx %08x\n", 2252 cpuname, bi_index, descs[3]); 2253 #endif 2254 break; 2255 } 2256 } 2257 } 2258 2259 #ifdef INTEL_ONDEMAND_CLOCKMOD 2260 clockmod_init(); 2261 #endif 2262 2263 if (cpu_vendor == CPUVENDOR_AMD) 2264 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2265 else if (cpu_vendor == CPUVENDOR_INTEL) 2266 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2267 else 2268 return; 2269 2270 ucode.data = &ucvers; 2271 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2272 #ifdef __i386__ 2273 struct cpu_ucode_version_64 ucode_64; 2274 if (errno != ENOTTY) 2275 return; 2276 /* Try the 64 bit ioctl */ 2277 memset(&ucode_64, 0, sizeof ucode_64); 2278 ucode_64.data = &ucvers; 2279 ucode_64.loader_version = ucode.loader_version; 2280 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2281 return; 2282 #else 2283 return; 2284 #endif 2285 } 2286 2287 if (cpu_vendor == CPUVENDOR_AMD) 2288 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2289 else if (cpu_vendor == CPUVENDOR_INTEL) 2290 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2291 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2292 } 2293 2294 static const struct x86_cache_info * 2295 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2296 { 2297 int i; 2298 2299 for (i = 0; cai[i].cai_desc != 0; i++) { 2300 if (cai[i].cai_desc == desc) 2301 return (&cai[i]); 2302 } 2303 2304 return (NULL); 2305 } 2306 2307 static const char * 2308 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2309 const char *sep) 2310 { 2311 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2312 char human_num[HUMAN_BUFSIZE]; 2313 2314 if (cai->cai_totalsize == 0) 2315 return sep; 2316 2317 if (sep == NULL) 2318 aprint_verbose_dev(ci->ci_dev, ""); 2319 else 2320 aprint_verbose("%s", sep); 2321 if (name != NULL) 2322 aprint_verbose("%s ", name); 2323 2324 if (cai->cai_string != NULL) { 2325 aprint_verbose("%s ", cai->cai_string); 2326 } else { 2327 (void)humanize_number(human_num, sizeof(human_num), 2328 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2329 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2330 } 2331 switch (cai->cai_associativity) { 2332 case 0: 2333 aprint_verbose("disabled"); 2334 break; 2335 case 1: 2336 aprint_verbose("direct-mapped"); 2337 break; 2338 case 0xff: 2339 aprint_verbose("fully associative"); 2340 break; 2341 default: 2342 aprint_verbose("%d-way", cai->cai_associativity); 2343 break; 2344 } 2345 return ", "; 2346 } 2347 2348 static const char * 2349 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2350 const char *sep) 2351 { 2352 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2353 char human_num[HUMAN_BUFSIZE]; 2354 2355 if (cai->cai_totalsize == 0) 2356 return sep; 2357 2358 if (sep == NULL) 2359 aprint_verbose_dev(ci->ci_dev, ""); 2360 else 2361 aprint_verbose("%s", sep); 2362 if (name != NULL) 2363 aprint_verbose("%s ", name); 2364 2365 if (cai->cai_string != NULL) { 2366 aprint_verbose("%s", cai->cai_string); 2367 } else { 2368 (void)humanize_number(human_num, sizeof(human_num), 2369 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2370 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2371 human_num); 2372 switch (cai->cai_associativity) { 2373 case 0: 2374 aprint_verbose("disabled"); 2375 break; 2376 case 1: 2377 aprint_verbose("direct-mapped"); 2378 break; 2379 case 0xff: 2380 aprint_verbose("fully associative"); 2381 break; 2382 default: 2383 aprint_verbose("%d-way", cai->cai_associativity); 2384 break; 2385 } 2386 } 2387 return ", "; 2388 } 2389 2390 static void 2391 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2392 { 2393 const char *sep = NULL; 2394 2395 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2396 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2397 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2398 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2399 if (sep != NULL) 2400 aprint_verbose("\n"); 2401 } 2402 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2403 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2404 if (sep != NULL) 2405 aprint_verbose("\n"); 2406 } 2407 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2408 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2409 if (sep != NULL) 2410 aprint_verbose("\n"); 2411 } 2412 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2413 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2414 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2415 if (sep != NULL) 2416 aprint_verbose("\n"); 2417 } 2418 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2419 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2420 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2421 if (sep != NULL) 2422 aprint_verbose("\n"); 2423 } 2424 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2425 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2426 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2427 if (sep != NULL) 2428 aprint_verbose("\n"); 2429 } 2430 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2431 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2432 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2433 if (sep != NULL) 2434 aprint_verbose("\n"); 2435 } 2436 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2437 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2438 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2439 if (sep != NULL) 2440 aprint_verbose("\n"); 2441 } 2442 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2443 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2444 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2445 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2446 if (sep != NULL) 2447 aprint_verbose("\n"); 2448 } 2449 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2450 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2451 NULL); 2452 if (sep != NULL) 2453 aprint_verbose("\n"); 2454 } 2455 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2456 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2457 NULL); 2458 if (sep != NULL) 2459 aprint_verbose("\n"); 2460 } 2461 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2462 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2463 NULL); 2464 if (sep != NULL) 2465 aprint_verbose("\n"); 2466 } 2467 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2468 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2469 NULL); 2470 if (sep != NULL) 2471 aprint_verbose("\n"); 2472 } 2473 } 2474 2475 static void 2476 powernow_probe(struct cpu_info *ci) 2477 { 2478 uint32_t regs[4]; 2479 char buf[256]; 2480 2481 x86_cpuid(0x80000007, regs); 2482 2483 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2484 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2485 buf); 2486 } 2487 2488 bool 2489 identifycpu_bind(void) 2490 { 2491 2492 return true; 2493 } 2494 2495 int 2496 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2497 { 2498 struct cpu_info ci; 2499 int loader_version, res; 2500 struct cpu_ucode_version versreq; 2501 2502 cpu_probe_base_features(&ci, "unknown"); 2503 2504 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2505 loader_version = CPU_UCODE_LOADER_AMD; 2506 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2507 loader_version = CPU_UCODE_LOADER_INTEL1; 2508 else 2509 return -1; 2510 2511 /* check whether the kernel understands this loader version */ 2512 versreq.loader_version = loader_version; 2513 versreq.data = 0; 2514 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2515 if (res) 2516 return -1; 2517 2518 switch (loader_version) { 2519 case CPU_UCODE_LOADER_AMD: 2520 if (uc->cpu_nr != -1) { 2521 /* printf? */ 2522 return -1; 2523 } 2524 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2525 break; 2526 case CPU_UCODE_LOADER_INTEL1: 2527 if (uc->cpu_nr == -1) 2528 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2529 else 2530 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2531 break; 2532 default: /* can't happen */ 2533 return -1; 2534 } 2535 uc->loader_version = loader_version; 2536 return 0; 2537 } 2538
Indexes created Sat Oct 25 16:10:12 GMT 2025