i386.c revision 1.97
1 /* $NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpufunc.h> 85 #include <x86/cacheinfo.h> 86 #include <x86/cpu_ucode.h> 87 88 #include "../cpuctl.h" 89 #include "cpuctl_i386.h" 90 91 /* Size of buffer for printing humanized numbers */ 92 #define HUMAN_BUFSIZE sizeof("999KB") 93 94 struct cpu_info { 95 const char *ci_dev; 96 int32_t ci_cpu_type; /* for cpu's without cpuid */ 97 int32_t ci_cpuid_level; /* highest cpuid supported */ 98 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 99 uint32_t ci_signature; /* X86 cpuid type */ 100 uint32_t ci_family; /* from ci_signature */ 101 uint32_t ci_model; /* from ci_signature */ 102 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 103 * [0] basic features %edx 104 * [1] basic features %ecx 105 * [2] extended features %edx 106 * [3] extended features %ecx 107 * [4] VIA padlock features 108 * [5] structure ext. feat. %ebx 109 * [6] structure ext. feat. %ecx 110 * [7] structure ext. feat. %edx 111 * [8] XCR0 bits (d:0 %eax) 112 * [9] xsave flags (d:1 %eax) 113 */ 114 uint32_t ci_cpu_class; /* CPU class */ 115 uint32_t ci_brand_id; /* Intel brand id */ 116 uint32_t ci_vendor[4]; /* vendor string */ 117 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 118 uint64_t ci_tsc_freq; /* cpu cycles/second */ 119 uint8_t ci_packageid; 120 uint8_t ci_coreid; 121 uint8_t ci_smtid; 122 uint32_t ci_initapicid; 123 uint32_t ci_max_ext_cpuid; 124 125 uint32_t ci_cur_xsave; 126 uint32_t ci_max_xsave; 127 128 struct x86_cache_info ci_cinfo[CAI_COUNT]; 129 void (*ci_info)(struct cpu_info *); 130 }; 131 132 struct cpu_nocpuid_nameclass { 133 int cpu_vendor; 134 const char *cpu_vendorname; 135 const char *cpu_name; 136 int cpu_class; 137 void (*cpu_setup)(struct cpu_info *); 138 void (*cpu_cacheinfo)(struct cpu_info *); 139 void (*cpu_info)(struct cpu_info *); 140 }; 141 142 struct cpu_cpuid_nameclass { 143 const char *cpu_id; 144 int cpu_vendor; 145 const char *cpu_vendorname; 146 struct cpu_cpuid_family { 147 int cpu_class; 148 const char *cpu_models[256]; 149 const char *cpu_model_default; 150 void (*cpu_setup)(struct cpu_info *); 151 void (*cpu_probe)(struct cpu_info *); 152 void (*cpu_info)(struct cpu_info *); 153 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 154 }; 155 156 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 157 158 /* 159 * Map Brand ID from cpuid instruction to brand name. 160 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 161 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 162 * Architectures Software Developer's Manual, Volume 2A". 163 */ 164 static const char * const i386_intel_brand[] = { 165 "", /* Unsupported */ 166 "Celeron", /* Intel (R) Celeron (TM) processor */ 167 "Pentium III", /* Intel (R) Pentium (R) III processor */ 168 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 169 "Pentium III", /* Intel (R) Pentium (R) III processor */ 170 "", /* 0x05: Reserved */ 171 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 172 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 173 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 174 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 175 "Celeron", /* Intel (R) Celeron (TM) processor */ 176 "Xeon", /* Intel (R) Xeon (TM) processor */ 177 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 178 "", /* 0x0d: Reserved */ 179 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 180 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 181 "", /* 0x10: Reserved */ 182 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 183 "Celeron M", /* Intel (R) Celeron (R) M processor */ 184 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 185 "Celeron", /* Intel (R) Celeron (R) processor */ 186 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 187 "Pentium M", /* Intel (R) Pentium (R) M processor */ 188 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 189 }; 190 191 /* 192 * AMD processors don't have Brand IDs, so we need these names for probe. 193 */ 194 static const char * const amd_brand[] = { 195 "", 196 "Duron", /* AMD Duron(tm) */ 197 "MP", /* AMD Athlon(tm) MP */ 198 "XP", /* AMD Athlon(tm) XP */ 199 "4" /* AMD Athlon(tm) 4 */ 200 }; 201 202 static int cpu_vendor; 203 static char cpu_brand_string[49]; 204 static char amd_brand_name[48]; 205 static int use_pae, largepagesize; 206 207 /* Setup functions */ 208 static void disable_tsc(struct cpu_info *); 209 static void amd_family5_setup(struct cpu_info *); 210 static void cyrix6x86_cpu_setup(struct cpu_info *); 211 static void winchip_cpu_setup(struct cpu_info *); 212 /* Brand/Model name functions */ 213 static const char *intel_family6_name(struct cpu_info *); 214 static const char *amd_amd64_name(struct cpu_info *); 215 /* Probe functions */ 216 static void amd_family6_probe(struct cpu_info *); 217 static void powernow_probe(struct cpu_info *); 218 static void intel_family_new_probe(struct cpu_info *); 219 static void via_cpu_probe(struct cpu_info *); 220 /* (Cache) Info functions */ 221 static void intel_cpu_cacheinfo(struct cpu_info *); 222 static void amd_cpu_cacheinfo(struct cpu_info *); 223 static void via_cpu_cacheinfo(struct cpu_info *); 224 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 225 static void transmeta_cpu_info(struct cpu_info *); 226 /* Common functions */ 227 static void cpu_probe_base_features(struct cpu_info *, const char *); 228 static void cpu_probe_hv_features(struct cpu_info *, const char *); 229 static void cpu_probe_features(struct cpu_info *); 230 static void print_bits(const char *, const char *, const char *, uint32_t); 231 static void identifycpu_cpuids(struct cpu_info *); 232 static const struct x86_cache_info *cache_info_lookup( 233 const struct x86_cache_info *, uint8_t); 234 static const char *print_cache_config(struct cpu_info *, int, const char *, 235 const char *); 236 static const char *print_tlb_config(struct cpu_info *, int, const char *, 237 const char *); 238 static void x86_print_cache_and_tlb_info(struct cpu_info *); 239 240 /* 241 * Note: these are just the ones that may not have a cpuid instruction. 242 * We deal with the rest in a different way. 243 */ 244 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 245 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 246 NULL, NULL, NULL }, /* CPU_386SX */ 247 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 248 NULL, NULL, NULL }, /* CPU_386 */ 249 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_486SX */ 251 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 252 NULL, NULL, NULL }, /* CPU_486 */ 253 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 254 NULL, NULL, NULL }, /* CPU_486DLC */ 255 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 256 NULL, NULL, NULL }, /* CPU_6x86 */ 257 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 258 NULL, NULL, NULL }, /* CPU_NX586 */ 259 }; 260 261 const char *classnames[] = { 262 "386", 263 "486", 264 "586", 265 "686" 266 }; 267 268 const char *modifiers[] = { 269 "", 270 "OverDrive", 271 "Dual", 272 "" 273 }; 274 275 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 276 { 277 /* 278 * For Intel processors, check Chapter 35Model-specific 279 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 280 * Software Developer's Manual, Volume 3C". 281 */ 282 "GenuineIntel", 283 CPUVENDOR_INTEL, 284 "Intel", 285 /* Family 4 */ 286 { { 287 CPUCLASS_486, 288 { 289 "486DX", "486DX", "486SX", "486DX2", "486SL", 290 "486SX2", 0, "486DX2 W/B Enhanced", 291 "486DX4", 0, 0, 0, 0, 0, 0, 0, 292 }, 293 "486", /* Default */ 294 NULL, 295 NULL, 296 intel_cpu_cacheinfo, 297 }, 298 /* Family 5 */ 299 { 300 CPUCLASS_586, 301 { 302 "Pentium (P5 A-step)", "Pentium (P5)", 303 "Pentium (P54C)", "Pentium (P24T)", 304 "Pentium/MMX", "Pentium", 0, 305 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 306 "Quark X1000", 0, 0, 0, 0, 0, 0, 307 }, 308 "Pentium", /* Default */ 309 NULL, 310 NULL, 311 intel_cpu_cacheinfo, 312 }, 313 /* Family 6 */ 314 { 315 CPUCLASS_686, 316 { 317 [0x00] = "Pentium Pro (A-step)", 318 [0x01] = "Pentium Pro", 319 [0x03] = "Pentium II (Klamath)", 320 [0x04] = "Pentium Pro", 321 [0x05] = "Pentium II/Celeron (Deschutes)", 322 [0x06] = "Celeron (Mendocino)", 323 [0x07] = "Pentium III (Katmai)", 324 [0x08] = "Pentium III (Coppermine)", 325 [0x09] = "Pentium M (Banias)", 326 [0x0a] = "Pentium III Xeon (Cascades)", 327 [0x0b] = "Pentium III (Tualatin)", 328 [0x0d] = "Pentium M (Dothan)", 329 [0x0e] = "Pentium Core Duo, Core solo", 330 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 331 "Core 2 Quad 6xxx, " 332 "Core 2 Extreme 6xxx, " 333 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 334 "and Pentium DC", 335 [0x15] = "EP80579 Integrated Processor", 336 [0x16] = "Celeron (45nm)", 337 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 338 "Core 2 Quad 8xxx and 9xxx", 339 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 340 "(Nehalem)", 341 [0x1c] = "45nm Atom Family", 342 [0x1d] = "XeonMP 74xx (Nehalem)", 343 [0x1e] = "Core i7 and i5", 344 [0x1f] = "Core i7 and i5", 345 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 346 [0x26] = "Atom Family", 347 [0x27] = "Atom Family", 348 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 349 "i3 2xxx", 350 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 351 [0x2d] = "Xeon E5 Sandy Bridge family, " 352 "Core i7-39xx Extreme", 353 [0x2e] = "Xeon 75xx & 65xx", 354 [0x2f] = "Xeon E7 family", 355 [0x35] = "Atom Family", 356 [0x36] = "Atom S1000", 357 [0x37] = "Atom E3000, Z3[67]00", 358 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 359 "Ivy Bridge", 360 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 361 "(Haswell)", 362 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 363 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 364 "Core i7-49xx Extreme", 365 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 366 "Core i7-59xx Extreme", 367 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 368 "(Haswell)", 369 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 370 "(Haswell)", 371 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 372 [0x4a] = "Atom Z3400", 373 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 374 [0x4d] = "Atom C2000", 375 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 376 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 377 [0x55] = "Xeon Scalable (Skylake)", 378 [0x56] = "Xeon D-1500 (Broadwell)", 379 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 380 [0x5a] = "Atom E3500", 381 [0x5c] = "Atom (Goldmont)", 382 [0x5d] = "Atom X3-C3000 (Silvermont)", 383 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 384 [0x5f] = "Atom (Goldmont, Denverton)", 385 [0x66] = "Future Core (Cannon Lake)", 386 [0x7a] = "Atom (Goldmont Plus)", 387 [0x7e] = "Future Core (Ice Lake)", 388 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 389 [0x86] = "Atom (Tremont)", 390 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 391 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)", 392 }, 393 "Pentium Pro, II or III", /* Default */ 394 NULL, 395 intel_family_new_probe, 396 intel_cpu_cacheinfo, 397 }, 398 /* Family > 6 */ 399 { 400 CPUCLASS_686, 401 { 402 0, 0, 0, 0, 0, 0, 0, 0, 403 0, 0, 0, 0, 0, 0, 0, 0, 404 }, 405 "Pentium 4", /* Default */ 406 NULL, 407 intel_family_new_probe, 408 intel_cpu_cacheinfo, 409 } } 410 }, 411 { 412 "AuthenticAMD", 413 CPUVENDOR_AMD, 414 "AMD", 415 /* Family 4 */ 416 { { 417 CPUCLASS_486, 418 { 419 0, 0, 0, "Am486DX2 W/T", 420 0, 0, 0, "Am486DX2 W/B", 421 "Am486DX4 W/T or Am5x86 W/T 150", 422 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 423 0, 0, "Am5x86 W/T 133/160", 424 "Am5x86 W/B 133/160", 425 }, 426 "Am486 or Am5x86", /* Default */ 427 NULL, 428 NULL, 429 NULL, 430 }, 431 /* Family 5 */ 432 { 433 CPUCLASS_586, 434 { 435 "K5", "K5", "K5", "K5", 0, 0, "K6", 436 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 437 "K6-2+/III+", 0, 0, 438 }, 439 "K5 or K6", /* Default */ 440 amd_family5_setup, 441 NULL, 442 amd_cpu_cacheinfo, 443 }, 444 /* Family 6 */ 445 { 446 CPUCLASS_686, 447 { 448 0, "Athlon Model 1", "Athlon Model 2", 449 "Duron", "Athlon Model 4 (Thunderbird)", 450 0, "Athlon", "Duron", "Athlon", 0, 451 "Athlon", 0, 0, 0, 0, 0, 452 }, 453 "K7 (Athlon)", /* Default */ 454 NULL, 455 amd_family6_probe, 456 amd_cpu_cacheinfo, 457 }, 458 /* Family > 6 */ 459 { 460 CPUCLASS_686, 461 { 462 0, 0, 0, 0, 0, 0, 0, 0, 463 0, 0, 0, 0, 0, 0, 0, 0, 464 }, 465 "Unknown K8 (Athlon)", /* Default */ 466 NULL, 467 amd_family6_probe, 468 amd_cpu_cacheinfo, 469 } } 470 }, 471 { 472 "CyrixInstead", 473 CPUVENDOR_CYRIX, 474 "Cyrix", 475 /* Family 4 */ 476 { { 477 CPUCLASS_486, 478 { 479 0, 0, 0, 480 "MediaGX", 481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 482 }, 483 "486", /* Default */ 484 cyrix6x86_cpu_setup, /* XXX ?? */ 485 NULL, 486 NULL, 487 }, 488 /* Family 5 */ 489 { 490 CPUCLASS_586, 491 { 492 0, 0, "6x86", 0, 493 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 495 }, 496 "6x86", /* Default */ 497 cyrix6x86_cpu_setup, 498 NULL, 499 NULL, 500 }, 501 /* Family 6 */ 502 { 503 CPUCLASS_686, 504 { 505 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 506 0, 0, 0, 0, 0, 0, 0, 0, 507 }, 508 "6x86MX", /* Default */ 509 cyrix6x86_cpu_setup, 510 NULL, 511 NULL, 512 }, 513 /* Family > 6 */ 514 { 515 CPUCLASS_686, 516 { 517 0, 0, 0, 0, 0, 0, 0, 0, 518 0, 0, 0, 0, 0, 0, 0, 0, 519 }, 520 "Unknown 6x86MX", /* Default */ 521 NULL, 522 NULL, 523 NULL, 524 } } 525 }, 526 { /* MediaGX is now owned by National Semiconductor */ 527 "Geode by NSC", 528 CPUVENDOR_CYRIX, /* XXX */ 529 "National Semiconductor", 530 /* Family 4, NSC never had any of these */ 531 { { 532 CPUCLASS_486, 533 { 534 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0, 536 }, 537 "486 compatible", /* Default */ 538 NULL, 539 NULL, 540 NULL, 541 }, 542 /* Family 5: Geode family, formerly MediaGX */ 543 { 544 CPUCLASS_586, 545 { 546 0, 0, 0, 0, 547 "Geode GX1", 548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 549 }, 550 "Geode", /* Default */ 551 cyrix6x86_cpu_setup, 552 NULL, 553 amd_cpu_cacheinfo, 554 }, 555 /* Family 6, not yet available from NSC */ 556 { 557 CPUCLASS_686, 558 { 559 0, 0, 0, 0, 0, 0, 0, 0, 560 0, 0, 0, 0, 0, 0, 0, 0, 561 }, 562 "Pentium Pro compatible", /* Default */ 563 NULL, 564 NULL, 565 NULL, 566 }, 567 /* Family > 6, not yet available from NSC */ 568 { 569 CPUCLASS_686, 570 { 571 0, 0, 0, 0, 0, 0, 0, 0, 572 0, 0, 0, 0, 0, 0, 0, 0, 573 }, 574 "Pentium Pro compatible", /* Default */ 575 NULL, 576 NULL, 577 NULL, 578 } } 579 }, 580 { 581 "CentaurHauls", 582 CPUVENDOR_IDT, 583 "IDT", 584 /* Family 4, IDT never had any of these */ 585 { { 586 CPUCLASS_486, 587 { 588 0, 0, 0, 0, 0, 0, 0, 0, 589 0, 0, 0, 0, 0, 0, 0, 0, 590 }, 591 "486 compatible", /* Default */ 592 NULL, 593 NULL, 594 NULL, 595 }, 596 /* Family 5 */ 597 { 598 CPUCLASS_586, 599 { 600 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 601 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 602 }, 603 "WinChip", /* Default */ 604 winchip_cpu_setup, 605 NULL, 606 NULL, 607 }, 608 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 609 { 610 CPUCLASS_686, 611 { 612 0, 0, 0, 0, 0, 0, "C3 Samuel", 613 "C3 Samuel 2/Ezra", "C3 Ezra-T", 614 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 615 0, "VIA Nano", 616 }, 617 "Unknown VIA/IDT", /* Default */ 618 NULL, 619 via_cpu_probe, 620 via_cpu_cacheinfo, 621 }, 622 /* Family > 6, not yet available from VIA */ 623 { 624 CPUCLASS_686, 625 { 626 0, 0, 0, 0, 0, 0, 0, 0, 627 0, 0, 0, 0, 0, 0, 0, 0, 628 }, 629 "Pentium Pro compatible", /* Default */ 630 NULL, 631 NULL, 632 NULL, 633 } } 634 }, 635 { 636 "GenuineTMx86", 637 CPUVENDOR_TRANSMETA, 638 "Transmeta", 639 /* Family 4, Transmeta never had any of these */ 640 { { 641 CPUCLASS_486, 642 { 643 0, 0, 0, 0, 0, 0, 0, 0, 644 0, 0, 0, 0, 0, 0, 0, 0, 645 }, 646 "486 compatible", /* Default */ 647 NULL, 648 NULL, 649 NULL, 650 }, 651 /* Family 5 */ 652 { 653 CPUCLASS_586, 654 { 655 0, 0, 0, 0, 0, 0, 0, 0, 656 0, 0, 0, 0, 0, 0, 0, 0, 657 }, 658 "Crusoe", /* Default */ 659 NULL, 660 NULL, 661 transmeta_cpu_info, 662 }, 663 /* Family 6, not yet available from Transmeta */ 664 { 665 CPUCLASS_686, 666 { 667 0, 0, 0, 0, 0, 0, 0, 0, 668 0, 0, 0, 0, 0, 0, 0, 0, 669 }, 670 "Pentium Pro compatible", /* Default */ 671 NULL, 672 NULL, 673 NULL, 674 }, 675 /* Family > 6, not yet available from Transmeta */ 676 { 677 CPUCLASS_686, 678 { 679 0, 0, 0, 0, 0, 0, 0, 0, 680 0, 0, 0, 0, 0, 0, 0, 0, 681 }, 682 "Pentium Pro compatible", /* Default */ 683 NULL, 684 NULL, 685 NULL, 686 } } 687 } 688 }; 689 690 /* 691 * disable the TSC such that we don't use the TSC in microtime(9) 692 * because some CPUs got the implementation wrong. 693 */ 694 static void 695 disable_tsc(struct cpu_info *ci) 696 { 697 if (ci->ci_feat_val[0] & CPUID_TSC) { 698 ci->ci_feat_val[0] &= ~CPUID_TSC; 699 aprint_error("WARNING: broken TSC disabled\n"); 700 } 701 } 702 703 static void 704 amd_family5_setup(struct cpu_info *ci) 705 { 706 707 switch (ci->ci_model) { 708 case 0: /* AMD-K5 Model 0 */ 709 /* 710 * According to the AMD Processor Recognition App Note, 711 * the AMD-K5 Model 0 uses the wrong bit to indicate 712 * support for global PTEs, instead using bit 9 (APIC) 713 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 714 */ 715 if (ci->ci_feat_val[0] & CPUID_APIC) 716 ci->ci_feat_val[0] = 717 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 718 /* 719 * XXX But pmap_pg_g is already initialized -- need to kick 720 * XXX the pmap somehow. How does the MP branch do this? 721 */ 722 break; 723 } 724 } 725 726 static void 727 cyrix6x86_cpu_setup(struct cpu_info *ci) 728 { 729 730 /* 731 * Do not disable the TSC on the Geode GX, it's reported to 732 * work fine. 733 */ 734 if (ci->ci_signature != 0x552) 735 disable_tsc(ci); 736 } 737 738 static void 739 winchip_cpu_setup(struct cpu_info *ci) 740 { 741 switch (ci->ci_model) { 742 case 4: /* WinChip C6 */ 743 disable_tsc(ci); 744 } 745 } 746 747 748 static const char * 749 intel_family6_name(struct cpu_info *ci) 750 { 751 const char *ret = NULL; 752 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 753 754 if (ci->ci_model == 5) { 755 switch (l2cache) { 756 case 0: 757 case 128 * 1024: 758 ret = "Celeron (Covington)"; 759 break; 760 case 256 * 1024: 761 ret = "Mobile Pentium II (Dixon)"; 762 break; 763 case 512 * 1024: 764 ret = "Pentium II"; 765 break; 766 case 1 * 1024 * 1024: 767 case 2 * 1024 * 1024: 768 ret = "Pentium II Xeon"; 769 break; 770 } 771 } else if (ci->ci_model == 6) { 772 switch (l2cache) { 773 case 256 * 1024: 774 case 512 * 1024: 775 ret = "Mobile Pentium II"; 776 break; 777 } 778 } else if (ci->ci_model == 7) { 779 switch (l2cache) { 780 case 512 * 1024: 781 ret = "Pentium III"; 782 break; 783 case 1 * 1024 * 1024: 784 case 2 * 1024 * 1024: 785 ret = "Pentium III Xeon"; 786 break; 787 } 788 } else if (ci->ci_model >= 8) { 789 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 790 switch (ci->ci_brand_id) { 791 case 0x3: 792 if (ci->ci_signature == 0x6B1) 793 ret = "Celeron"; 794 break; 795 case 0x8: 796 if (ci->ci_signature >= 0xF13) 797 ret = "genuine processor"; 798 break; 799 case 0xB: 800 if (ci->ci_signature >= 0xF13) 801 ret = "Xeon MP"; 802 break; 803 case 0xE: 804 if (ci->ci_signature < 0xF13) 805 ret = "Xeon"; 806 break; 807 } 808 if (ret == NULL) 809 ret = i386_intel_brand[ci->ci_brand_id]; 810 } 811 } 812 813 return ret; 814 } 815 816 /* 817 * Identify AMD64 CPU names from cpuid. 818 * 819 * Based on: 820 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 821 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 822 * "Revision Guide for AMD NPT Family 0Fh Processors" 823 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 824 * and other miscellaneous reports. 825 * 826 * This is all rather pointless, these are cross 'brand' since the raw 827 * silicon is shared. 828 */ 829 static const char * 830 amd_amd64_name(struct cpu_info *ci) 831 { 832 static char family_str[32]; 833 834 /* Only called if family >= 15 */ 835 836 switch (ci->ci_family) { 837 case 15: 838 switch (ci->ci_model) { 839 case 0x21: /* rev JH-E1/E6 */ 840 case 0x41: /* rev JH-F2 */ 841 return "Dual-Core Opteron"; 842 case 0x23: /* rev JH-E6 (Toledo) */ 843 return "Dual-Core Opteron or Athlon 64 X2"; 844 case 0x43: /* rev JH-F2 (Windsor) */ 845 return "Athlon 64 FX or Athlon 64 X2"; 846 case 0x24: /* rev SH-E5 (Lancaster?) */ 847 return "Mobile Athlon 64 or Turion 64"; 848 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 849 return "Opteron or Athlon 64 FX"; 850 case 0x15: /* rev SH-D0 */ 851 case 0x25: /* rev SH-E4 */ 852 return "Opteron"; 853 case 0x27: /* rev DH-E4, SH-E4 */ 854 return "Athlon 64 or Athlon 64 FX or Opteron"; 855 case 0x48: /* rev BH-F2 */ 856 return "Turion 64 X2"; 857 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 858 case 0x07: /* rev SH-CG (ClawHammer) */ 859 case 0x0b: /* rev CH-CG */ 860 case 0x14: /* rev SH-D0 */ 861 case 0x17: /* rev SH-D0 */ 862 case 0x1b: /* rev CH-D0 */ 863 return "Athlon 64"; 864 case 0x2b: /* rev BH-E4 (Manchester) */ 865 case 0x4b: /* rev BH-F2 (Windsor) */ 866 return "Athlon 64 X2"; 867 case 0x6b: /* rev BH-G1 (Brisbane) */ 868 return "Athlon X2 or Athlon 64 X2"; 869 case 0x08: /* rev CH-CG */ 870 case 0x0c: /* rev DH-CG (Newcastle) */ 871 case 0x0e: /* rev DH-CG (Newcastle?) */ 872 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 873 case 0x18: /* rev CH-D0 */ 874 case 0x1c: /* rev DH-D0 (Winchester) */ 875 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 876 case 0x2c: /* rev DH-E3/E6 */ 877 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 878 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 879 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 880 case 0x6f: /* rev DH-G1 */ 881 return "Athlon 64 or Sempron"; 882 default: 883 break; 884 } 885 return "Unknown AMD64 CPU"; 886 887 #if 0 888 case 16: 889 return "Family 10h"; 890 case 17: 891 return "Family 11h"; 892 case 18: 893 return "Family 12h"; 894 case 19: 895 return "Family 14h"; 896 case 20: 897 return "Family 15h"; 898 #endif 899 900 default: 901 break; 902 } 903 904 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 905 return family_str; 906 } 907 908 static void 909 intel_family_new_probe(struct cpu_info *ci) 910 { 911 uint32_t descs[4]; 912 913 x86_cpuid(0x80000000, descs); 914 915 /* 916 * Determine extended feature flags. 917 */ 918 if (descs[0] >= 0x80000001) { 919 x86_cpuid(0x80000001, descs); 920 ci->ci_feat_val[2] |= descs[3]; 921 ci->ci_feat_val[3] |= descs[2]; 922 } 923 } 924 925 static void 926 via_cpu_probe(struct cpu_info *ci) 927 { 928 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 929 u_int descs[4]; 930 u_int lfunc; 931 932 /* 933 * Determine the largest extended function value. 934 */ 935 x86_cpuid(0x80000000, descs); 936 lfunc = descs[0]; 937 938 /* 939 * Determine the extended feature flags. 940 */ 941 if (lfunc >= 0x80000001) { 942 x86_cpuid(0x80000001, descs); 943 ci->ci_feat_val[2] |= descs[3]; 944 } 945 946 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 947 return; 948 949 /* Nehemiah or Esther */ 950 x86_cpuid(0xc0000000, descs); 951 lfunc = descs[0]; 952 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 953 return; 954 955 x86_cpuid(0xc0000001, descs); 956 lfunc = descs[3]; 957 ci->ci_feat_val[4] = lfunc; 958 } 959 960 static void 961 amd_family6_probe(struct cpu_info *ci) 962 { 963 uint32_t descs[4]; 964 char *p; 965 size_t i; 966 967 x86_cpuid(0x80000000, descs); 968 969 /* 970 * Determine the extended feature flags. 971 */ 972 if (descs[0] >= 0x80000001) { 973 x86_cpuid(0x80000001, descs); 974 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 975 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 976 } 977 978 if (*cpu_brand_string == '\0') 979 return; 980 981 for (i = 1; i < __arraycount(amd_brand); i++) 982 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 983 ci->ci_brand_id = i; 984 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 985 break; 986 } 987 } 988 989 static void 990 intel_cpu_cacheinfo(struct cpu_info *ci) 991 { 992 const struct x86_cache_info *cai; 993 u_int descs[4]; 994 int iterations, i, j; 995 int type, level; 996 int ways, partitions, linesize, sets; 997 int caitype = -1; 998 int totalsize; 999 uint8_t desc; 1000 1001 /* Return if the cpu is old pre-cpuid instruction cpu */ 1002 if (ci->ci_cpu_type >= 0) 1003 return; 1004 1005 if (ci->ci_cpuid_level < 2) 1006 return; 1007 1008 /* 1009 * Parse the cache info from `cpuid leaf 2', if we have it. 1010 * XXX This is kinda ugly, but hey, so is the architecture... 1011 */ 1012 x86_cpuid(2, descs); 1013 iterations = descs[0] & 0xff; 1014 while (iterations-- > 0) { 1015 for (i = 0; i < 4; i++) { 1016 if (descs[i] & 0x80000000) 1017 continue; 1018 for (j = 0; j < 4; j++) { 1019 /* 1020 * The least significant byte in EAX 1021 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1022 * it should be ignored. 1023 */ 1024 if (i == 0 && j == 0) 1025 continue; 1026 desc = (descs[i] >> (j * 8)) & 0xff; 1027 if (desc == 0) 1028 continue; 1029 cai = cache_info_lookup(intel_cpuid_cache_info, 1030 desc); 1031 if (cai != NULL) 1032 ci->ci_cinfo[cai->cai_index] = *cai; 1033 else if ((verbose != 0) && (desc != 0xff) 1034 && (desc != 0xfe)) 1035 aprint_error_dev(ci->ci_dev, "error:" 1036 " Unknown cacheinfo desc %02x\n", 1037 desc); 1038 } 1039 } 1040 x86_cpuid(2, descs); 1041 } 1042 1043 if (ci->ci_cpuid_level < 4) 1044 return; 1045 1046 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1047 for (i = 0; ; i++) { 1048 x86_cpuid2(4, i, descs); 1049 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1050 if (type == CPUID_DCP_CACHETYPE_N) 1051 break; 1052 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1053 switch (level) { 1054 case 1: 1055 if (type == CPUID_DCP_CACHETYPE_I) 1056 caitype = CAI_ICACHE; 1057 else if (type == CPUID_DCP_CACHETYPE_D) 1058 caitype = CAI_DCACHE; 1059 else 1060 caitype = -1; 1061 break; 1062 case 2: 1063 if (type == CPUID_DCP_CACHETYPE_U) 1064 caitype = CAI_L2CACHE; 1065 else 1066 caitype = -1; 1067 break; 1068 case 3: 1069 if (type == CPUID_DCP_CACHETYPE_U) 1070 caitype = CAI_L3CACHE; 1071 else 1072 caitype = -1; 1073 break; 1074 default: 1075 caitype = -1; 1076 break; 1077 } 1078 if (caitype == -1) { 1079 aprint_error_dev(ci->ci_dev, 1080 "error: unknown cache level&type (%d & %d)\n", 1081 level, type); 1082 continue; 1083 } 1084 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1085 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1086 + 1; 1087 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1088 + 1; 1089 sets = descs[2] + 1; 1090 totalsize = ways * partitions * linesize * sets; 1091 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1092 ci->ci_cinfo[caitype].cai_associativity = ways; 1093 ci->ci_cinfo[caitype].cai_linesize = linesize; 1094 } 1095 1096 if (ci->ci_cpuid_level < 0x18) 1097 return; 1098 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1099 x86_cpuid(0x18, descs); 1100 iterations = descs[0]; 1101 for (i = 0; i <= iterations; i++) { 1102 uint32_t pgsize; 1103 bool full; 1104 1105 x86_cpuid2(0x18, i, descs); 1106 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1107 if (type == CPUID_DATP_TCTYPE_N) 1108 continue; 1109 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1110 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1111 switch (level) { 1112 case 1: 1113 if (type == CPUID_DATP_TCTYPE_I) { 1114 switch (pgsize) { 1115 case CPUID_DATP_PGSIZE_4KB: 1116 caitype = CAI_ITLB; 1117 break; 1118 case CPUID_DATP_PGSIZE_2MB 1119 | CPUID_DATP_PGSIZE_4MB: 1120 caitype = CAI_ITLB2; 1121 break; 1122 case CPUID_DATP_PGSIZE_1GB: 1123 caitype = CAI_L1_1GBITLB; 1124 break; 1125 default: 1126 aprint_error_dev(ci->ci_dev, 1127 "error: unknown ITLB size (%d)\n", 1128 pgsize); 1129 caitype = CAI_ITLB; 1130 break; 1131 } 1132 } else if (type == CPUID_DATP_TCTYPE_D) { 1133 switch (pgsize) { 1134 case CPUID_DATP_PGSIZE_4KB: 1135 caitype = CAI_DTLB; 1136 break; 1137 case CPUID_DATP_PGSIZE_2MB 1138 | CPUID_DATP_PGSIZE_4MB: 1139 caitype = CAI_DTLB2; 1140 break; 1141 case CPUID_DATP_PGSIZE_1GB: 1142 caitype = CAI_L1_1GBDTLB; 1143 break; 1144 default: 1145 aprint_error_dev(ci->ci_dev, 1146 "error: unknown DTLB size (%d)\n", 1147 pgsize); 1148 caitype = CAI_DTLB; 1149 break; 1150 } 1151 } else 1152 caitype = -1; 1153 break; 1154 case 2: 1155 if (type == CPUID_DATP_TCTYPE_I) 1156 caitype = CAI_L2_ITLB; 1157 else if (type == CPUID_DATP_TCTYPE_D) 1158 caitype = CAI_L2_DTLB; 1159 else if (type == CPUID_DATP_TCTYPE_U) { 1160 switch (pgsize) { 1161 case CPUID_DATP_PGSIZE_4KB: 1162 caitype = CAI_L2_STLB; 1163 break; 1164 case CPUID_DATP_PGSIZE_4KB 1165 | CPUID_DATP_PGSIZE_2MB: 1166 caitype = CAI_L2_STLB2; 1167 break; 1168 case CPUID_DATP_PGSIZE_2MB 1169 | CPUID_DATP_PGSIZE_4MB: 1170 caitype = CAI_L2_STLB3; 1171 break; 1172 default: 1173 aprint_error_dev(ci->ci_dev, 1174 "error: unknown L2 STLB size (%d)\n", 1175 pgsize); 1176 caitype = CAI_DTLB; 1177 break; 1178 } 1179 } else 1180 caitype = -1; 1181 break; 1182 case 3: 1183 /* XXX need work for L3 TLB */ 1184 caitype = CAI_L3CACHE; 1185 break; 1186 default: 1187 caitype = -1; 1188 break; 1189 } 1190 if (caitype == -1) { 1191 aprint_error_dev(ci->ci_dev, 1192 "error: unknown TLB level&type (%d & %d)\n", 1193 level, type); 1194 continue; 1195 } 1196 switch (pgsize) { 1197 case CPUID_DATP_PGSIZE_4KB: 1198 linesize = 4 * 1024; 1199 break; 1200 case CPUID_DATP_PGSIZE_2MB: 1201 linesize = 2 * 1024 * 1024; 1202 break; 1203 case CPUID_DATP_PGSIZE_4MB: 1204 linesize = 4 * 1024 * 1024; 1205 break; 1206 case CPUID_DATP_PGSIZE_1GB: 1207 linesize = 1024 * 1024 * 1024; 1208 break; 1209 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1210 aprint_error_dev(ci->ci_dev, 1211 "WARINING: Currently 2M/4M info can't print correctly\n"); 1212 linesize = 4 * 1024 * 1024; 1213 break; 1214 default: 1215 aprint_error_dev(ci->ci_dev, 1216 "error: Unknown size combination\n"); 1217 linesize = 4 * 1024; 1218 break; 1219 } 1220 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1221 sets = descs[2]; 1222 full = descs[3] & CPUID_DATP_FULLASSOC; 1223 ci->ci_cinfo[caitype].cai_totalsize 1224 = ways * sets; /* entries */ 1225 ci->ci_cinfo[caitype].cai_associativity 1226 = full ? 0xff : ways; 1227 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1228 } 1229 } 1230 1231 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1232 AMD_L2CACHE_INFO; 1233 1234 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1235 AMD_L3CACHE_INFO; 1236 1237 static void 1238 amd_cpu_cacheinfo(struct cpu_info *ci) 1239 { 1240 const struct x86_cache_info *cp; 1241 struct x86_cache_info *cai; 1242 u_int descs[4]; 1243 u_int lfunc; 1244 1245 /* 1246 * K5 model 0 has none of this info. 1247 */ 1248 if (ci->ci_family == 5 && ci->ci_model == 0) 1249 return; 1250 1251 /* 1252 * Determine the largest extended function value. 1253 */ 1254 x86_cpuid(0x80000000, descs); 1255 lfunc = descs[0]; 1256 1257 /* 1258 * Determine L1 cache/TLB info. 1259 */ 1260 if (lfunc < 0x80000005) { 1261 /* No L1 cache info available. */ 1262 return; 1263 } 1264 1265 x86_cpuid(0x80000005, descs); 1266 1267 /* 1268 * K6-III and higher have large page TLBs. 1269 */ 1270 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1271 cai = &ci->ci_cinfo[CAI_ITLB2]; 1272 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1273 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1274 cai->cai_linesize = largepagesize; 1275 1276 cai = &ci->ci_cinfo[CAI_DTLB2]; 1277 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1278 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1279 cai->cai_linesize = largepagesize; 1280 } 1281 1282 cai = &ci->ci_cinfo[CAI_ITLB]; 1283 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1284 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1285 cai->cai_linesize = (4 * 1024); 1286 1287 cai = &ci->ci_cinfo[CAI_DTLB]; 1288 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1289 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1290 cai->cai_linesize = (4 * 1024); 1291 1292 cai = &ci->ci_cinfo[CAI_DCACHE]; 1293 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1294 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1295 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1296 1297 cai = &ci->ci_cinfo[CAI_ICACHE]; 1298 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1299 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1300 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1301 1302 /* 1303 * Determine L2 cache/TLB info. 1304 */ 1305 if (lfunc < 0x80000006) { 1306 /* No L2 cache info available. */ 1307 return; 1308 } 1309 1310 x86_cpuid(0x80000006, descs); 1311 1312 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1313 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1314 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1315 cai->cai_linesize = (4 * 1024); 1316 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1317 cai->cai_associativity); 1318 if (cp != NULL) 1319 cai->cai_associativity = cp->cai_associativity; 1320 else 1321 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1322 1323 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1324 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1325 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1326 cai->cai_linesize = largepagesize; 1327 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1328 cai->cai_associativity); 1329 if (cp != NULL) 1330 cai->cai_associativity = cp->cai_associativity; 1331 else 1332 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1333 1334 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1335 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1336 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1337 cai->cai_linesize = (4 * 1024); 1338 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1339 cai->cai_associativity); 1340 if (cp != NULL) 1341 cai->cai_associativity = cp->cai_associativity; 1342 else 1343 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1344 1345 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1346 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1347 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1348 cai->cai_linesize = largepagesize; 1349 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1350 cai->cai_associativity); 1351 if (cp != NULL) 1352 cai->cai_associativity = cp->cai_associativity; 1353 else 1354 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1355 1356 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1357 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1358 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1359 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1360 1361 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1362 cai->cai_associativity); 1363 if (cp != NULL) 1364 cai->cai_associativity = cp->cai_associativity; 1365 else 1366 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1367 1368 /* 1369 * Determine L3 cache info on AMD Family 10h and newer processors 1370 */ 1371 if (ci->ci_family >= 0x10) { 1372 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1373 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1374 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1375 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1376 1377 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1378 cai->cai_associativity); 1379 if (cp != NULL) 1380 cai->cai_associativity = cp->cai_associativity; 1381 else 1382 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1383 } 1384 1385 /* 1386 * Determine 1GB TLB info. 1387 */ 1388 if (lfunc < 0x80000019) { 1389 /* No 1GB TLB info available. */ 1390 return; 1391 } 1392 1393 x86_cpuid(0x80000019, descs); 1394 1395 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1396 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1397 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1398 cai->cai_linesize = (1024 * 1024 * 1024); 1399 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1400 cai->cai_associativity); 1401 if (cp != NULL) 1402 cai->cai_associativity = cp->cai_associativity; 1403 else 1404 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1405 1406 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1407 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1408 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1409 cai->cai_linesize = (1024 * 1024 * 1024); 1410 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1411 cai->cai_associativity); 1412 if (cp != NULL) 1413 cai->cai_associativity = cp->cai_associativity; 1414 else 1415 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1416 1417 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1418 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1419 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1420 cai->cai_linesize = (1024 * 1024 * 1024); 1421 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1422 cai->cai_associativity); 1423 if (cp != NULL) 1424 cai->cai_associativity = cp->cai_associativity; 1425 else 1426 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1427 1428 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1429 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1430 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1431 cai->cai_linesize = (1024 * 1024 * 1024); 1432 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1433 cai->cai_associativity); 1434 if (cp != NULL) 1435 cai->cai_associativity = cp->cai_associativity; 1436 else 1437 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1438 } 1439 1440 static void 1441 via_cpu_cacheinfo(struct cpu_info *ci) 1442 { 1443 struct x86_cache_info *cai; 1444 int stepping; 1445 u_int descs[4]; 1446 u_int lfunc; 1447 1448 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1449 1450 /* 1451 * Determine the largest extended function value. 1452 */ 1453 x86_cpuid(0x80000000, descs); 1454 lfunc = descs[0]; 1455 1456 /* 1457 * Determine L1 cache/TLB info. 1458 */ 1459 if (lfunc < 0x80000005) { 1460 /* No L1 cache info available. */ 1461 return; 1462 } 1463 1464 x86_cpuid(0x80000005, descs); 1465 1466 cai = &ci->ci_cinfo[CAI_ITLB]; 1467 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1468 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1469 cai->cai_linesize = (4 * 1024); 1470 1471 cai = &ci->ci_cinfo[CAI_DTLB]; 1472 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1473 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1474 cai->cai_linesize = (4 * 1024); 1475 1476 cai = &ci->ci_cinfo[CAI_DCACHE]; 1477 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1478 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1479 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1480 if (ci->ci_model == 9 && stepping == 8) { 1481 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1482 cai->cai_associativity = 2; 1483 } 1484 1485 cai = &ci->ci_cinfo[CAI_ICACHE]; 1486 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1487 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1488 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1489 if (ci->ci_model == 9 && stepping == 8) { 1490 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1491 cai->cai_associativity = 2; 1492 } 1493 1494 /* 1495 * Determine L2 cache/TLB info. 1496 */ 1497 if (lfunc < 0x80000006) { 1498 /* No L2 cache info available. */ 1499 return; 1500 } 1501 1502 x86_cpuid(0x80000006, descs); 1503 1504 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1505 if (ci->ci_model >= 9) { 1506 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1507 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1508 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1509 } else { 1510 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1511 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1512 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1513 } 1514 } 1515 1516 static void 1517 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1518 { 1519 u_int descs[4]; 1520 1521 x86_cpuid(0x80860007, descs); 1522 *frequency = descs[0]; 1523 *voltage = descs[1]; 1524 *percentage = descs[2]; 1525 } 1526 1527 static void 1528 transmeta_cpu_info(struct cpu_info *ci) 1529 { 1530 u_int descs[4], nreg; 1531 u_int frequency, voltage, percentage; 1532 1533 x86_cpuid(0x80860000, descs); 1534 nreg = descs[0]; 1535 if (nreg >= 0x80860001) { 1536 x86_cpuid(0x80860001, descs); 1537 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1538 (descs[1] >> 24) & 0xff, 1539 (descs[1] >> 16) & 0xff, 1540 (descs[1] >> 8) & 0xff, 1541 descs[1] & 0xff); 1542 } 1543 if (nreg >= 0x80860002) { 1544 x86_cpuid(0x80860002, descs); 1545 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1546 (descs[1] >> 24) & 0xff, 1547 (descs[1] >> 16) & 0xff, 1548 (descs[1] >> 8) & 0xff, 1549 descs[1] & 0xff, 1550 descs[2]); 1551 } 1552 if (nreg >= 0x80860006) { 1553 union { 1554 char text[65]; 1555 u_int descs[4][4]; 1556 } info; 1557 int i; 1558 1559 for (i=0; i<4; i++) { 1560 x86_cpuid(0x80860003 + i, info.descs[i]); 1561 } 1562 info.text[64] = '\0'; 1563 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1564 } 1565 1566 if (nreg >= 0x80860007) { 1567 tmx86_get_longrun_status(&frequency, 1568 &voltage, &percentage); 1569 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1570 frequency, voltage, percentage); 1571 } 1572 } 1573 1574 static void 1575 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1576 { 1577 u_int descs[4]; 1578 int i; 1579 uint32_t brand[12]; 1580 1581 memset(ci, 0, sizeof(*ci)); 1582 ci->ci_dev = cpuname; 1583 1584 ci->ci_cpu_type = x86_identify(); 1585 if (ci->ci_cpu_type >= 0) { 1586 /* Old pre-cpuid instruction cpu */ 1587 ci->ci_cpuid_level = -1; 1588 return; 1589 } 1590 1591 /* 1592 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1593 * function. 1594 */ 1595 1596 /* 1597 * Fn0000_0000: 1598 * - Save cpuid max level. 1599 * - Save vendor string. 1600 */ 1601 x86_cpuid(0, descs); 1602 ci->ci_cpuid_level = descs[0]; 1603 /* Save vendor string */ 1604 ci->ci_vendor[0] = descs[1]; 1605 ci->ci_vendor[2] = descs[2]; 1606 ci->ci_vendor[1] = descs[3]; 1607 ci->ci_vendor[3] = 0; 1608 1609 /* 1610 * Fn8000_0000: 1611 * - Get cpuid extended function's max level. 1612 */ 1613 x86_cpuid(0x80000000, descs); 1614 if (descs[0] >= 0x80000000) 1615 ci->ci_cpuid_extlevel = descs[0]; 1616 else { 1617 /* Set lower value than 0x80000000 */ 1618 ci->ci_cpuid_extlevel = 0; 1619 } 1620 1621 /* 1622 * Fn8000_000[2-4]: 1623 * - Save brand string. 1624 */ 1625 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1626 x86_cpuid(0x80000002, brand); 1627 x86_cpuid(0x80000003, brand + 4); 1628 x86_cpuid(0x80000004, brand + 8); 1629 for (i = 0; i < 48; i++) 1630 if (((char *) brand)[i] != ' ') 1631 break; 1632 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1633 } 1634 1635 if (ci->ci_cpuid_level < 1) 1636 return; 1637 1638 /* 1639 * Fn0000_0001: 1640 * - Get CPU family, model and stepping (from eax). 1641 * - Initial local APIC ID and brand ID (from ebx) 1642 * - CPUID2 (from ecx) 1643 * - CPUID (from edx) 1644 */ 1645 x86_cpuid(1, descs); 1646 ci->ci_signature = descs[0]; 1647 1648 /* Extract full family/model values */ 1649 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1650 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1651 1652 /* Brand is low order 8 bits of ebx */ 1653 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1654 /* Initial local APIC ID */ 1655 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1656 1657 ci->ci_feat_val[1] = descs[2]; 1658 ci->ci_feat_val[0] = descs[3]; 1659 1660 if (ci->ci_cpuid_level < 3) 1661 return; 1662 1663 /* 1664 * If the processor serial number misfeature is present and supported, 1665 * extract it here. 1666 */ 1667 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1668 ci->ci_cpu_serial[0] = ci->ci_signature; 1669 x86_cpuid(3, descs); 1670 ci->ci_cpu_serial[2] = descs[2]; 1671 ci->ci_cpu_serial[1] = descs[3]; 1672 } 1673 1674 if (ci->ci_cpuid_level < 0x7) 1675 return; 1676 1677 x86_cpuid(7, descs); 1678 ci->ci_feat_val[5] = descs[1]; 1679 ci->ci_feat_val[6] = descs[2]; 1680 ci->ci_feat_val[7] = descs[3]; 1681 1682 if (ci->ci_cpuid_level < 0xd) 1683 return; 1684 1685 /* Get support XCR0 bits */ 1686 x86_cpuid2(0xd, 0, descs); 1687 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1688 ci->ci_cur_xsave = descs[1]; 1689 ci->ci_max_xsave = descs[2]; 1690 1691 /* Additional flags (eg xsaveopt support) */ 1692 x86_cpuid2(0xd, 1, descs); 1693 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1694 } 1695 1696 static void 1697 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1698 { 1699 uint32_t descs[4]; 1700 char hv_sig[13]; 1701 char *p; 1702 const char *hv_name; 1703 int i; 1704 1705 /* 1706 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1707 * http://lkml.org/lkml/2008/10/1/246 1708 * 1709 * KB1009458: Mechanisms to determine if software is running in 1710 * a VMware virtual machine 1711 * http://kb.vmware.com/kb/1009458 1712 */ 1713 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1714 x86_cpuid(0x40000000, descs); 1715 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1716 memcpy(p, &descs[i], sizeof(descs[i])); 1717 *p = '\0'; 1718 /* 1719 * HV vendor ID string 1720 * ------------+-------------- 1721 * HAXM "HAXMHAXMHAXM" 1722 * KVM "KVMKVMKVM" 1723 * Microsoft "Microsoft Hv" 1724 * QEMU(TCG) "TCGTCGTCGTCG" 1725 * VMware "VMwareVMware" 1726 * Xen "XenVMMXenVMM" 1727 * NetBSD "___ NVMM ___" 1728 */ 1729 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1730 hv_name = "HAXM"; 1731 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1732 hv_name = "KVM"; 1733 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1734 hv_name = "Hyper-V"; 1735 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1736 hv_name = "QEMU(TCG)"; 1737 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1738 hv_name = "VMware"; 1739 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1740 hv_name = "Xen"; 1741 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1742 hv_name = "NVMM"; 1743 else 1744 hv_name = "unknown"; 1745 1746 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1747 } 1748 } 1749 1750 static void 1751 cpu_probe_features(struct cpu_info *ci) 1752 { 1753 const struct cpu_cpuid_nameclass *cpup = NULL; 1754 unsigned int i; 1755 1756 if (ci->ci_cpuid_level < 1) 1757 return; 1758 1759 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1760 if (!strncmp((char *)ci->ci_vendor, 1761 i386_cpuid_cpus[i].cpu_id, 12)) { 1762 cpup = &i386_cpuid_cpus[i]; 1763 break; 1764 } 1765 } 1766 1767 if (cpup == NULL) 1768 return; 1769 1770 i = ci->ci_family - CPU_MINFAMILY; 1771 1772 if (i >= __arraycount(cpup->cpu_family)) 1773 i = __arraycount(cpup->cpu_family) - 1; 1774 1775 if (cpup->cpu_family[i].cpu_probe == NULL) 1776 return; 1777 1778 (*cpup->cpu_family[i].cpu_probe)(ci); 1779 } 1780 1781 static void 1782 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1783 { 1784 char buf[32 * 16]; 1785 char *bp; 1786 1787 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1788 1789 if (val == 0 || fmt == NULL) 1790 return; 1791 1792 snprintb_m(buf, sizeof(buf), fmt, val, 1793 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1794 bp = buf; 1795 while (*bp != '\0') { 1796 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1797 bp += strlen(bp) + 1; 1798 } 1799 } 1800 1801 static void 1802 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1803 const char *blockname) 1804 { 1805 uint32_t descs[4]; 1806 uint32_t leaf; 1807 1808 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1809 leafend); 1810 1811 if (verbose) { 1812 for (leaf = leafstart; leaf <= leafend; leaf++) { 1813 x86_cpuid(leaf, descs); 1814 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1815 leaf, descs[0], descs[1], descs[2], descs[3]); 1816 } 1817 } 1818 } 1819 1820 static void 1821 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1822 { 1823 u_int lp_max = 1; /* logical processors per package */ 1824 u_int smt_max; /* smt per core */ 1825 u_int core_max = 1; /* core per package */ 1826 u_int smt_bits, core_bits; 1827 uint32_t descs[4]; 1828 1829 /* 1830 * 253668.pdf 7.10.2 1831 */ 1832 1833 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1834 x86_cpuid(1, descs); 1835 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1836 } 1837 x86_cpuid2(4, 0, descs); 1838 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1839 1840 assert(lp_max >= core_max); 1841 smt_max = lp_max / core_max; 1842 smt_bits = ilog2(smt_max - 1) + 1; 1843 core_bits = ilog2(core_max - 1) + 1; 1844 1845 if (smt_bits + core_bits) 1846 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1847 1848 if (core_bits) 1849 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1850 __BITS(smt_bits, smt_bits + core_bits - 1)); 1851 1852 if (smt_bits) 1853 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1854 __BITS((int)0, (int)(smt_bits - 1))); 1855 } 1856 1857 static void 1858 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1859 { 1860 const char *cpuname = ci->ci_dev; 1861 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1862 uint32_t descs[4]; 1863 int i; 1864 1865 x86_cpuid(0x0b, descs); 1866 if (descs[1] == 0) { 1867 identifycpu_cpuids_intel_0x04(ci); 1868 return; 1869 } 1870 1871 for (i = 0; ; i++) { 1872 unsigned int shiftnum, lvltype; 1873 x86_cpuid2(0x0b, i, descs); 1874 1875 /* On invalid level, (EAX and) EBX return 0 */ 1876 if (descs[1] == 0) 1877 break; 1878 1879 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1880 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1881 switch (lvltype) { 1882 case CPUID_TOP_LVLTYPE_SMT: 1883 core_shift = shiftnum; 1884 break; 1885 case CPUID_TOP_LVLTYPE_CORE: 1886 pkg_shift = shiftnum; 1887 break; 1888 case CPUID_TOP_LVLTYPE_INVAL: 1889 aprint_verbose("%s: Invalid level type\n", cpuname); 1890 break; 1891 default: 1892 aprint_verbose("%s: Unknown level type(%d) \n", 1893 cpuname, lvltype); 1894 break; 1895 } 1896 } 1897 1898 assert(pkg_shift >= core_shift); 1899 smt_bits = core_shift; 1900 core_bits = pkg_shift - core_shift; 1901 1902 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1903 1904 if (core_bits) 1905 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1906 __BITS(core_shift, pkg_shift - 1)); 1907 1908 if (smt_bits) 1909 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1910 __BITS((int)0, core_shift - 1)); 1911 } 1912 1913 static void 1914 identifycpu_cpuids_intel(struct cpu_info *ci) 1915 { 1916 const char *cpuname = ci->ci_dev; 1917 1918 if (ci->ci_cpuid_level >= 0x0b) 1919 identifycpu_cpuids_intel_0x0b(ci); 1920 else if (ci->ci_cpuid_level >= 4) 1921 identifycpu_cpuids_intel_0x04(ci); 1922 1923 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1924 ci->ci_packageid); 1925 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1926 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1927 } 1928 1929 static void 1930 identifycpu_cpuids_amd(struct cpu_info *ci) 1931 { 1932 const char *cpuname = ci->ci_dev; 1933 u_int lp_max, core_max; 1934 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1935 uint32_t descs[4]; 1936 1937 apic_id = ci->ci_initapicid; 1938 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1939 1940 if (cpu_family < 0xf) 1941 return; 1942 1943 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1944 x86_cpuid(1, descs); 1945 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1946 1947 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1948 x86_cpuid(0x8000008, descs); 1949 core_max = (descs[2] & 0xff) + 1; 1950 n = (descs[2] >> 12) & 0x0f; 1951 if (n != 0) 1952 core_bits = n; 1953 } 1954 } else { 1955 lp_max = 1; 1956 } 1957 core_max = lp_max; 1958 1959 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1960 if (core_bits == 0) 1961 core_bits = ilog2(core_max - 1) + 1; 1962 1963 if (cpu_family < 0x11) { 1964 const uint64_t reg = rdmsr(MSR_NB_CFG); 1965 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1966 const u_int node_id = apic_id & __BITS(0, 2); 1967 apic_id = (cpu_family == 0xf) ? 1968 (apic_id >> core_bits) | (node_id << core_bits) : 1969 (apic_id >> 5) | (node_id << 2); 1970 } 1971 } 1972 1973 if (cpu_family == 0x17) { 1974 x86_cpuid(0x8000001e, descs); 1975 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1976 smt_bits = ilog2(threads); 1977 core_bits -= smt_bits; 1978 } 1979 1980 if (smt_bits + core_bits) { 1981 if (smt_bits + core_bits < 32) 1982 ci->ci_packageid = 0; 1983 } 1984 if (core_bits) { 1985 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1986 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1987 } 1988 if (smt_bits) { 1989 u_int smt_mask = __BITS(0, smt_bits - 1); 1990 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1991 } 1992 1993 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1994 ci->ci_packageid); 1995 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1996 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1997 } 1998 1999 static void 2000 identifycpu_cpuids(struct cpu_info *ci) 2001 { 2002 const char *cpuname = ci->ci_dev; 2003 2004 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 2005 ci->ci_packageid = ci->ci_initapicid; 2006 ci->ci_coreid = 0; 2007 ci->ci_smtid = 0; 2008 2009 if (cpu_vendor == CPUVENDOR_INTEL) 2010 identifycpu_cpuids_intel(ci); 2011 else if (cpu_vendor == CPUVENDOR_AMD) 2012 identifycpu_cpuids_amd(ci); 2013 } 2014 2015 void 2016 identifycpu(int fd, const char *cpuname) 2017 { 2018 const char *name = "", *modifier, *vendorname, *brand = ""; 2019 int class = CPUCLASS_386; 2020 unsigned int i; 2021 int modif, family; 2022 const struct cpu_cpuid_nameclass *cpup = NULL; 2023 const struct cpu_cpuid_family *cpufam; 2024 struct cpu_info *ci, cistore; 2025 u_int descs[4]; 2026 size_t sz; 2027 struct cpu_ucode_version ucode; 2028 union { 2029 struct cpu_ucode_version_amd amd; 2030 struct cpu_ucode_version_intel1 intel1; 2031 } ucvers; 2032 2033 ci = &cistore; 2034 cpu_probe_base_features(ci, cpuname); 2035 dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic"); 2036 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2037 x86_cpuid(0x40000000, descs); 2038 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2039 } 2040 dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended"); 2041 2042 cpu_probe_hv_features(ci, cpuname); 2043 cpu_probe_features(ci); 2044 2045 if (ci->ci_cpu_type >= 0) { 2046 /* Old pre-cpuid instruction cpu */ 2047 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2048 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2049 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2050 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2051 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2052 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2053 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2054 modifier = ""; 2055 } else { 2056 /* CPU which support cpuid instruction */ 2057 modif = (ci->ci_signature >> 12) & 0x3; 2058 family = ci->ci_family; 2059 if (family < CPU_MINFAMILY) 2060 errx(1, "identifycpu: strange family value"); 2061 if (family > CPU_MAXFAMILY) 2062 family = CPU_MAXFAMILY; 2063 2064 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2065 if (!strncmp((char *)ci->ci_vendor, 2066 i386_cpuid_cpus[i].cpu_id, 12)) { 2067 cpup = &i386_cpuid_cpus[i]; 2068 break; 2069 } 2070 } 2071 2072 if (cpup == NULL) { 2073 cpu_vendor = CPUVENDOR_UNKNOWN; 2074 if (ci->ci_vendor[0] != '\0') 2075 vendorname = (char *)&ci->ci_vendor[0]; 2076 else 2077 vendorname = "Unknown"; 2078 class = family - 3; 2079 modifier = ""; 2080 name = ""; 2081 ci->ci_info = NULL; 2082 } else { 2083 cpu_vendor = cpup->cpu_vendor; 2084 vendorname = cpup->cpu_vendorname; 2085 modifier = modifiers[modif]; 2086 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2087 name = cpufam->cpu_models[ci->ci_model]; 2088 if (name == NULL || *name == '\0') 2089 name = cpufam->cpu_model_default; 2090 class = cpufam->cpu_class; 2091 ci->ci_info = cpufam->cpu_info; 2092 2093 if (cpu_vendor == CPUVENDOR_INTEL) { 2094 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2095 const char *tmp; 2096 tmp = intel_family6_name(ci); 2097 if (tmp != NULL) 2098 name = tmp; 2099 } 2100 if (ci->ci_family == 15 && 2101 ci->ci_brand_id < 2102 __arraycount(i386_intel_brand) && 2103 i386_intel_brand[ci->ci_brand_id]) 2104 name = 2105 i386_intel_brand[ci->ci_brand_id]; 2106 } 2107 2108 if (cpu_vendor == CPUVENDOR_AMD) { 2109 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2110 if (ci->ci_brand_id == 1) 2111 /* 2112 * It's Duron. We override the 2113 * name, since it might have 2114 * been misidentified as Athlon. 2115 */ 2116 name = 2117 amd_brand[ci->ci_brand_id]; 2118 else 2119 brand = amd_brand_name; 2120 } 2121 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2122 == 0xf) { 2123 /* Identify AMD64 CPU names. */ 2124 const char *tmp; 2125 tmp = amd_amd64_name(ci); 2126 if (tmp != NULL) 2127 name = tmp; 2128 } 2129 } 2130 2131 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2132 vendorname = "VIA"; 2133 } 2134 } 2135 2136 ci->ci_cpu_class = class; 2137 2138 sz = sizeof(ci->ci_tsc_freq); 2139 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2140 sz = sizeof(use_pae); 2141 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2142 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2143 2144 /* 2145 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2146 * we try to determine from the family/model values. 2147 */ 2148 if (*cpu_brand_string != '\0') 2149 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2150 2151 aprint_normal("%s: %s", cpuname, vendorname); 2152 if (*modifier) 2153 aprint_normal(" %s", modifier); 2154 if (*name) 2155 aprint_normal(" %s", name); 2156 if (*brand) 2157 aprint_normal(" %s", brand); 2158 aprint_normal(" (%s-class)", classnames[class]); 2159 2160 if (ci->ci_tsc_freq != 0) 2161 aprint_normal(", %ju.%02ju MHz", 2162 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2163 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2164 aprint_normal("\n"); 2165 2166 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2167 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2168 if (ci->ci_signature != 0) 2169 aprint_normal(" (id %#x)", ci->ci_signature); 2170 aprint_normal("\n"); 2171 2172 if (ci->ci_info) 2173 (*ci->ci_info)(ci); 2174 2175 /* 2176 * display CPU feature flags 2177 */ 2178 2179 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2180 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2181 2182 /* These next two are actually common definitions! */ 2183 print_bits(cpuname, "features2", 2184 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2185 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2186 print_bits(cpuname, "features3", 2187 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2188 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2189 2190 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2191 ci->ci_feat_val[4]); 2192 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2193 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2194 ci->ci_feat_val[5]); 2195 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2196 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2197 ci->ci_feat_val[6]); 2198 2199 if (cpu_vendor == CPUVENDOR_INTEL) 2200 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2201 ci->ci_feat_val[7]); 2202 2203 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2204 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2205 ci->ci_feat_val[9]); 2206 2207 if (ci->ci_max_xsave != 0) { 2208 aprint_normal("%s: xsave area size: current %d, maximum %d", 2209 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2210 aprint_normal(", xgetbv %sabled\n", 2211 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2212 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2213 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2214 x86_xgetbv()); 2215 } 2216 2217 x86_print_cache_and_tlb_info(ci); 2218 2219 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2220 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2221 cpuname, 2222 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2223 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2224 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2225 } 2226 2227 if (ci->ci_cpu_class == CPUCLASS_386) 2228 errx(1, "NetBSD requires an 80486 or later processor"); 2229 2230 if (ci->ci_cpu_type == CPU_486DLC) { 2231 #ifndef CYRIX_CACHE_WORKS 2232 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2233 #else 2234 #ifndef CYRIX_CACHE_REALLY_WORKS 2235 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2236 #else 2237 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2238 #endif 2239 #endif 2240 } 2241 2242 /* 2243 * Everything past this point requires a Pentium or later. 2244 */ 2245 if (ci->ci_cpuid_level < 0) 2246 return; 2247 2248 identifycpu_cpuids(ci); 2249 2250 if ((ci->ci_cpuid_level >= 5) 2251 && ((cpu_vendor == CPUVENDOR_INTEL) 2252 || (cpu_vendor == CPUVENDOR_AMD))) { 2253 uint16_t lmin, lmax; 2254 x86_cpuid(5, descs); 2255 2256 print_bits(cpuname, "MONITOR/MWAIT extensions", 2257 CPUID_MON_FLAGS, descs[2]); 2258 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2259 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2260 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2261 if (lmin != lmax) 2262 aprint_normal("-%hu", lmax); 2263 aprint_normal("\n"); 2264 2265 for (i = 0; i <= 7; i++) { 2266 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2267 2268 if (num != 0) 2269 aprint_normal("%s: C%u substates %u\n", 2270 cpuname, i, num); 2271 } 2272 } 2273 if ((ci->ci_cpuid_level >= 6) 2274 && ((cpu_vendor == CPUVENDOR_INTEL) 2275 || (cpu_vendor == CPUVENDOR_AMD))) { 2276 x86_cpuid(6, descs); 2277 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2278 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2279 } 2280 if ((ci->ci_cpuid_level >= 7) 2281 && ((cpu_vendor == CPUVENDOR_INTEL) 2282 || (cpu_vendor == CPUVENDOR_AMD))) { 2283 x86_cpuid(7, descs); 2284 aprint_verbose("%s: SEF highest subleaf %08x\n", 2285 cpuname, descs[0]); 2286 } 2287 2288 if (cpu_vendor == CPUVENDOR_AMD) { 2289 x86_cpuid(0x80000000, descs); 2290 if (descs[0] >= 0x80000000) 2291 ci->ci_max_ext_cpuid = descs[0]; 2292 else 2293 ci->ci_max_ext_cpuid = 0; 2294 if (descs[0] >= 0x80000007) 2295 powernow_probe(ci); 2296 2297 if ((descs[0] >= 0x8000000a) 2298 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2299 x86_cpuid(0x8000000a, descs); 2300 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2301 descs[0] & 0xf); 2302 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2303 descs[1]); 2304 print_bits(cpuname, "SVM features", 2305 CPUID_AMD_SVM_FLAGS, descs[3]); 2306 } 2307 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2308 int32_t bi_index; 2309 2310 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2311 x86_cpuid(bi_index, descs); 2312 switch (bi_index) { 2313 case 0x0a: 2314 print_bits(cpuname, "Perfmon-eax", 2315 CPUID_PERF_FLAGS0, descs[0]); 2316 print_bits(cpuname, "Perfmon-ebx", 2317 CPUID_PERF_FLAGS1, descs[1]); 2318 print_bits(cpuname, "Perfmon-edx", 2319 CPUID_PERF_FLAGS3, descs[3]); 2320 break; 2321 default: 2322 #if 0 2323 aprint_verbose("%s: basic %08x-eax %08x\n", 2324 cpuname, bi_index, descs[0]); 2325 aprint_verbose("%s: basic %08x-ebx %08x\n", 2326 cpuname, bi_index, descs[1]); 2327 aprint_verbose("%s: basic %08x-ecx %08x\n", 2328 cpuname, bi_index, descs[2]); 2329 aprint_verbose("%s: basic %08x-edx %08x\n", 2330 cpuname, bi_index, descs[3]); 2331 #endif 2332 break; 2333 } 2334 } 2335 } 2336 2337 #ifdef INTEL_ONDEMAND_CLOCKMOD 2338 clockmod_init(); 2339 #endif 2340 2341 if (cpu_vendor == CPUVENDOR_AMD) 2342 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2343 else if (cpu_vendor == CPUVENDOR_INTEL) 2344 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2345 else 2346 return; 2347 2348 ucode.data = &ucvers; 2349 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2350 #ifdef __i386__ 2351 struct cpu_ucode_version_64 ucode_64; 2352 if (errno != ENOTTY) 2353 return; 2354 /* Try the 64 bit ioctl */ 2355 memset(&ucode_64, 0, sizeof ucode_64); 2356 ucode_64.data = &ucvers; 2357 ucode_64.loader_version = ucode.loader_version; 2358 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2359 return; 2360 #else 2361 return; 2362 #endif 2363 } 2364 2365 if (cpu_vendor == CPUVENDOR_AMD) 2366 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2367 else if (cpu_vendor == CPUVENDOR_INTEL) 2368 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2369 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2370 } 2371 2372 static const struct x86_cache_info * 2373 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2374 { 2375 int i; 2376 2377 for (i = 0; cai[i].cai_desc != 0; i++) { 2378 if (cai[i].cai_desc == desc) 2379 return (&cai[i]); 2380 } 2381 2382 return (NULL); 2383 } 2384 2385 static const char * 2386 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2387 const char *sep) 2388 { 2389 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2390 char human_num[HUMAN_BUFSIZE]; 2391 2392 if (cai->cai_totalsize == 0) 2393 return sep; 2394 2395 if (sep == NULL) 2396 aprint_verbose_dev(ci->ci_dev, ""); 2397 else 2398 aprint_verbose("%s", sep); 2399 if (name != NULL) 2400 aprint_verbose("%s ", name); 2401 2402 if (cai->cai_string != NULL) { 2403 aprint_verbose("%s ", cai->cai_string); 2404 } else { 2405 (void)humanize_number(human_num, sizeof(human_num), 2406 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2407 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2408 } 2409 switch (cai->cai_associativity) { 2410 case 0: 2411 aprint_verbose("disabled"); 2412 break; 2413 case 1: 2414 aprint_verbose("direct-mapped"); 2415 break; 2416 case 0xff: 2417 aprint_verbose("fully associative"); 2418 break; 2419 default: 2420 aprint_verbose("%d-way", cai->cai_associativity); 2421 break; 2422 } 2423 return ", "; 2424 } 2425 2426 static const char * 2427 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2428 const char *sep) 2429 { 2430 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2431 char human_num[HUMAN_BUFSIZE]; 2432 2433 if (cai->cai_totalsize == 0) 2434 return sep; 2435 2436 if (sep == NULL) 2437 aprint_verbose_dev(ci->ci_dev, ""); 2438 else 2439 aprint_verbose("%s", sep); 2440 if (name != NULL) 2441 aprint_verbose("%s ", name); 2442 2443 if (cai->cai_string != NULL) { 2444 aprint_verbose("%s", cai->cai_string); 2445 } else { 2446 (void)humanize_number(human_num, sizeof(human_num), 2447 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2448 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2449 human_num); 2450 switch (cai->cai_associativity) { 2451 case 0: 2452 aprint_verbose("disabled"); 2453 break; 2454 case 1: 2455 aprint_verbose("direct-mapped"); 2456 break; 2457 case 0xff: 2458 aprint_verbose("fully associative"); 2459 break; 2460 default: 2461 aprint_verbose("%d-way", cai->cai_associativity); 2462 break; 2463 } 2464 } 2465 return ", "; 2466 } 2467 2468 static void 2469 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2470 { 2471 const char *sep = NULL; 2472 2473 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2474 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2475 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2476 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2477 if (sep != NULL) 2478 aprint_verbose("\n"); 2479 } 2480 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2481 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2482 if (sep != NULL) 2483 aprint_verbose("\n"); 2484 } 2485 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2486 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2487 if (sep != NULL) 2488 aprint_verbose("\n"); 2489 } 2490 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2491 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2492 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2493 if (sep != NULL) 2494 aprint_verbose("\n"); 2495 } 2496 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2497 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2498 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2499 if (sep != NULL) 2500 aprint_verbose("\n"); 2501 } 2502 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2503 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2504 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2505 if (sep != NULL) 2506 aprint_verbose("\n"); 2507 } 2508 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2509 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2510 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2511 if (sep != NULL) 2512 aprint_verbose("\n"); 2513 } 2514 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2515 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2516 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2517 if (sep != NULL) 2518 aprint_verbose("\n"); 2519 } 2520 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2521 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2522 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2523 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2524 if (sep != NULL) 2525 aprint_verbose("\n"); 2526 } 2527 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2528 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2529 NULL); 2530 if (sep != NULL) 2531 aprint_verbose("\n"); 2532 } 2533 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2534 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2535 NULL); 2536 if (sep != NULL) 2537 aprint_verbose("\n"); 2538 } 2539 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2540 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2541 NULL); 2542 if (sep != NULL) 2543 aprint_verbose("\n"); 2544 } 2545 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2546 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2547 NULL); 2548 if (sep != NULL) 2549 aprint_verbose("\n"); 2550 } 2551 } 2552 2553 static void 2554 powernow_probe(struct cpu_info *ci) 2555 { 2556 uint32_t regs[4]; 2557 char buf[256]; 2558 2559 x86_cpuid(0x80000007, regs); 2560 2561 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2562 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2563 buf); 2564 } 2565 2566 bool 2567 identifycpu_bind(void) 2568 { 2569 2570 return true; 2571 } 2572 2573 int 2574 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2575 { 2576 struct cpu_info ci; 2577 int loader_version, res; 2578 struct cpu_ucode_version versreq; 2579 2580 cpu_probe_base_features(&ci, "unknown"); 2581 2582 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2583 loader_version = CPU_UCODE_LOADER_AMD; 2584 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2585 loader_version = CPU_UCODE_LOADER_INTEL1; 2586 else 2587 return -1; 2588 2589 /* check whether the kernel understands this loader version */ 2590 versreq.loader_version = loader_version; 2591 versreq.data = 0; 2592 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2593 if (res) 2594 return -1; 2595 2596 switch (loader_version) { 2597 case CPU_UCODE_LOADER_AMD: 2598 if (uc->cpu_nr != -1) { 2599 /* printf? */ 2600 return -1; 2601 } 2602 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2603 break; 2604 case CPU_UCODE_LOADER_INTEL1: 2605 if (uc->cpu_nr == -1) 2606 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2607 else 2608 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2609 break; 2610 default: /* can't happen */ 2611 return -1; 2612 } 2613 uc->loader_version = loader_version; 2614 return 0; 2615 } 2616
Indexes created Sat Oct 25 16:10:12 GMT 2025