1b8e80941Smrg<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2b8e80941Smrg<html lang="en"> 3b8e80941Smrg<head> 4b8e80941Smrg <meta http-equiv="content-type" content="text/html; charset=utf-8"> 5b8e80941Smrg <title>Mesa Release Notes</title> 6b8e80941Smrg <link rel="stylesheet" type="text/css" href="../mesa.css"> 7b8e80941Smrg</head> 8b8e80941Smrg<body> 9b8e80941Smrg 10b8e80941Smrg<div class="header"> 11b8e80941Smrg <h1>The Mesa 3D Graphics Library</h1> 12b8e80941Smrg</div> 13b8e80941Smrg 14b8e80941Smrg<iframe src="../contents.html"></iframe> 15b8e80941Smrg<div class="content"> 16b8e80941Smrg 17b8e80941Smrg<h1>Mesa 17.0.2 Release Notes / March 20, 2017</h1> 18b8e80941Smrg 19b8e80941Smrg<p> 20b8e80941SmrgMesa 17.0.2 is a bug fix release which fixes bugs found since the 17.0.1 release. 21b8e80941Smrg</p> 22b8e80941Smrg<p> 23b8e80941SmrgMesa 17.0.2 implements the OpenGL 4.5 API, but the version reported by 24b8e80941SmrgglGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / 25b8e80941SmrgglGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. 26b8e80941SmrgSome drivers don't support all the features required in OpenGL 4.5. OpenGL 27b8e80941Smrg4.5 is <strong>only</strong> available if requested at context creation 28b8e80941Smrgbecause compatibility contexts are not supported. 29b8e80941Smrg</p> 30b8e80941Smrg 31b8e80941Smrg 32b8e80941Smrg<h2>SHA256 checksums</h2> 33b8e80941Smrg<pre> 34b8e80941Smrg2e0f41e7974ba7a36ca32bbeaf8ebcd65c8fd4d2dc9872f04d4becbd5e7a8cb5 mesa-17.0.2.tar.gz 35b8e80941Smrgf8f191f909e01e65de38d5bdea5fb057f21649a3aed20948be02348e77a689d4 mesa-17.0.2.tar.xz 36b8e80941Smrg</pre> 37b8e80941Smrg 38b8e80941Smrg 39b8e80941Smrg<h2>New features</h2> 40b8e80941Smrg<p>None</p> 41b8e80941Smrg 42b8e80941Smrg 43b8e80941Smrg<h2>Bug fixes</h2> 44b8e80941Smrg 45b8e80941Smrg<ul> 46b8e80941Smrg 47b8e80941Smrg<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68504">Bug 68504</a> - 9.2-rc1 workaround for clover build failure on ppc/altivec: cannot convert 'bool' to '__vector(4) __bool int' in return</li> 48b8e80941Smrg 49b8e80941Smrg<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97988">Bug 97988</a> - [radeonsi] playing back videos with VDPAU exhibits deinterlacing/anti-aliasing issues not visible with VA-API</li> 50b8e80941Smrg 51b8e80941Smrg<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99484">Bug 99484</a> - Crusader Kings 2 - Loading bars, siege bars, morale bars, etc. do not render correctly</li> 52b8e80941Smrg 53b8e80941Smrg<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99715">Bug 99715</a> - Don't print: "Note: Buggy applications may crash, if they do please report to vendor"</li> 54b8e80941Smrg 55b8e80941Smrg<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100049">Bug 100049</a> - "ralloc: Make sure ralloc() allocations match malloc()'s alignment." causes seg fault in 32bit build</li> 56b8e80941Smrg 57b8e80941Smrg</ul> 58b8e80941Smrg 59b8e80941Smrg 60b8e80941Smrg<h2>Changes</h2> 61b8e80941Smrg 62b8e80941Smrg<p>Alex Smith (3):</p> 63b8e80941Smrg<ul> 64b8e80941Smrg <li>radv: Emit pending flushes before executing a secondary command buffer</li> 65b8e80941Smrg <li>radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer</li> 66b8e80941Smrg <li>radv/ac: Fix shared memory offset calculation</li> 67b8e80941Smrg</ul> 68b8e80941Smrg 69b8e80941Smrg<p>Bas Nieuwenhuizen (3):</p> 70b8e80941Smrg<ul> 71b8e80941Smrg <li>radv: Disable HTILE for textures with multiple layers/levels.</li> 72b8e80941Smrg <li>radv: Emit cache flushes before CP DMA.</li> 73b8e80941Smrg <li>Revert "radv: Emit cache flushes before CP DMA."</li> 74b8e80941Smrg</ul> 75b8e80941Smrg 76b8e80941Smrg<p>Dave Airlie (3):</p> 77b8e80941Smrg<ul> 78b8e80941Smrg <li>radv: drop Z24 support.</li> 79b8e80941Smrg <li>radv: disable mip point pre clamping.</li> 80b8e80941Smrg <li>radv: setup llvm target data layout</li> 81b8e80941Smrg</ul> 82b8e80941Smrg 83b8e80941Smrg<p>Emil Velikov (4):</p> 84b8e80941Smrg<ul> 85b8e80941Smrg <li>docs: add sha256 checksums for 17.0.1</li> 86b8e80941Smrg <li>cherry-ignore: add the swizzle blorp_clear fix</li> 87b8e80941Smrg <li>i965: move brw_define.h ifndef guard to the top</li> 88b8e80941Smrg <li>Update version to 17.0.2</li> 89b8e80941Smrg</ul> 90b8e80941Smrg 91b8e80941Smrg<p>Fredrik Höglund (2):</p> 92b8e80941Smrg<ul> 93b8e80941Smrg <li>radv: fix the dynamic buffer index in vkCmdBindDescriptorSets</li> 94b8e80941Smrg <li>radv/ac: fix multiple descriptor sets with dynamic buffers</li> 95b8e80941Smrg</ul> 96b8e80941Smrg 97b8e80941Smrg<p>Gregory Hainaut (1):</p> 98b8e80941Smrg<ul> 99b8e80941Smrg <li>glapi: fix typo in count_scale</li> 100b8e80941Smrg</ul> 101b8e80941Smrg 102b8e80941Smrg<p>Ilia Mirkin (2):</p> 103b8e80941Smrg<ul> 104b8e80941Smrg <li>nvc0: take extra pushbuf space into account for pushbuf_space calls</li> 105b8e80941Smrg <li>nvc0: increase alignment to 256 for texture buffers on fermi</li> 106b8e80941Smrg</ul> 107b8e80941Smrg 108b8e80941Smrg<p>Jacob Lifshay (1):</p> 109b8e80941Smrg<ul> 110b8e80941Smrg <li>vulkan/wsi: Improve the DRI3 error message</li> 111b8e80941Smrg</ul> 112b8e80941Smrg 113b8e80941Smrg<p>James Legg (1):</p> 114b8e80941Smrg<ul> 115b8e80941Smrg <li>radv: Fix using more than 4 bound descriptor sets</li> 116b8e80941Smrg</ul> 117b8e80941Smrg 118b8e80941Smrg<p>Jason Ekstrand (7):</p> 119b8e80941Smrg<ul> 120b8e80941Smrg <li>anv/blorp/clear_subpass: Only set surface clear color for fast clears</li> 121b8e80941Smrg <li>anv: Accurately advertise dynamic descriptor limits</li> 122b8e80941Smrg <li>anv: Stall before fast-clear operations</li> 123b8e80941Smrg <li>anv: Properly handle destroying NULL devices and instances</li> 124b8e80941Smrg <li>anv/blorp: Turn off AUX after doing a CCS_D resolve</li> 125b8e80941Smrg <li>anv/blorp: Only set a clear color for resolves if fast-cleared</li> 126b8e80941Smrg <li>nir/intrinsics: Make load_barycentric_input take a 2-component coor</li> 127b8e80941Smrg</ul> 128b8e80941Smrg 129b8e80941Smrg<p>Jonas Pfeil (1):</p> 130b8e80941Smrg<ul> 131b8e80941Smrg <li>ralloc: Make sure ralloc() allocations match malloc()'s alignment.</li> 132b8e80941Smrg</ul> 133b8e80941Smrg 134b8e80941Smrg<p>Kenneth Graunke (1):</p> 135b8e80941Smrg<ul> 136b8e80941Smrg <li>egl: Ensure ResetNotificationStrategy matches for shared contexts.</li> 137b8e80941Smrg</ul> 138b8e80941Smrg 139b8e80941Smrg<p>Marek Olšák (3):</p> 140b8e80941Smrg<ul> 141b8e80941Smrg <li>st/mesa: reset sample_mask, min_sample, and render_condition for PBO ops</li> 142b8e80941Smrg <li>st/mesa: set blend state for PBO readbacks</li> 143b8e80941Smrg <li>radeonsi: mark all bound shader buffer ranges as initialized</li> 144b8e80941Smrg</ul> 145b8e80941Smrg 146b8e80941Smrg<p>Matt Turner (1):</p> 147b8e80941Smrg<ul> 148b8e80941Smrg <li>clover: Work around build failure with AltiVec.</li> 149b8e80941Smrg</ul> 150b8e80941Smrg 151b8e80941Smrg<p>Nanley Chery (2):</p> 152b8e80941Smrg<ul> 153b8e80941Smrg <li>anv/pass: Avoid accessing attachment array out of bounds</li> 154b8e80941Smrg <li>anv/image: Remove extra dependency on HiZ-specific variable</li> 155b8e80941Smrg</ul> 156b8e80941Smrg 157b8e80941Smrg<p>Nicolai Hähnle (2):</p> 158b8e80941Smrg<ul> 159b8e80941Smrg <li>st/glsl_to_tgsi: avoid iterating past the head of the instruction list</li> 160b8e80941Smrg <li>st/mesa: inform the driver of framebuffer changes before compute dispatches</li> 161b8e80941Smrg</ul> 162b8e80941Smrg 163b8e80941Smrg<p>Robert Foss (1):</p> 164b8e80941Smrg<ul> 165b8e80941Smrg <li>mesa: Avoid read of uninitialized variable</li> 166b8e80941Smrg</ul> 167b8e80941Smrg 168b8e80941Smrg<p>Samuel Iglesias Gonsálvez (5):</p> 169b8e80941Smrg<ul> 170b8e80941Smrg <li>i965/fs: mark last DF uniform array element as 64 bit live one</li> 171b8e80941Smrg <li>i965/fs: detect different bit size accesses to uniforms to push them in proper locations</li> 172b8e80941Smrg <li>i965/fs: fix indirect load DF uniforms on BSW/BXT</li> 173b8e80941Smrg <li>i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles</li> 174b8e80941Smrg <li>i965/fs: emit MOV_INDIRECT with the source with the right register type</li> 175b8e80941Smrg</ul> 176b8e80941Smrg 177b8e80941Smrg<p>Samuel Pitoiset (1):</p> 178b8e80941Smrg<ul> 179b8e80941Smrg <li>radeonsi: disable sinking common instructions down to the end block</li> 180b8e80941Smrg</ul> 181b8e80941Smrg 182b8e80941Smrg 183b8e80941Smrg</div> 184b8e80941Smrg</body> 185b8e80941Smrg</html> 186