1b8e80941Smrg/******************************************************************************* 2b8e80941Smrg * Copyright (c) 2008-2019 The Khronos Group Inc. 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and/or associated documentation files (the 6b8e80941Smrg * "Materials"), to deal in the Materials without restriction, including 7b8e80941Smrg * without limitation the rights to use, copy, modify, merge, publish, 8b8e80941Smrg * distribute, sublicense, and/or sell copies of the Materials, and to 9b8e80941Smrg * permit persons to whom the Materials are furnished to do so, subject to 10b8e80941Smrg * the following conditions: 11b8e80941Smrg * 12b8e80941Smrg * The above copyright notice and this permission notice shall be included 13b8e80941Smrg * in all copies or substantial portions of the Materials. 14b8e80941Smrg * 15b8e80941Smrg * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS 16b8e80941Smrg * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS 17b8e80941Smrg * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT 18b8e80941Smrg * https://www.khronos.org/registry/ 19b8e80941Smrg * 20b8e80941Smrg * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21b8e80941Smrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22b8e80941Smrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23b8e80941Smrg * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24b8e80941Smrg * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25b8e80941Smrg * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26b8e80941Smrg * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. 27b8e80941Smrg ******************************************************************************/ 28b8e80941Smrg/*****************************************************************************\ 29b8e80941Smrg 30b8e80941SmrgCopyright (c) 2013-2019 Intel Corporation All Rights Reserved. 31b8e80941Smrg 32b8e80941SmrgTHESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33b8e80941Smrg"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34b8e80941SmrgLIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 35b8e80941SmrgA PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 36b8e80941SmrgCONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 37b8e80941SmrgEXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 38b8e80941SmrgPROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 39b8e80941SmrgPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40b8e80941SmrgOF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 41b8e80941SmrgNEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE 42b8e80941SmrgMATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43b8e80941Smrg 44b8e80941SmrgFile Name: cl_ext_intel.h 45b8e80941Smrg 46b8e80941SmrgAbstract: 47b8e80941Smrg 48b8e80941SmrgNotes: 49b8e80941Smrg 50b8e80941Smrg\*****************************************************************************/ 51b8e80941Smrg 52b8e80941Smrg#ifndef __CL_EXT_INTEL_H 53b8e80941Smrg#define __CL_EXT_INTEL_H 54b8e80941Smrg 55b8e80941Smrg#include <CL/cl.h> 56b8e80941Smrg#include <CL/cl_platform.h> 57b8e80941Smrg 58b8e80941Smrg#ifdef __cplusplus 59b8e80941Smrgextern "C" { 60b8e80941Smrg#endif 61b8e80941Smrg 62b8e80941Smrg/*************************************** 63b8e80941Smrg* cl_intel_thread_local_exec extension * 64b8e80941Smrg****************************************/ 65b8e80941Smrg 66b8e80941Smrg#define cl_intel_thread_local_exec 1 67b8e80941Smrg 68b8e80941Smrg#define CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL (((cl_bitfield)1) << 31) 69b8e80941Smrg 70b8e80941Smrg/*********************************************** 71b8e80941Smrg* cl_intel_device_partition_by_names extension * 72b8e80941Smrg************************************************/ 73b8e80941Smrg 74b8e80941Smrg#define cl_intel_device_partition_by_names 1 75b8e80941Smrg 76b8e80941Smrg#define CL_DEVICE_PARTITION_BY_NAMES_INTEL 0x4052 77b8e80941Smrg#define CL_PARTITION_BY_NAMES_LIST_END_INTEL -1 78b8e80941Smrg 79b8e80941Smrg/************************************************ 80b8e80941Smrg* cl_intel_accelerator extension * 81b8e80941Smrg* cl_intel_motion_estimation extension * 82b8e80941Smrg* cl_intel_advanced_motion_estimation extension * 83b8e80941Smrg*************************************************/ 84b8e80941Smrg 85b8e80941Smrg#define cl_intel_accelerator 1 86b8e80941Smrg#define cl_intel_motion_estimation 1 87b8e80941Smrg#define cl_intel_advanced_motion_estimation 1 88b8e80941Smrg 89b8e80941Smrgtypedef struct _cl_accelerator_intel* cl_accelerator_intel; 90b8e80941Smrgtypedef cl_uint cl_accelerator_type_intel; 91b8e80941Smrgtypedef cl_uint cl_accelerator_info_intel; 92b8e80941Smrg 93b8e80941Smrgtypedef struct _cl_motion_estimation_desc_intel { 94b8e80941Smrg cl_uint mb_block_type; 95b8e80941Smrg cl_uint subpixel_mode; 96b8e80941Smrg cl_uint sad_adjust_mode; 97b8e80941Smrg cl_uint search_path_type; 98b8e80941Smrg} cl_motion_estimation_desc_intel; 99b8e80941Smrg 100b8e80941Smrg/* error codes */ 101b8e80941Smrg#define CL_INVALID_ACCELERATOR_INTEL -1094 102b8e80941Smrg#define CL_INVALID_ACCELERATOR_TYPE_INTEL -1095 103b8e80941Smrg#define CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL -1096 104b8e80941Smrg#define CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL -1097 105b8e80941Smrg 106b8e80941Smrg/* cl_accelerator_type_intel */ 107b8e80941Smrg#define CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL 0x0 108b8e80941Smrg 109b8e80941Smrg/* cl_accelerator_info_intel */ 110b8e80941Smrg#define CL_ACCELERATOR_DESCRIPTOR_INTEL 0x4090 111b8e80941Smrg#define CL_ACCELERATOR_REFERENCE_COUNT_INTEL 0x4091 112b8e80941Smrg#define CL_ACCELERATOR_CONTEXT_INTEL 0x4092 113b8e80941Smrg#define CL_ACCELERATOR_TYPE_INTEL 0x4093 114b8e80941Smrg 115b8e80941Smrg/* cl_motion_detect_desc_intel flags */ 116b8e80941Smrg#define CL_ME_MB_TYPE_16x16_INTEL 0x0 117b8e80941Smrg#define CL_ME_MB_TYPE_8x8_INTEL 0x1 118b8e80941Smrg#define CL_ME_MB_TYPE_4x4_INTEL 0x2 119b8e80941Smrg 120b8e80941Smrg#define CL_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 121b8e80941Smrg#define CL_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 122b8e80941Smrg#define CL_ME_SUBPIXEL_MODE_QPEL_INTEL 0x2 123b8e80941Smrg 124b8e80941Smrg#define CL_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 125b8e80941Smrg#define CL_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x1 126b8e80941Smrg 127b8e80941Smrg#define CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL 0x0 128b8e80941Smrg#define CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL 0x1 129b8e80941Smrg#define CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL 0x5 130b8e80941Smrg 131b8e80941Smrg#define CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL 0x0 132b8e80941Smrg#define CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL 0x1 133b8e80941Smrg#define CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL 0x2 134b8e80941Smrg#define CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL 0x4 135b8e80941Smrg 136b8e80941Smrg#define CL_ME_FORWARD_INPUT_MODE_INTEL 0x1 137b8e80941Smrg#define CL_ME_BACKWARD_INPUT_MODE_INTEL 0x2 138b8e80941Smrg#define CL_ME_BIDIRECTION_INPUT_MODE_INTEL 0x3 139b8e80941Smrg 140b8e80941Smrg#define CL_ME_BIDIR_WEIGHT_QUARTER_INTEL 16 141b8e80941Smrg#define CL_ME_BIDIR_WEIGHT_THIRD_INTEL 21 142b8e80941Smrg#define CL_ME_BIDIR_WEIGHT_HALF_INTEL 32 143b8e80941Smrg#define CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 43 144b8e80941Smrg#define CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 48 145b8e80941Smrg 146b8e80941Smrg#define CL_ME_COST_PENALTY_NONE_INTEL 0x0 147b8e80941Smrg#define CL_ME_COST_PENALTY_LOW_INTEL 0x1 148b8e80941Smrg#define CL_ME_COST_PENALTY_NORMAL_INTEL 0x2 149b8e80941Smrg#define CL_ME_COST_PENALTY_HIGH_INTEL 0x3 150b8e80941Smrg 151b8e80941Smrg#define CL_ME_COST_PRECISION_QPEL_INTEL 0x0 152b8e80941Smrg#define CL_ME_COST_PRECISION_HPEL_INTEL 0x1 153b8e80941Smrg#define CL_ME_COST_PRECISION_PEL_INTEL 0x2 154b8e80941Smrg#define CL_ME_COST_PRECISION_DPEL_INTEL 0x3 155b8e80941Smrg 156b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 157b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 158b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 159b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 160b8e80941Smrg 161b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 162b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 163b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 164b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 165b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 166b8e80941Smrg#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 167b8e80941Smrg 168b8e80941Smrg#define CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 169b8e80941Smrg#define CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 170b8e80941Smrg#define CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 171b8e80941Smrg#define CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 172b8e80941Smrg 173b8e80941Smrg/* cl_device_info */ 174b8e80941Smrg#define CL_DEVICE_ME_VERSION_INTEL 0x407E 175b8e80941Smrg 176b8e80941Smrg#define CL_ME_VERSION_LEGACY_INTEL 0x0 177b8e80941Smrg#define CL_ME_VERSION_ADVANCED_VER_1_INTEL 0x1 178b8e80941Smrg#define CL_ME_VERSION_ADVANCED_VER_2_INTEL 0x2 179b8e80941Smrg 180b8e80941Smrgextern CL_API_ENTRY cl_accelerator_intel CL_API_CALL 181b8e80941SmrgclCreateAcceleratorINTEL( 182b8e80941Smrg cl_context context, 183b8e80941Smrg cl_accelerator_type_intel accelerator_type, 184b8e80941Smrg size_t descriptor_size, 185b8e80941Smrg const void* descriptor, 186b8e80941Smrg cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; 187b8e80941Smrg 188b8e80941Smrgtypedef CL_API_ENTRY cl_accelerator_intel (CL_API_CALL *clCreateAcceleratorINTEL_fn)( 189b8e80941Smrg cl_context context, 190b8e80941Smrg cl_accelerator_type_intel accelerator_type, 191b8e80941Smrg size_t descriptor_size, 192b8e80941Smrg const void* descriptor, 193b8e80941Smrg cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; 194b8e80941Smrg 195b8e80941Smrgextern CL_API_ENTRY cl_int CL_API_CALL 196b8e80941SmrgclGetAcceleratorInfoINTEL( 197b8e80941Smrg cl_accelerator_intel accelerator, 198b8e80941Smrg cl_accelerator_info_intel param_name, 199b8e80941Smrg size_t param_value_size, 200b8e80941Smrg void* param_value, 201b8e80941Smrg size_t* param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2; 202b8e80941Smrg 203b8e80941Smrgtypedef CL_API_ENTRY cl_int (CL_API_CALL *clGetAcceleratorInfoINTEL_fn)( 204b8e80941Smrg cl_accelerator_intel accelerator, 205b8e80941Smrg cl_accelerator_info_intel param_name, 206b8e80941Smrg size_t param_value_size, 207b8e80941Smrg void* param_value, 208b8e80941Smrg size_t* param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2; 209b8e80941Smrg 210b8e80941Smrgextern CL_API_ENTRY cl_int CL_API_CALL 211b8e80941SmrgclRetainAcceleratorINTEL( 212b8e80941Smrg cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; 213b8e80941Smrg 214b8e80941Smrgtypedef CL_API_ENTRY cl_int (CL_API_CALL *clRetainAcceleratorINTEL_fn)( 215b8e80941Smrg cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; 216b8e80941Smrg 217b8e80941Smrgextern CL_API_ENTRY cl_int CL_API_CALL 218b8e80941SmrgclReleaseAcceleratorINTEL( 219b8e80941Smrg cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; 220b8e80941Smrg 221b8e80941Smrgtypedef CL_API_ENTRY cl_int (CL_API_CALL *clReleaseAcceleratorINTEL_fn)( 222b8e80941Smrg cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; 223b8e80941Smrg 224b8e80941Smrg/****************************************** 225b8e80941Smrg* cl_intel_simultaneous_sharing extension * 226b8e80941Smrg*******************************************/ 227b8e80941Smrg 228b8e80941Smrg#define cl_intel_simultaneous_sharing 1 229b8e80941Smrg 230b8e80941Smrg#define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL 0x4104 231b8e80941Smrg#define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL 0x4105 232b8e80941Smrg 233b8e80941Smrg/*********************************** 234b8e80941Smrg* cl_intel_egl_image_yuv extension * 235b8e80941Smrg************************************/ 236b8e80941Smrg 237b8e80941Smrg#define cl_intel_egl_image_yuv 1 238b8e80941Smrg 239b8e80941Smrg#define CL_EGL_YUV_PLANE_INTEL 0x4107 240b8e80941Smrg 241b8e80941Smrg/******************************** 242b8e80941Smrg* cl_intel_packed_yuv extension * 243b8e80941Smrg*********************************/ 244b8e80941Smrg 245b8e80941Smrg#define cl_intel_packed_yuv 1 246b8e80941Smrg 247b8e80941Smrg#define CL_YUYV_INTEL 0x4076 248b8e80941Smrg#define CL_UYVY_INTEL 0x4077 249b8e80941Smrg#define CL_YVYU_INTEL 0x4078 250b8e80941Smrg#define CL_VYUY_INTEL 0x4079 251b8e80941Smrg 252b8e80941Smrg/******************************************** 253b8e80941Smrg* cl_intel_required_subgroup_size extension * 254b8e80941Smrg*********************************************/ 255b8e80941Smrg 256b8e80941Smrg#define cl_intel_required_subgroup_size 1 257b8e80941Smrg 258b8e80941Smrg#define CL_DEVICE_SUB_GROUP_SIZES_INTEL 0x4108 259b8e80941Smrg#define CL_KERNEL_SPILL_MEM_SIZE_INTEL 0x4109 260b8e80941Smrg#define CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL 0x410A 261b8e80941Smrg 262b8e80941Smrg/**************************************** 263b8e80941Smrg* cl_intel_driver_diagnostics extension * 264b8e80941Smrg*****************************************/ 265b8e80941Smrg 266b8e80941Smrg#define cl_intel_driver_diagnostics 1 267b8e80941Smrg 268b8e80941Smrgtypedef cl_uint cl_diagnostics_verbose_level; 269b8e80941Smrg 270b8e80941Smrg#define CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL 0x4106 271b8e80941Smrg 272b8e80941Smrg#define CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL ( 0xff ) 273b8e80941Smrg#define CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL ( 1 ) 274b8e80941Smrg#define CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL ( 1 << 1 ) 275b8e80941Smrg#define CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL ( 1 << 2 ) 276b8e80941Smrg 277b8e80941Smrg/******************************** 278b8e80941Smrg* cl_intel_planar_yuv extension * 279b8e80941Smrg*********************************/ 280b8e80941Smrg 281b8e80941Smrg#define CL_NV12_INTEL 0x410E 282b8e80941Smrg 283b8e80941Smrg#define CL_MEM_NO_ACCESS_INTEL ( 1 << 24 ) 284b8e80941Smrg#define CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL ( 1 << 25 ) 285b8e80941Smrg 286b8e80941Smrg#define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL 0x417E 287b8e80941Smrg#define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL 0x417F 288b8e80941Smrg 289b8e80941Smrg/******************************************************* 290b8e80941Smrg* cl_intel_device_side_avc_motion_estimation extension * 291b8e80941Smrg********************************************************/ 292b8e80941Smrg 293b8e80941Smrg#define CL_DEVICE_AVC_ME_VERSION_INTEL 0x410B 294b8e80941Smrg#define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL 0x410C 295b8e80941Smrg#define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL 0x410D 296b8e80941Smrg 297b8e80941Smrg#define CL_AVC_ME_VERSION_0_INTEL 0x0; // No support. 298b8e80941Smrg#define CL_AVC_ME_VERSION_1_INTEL 0x1; // First supported version. 299b8e80941Smrg 300b8e80941Smrg#define CL_AVC_ME_MAJOR_16x16_INTEL 0x0 301b8e80941Smrg#define CL_AVC_ME_MAJOR_16x8_INTEL 0x1 302b8e80941Smrg#define CL_AVC_ME_MAJOR_8x16_INTEL 0x2 303b8e80941Smrg#define CL_AVC_ME_MAJOR_8x8_INTEL 0x3 304b8e80941Smrg 305b8e80941Smrg#define CL_AVC_ME_MINOR_8x8_INTEL 0x0 306b8e80941Smrg#define CL_AVC_ME_MINOR_8x4_INTEL 0x1 307b8e80941Smrg#define CL_AVC_ME_MINOR_4x8_INTEL 0x2 308b8e80941Smrg#define CL_AVC_ME_MINOR_4x4_INTEL 0x3 309b8e80941Smrg 310b8e80941Smrg#define CL_AVC_ME_MAJOR_FORWARD_INTEL 0x0 311b8e80941Smrg#define CL_AVC_ME_MAJOR_BACKWARD_INTEL 0x1 312b8e80941Smrg#define CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL 0x2 313b8e80941Smrg 314b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_ALL_INTEL 0x0 315b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_16x16_INTEL 0x7E 316b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_16x8_INTEL 0x7D 317b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_8x16_INTEL 0x7B 318b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_8x8_INTEL 0x77 319b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_8x4_INTEL 0x6F 320b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_4x8_INTEL 0x5F 321b8e80941Smrg#define CL_AVC_ME_PARTITION_MASK_4x4_INTEL 0x3F 322b8e80941Smrg 323b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL 0x0 324b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL 0x1 325b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL 0x2 326b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3 327b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL 0x4 328b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL 0x5 329b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL 0x6 330b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL 0x7 331b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL 0x8 332b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL 0x9 333b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL 0x2 334b8e80941Smrg#define CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL 0xa 335b8e80941Smrg 336b8e80941Smrg#define CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 337b8e80941Smrg#define CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x2 338b8e80941Smrg 339b8e80941Smrg#define CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 340b8e80941Smrg#define CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 341b8e80941Smrg#define CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3 342b8e80941Smrg 343b8e80941Smrg#define CL_AVC_ME_COST_PRECISION_QPEL_INTEL 0x0 344b8e80941Smrg#define CL_AVC_ME_COST_PRECISION_HPEL_INTEL 0x1 345b8e80941Smrg#define CL_AVC_ME_COST_PRECISION_PEL_INTEL 0x2 346b8e80941Smrg#define CL_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3 347b8e80941Smrg 348b8e80941Smrg#define CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL 0x10 349b8e80941Smrg#define CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL 0x15 350b8e80941Smrg#define CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL 0x20 351b8e80941Smrg#define CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 0x2B 352b8e80941Smrg#define CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 0x30 353b8e80941Smrg 354b8e80941Smrg#define CL_AVC_ME_BORDER_REACHED_LEFT_INTEL 0x0 355b8e80941Smrg#define CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL 0x2 356b8e80941Smrg#define CL_AVC_ME_BORDER_REACHED_TOP_INTEL 0x4 357b8e80941Smrg#define CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL 0x8 358b8e80941Smrg 359b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL 0x0 360b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL 0x4000 361b8e80941Smrg 362b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) 363b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) 364b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL ( 0x3 << 24 ) 365b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL ( 0x55 << 24 ) 366b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL ( 0xAA << 24 ) 367b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL ( 0xFF << 24 ) 368b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) 369b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) 370b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL ( 0x1 << 26 ) 371b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL ( 0x2 << 26 ) 372b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL ( 0x1 << 28 ) 373b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL ( 0x2 << 28 ) 374b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL ( 0x1 << 30 ) 375b8e80941Smrg#define CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL ( 0x2 << 30 ) 376b8e80941Smrg 377b8e80941Smrg#define CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL 0x00 378b8e80941Smrg#define CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL 0x80 379b8e80941Smrg 380b8e80941Smrg#define CL_AVC_ME_INTRA_16x16_INTEL 0x0 381b8e80941Smrg#define CL_AVC_ME_INTRA_8x8_INTEL 0x1 382b8e80941Smrg#define CL_AVC_ME_INTRA_4x4_INTEL 0x2 383b8e80941Smrg 384b8e80941Smrg#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL 0x6 385b8e80941Smrg#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL 0x5 386b8e80941Smrg#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3 387b8e80941Smrg 388b8e80941Smrg#define CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL 0x60 389b8e80941Smrg#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL 0x10 390b8e80941Smrg#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL 0x8 391b8e80941Smrg#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL 0x4 392b8e80941Smrg 393b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 394b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 395b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 396b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 397b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 398b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 399b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 400b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 401b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 402b8e80941Smrg#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 403b8e80941Smrg#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 404b8e80941Smrg#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 405b8e80941Smrg#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 406b8e80941Smrg#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 407b8e80941Smrg 408b8e80941Smrg#define CL_AVC_ME_FRAME_FORWARD_INTEL 0x1 409b8e80941Smrg#define CL_AVC_ME_FRAME_BACKWARD_INTEL 0x2 410b8e80941Smrg#define CL_AVC_ME_FRAME_DUAL_INTEL 0x3 411b8e80941Smrg 412b8e80941Smrg#define CL_AVC_ME_SLICE_TYPE_PRED_INTEL 0x0 413b8e80941Smrg#define CL_AVC_ME_SLICE_TYPE_BPRED_INTEL 0x1 414b8e80941Smrg#define CL_AVC_ME_SLICE_TYPE_INTRA_INTEL 0x2 415b8e80941Smrg 416b8e80941Smrg#define CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL 0x0 417b8e80941Smrg#define CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL 0x1 418b8e80941Smrg 419b8e80941Smrg#ifdef __cplusplus 420b8e80941Smrg} 421b8e80941Smrg#endif 422b8e80941Smrg 423b8e80941Smrg#endif /* __CL_EXT_INTEL_H */ 424