radv_debug.c revision b8e80941
1/* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 25 * IN THE SOFTWARE. 26 */ 27 28#include <stdlib.h> 29#include <stdio.h> 30#include <sys/utsname.h> 31 32#include "util/mesa-sha1.h" 33#include "sid.h" 34#include "gfx9d.h" 35#include "ac_debug.h" 36#include "radv_debug.h" 37#include "radv_shader.h" 38 39#define TRACE_BO_SIZE 4096 40 41#define COLOR_RESET "\033[0m" 42#define COLOR_RED "\033[31m" 43#define COLOR_GREEN "\033[1;32m" 44#define COLOR_YELLOW "\033[1;33m" 45#define COLOR_CYAN "\033[1;36m" 46 47/* Trace BO layout (offsets are 4 bytes): 48 * 49 * [0]: primary trace ID 50 * [1]: secondary trace ID 51 * [2-3]: 64-bit GFX pipeline pointer 52 * [4-5]: 64-bit COMPUTE pipeline pointer 53 * [6-7]: 64-bit descriptor set #0 pointer 54 * ... 55 * [68-69]: 64-bit descriptor set #31 pointer 56 */ 57 58bool 59radv_init_trace(struct radv_device *device) 60{ 61 struct radeon_winsys *ws = device->ws; 62 63 device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8, 64 RADEON_DOMAIN_VRAM, 65 RADEON_FLAG_CPU_ACCESS| 66 RADEON_FLAG_NO_INTERPROCESS_SHARING, 67 RADV_BO_PRIORITY_UPLOAD_BUFFER); 68 if (!device->trace_bo) 69 return false; 70 71 device->trace_id_ptr = ws->buffer_map(device->trace_bo); 72 if (!device->trace_id_ptr) 73 return false; 74 75 memset(device->trace_id_ptr, 0, TRACE_BO_SIZE); 76 77 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, 78 &device->dmesg_timestamp, NULL); 79 80 return true; 81} 82 83static void 84radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs) 85{ 86 const char *filename = getenv("RADV_TRACE_FILE"); 87 FILE *f = fopen(filename, "w"); 88 89 if (!f) { 90 fprintf(stderr, "Failed to write trace dump to %s\n", filename); 91 return; 92 } 93 94 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr); 95 device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2); 96 fclose(f); 97} 98 99static void 100radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset) 101{ 102 struct radeon_winsys *ws = device->ws; 103 uint32_t value; 104 105 if (ws->read_registers(ws, offset, 1, &value)) 106 ac_dump_reg(f, device->physical_device->rad_info.chip_class, 107 offset, value, ~0); 108} 109 110static void 111radv_dump_debug_registers(struct radv_device *device, FILE *f) 112{ 113 struct radeon_info *info = &device->physical_device->rad_info; 114 115 if (info->drm_major == 2 && info->drm_minor < 42) 116 return; /* no radeon support */ 117 118 fprintf(f, "Memory-mapped registers:\n"); 119 radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS); 120 121 /* No other registers can be read on DRM < 3.1.0. */ 122 if (info->drm_major < 3 || info->drm_minor < 1) { 123 fprintf(f, "\n"); 124 return; 125 } 126 127 radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2); 128 radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0); 129 radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1); 130 radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2); 131 radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3); 132 radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG); 133 radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG); 134 if (info->chip_class <= VI) { 135 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS); 136 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2); 137 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3); 138 } 139 radv_dump_mmapped_reg(device, f, R_008680_CP_STAT); 140 radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1); 141 radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2); 142 radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3); 143 radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS); 144 radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT); 145 radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1); 146 radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS); 147 radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT); 148 radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1); 149 fprintf(f, "\n"); 150} 151 152static const char * 153radv_get_descriptor_name(enum VkDescriptorType type) 154{ 155 switch (type) { 156 case VK_DESCRIPTOR_TYPE_SAMPLER: 157 return "SAMPLER"; 158 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: 159 return "COMBINED_IMAGE_SAMPLER"; 160 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: 161 return "SAMPLED_IMAGE"; 162 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: 163 return "STORAGE_IMAGE"; 164 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: 165 return "UNIFORM_TEXEL_BUFFER"; 166 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: 167 return "STORAGE_TEXEL_BUFFER"; 168 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: 169 return "UNIFORM_BUFFER"; 170 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: 171 return "STORAGE_BUFFER"; 172 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: 173 return "UNIFORM_BUFFER_DYNAMIC"; 174 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: 175 return "STORAGE_BUFFER_DYNAMIC"; 176 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: 177 return "INPUT_ATTACHMENT"; 178 default: 179 return "UNKNOWN"; 180 } 181} 182 183static void 184radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, 185 FILE *f) 186{ 187 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); 188 for (unsigned j = 0; j < 4; j++) 189 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, 190 desc[j], 0xffffffff); 191} 192 193static void 194radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, 195 FILE *f) 196{ 197 fprintf(f, COLOR_CYAN " Image:" COLOR_RESET "\n"); 198 for (unsigned j = 0; j < 8; j++) 199 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, 200 desc[j], 0xffffffff); 201 202 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n"); 203 for (unsigned j = 0; j < 8; j++) 204 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, 205 desc[8 + j], 0xffffffff); 206} 207 208static void 209radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, 210 FILE *f) 211{ 212 fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n"); 213 for (unsigned j = 0; j < 4; j++) { 214 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, 215 desc[j], 0xffffffff); 216 } 217} 218 219static void 220radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class, 221 const uint32_t *desc, FILE *f) 222{ 223 radv_dump_image_descriptor(chip_class, desc, f); 224 radv_dump_sampler_descriptor(chip_class, desc + 16, f); 225} 226 227static void 228radv_dump_descriptor_set(enum chip_class chip_class, 229 struct radv_descriptor_set *set, unsigned id, FILE *f) 230{ 231 const struct radv_descriptor_set_layout *layout; 232 int i; 233 234 if (!set) 235 return; 236 layout = set->layout; 237 238 fprintf(f, "** descriptor set (%d) **\n", id); 239 fprintf(f, "va: 0x%"PRIx64"\n", set->va); 240 fprintf(f, "size: %d\n", set->size); 241 fprintf(f, "mapped_ptr:\n"); 242 243 for (i = 0; i < set->size / 4; i++) { 244 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]); 245 } 246 fprintf(f, "\n"); 247 248 fprintf(f, "\t*** layout ***\n"); 249 fprintf(f, "\tbinding_count: %d\n", layout->binding_count); 250 fprintf(f, "\tsize: %d\n", layout->size); 251 fprintf(f, "\tshader_stages: %x\n", layout->shader_stages); 252 fprintf(f, "\tdynamic_shader_stages: %x\n", 253 layout->dynamic_shader_stages); 254 fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count); 255 fprintf(f, "\tdynamic_offset_count: %d\n", 256 layout->dynamic_offset_count); 257 fprintf(f, "\n"); 258 259 for (i = 0; i < set->layout->binding_count; i++) { 260 uint32_t *desc = 261 set->mapped_ptr + layout->binding[i].offset / 4; 262 263 fprintf(f, "\t\t**** binding layout (%d) ****\n", i); 264 fprintf(f, "\t\ttype: %s\n", 265 radv_get_descriptor_name(layout->binding[i].type)); 266 fprintf(f, "\t\tarray_size: %d\n", 267 layout->binding[i].array_size); 268 fprintf(f, "\t\toffset: %d\n", 269 layout->binding[i].offset); 270 fprintf(f, "\t\tbuffer_offset: %d\n", 271 layout->binding[i].buffer_offset); 272 fprintf(f, "\t\tdynamic_offset_offset: %d\n", 273 layout->binding[i].dynamic_offset_offset); 274 fprintf(f, "\t\tdynamic_offset_count: %d\n", 275 layout->binding[i].dynamic_offset_count); 276 fprintf(f, "\t\tsize: %d\n", 277 layout->binding[i].size); 278 fprintf(f, "\t\timmutable_samplers_offset: %d\n", 279 layout->binding[i].immutable_samplers_offset); 280 fprintf(f, "\t\timmutable_samplers_equal: %d\n", 281 layout->binding[i].immutable_samplers_equal); 282 fprintf(f, "\n"); 283 284 switch (layout->binding[i].type) { 285 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: 286 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: 287 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: 288 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: 289 radv_dump_buffer_descriptor(chip_class, desc, f); 290 break; 291 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: 292 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: 293 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: 294 radv_dump_image_descriptor(chip_class, desc, f); 295 break; 296 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: 297 radv_dump_combined_image_sampler_descriptor(chip_class, desc, f); 298 break; 299 case VK_DESCRIPTOR_TYPE_SAMPLER: 300 radv_dump_sampler_descriptor(chip_class, desc, f); 301 break; 302 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: 303 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: 304 /* todo */ 305 break; 306 default: 307 assert(!"unknown descriptor type"); 308 break; 309 } 310 fprintf(f, "\n"); 311 } 312 fprintf(f, "\n\n"); 313} 314 315static void 316radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f) 317{ 318 struct radv_device *device = pipeline->device; 319 enum chip_class chip_class = device->physical_device->rad_info.chip_class; 320 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 321 int i; 322 323 fprintf(f, "List of descriptors:\n"); 324 for (i = 0; i < MAX_SETS; i++) { 325 struct radv_descriptor_set *set = 326 (struct radv_descriptor_set *)ptr[i + 3]; 327 328 radv_dump_descriptor_set(chip_class, set, i, f); 329 } 330} 331 332struct radv_shader_inst { 333 char text[160]; /* one disasm line */ 334 unsigned offset; /* instruction offset */ 335 unsigned size; /* instruction size = 4 or 8 */ 336}; 337 338/* Split a disassembly string into lines and add them to the array pointed 339 * to by "instructions". */ 340static void si_add_split_disasm(const char *disasm, 341 uint64_t start_addr, 342 unsigned *num, 343 struct radv_shader_inst *instructions) 344{ 345 struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL; 346 char *next; 347 348 while ((next = strchr(disasm, '\n'))) { 349 struct radv_shader_inst *inst = &instructions[*num]; 350 unsigned len = next - disasm; 351 352 assert(len < ARRAY_SIZE(inst->text)); 353 memcpy(inst->text, disasm, len); 354 inst->text[len] = 0; 355 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0; 356 357 const char *semicolon = strchr(disasm, ';'); 358 assert(semicolon); 359 /* More than 16 chars after ";" means the instruction is 8 bytes long. */ 360 inst->size = next - semicolon > 16 ? 8 : 4; 361 362 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len, 363 " [PC=0x%"PRIx64", off=%u, size=%u]", 364 start_addr + inst->offset, inst->offset, inst->size); 365 366 last_inst = inst; 367 (*num)++; 368 disasm = next + 1; 369 } 370} 371 372static void 373radv_dump_annotated_shader(struct radv_shader_variant *shader, 374 gl_shader_stage stage, struct ac_wave_info *waves, 375 unsigned num_waves, FILE *f) 376{ 377 uint64_t start_addr, end_addr; 378 unsigned i; 379 380 if (!shader) 381 return; 382 383 start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset; 384 end_addr = start_addr + shader->code_size; 385 386 /* See if any wave executes the shader. */ 387 for (i = 0; i < num_waves; i++) { 388 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr) 389 break; 390 } 391 392 if (i == num_waves) 393 return; /* the shader is not being executed */ 394 395 /* Remember the first found wave. The waves are sorted according to PC. */ 396 waves = &waves[i]; 397 num_waves -= i; 398 399 /* Get the list of instructions. 400 * Buffer size / 4 is the upper bound of the instruction count. 401 */ 402 unsigned num_inst = 0; 403 struct radv_shader_inst *instructions = 404 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst)); 405 406 si_add_split_disasm(shader->disasm_string, 407 start_addr, &num_inst, instructions); 408 409 fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n", 410 radv_get_shader_name(shader, stage)); 411 412 /* Print instructions with annotations. */ 413 for (i = 0; i < num_inst; i++) { 414 struct radv_shader_inst *inst = &instructions[i]; 415 416 fprintf(f, "%s\n", inst->text); 417 418 /* Print which waves execute the instruction right now. */ 419 while (num_waves && start_addr + inst->offset == waves->pc) { 420 fprintf(f, 421 " " COLOR_GREEN "^ SE%u SH%u CU%u " 422 "SIMD%u WAVE%u EXEC=%016"PRIx64 " ", 423 waves->se, waves->sh, waves->cu, waves->simd, 424 waves->wave, waves->exec); 425 426 if (inst->size == 4) { 427 fprintf(f, "INST32=%08X" COLOR_RESET "\n", 428 waves->inst_dw0); 429 } else { 430 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n", 431 waves->inst_dw0, waves->inst_dw1); 432 } 433 434 waves->matched = true; 435 waves = &waves[1]; 436 num_waves--; 437 } 438 } 439 440 fprintf(f, "\n\n"); 441 free(instructions); 442} 443 444static void 445radv_dump_annotated_shaders(struct radv_pipeline *pipeline, 446 VkShaderStageFlagBits active_stages, FILE *f) 447{ 448 struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]; 449 unsigned num_waves = ac_get_wave_info(waves); 450 451 fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET 452 "\n\n", num_waves); 453 454 /* Dump annotated active graphics shaders. */ 455 while (active_stages) { 456 int stage = u_bit_scan(&active_stages); 457 458 radv_dump_annotated_shader(pipeline->shaders[stage], 459 stage, waves, num_waves, f); 460 } 461 462 /* Print waves executing shaders that are not currently bound. */ 463 unsigned i; 464 bool found = false; 465 for (i = 0; i < num_waves; i++) { 466 if (waves[i].matched) 467 continue; 468 469 if (!found) { 470 fprintf(f, COLOR_CYAN 471 "Waves not executing currently-bound shaders:" 472 COLOR_RESET "\n"); 473 found = true; 474 } 475 fprintf(f, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64 476 " INST=%08X %08X PC=%"PRIx64"\n", 477 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, 478 waves[i].wave, waves[i].exec, waves[i].inst_dw0, 479 waves[i].inst_dw1, waves[i].pc); 480 } 481 if (found) 482 fprintf(f, "\n\n"); 483} 484 485static void 486radv_dump_shader(struct radv_pipeline *pipeline, 487 struct radv_shader_variant *shader, gl_shader_stage stage, 488 FILE *f) 489{ 490 if (!shader) 491 return; 492 493 fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage)); 494 495 if (shader->spirv) { 496 unsigned char sha1[21]; 497 char sha1buf[41]; 498 499 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1); 500 _mesa_sha1_format(sha1buf, sha1); 501 502 fprintf(f, "SPIRV (sha1: %s):\n", sha1buf); 503 radv_print_spirv(shader->spirv, shader->spirv_size, f); 504 } 505 506 if (shader->nir) { 507 fprintf(f, "NIR:\n"); 508 nir_print_shader(shader->nir, f); 509 } 510 511 fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string); 512 fprintf(f, "DISASM:\n%s\n", shader->disasm_string); 513 514 radv_shader_dump_stats(pipeline->device, shader, stage, f); 515} 516 517static void 518radv_dump_shaders(struct radv_pipeline *pipeline, 519 VkShaderStageFlagBits active_stages, FILE *f) 520{ 521 /* Dump active graphics shaders. */ 522 while (active_stages) { 523 int stage = u_bit_scan(&active_stages); 524 525 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f); 526 } 527} 528 529static void 530radv_dump_pipeline_state(struct radv_pipeline *pipeline, 531 VkShaderStageFlagBits active_stages, FILE *f) 532{ 533 radv_dump_shaders(pipeline, active_stages, f); 534 radv_dump_annotated_shaders(pipeline, active_stages, f); 535 radv_dump_descriptors(pipeline, f); 536} 537 538static void 539radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline, 540 struct radv_pipeline *compute_pipeline, FILE *f) 541{ 542 VkShaderStageFlagBits active_stages; 543 544 if (graphics_pipeline) { 545 active_stages = graphics_pipeline->active_stages; 546 radv_dump_pipeline_state(graphics_pipeline, active_stages, f); 547 } 548 549 if (compute_pipeline) { 550 active_stages = VK_SHADER_STAGE_COMPUTE_BIT; 551 radv_dump_pipeline_state(compute_pipeline, active_stages, f); 552 } 553} 554 555static void 556radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f) 557{ 558 VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT; 559 560 if (!compute_pipeline) 561 return; 562 563 radv_dump_pipeline_state(compute_pipeline, active_stages, f); 564} 565 566static struct radv_pipeline * 567radv_get_saved_graphics_pipeline(struct radv_device *device) 568{ 569 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 570 571 return (struct radv_pipeline *)ptr[1]; 572} 573 574static struct radv_pipeline * 575radv_get_saved_compute_pipeline(struct radv_device *device) 576{ 577 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 578 579 return (struct radv_pipeline *)ptr[2]; 580} 581 582static void 583radv_dump_dmesg(FILE *f) 584{ 585 char line[2000]; 586 FILE *p; 587 588 p = popen("dmesg | tail -n60", "r"); 589 if (!p) 590 return; 591 592 fprintf(f, "\nLast 60 lines of dmesg:\n\n"); 593 while (fgets(line, sizeof(line), p)) 594 fputs(line, f); 595 fprintf(f, "\n"); 596 597 pclose(p); 598} 599 600void 601radv_dump_enabled_options(struct radv_device *device, FILE *f) 602{ 603 uint64_t mask; 604 605 if (device->instance->debug_flags) { 606 fprintf(f, "Enabled debug options: "); 607 608 mask = device->instance->debug_flags; 609 while (mask) { 610 int i = u_bit_scan64(&mask); 611 fprintf(f, "%s, ", radv_get_debug_option_name(i)); 612 } 613 fprintf(f, "\n"); 614 } 615 616 if (device->instance->perftest_flags) { 617 fprintf(f, "Enabled perftest options: "); 618 619 mask = device->instance->perftest_flags; 620 while (mask) { 621 int i = u_bit_scan64(&mask); 622 fprintf(f, "%s, ", radv_get_perftest_option_name(i)); 623 } 624 fprintf(f, "\n"); 625 } 626} 627 628static void 629radv_dump_device_name(struct radv_device *device, FILE *f) 630{ 631 struct radeon_info *info = &device->physical_device->rad_info; 632 char kernel_version[128] = {}; 633 struct utsname uname_data; 634 const char *chip_name; 635 636 chip_name = device->ws->get_chip_name(device->ws); 637 638 if (uname(&uname_data) == 0) 639 snprintf(kernel_version, sizeof(kernel_version), 640 " / %s", uname_data.release); 641 642 fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM " 643 MESA_LLVM_VERSION_STRING ")\n\n", 644 chip_name, device->physical_device->name, 645 info->drm_major, info->drm_minor, info->drm_patchlevel, 646 kernel_version); 647} 648 649static bool 650radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring) 651{ 652 struct radeon_winsys *ws = queue->device->ws; 653 654 if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx)) 655 return true; 656 657 return false; 658} 659 660void 661radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs) 662{ 663 struct radv_pipeline *graphics_pipeline, *compute_pipeline; 664 struct radv_device *device = queue->device; 665 enum ring_type ring; 666 uint64_t addr; 667 668 ring = radv_queue_family_to_ring(queue->queue_family_index); 669 670 bool hang_occurred = radv_gpu_hang_occured(queue, ring); 671 bool vm_fault_occurred = false; 672 if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS) 673 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class, 674 &device->dmesg_timestamp, &addr); 675 if (!hang_occurred && !vm_fault_occurred) 676 return; 677 678 graphics_pipeline = radv_get_saved_graphics_pipeline(device); 679 compute_pipeline = radv_get_saved_compute_pipeline(device); 680 681 fprintf(stderr, "GPU hang report:\n\n"); 682 radv_dump_device_name(device, stderr); 683 684 radv_dump_enabled_options(device, stderr); 685 radv_dump_dmesg(stderr); 686 687 if (vm_fault_occurred) { 688 fprintf(stderr, "VM fault report.\n\n"); 689 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr); 690 } 691 692 radv_dump_debug_registers(device, stderr); 693 694 switch (ring) { 695 case RING_GFX: 696 radv_dump_graphics_state(graphics_pipeline, compute_pipeline, 697 stderr); 698 break; 699 case RING_COMPUTE: 700 radv_dump_compute_state(compute_pipeline, stderr); 701 break; 702 default: 703 assert(0); 704 break; 705 } 706 707 radv_dump_trace(queue->device, cs); 708 abort(); 709} 710 711void 712radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp) 713{ 714 char path[] = "/tmp/fileXXXXXX"; 715 char line[2048], command[128]; 716 FILE *p; 717 int fd; 718 719 /* Dump the binary into a temporary file. */ 720 fd = mkstemp(path); 721 if (fd < 0) 722 return; 723 724 if (write(fd, data, size) == -1) 725 goto fail; 726 727 sprintf(command, "spirv-dis %s", path); 728 729 /* Disassemble using spirv-dis if installed. */ 730 p = popen(command, "r"); 731 if (p) { 732 while (fgets(line, sizeof(line), p)) 733 fprintf(fp, "%s", line); 734 pclose(p); 735 } 736 737fail: 738 close(fd); 739 unlink(path); 740} 741