1b8e80941Smrg/*
2b8e80941Smrg * Copyright (c) 2012-2015 Etnaviv Project
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sub license,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the
12b8e80941Smrg * next paragraph) shall be included in all copies or substantial portions
13b8e80941Smrg * of the Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21b8e80941Smrg * DEALINGS IN THE SOFTWARE.
22b8e80941Smrg *
23b8e80941Smrg * Authors:
24b8e80941Smrg *    Wladimir J. van der Laan <laanwj@gmail.com>
25b8e80941Smrg */
26b8e80941Smrg
27b8e80941Smrg#ifndef H_ETNAVIV_RESOURCE
28b8e80941Smrg#define H_ETNAVIV_RESOURCE
29b8e80941Smrg
30b8e80941Smrg#include "etnaviv_internal.h"
31b8e80941Smrg#include "etnaviv_tiling.h"
32b8e80941Smrg#include "pipe/p_state.h"
33b8e80941Smrg#include "util/list.h"
34b8e80941Smrg#include "util/set.h"
35b8e80941Smrg#include "util/u_helpers.h"
36b8e80941Smrg
37b8e80941Smrgstruct etna_context;
38b8e80941Smrgstruct pipe_screen;
39b8e80941Smrgstruct util_dynarray;
40b8e80941Smrg
41b8e80941Smrgstruct etna_resource_level {
42b8e80941Smrg   unsigned width, padded_width; /* in pixels */
43b8e80941Smrg   unsigned height, padded_height; /* in samples */
44b8e80941Smrg   unsigned offset; /* offset into memory area */
45b8e80941Smrg   uint32_t stride; /* row stride */
46b8e80941Smrg   uint32_t layer_stride; /* layer stride */
47b8e80941Smrg   unsigned size; /* total size of memory area */
48b8e80941Smrg
49b8e80941Smrg   uint32_t ts_offset;
50b8e80941Smrg   uint32_t ts_layer_stride;
51b8e80941Smrg   uint32_t ts_size;
52b8e80941Smrg   uint32_t clear_value; /* clear value of resource level (mainly for TS) */
53b8e80941Smrg   bool ts_valid;
54b8e80941Smrg
55b8e80941Smrg   /* keep track if we have done some per block patching */
56b8e80941Smrg   bool patched;
57b8e80941Smrg   struct util_dynarray *patch_offsets;
58b8e80941Smrg};
59b8e80941Smrg
60b8e80941Smrgenum etna_resource_addressing_mode {
61b8e80941Smrg   ETNA_ADDRESSING_MODE_TILED = 0,
62b8e80941Smrg   ETNA_ADDRESSING_MODE_LINEAR,
63b8e80941Smrg};
64b8e80941Smrg
65b8e80941Smrg/* status of queued up but not flushed reads and write operations.
66b8e80941Smrg * In _transfer_map() we need to know if queued up rendering needs
67b8e80941Smrg * to be flushed to preserve the order of cpu and gpu access. */
68b8e80941Smrgenum etna_resource_status {
69b8e80941Smrg   ETNA_PENDING_WRITE = 0x01,
70b8e80941Smrg   ETNA_PENDING_READ = 0x02,
71b8e80941Smrg};
72b8e80941Smrg
73b8e80941Smrgstruct etna_resource {
74b8e80941Smrg   struct pipe_resource base;
75b8e80941Smrg   struct renderonly_scanout *scanout;
76b8e80941Smrg   uint32_t seqno;
77b8e80941Smrg   uint32_t flush_seqno;
78b8e80941Smrg
79b8e80941Smrg   /* only lod 0 used for non-texture buffers */
80b8e80941Smrg   /* Layout for surface (tiled, multitiled, split tiled, ...) */
81b8e80941Smrg   enum etna_surface_layout layout;
82b8e80941Smrg   enum etna_resource_addressing_mode addressing_mode;
83b8e80941Smrg   /* Horizontal alignment for texture unit (TEXTURE_HALIGN_*) */
84b8e80941Smrg   unsigned halign;
85b8e80941Smrg   struct etna_bo *bo; /* Surface video memory */
86b8e80941Smrg   struct etna_bo *ts_bo; /* Tile status video memory */
87b8e80941Smrg
88b8e80941Smrg   struct etna_resource_level levels[ETNA_NUM_LOD];
89b8e80941Smrg
90b8e80941Smrg   /* When we are rendering to a texture, we need a differently tiled resource */
91b8e80941Smrg   struct pipe_resource *texture;
92b8e80941Smrg   /*
93b8e80941Smrg    * If imported resources have an render/sampler incompatible tiling, we keep
94b8e80941Smrg    * them as an external resource, which is blitted as needed.
95b8e80941Smrg    */
96b8e80941Smrg   struct pipe_resource *external;
97b8e80941Smrg
98b8e80941Smrg   enum etna_resource_status status;
99b8e80941Smrg
100b8e80941Smrg   struct set *pending_ctx;
101b8e80941Smrg};
102b8e80941Smrg
103b8e80941Smrg/* returns TRUE if a is newer than b */
104b8e80941Smrgstatic inline bool
105b8e80941Smrgetna_resource_newer(struct etna_resource *a, struct etna_resource *b)
106b8e80941Smrg{
107b8e80941Smrg   return (int)(a->seqno - b->seqno) > 0;
108b8e80941Smrg}
109b8e80941Smrg
110b8e80941Smrg/* returns TRUE if a is older than b */
111b8e80941Smrgstatic inline bool
112b8e80941Smrgetna_resource_older(struct etna_resource *a, struct etna_resource *b)
113b8e80941Smrg{
114b8e80941Smrg   return (int)(a->seqno - b->seqno) < 0;
115b8e80941Smrg}
116b8e80941Smrg
117b8e80941Smrg/* returns TRUE if a resource has a TS, and it is valid for at least one level */
118b8e80941Smrgbool
119b8e80941Smrgetna_resource_has_valid_ts(struct etna_resource *res);
120b8e80941Smrg
121b8e80941Smrg/* returns TRUE if the resource needs a resolve to itself */
122b8e80941Smrgstatic inline bool
123b8e80941Smrgetna_resource_needs_flush(struct etna_resource *res)
124b8e80941Smrg{
125b8e80941Smrg   return etna_resource_has_valid_ts(res) && ((int)(res->seqno - res->flush_seqno) > 0);
126b8e80941Smrg}
127b8e80941Smrg
128b8e80941Smrg/* is the resource only used on the sampler? */
129b8e80941Smrgstatic inline bool
130b8e80941Smrgetna_resource_sampler_only(const struct pipe_resource *pres)
131b8e80941Smrg{
132b8e80941Smrg   return (pres->bind & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET |
133b8e80941Smrg                         PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_BLENDABLE)) ==
134b8e80941Smrg          PIPE_BIND_SAMPLER_VIEW;
135b8e80941Smrg}
136b8e80941Smrg
137b8e80941Smrgstatic inline struct etna_resource *
138b8e80941Smrgetna_resource(struct pipe_resource *p)
139b8e80941Smrg{
140b8e80941Smrg   return (struct etna_resource *)p;
141b8e80941Smrg}
142b8e80941Smrg
143b8e80941Smrgvoid
144b8e80941Smrgetna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc,
145b8e80941Smrg                   enum etna_resource_status status);
146b8e80941Smrg
147b8e80941Smrgstatic inline void
148b8e80941Smrgresource_read(struct etna_context *ctx, struct pipe_resource *prsc)
149b8e80941Smrg{
150b8e80941Smrg   etna_resource_used(ctx, prsc, ETNA_PENDING_READ);
151b8e80941Smrg}
152b8e80941Smrg
153b8e80941Smrgstatic inline void
154b8e80941Smrgresource_written(struct etna_context *ctx, struct pipe_resource *prsc)
155b8e80941Smrg{
156b8e80941Smrg   etna_resource_used(ctx, prsc, ETNA_PENDING_WRITE);
157b8e80941Smrg}
158b8e80941Smrg
159b8e80941Smrg/* Allocate Tile Status for an etna resource.
160b8e80941Smrg * Tile status is a cache of the clear status per tile. This means a smaller
161b8e80941Smrg * surface has to be cleared which is faster.
162b8e80941Smrg * This is also called "fast clear". */
163b8e80941Smrgbool
164b8e80941Smrgetna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
165b8e80941Smrg                              struct etna_resource *prsc);
166b8e80941Smrg
167b8e80941Smrgstruct pipe_resource *
168b8e80941Smrgetna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
169b8e80941Smrg                    enum etna_resource_addressing_mode mode, uint64_t modifier,
170b8e80941Smrg                    const struct pipe_resource *templat);
171b8e80941Smrg
172b8e80941Smrgvoid
173b8e80941Smrgetna_resource_screen_init(struct pipe_screen *pscreen);
174b8e80941Smrg
175b8e80941Smrg#endif
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