etnaviv_screen.c revision b8e80941
1/* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 * Christian Gmeiner <christian.gmeiner@gmail.com> 26 */ 27 28#include "etnaviv_screen.h" 29 30#include "hw/common.xml.h" 31 32#include "etnaviv_compiler.h" 33#include "etnaviv_context.h" 34#include "etnaviv_debug.h" 35#include "etnaviv_fence.h" 36#include "etnaviv_format.h" 37#include "etnaviv_query.h" 38#include "etnaviv_resource.h" 39#include "etnaviv_translate.h" 40 41#include "util/hash_table.h" 42#include "util/os_time.h" 43#include "util/u_math.h" 44#include "util/u_memory.h" 45#include "util/u_screen.h" 46#include "util/u_string.h" 47 48#include "state_tracker/drm_driver.h" 49 50#include "drm-uapi/drm_fourcc.h" 51 52#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor)) 53#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) 54#define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2) 55 56static const struct debug_named_value debug_options[] = { 57 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, 58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, 59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"}, 60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"}, 61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"}, 62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"}, 63 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"}, 64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"}, 65 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"}, 66 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"}, 67 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"}, 68 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"}, 69 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"}, 70 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, 71 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, 72 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, 73 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, 74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"}, 75 DEBUG_NAMED_VALUE_END 76}; 77 78DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0) 79int etna_mesa_debug = 0; 80 81static void 82etna_screen_destroy(struct pipe_screen *pscreen) 83{ 84 struct etna_screen *screen = etna_screen(pscreen); 85 86 _mesa_set_destroy(screen->used_resources, NULL); 87 mtx_destroy(&screen->lock); 88 89 if (screen->perfmon) 90 etna_perfmon_del(screen->perfmon); 91 92 if (screen->pipe) 93 etna_pipe_del(screen->pipe); 94 95 if (screen->gpu) 96 etna_gpu_del(screen->gpu); 97 98 if (screen->ro) 99 FREE(screen->ro); 100 101 if (screen->dev) 102 etna_device_del(screen->dev); 103 104 FREE(screen); 105} 106 107static const char * 108etna_screen_get_name(struct pipe_screen *pscreen) 109{ 110 struct etna_screen *priv = etna_screen(pscreen); 111 static char buffer[128]; 112 113 util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model, 114 priv->revision); 115 116 return buffer; 117} 118 119static const char * 120etna_screen_get_vendor(struct pipe_screen *pscreen) 121{ 122 return "etnaviv"; 123} 124 125static const char * 126etna_screen_get_device_vendor(struct pipe_screen *pscreen) 127{ 128 return "Vivante"; 129} 130 131static int 132etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 133{ 134 struct etna_screen *screen = etna_screen(pscreen); 135 136 switch (param) { 137 /* Supported features (boolean caps). */ 138 case PIPE_CAP_ANISOTROPIC_FILTER: 139 case PIPE_CAP_POINT_SPRITE: 140 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 141 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 142 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 143 case PIPE_CAP_SM3: 144 case PIPE_CAP_TEXTURE_BARRIER: 145 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 146 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 147 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 148 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 149 case PIPE_CAP_TGSI_TEXCOORD: 150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 151 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 152 return 1; 153 case PIPE_CAP_NATIVE_FENCE_FD: 154 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; 155 156 /* Memory */ 157 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 158 return 256; 159 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 160 return 4; /* XXX could easily be supported */ 161 case PIPE_CAP_GLSL_FEATURE_LEVEL: 162 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 163 return 120; 164 165 case PIPE_CAP_NPOT_TEXTURES: 166 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, 167 NON_POWER_OF_TWO); */ 168 169 case PIPE_CAP_TEXTURE_SWIZZLE: 170 case PIPE_CAP_PRIMITIVE_RESTART: 171 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 172 173 case PIPE_CAP_ENDIANNESS: 174 return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature 175 ENDIANNESS_CONFIG) */ 176 177 /* Unsupported features. */ 178 case PIPE_CAP_SEAMLESS_CUBE_MAP: 179 case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */ 180 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */ 181 case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */ 182 case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */ 183 case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */ 184 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */ 185 case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */ 186 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */ 187 case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */ 188 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */ 189 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: /* only mirrored repeat */ 190 case PIPE_CAP_INDEP_BLEND_ENABLE: 191 case PIPE_CAP_INDEP_BLEND_FUNC: 192 case PIPE_CAP_DEPTH_CLIP_DISABLE: 193 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 194 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 195 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 196 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 197 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */ 198 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 199 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 200 case PIPE_CAP_USER_VERTEX_BUFFERS: 201 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 202 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 203 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */ 205 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 206 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 207 case PIPE_CAP_TEXTURE_GATHER_SM5: 208 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 209 case PIPE_CAP_FAKE_SW_MSAA: 210 case PIPE_CAP_TEXTURE_QUERY_LOD: 211 case PIPE_CAP_SAMPLE_SHADING: 212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 213 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 214 case PIPE_CAP_DRAW_INDIRECT: 215 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 216 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 217 case PIPE_CAP_SAMPLER_VIEW_TARGET: 218 case PIPE_CAP_CLIP_HALFZ: 219 case PIPE_CAP_VERTEXID_NOBASE: 220 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 221 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 222 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 223 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 224 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 225 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 226 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 227 case PIPE_CAP_DEPTH_BOUNDS_TEST: 228 case PIPE_CAP_TGSI_TXQS: 229 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 230 case PIPE_CAP_SHAREABLE_SHADERS: 231 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 232 case PIPE_CAP_CLEAR_TEXTURE: 233 case PIPE_CAP_DRAW_PARAMETERS: 234 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 235 case PIPE_CAP_MULTI_DRAW_INDIRECT: 236 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 237 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 238 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 239 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 240 case PIPE_CAP_INVALIDATE_BUFFER: 241 case PIPE_CAP_GENERATE_MIPMAP: 242 case PIPE_CAP_STRING_MARKER: 243 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 244 case PIPE_CAP_QUERY_BUFFER_OBJECT: 245 case PIPE_CAP_QUERY_MEMORY_INFO: 246 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 247 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 248 case PIPE_CAP_CULL_DISTANCE: 249 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 250 case PIPE_CAP_TGSI_VOTE: 251 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 252 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 253 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 254 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 255 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 256 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 257 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 258 case PIPE_CAP_TGSI_FS_FBFETCH: 259 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 260 case PIPE_CAP_DOUBLES: 261 case PIPE_CAP_INT64: 262 case PIPE_CAP_INT64_DIVMOD: 263 case PIPE_CAP_TGSI_TEX_TXF_LZ: 264 case PIPE_CAP_TGSI_CLOCK: 265 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 266 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 267 case PIPE_CAP_TGSI_BALLOT: 268 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 269 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 270 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 271 case PIPE_CAP_POST_DEPTH_COVERAGE: 272 case PIPE_CAP_BINDLESS_TEXTURE: 273 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 274 case PIPE_CAP_QUERY_SO_OVERFLOW: 275 case PIPE_CAP_MEMOBJ: 276 case PIPE_CAP_LOAD_CONSTBUF: 277 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 278 case PIPE_CAP_TILE_RASTER_ORDER: 279 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 280 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: 281 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 282 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 283 case PIPE_CAP_FENCE_SIGNAL: 284 case PIPE_CAP_CONSTBUF0_FLAGS: 285 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: 286 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: 287 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: 288 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: 289 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: 290 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: 291 case PIPE_CAP_PACKED_UNIFORMS: 292 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: 293 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: 294 return 0; 295 296 case PIPE_CAP_MAX_GS_INVOCATIONS: 297 return 32; 298 299 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: 300 return 1 << 27; 301 302 /* Stream output. */ 303 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 304 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 305 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 306 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 307 return 0; 308 309 /* Geometry shader output, unsupported. */ 310 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 311 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 312 case PIPE_CAP_MAX_VERTEX_STREAMS: 313 return 0; 314 315 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 316 return 128; 317 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: 318 return 255; 319 320 /* Texturing. */ 321 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 322 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 323 { 324 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); 325 assert(log2_max_tex_size > 0); 326 return log2_max_tex_size; 327 } 328 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */ 329 return 5; 330 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 331 return 0; 332 case PIPE_CAP_CUBE_MAP_ARRAY: 333 return 0; 334 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 335 case PIPE_CAP_MIN_TEXEL_OFFSET: 336 return -8; 337 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 338 case PIPE_CAP_MAX_TEXEL_OFFSET: 339 return 7; 340 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 341 return 0; 342 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 343 return 65536; 344 345 /* Render targets. */ 346 case PIPE_CAP_MAX_RENDER_TARGETS: 347 return 1; 348 349 /* Viewports and scissors. */ 350 case PIPE_CAP_MAX_VIEWPORTS: 351 return 1; 352 353 /* Timer queries. */ 354 case PIPE_CAP_QUERY_TIME_ELAPSED: 355 return 0; 356 case PIPE_CAP_OCCLUSION_QUERY: 357 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 358 case PIPE_CAP_QUERY_TIMESTAMP: 359 return 1; 360 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 361 return 0; 362 363 /* Preferences */ 364 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 365 return 0; 366 367 case PIPE_CAP_MAX_VARYINGS: 368 return screen->specs.max_varyings; 369 370 case PIPE_CAP_PCI_GROUP: 371 case PIPE_CAP_PCI_BUS: 372 case PIPE_CAP_PCI_DEVICE: 373 case PIPE_CAP_PCI_FUNCTION: 374 return 0; 375 case PIPE_CAP_VENDOR_ID: 376 case PIPE_CAP_DEVICE_ID: 377 return 0xFFFFFFFF; 378 case PIPE_CAP_ACCELERATED: 379 return 1; 380 case PIPE_CAP_VIDEO_MEMORY: 381 return 0; 382 case PIPE_CAP_UMA: 383 return 1; 384 default: 385 return u_pipe_screen_get_param_defaults(pscreen, param); 386 } 387} 388 389static float 390etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 391{ 392 struct etna_screen *screen = etna_screen(pscreen); 393 394 switch (param) { 395 case PIPE_CAPF_MAX_LINE_WIDTH: 396 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 397 case PIPE_CAPF_MAX_POINT_WIDTH: 398 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 399 return 8192.0f; 400 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 401 return 16.0f; 402 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 403 return util_last_bit(screen->specs.max_texture_size); 404 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 405 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 406 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 407 return 0.0f; 408 } 409 410 debug_printf("unknown paramf %d", param); 411 return 0; 412} 413 414static int 415etna_screen_get_shader_param(struct pipe_screen *pscreen, 416 enum pipe_shader_type shader, 417 enum pipe_shader_cap param) 418{ 419 struct etna_screen *screen = etna_screen(pscreen); 420 421 switch (shader) { 422 case PIPE_SHADER_FRAGMENT: 423 case PIPE_SHADER_VERTEX: 424 break; 425 case PIPE_SHADER_COMPUTE: 426 case PIPE_SHADER_GEOMETRY: 427 case PIPE_SHADER_TESS_CTRL: 428 case PIPE_SHADER_TESS_EVAL: 429 return 0; 430 default: 431 DBG("unknown shader type %d", shader); 432 return 0; 433 } 434 435 switch (param) { 436 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 437 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 438 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 439 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 440 return ETNA_MAX_TOKENS; 441 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 442 return ETNA_MAX_DEPTH; /* XXX */ 443 case PIPE_SHADER_CAP_MAX_INPUTS: 444 /* Maximum number of inputs for the vertex shader is the number 445 * of vertex elements - each element defines one vertex shader 446 * input register. For the fragment shader, this is the number 447 * of varyings. */ 448 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings 449 : screen->specs.vertex_max_elements; 450 case PIPE_SHADER_CAP_MAX_OUTPUTS: 451 return 16; /* see VIVS_VS_OUTPUT */ 452 case PIPE_SHADER_CAP_MAX_TEMPS: 453 return 64; /* Max native temporaries. */ 454 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 455 return 1; 456 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 457 return 1; 458 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 459 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 460 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 461 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 462 return 1; 463 case PIPE_SHADER_CAP_SUBROUTINES: 464 return 0; 465 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 466 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 467 case PIPE_SHADER_CAP_INTEGERS: 468 case PIPE_SHADER_CAP_INT64_ATOMICS: 469 case PIPE_SHADER_CAP_FP16: 470 return 0; 471 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 472 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 473 return shader == PIPE_SHADER_FRAGMENT 474 ? screen->specs.fragment_sampler_count 475 : screen->specs.vertex_sampler_count; 476 case PIPE_SHADER_CAP_PREFERRED_IR: 477 return PIPE_SHADER_IR_TGSI; 478 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 479 return 4096; 480 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 481 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 482 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 483 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 484 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 485 return false; 486 case PIPE_SHADER_CAP_SUPPORTED_IRS: 487 return 0; 488 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 489 return 32; 490 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 491 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 492 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 493 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 494 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 495 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 496 case PIPE_SHADER_CAP_SCALAR_ISA: 497 return 0; 498 } 499 500 debug_printf("unknown shader param %d", param); 501 return 0; 502} 503 504static uint64_t 505etna_screen_get_timestamp(struct pipe_screen *pscreen) 506{ 507 return os_time_get_nano(); 508} 509 510static bool 511gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt, 512 enum pipe_format format) 513{ 514 bool supported = true; 515 516 if (fmt == TEXTURE_FORMAT_ETC1) 517 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); 518 519 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) 520 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); 521 522 if (util_format_is_srgb(format)) 523 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 524 525 if (fmt & EXT_FORMAT) 526 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 527 528 if (fmt & ASTC_FORMAT) { 529 supported = screen->specs.tex_astc; 530 } 531 532 if (!supported) 533 return false; 534 535 if (texture_format_needs_swiz(format)) 536 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 537 538 return true; 539} 540 541static boolean 542etna_screen_is_format_supported(struct pipe_screen *pscreen, 543 enum pipe_format format, 544 enum pipe_texture_target target, 545 unsigned sample_count, 546 unsigned storage_sample_count, 547 unsigned usage) 548{ 549 struct etna_screen *screen = etna_screen(pscreen); 550 unsigned allowed = 0; 551 552 if (target != PIPE_BUFFER && 553 target != PIPE_TEXTURE_1D && 554 target != PIPE_TEXTURE_2D && 555 target != PIPE_TEXTURE_3D && 556 target != PIPE_TEXTURE_CUBE && 557 target != PIPE_TEXTURE_RECT) 558 return FALSE; 559 560 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 561 return false; 562 563 if (usage & PIPE_BIND_RENDER_TARGET) { 564 /* if render target, must be RS-supported format */ 565 if (translate_rs_format(format) != ETNA_NO_MATCH) { 566 /* Validate MSAA; number of samples must be allowed, and render target 567 * must have MSAA'able format. */ 568 if (sample_count > 1) { 569 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && 570 translate_msaa_format(format) != ETNA_NO_MATCH) { 571 allowed |= PIPE_BIND_RENDER_TARGET; 572 } 573 } else { 574 allowed |= PIPE_BIND_RENDER_TARGET; 575 } 576 } 577 } 578 579 if (usage & PIPE_BIND_DEPTH_STENCIL) { 580 if (translate_depth_format(format) != ETNA_NO_MATCH) 581 allowed |= PIPE_BIND_DEPTH_STENCIL; 582 } 583 584 if (usage & PIPE_BIND_SAMPLER_VIEW) { 585 uint32_t fmt = translate_texture_format(format); 586 587 if (!gpu_supports_texure_format(screen, fmt, format)) 588 fmt = ETNA_NO_MATCH; 589 590 if (sample_count < 2 && fmt != ETNA_NO_MATCH) 591 allowed |= PIPE_BIND_SAMPLER_VIEW; 592 } 593 594 if (usage & PIPE_BIND_VERTEX_BUFFER) { 595 if (translate_vertex_format_type(format) != ETNA_NO_MATCH) 596 allowed |= PIPE_BIND_VERTEX_BUFFER; 597 } 598 599 if (usage & PIPE_BIND_INDEX_BUFFER) { 600 /* must be supported index format */ 601 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT || 602 (format == PIPE_FORMAT_I32_UINT && 603 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { 604 allowed |= PIPE_BIND_INDEX_BUFFER; 605 } 606 } 607 608 /* Always allowed */ 609 allowed |= 610 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); 611 612 if (usage != allowed) { 613 DBG("not supported: format=%s, target=%d, sample_count=%d, " 614 "usage=%x, allowed=%x", 615 util_format_name(format), target, sample_count, usage, allowed); 616 } 617 618 return usage == allowed; 619} 620 621const uint64_t supported_modifiers[] = { 622 DRM_FORMAT_MOD_LINEAR, 623 DRM_FORMAT_MOD_VIVANTE_TILED, 624 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED, 625 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED, 626 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED, 627}; 628 629static void 630etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 631 enum pipe_format format, int max, 632 uint64_t *modifiers, 633 unsigned int *external_only, int *count) 634{ 635 struct etna_screen *screen = etna_screen(pscreen); 636 int i, num_modifiers = 0; 637 638 if (max > ARRAY_SIZE(supported_modifiers)) 639 max = ARRAY_SIZE(supported_modifiers); 640 641 if (!max) { 642 modifiers = NULL; 643 max = ARRAY_SIZE(supported_modifiers); 644 } 645 646 for (i = 0; num_modifiers < max; i++) { 647 /* don't advertise split tiled formats on single pipe/buffer GPUs */ 648 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) && 649 i >= 3) 650 break; 651 652 if (modifiers) 653 modifiers[num_modifiers] = supported_modifiers[i]; 654 if (external_only) 655 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0; 656 num_modifiers++; 657 } 658 659 *count = num_modifiers; 660} 661 662static boolean 663etna_get_specs(struct etna_screen *screen) 664{ 665 uint64_t val; 666 uint32_t instruction_count; 667 668 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { 669 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); 670 goto fail; 671 } 672 instruction_count = val; 673 674 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, 675 &val)) { 676 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); 677 goto fail; 678 } 679 screen->specs.vertex_output_buffer_size = val; 680 681 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { 682 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); 683 goto fail; 684 } 685 screen->specs.vertex_cache_size = val; 686 687 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { 688 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); 689 goto fail; 690 } 691 screen->specs.shader_core_count = val; 692 693 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { 694 DBG("could not get ETNA_GPU_STREAM_COUNT"); 695 goto fail; 696 } 697 screen->specs.stream_count = val; 698 699 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { 700 DBG("could not get ETNA_GPU_REGISTER_MAX"); 701 goto fail; 702 } 703 screen->specs.max_registers = val; 704 705 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { 706 DBG("could not get ETNA_GPU_PIXEL_PIPES"); 707 goto fail; 708 } 709 screen->specs.pixel_pipes = val; 710 711 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { 712 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); 713 goto fail; 714 } 715 if (val == 0) { 716 fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); 717 val = 168; 718 } 719 screen->specs.num_constants = val; 720 721 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific 722 * description of the differences. */ 723 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) 724 screen->specs.halti = 5; /* New GC7000/GC8x00 */ 725 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) 726 screen->specs.halti = 4; /* Old GC7000/GC7400 */ 727 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) 728 screen->specs.halti = 3; /* None? */ 729 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) 730 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ 731 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) 732 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ 733 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) 734 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ 735 else 736 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ 737 if (screen->specs.halti >= 0) 738 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); 739 else 740 DBG("etnaviv: GPU arch: pre-HALTI"); 741 742 screen->specs.can_supertile = 743 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); 744 screen->specs.bits_per_tile = 745 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; 746 screen->specs.ts_clear_value = 747 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 748 : 0x11111111; 749 750 /* vertex and fragment samplers live in one address space */ 751 screen->specs.vertex_sampler_offset = 8; 752 screen->specs.fragment_sampler_count = 8; 753 screen->specs.vertex_sampler_count = 4; 754 screen->specs.vs_need_z_div = 755 screen->model < 0x1000 && screen->model != 0x880; 756 screen->specs.has_sin_cos_sqrt = 757 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 758 screen->specs.has_sign_floor_ceil = 759 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); 760 screen->specs.has_shader_range_registers = 761 screen->model >= 0x1000 || screen->model == 0x880; 762 screen->specs.npot_tex_any_wrap = 763 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); 764 screen->specs.has_new_transcendentals = 765 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); 766 screen->specs.has_halti2_instructions = 767 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 768 769 if (screen->specs.halti >= 5) { 770 /* GC7000 - this core must load shaders from memory. */ 771 screen->specs.vs_offset = 0; 772 screen->specs.ps_offset = 0; 773 screen->specs.max_instructions = 0; /* Do not program shaders manually */ 774 screen->specs.has_icache = true; 775 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { 776 /* GC3000 - this core is capable of loading shaders from 777 * memory. It can also run shaders from registers, as a fallback, but 778 * "max_instructions" does not have the correct value. It has place for 779 * 2*256 instructions just like GC2000, but the offsets are slightly 780 * different. 781 */ 782 screen->specs.vs_offset = 0xC000; 783 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses 784 * this mirror for writing PS instructions, probably safest to do the 785 * same. 786 */ 787 screen->specs.ps_offset = 0x8000 + 0x1000; 788 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ 789 screen->specs.has_icache = true; 790 } else { 791 if (instruction_count > 256) { /* unified instruction memory? */ 792 screen->specs.vs_offset = 0xC000; 793 screen->specs.ps_offset = 0xD000; /* like vivante driver */ 794 screen->specs.max_instructions = 256; 795 } else { 796 screen->specs.vs_offset = 0x4000; 797 screen->specs.ps_offset = 0x6000; 798 screen->specs.max_instructions = instruction_count / 2; 799 } 800 screen->specs.has_icache = false; 801 } 802 803 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { 804 screen->specs.max_varyings = 12; 805 screen->specs.vertex_max_elements = 16; 806 } else { 807 screen->specs.max_varyings = 8; 808 /* Etna_viv documentation seems confused over the correct value 809 * here so choose the lower to be safe: HALTI0 says 16 i.s.o. 810 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ 811 screen->specs.vertex_max_elements = 10; 812 } 813 814 /* Etna_viv documentation does not indicate where varyings above 8 are 815 * stored. Moreover, if we are passed more than 8 varyings, we will 816 * walk off the end of some arrays. Limit the maximum number of varyings. */ 817 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) 818 screen->specs.max_varyings = ETNA_NUM_VARYINGS; 819 820 /* from QueryShaderCaps in kernel driver */ 821 if (screen->model < chipModel_GC4000) { 822 screen->specs.max_vs_uniforms = 168; 823 screen->specs.max_ps_uniforms = 64; 824 } else { 825 screen->specs.max_vs_uniforms = 256; 826 screen->specs.max_ps_uniforms = 256; 827 } 828 829 if (screen->specs.halti >= 5) { 830 screen->specs.has_unified_uniforms = true; 831 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); 832 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); 833 } else if (screen->specs.halti >= 1) { 834 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess 835 */ 836 screen->specs.has_unified_uniforms = true; 837 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); 838 /* hardcode PS uniforms to start after end of VS uniforms - 839 * for more flexibility this offset could be variable based on the 840 * shader. 841 */ 842 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); 843 } else { 844 screen->specs.has_unified_uniforms = false; 845 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); 846 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); 847 } 848 849 screen->specs.max_texture_size = 850 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; 851 screen->specs.max_rendertarget_size = 852 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; 853 854 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); 855 if (screen->specs.single_buffer) 856 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); 857 858 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); 859 860 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); 861 862 return true; 863 864fail: 865 return false; 866} 867 868struct etna_bo * 869etna_screen_bo_from_handle(struct pipe_screen *pscreen, 870 struct winsys_handle *whandle, unsigned *out_stride) 871{ 872 struct etna_screen *screen = etna_screen(pscreen); 873 struct etna_bo *bo; 874 875 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 876 bo = etna_bo_from_name(screen->dev, whandle->handle); 877 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 878 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle); 879 } else { 880 DBG("Attempt to import unsupported handle type %d", whandle->type); 881 return NULL; 882 } 883 884 if (!bo) { 885 DBG("ref name 0x%08x failed", whandle->handle); 886 return NULL; 887 } 888 889 *out_stride = whandle->stride; 890 891 return bo; 892} 893 894struct pipe_screen * 895etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, 896 struct renderonly *ro) 897{ 898 struct etna_screen *screen = CALLOC_STRUCT(etna_screen); 899 struct pipe_screen *pscreen; 900 drmVersionPtr version; 901 uint64_t val; 902 903 if (!screen) 904 return NULL; 905 906 pscreen = &screen->base; 907 screen->dev = dev; 908 screen->gpu = gpu; 909 screen->ro = renderonly_dup(ro); 910 screen->refcnt = 1; 911 912 if (!screen->ro) { 913 DBG("could not create renderonly object"); 914 goto fail; 915 } 916 917 version = drmGetVersion(screen->ro->gpu_fd); 918 screen->drm_version = ETNA_DRM_VERSION(version->version_major, 919 version->version_minor); 920 drmFreeVersion(version); 921 922 etna_mesa_debug = debug_get_option_etna_mesa_debug(); 923 924 /* Disable autodisable for correct rendering with TS */ 925 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; 926 927 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); 928 if (!screen->pipe) { 929 DBG("could not create 3d pipe"); 930 goto fail; 931 } 932 933 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { 934 DBG("could not get ETNA_GPU_MODEL"); 935 goto fail; 936 } 937 screen->model = val; 938 939 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { 940 DBG("could not get ETNA_GPU_REVISION"); 941 goto fail; 942 } 943 screen->revision = val; 944 945 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { 946 DBG("could not get ETNA_GPU_FEATURES_0"); 947 goto fail; 948 } 949 screen->features[0] = val; 950 951 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { 952 DBG("could not get ETNA_GPU_FEATURES_1"); 953 goto fail; 954 } 955 screen->features[1] = val; 956 957 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { 958 DBG("could not get ETNA_GPU_FEATURES_2"); 959 goto fail; 960 } 961 screen->features[2] = val; 962 963 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { 964 DBG("could not get ETNA_GPU_FEATURES_3"); 965 goto fail; 966 } 967 screen->features[3] = val; 968 969 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { 970 DBG("could not get ETNA_GPU_FEATURES_4"); 971 goto fail; 972 } 973 screen->features[4] = val; 974 975 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { 976 DBG("could not get ETNA_GPU_FEATURES_5"); 977 goto fail; 978 } 979 screen->features[5] = val; 980 981 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { 982 DBG("could not get ETNA_GPU_FEATURES_6"); 983 goto fail; 984 } 985 screen->features[6] = val; 986 987 if (!etna_get_specs(screen)) 988 goto fail; 989 990 /* apply debug options that disable individual features */ 991 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) 992 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; 993 if (DBG_ENABLED(ETNA_DBG_NO_TS)) 994 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 995 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) 996 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; 997 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) 998 screen->specs.can_supertile = 0; 999 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) 1000 screen->specs.single_buffer = 0; 1001 1002 pscreen->destroy = etna_screen_destroy; 1003 pscreen->get_param = etna_screen_get_param; 1004 pscreen->get_paramf = etna_screen_get_paramf; 1005 pscreen->get_shader_param = etna_screen_get_shader_param; 1006 1007 pscreen->get_name = etna_screen_get_name; 1008 pscreen->get_vendor = etna_screen_get_vendor; 1009 pscreen->get_device_vendor = etna_screen_get_device_vendor; 1010 1011 pscreen->get_timestamp = etna_screen_get_timestamp; 1012 pscreen->context_create = etna_context_create; 1013 pscreen->is_format_supported = etna_screen_is_format_supported; 1014 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; 1015 1016 etna_fence_screen_init(pscreen); 1017 etna_query_screen_init(pscreen); 1018 etna_resource_screen_init(pscreen); 1019 1020 util_dynarray_init(&screen->supported_pm_queries, NULL); 1021 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); 1022 1023 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) 1024 etna_pm_query_setup(screen); 1025 1026 mtx_init(&screen->lock, mtx_recursive); 1027 screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer, 1028 _mesa_key_pointer_equal); 1029 if (!screen->used_resources) 1030 goto fail2; 1031 1032 return pscreen; 1033 1034fail2: 1035 mtx_destroy(&screen->lock); 1036fail: 1037 etna_screen_destroy(pscreen); 1038 return NULL; 1039} 1040