1b8e80941Smrg/* 2b8e80941Smrg * Copyright (c) 2012-2015 Etnaviv Project 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sub license, 8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 9b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the 12b8e80941Smrg * next paragraph) shall be included in all copies or substantial portions 13b8e80941Smrg * of the Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21b8e80941Smrg * DEALINGS IN THE SOFTWARE. 22b8e80941Smrg * 23b8e80941Smrg * Authors: 24b8e80941Smrg * Wladimir J. van der Laan <laanwj@gmail.com> 25b8e80941Smrg */ 26b8e80941Smrg 27b8e80941Smrg#include "etnaviv_texture.h" 28b8e80941Smrg 29b8e80941Smrg#include "hw/common.xml.h" 30b8e80941Smrg 31b8e80941Smrg#include "etnaviv_clear_blit.h" 32b8e80941Smrg#include "etnaviv_context.h" 33b8e80941Smrg#include "etnaviv_emit.h" 34b8e80941Smrg#include "etnaviv_format.h" 35b8e80941Smrg#include "etnaviv_texture_state.h" 36b8e80941Smrg#include "etnaviv_translate.h" 37b8e80941Smrg#include "util/u_inlines.h" 38b8e80941Smrg#include "util/u_memory.h" 39b8e80941Smrg 40b8e80941Smrg#include "drm-uapi/drm_fourcc.h" 41b8e80941Smrg 42b8e80941Smrgstatic void 43b8e80941Smrgetna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader, 44b8e80941Smrg unsigned start_slot, unsigned num_samplers, 45b8e80941Smrg void **samplers) 46b8e80941Smrg{ 47b8e80941Smrg /* bind fragment sampler */ 48b8e80941Smrg struct etna_context *ctx = etna_context(pctx); 49b8e80941Smrg int offset; 50b8e80941Smrg 51b8e80941Smrg switch (shader) { 52b8e80941Smrg case PIPE_SHADER_FRAGMENT: 53b8e80941Smrg offset = 0; 54b8e80941Smrg ctx->num_fragment_samplers = num_samplers; 55b8e80941Smrg break; 56b8e80941Smrg case PIPE_SHADER_VERTEX: 57b8e80941Smrg offset = ctx->specs.vertex_sampler_offset; 58b8e80941Smrg break; 59b8e80941Smrg default: 60b8e80941Smrg assert(!"Invalid shader"); 61b8e80941Smrg return; 62b8e80941Smrg } 63b8e80941Smrg 64b8e80941Smrg uint32_t mask = 1 << offset; 65b8e80941Smrg for (int idx = 0; idx < num_samplers; ++idx, mask <<= 1) { 66b8e80941Smrg ctx->sampler[offset + idx] = samplers[idx]; 67b8e80941Smrg if (samplers[idx]) 68b8e80941Smrg ctx->active_samplers |= mask; 69b8e80941Smrg else 70b8e80941Smrg ctx->active_samplers &= ~mask; 71b8e80941Smrg } 72b8e80941Smrg 73b8e80941Smrg ctx->dirty |= ETNA_DIRTY_SAMPLERS; 74b8e80941Smrg} 75b8e80941Smrg 76b8e80941Smrgstatic void 77b8e80941Smrgetna_configure_sampler_ts(struct etna_sampler_ts *sts, struct pipe_sampler_view *pview, bool enable) 78b8e80941Smrg{ 79b8e80941Smrg assert(sts); 80b8e80941Smrg sts->enable = enable; 81b8e80941Smrg if (enable) { 82b8e80941Smrg struct etna_resource *rsc = etna_resource(pview->texture); 83b8e80941Smrg struct etna_resource_level *lev = &rsc->levels[0]; 84b8e80941Smrg assert(rsc->ts_bo && lev->ts_valid); 85b8e80941Smrg 86b8e80941Smrg sts->TS_SAMPLER_CONFIG = 87b8e80941Smrg VIVS_TS_SAMPLER_CONFIG_ENABLE(1) | 88b8e80941Smrg VIVS_TS_SAMPLER_CONFIG_FORMAT(translate_ts_sampler_format(rsc->base.format)); 89b8e80941Smrg sts->TS_SAMPLER_CLEAR_VALUE = lev->clear_value; 90b8e80941Smrg sts->TS_SAMPLER_CLEAR_VALUE2 = lev->clear_value; /* To handle 64-bit formats this needs a different value */ 91b8e80941Smrg sts->TS_SAMPLER_STATUS_BASE.bo = rsc->ts_bo; 92b8e80941Smrg sts->TS_SAMPLER_STATUS_BASE.offset = lev->ts_offset; 93b8e80941Smrg sts->TS_SAMPLER_STATUS_BASE.flags = ETNA_RELOC_READ; 94b8e80941Smrg } else { 95b8e80941Smrg sts->TS_SAMPLER_CONFIG = 0; 96b8e80941Smrg sts->TS_SAMPLER_STATUS_BASE.bo = NULL; 97b8e80941Smrg } 98b8e80941Smrg /* n.b.: relies on caller to mark ETNA_DIRTY_SAMPLER_VIEWS */ 99b8e80941Smrg} 100b8e80941Smrg 101b8e80941Smrg/* Return true if the GPU can use sampler TS with this sampler view. 102b8e80941Smrg * Sampler TS is an optimization used when rendering to textures, where 103b8e80941Smrg * a resolve-in-place can be avoided when rendering has left a (valid) TS. 104b8e80941Smrg */ 105b8e80941Smrgstatic bool 106b8e80941Smrgetna_can_use_sampler_ts(struct pipe_sampler_view *view, int num) 107b8e80941Smrg{ 108b8e80941Smrg /* Can use sampler TS when: 109b8e80941Smrg * - the hardware supports sampler TS. 110b8e80941Smrg * - the sampler view will be bound to sampler <VIVS_TS_SAMPLER__LEN. 111b8e80941Smrg * HALTI5 adds a mapping from sampler to sampler TS unit, but this is AFAIK 112b8e80941Smrg * absent on earlier models. 113b8e80941Smrg * - it is a texture, not a buffer. 114b8e80941Smrg * - the sampler view has a supported format for sampler TS. 115b8e80941Smrg * - the sampler will have one LOD, and it happens to be level 0. 116b8e80941Smrg * (it is not sure if the hw supports it for other levels, but available 117b8e80941Smrg * state strongly suggests only one at a time). 118b8e80941Smrg * - the resource TS is valid for level 0. 119b8e80941Smrg */ 120b8e80941Smrg struct etna_resource *rsc = etna_resource(view->texture); 121b8e80941Smrg struct etna_screen *screen = etna_screen(rsc->base.screen); 122b8e80941Smrg return VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ) && 123b8e80941Smrg num < VIVS_TS_SAMPLER__LEN && 124b8e80941Smrg rsc->base.target != PIPE_BUFFER && 125b8e80941Smrg translate_ts_sampler_format(rsc->base.format) != ETNA_NO_MATCH && 126b8e80941Smrg view->u.tex.first_level == 0 && MIN2(view->u.tex.last_level, rsc->base.last_level) == 0 && 127b8e80941Smrg rsc->levels[0].ts_valid; 128b8e80941Smrg} 129b8e80941Smrg 130b8e80941Smrgstatic void 131b8e80941Smrgetna_update_sampler_source(struct pipe_sampler_view *view, int num) 132b8e80941Smrg{ 133b8e80941Smrg struct etna_resource *base = etna_resource(view->texture); 134b8e80941Smrg struct etna_resource *to = base, *from = base; 135b8e80941Smrg struct etna_context *ctx = etna_context(view->context); 136b8e80941Smrg bool enable_sampler_ts = false; 137b8e80941Smrg 138b8e80941Smrg if (base->external && etna_resource_newer(etna_resource(base->external), base)) 139b8e80941Smrg from = etna_resource(base->external); 140b8e80941Smrg 141b8e80941Smrg if (base->texture) 142b8e80941Smrg to = etna_resource(base->texture); 143b8e80941Smrg 144b8e80941Smrg if ((to != from) && etna_resource_older(to, from)) { 145b8e80941Smrg etna_copy_resource(view->context, &to->base, &from->base, 0, 146b8e80941Smrg view->texture->last_level); 147b8e80941Smrg to->seqno = from->seqno; 148b8e80941Smrg } else if ((to == from) && etna_resource_needs_flush(to)) { 149b8e80941Smrg if (ctx->ts_for_sampler_view && etna_can_use_sampler_ts(view, num)) { 150b8e80941Smrg enable_sampler_ts = true; 151b8e80941Smrg /* Do not set flush_seqno because the resolve-to-self was bypassed */ 152b8e80941Smrg } else { 153b8e80941Smrg /* Resolve TS if needed */ 154b8e80941Smrg etna_copy_resource(view->context, &to->base, &from->base, 0, 155b8e80941Smrg view->texture->last_level); 156b8e80941Smrg to->flush_seqno = from->seqno; 157b8e80941Smrg } 158b8e80941Smrg } 159b8e80941Smrg if (ctx->ts_for_sampler_view) { 160b8e80941Smrg etna_configure_sampler_ts(ctx->ts_for_sampler_view(view), view, enable_sampler_ts); 161b8e80941Smrg } 162b8e80941Smrg} 163b8e80941Smrg 164b8e80941Smrgstatic bool 165b8e80941Smrgetna_resource_sampler_compatible(struct etna_resource *res) 166b8e80941Smrg{ 167b8e80941Smrg if (util_format_is_compressed(res->base.format)) 168b8e80941Smrg return true; 169b8e80941Smrg 170b8e80941Smrg struct etna_screen *screen = etna_screen(res->base.screen); 171b8e80941Smrg /* This GPU supports texturing from supertiled textures? */ 172b8e80941Smrg if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE)) 173b8e80941Smrg return true; 174b8e80941Smrg 175b8e80941Smrg /* This GPU supports texturing from linear textures? */ 176b8e80941Smrg if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT)) 177b8e80941Smrg return true; 178b8e80941Smrg 179b8e80941Smrg /* Otherwise, only support tiled layouts */ 180b8e80941Smrg if (res->layout != ETNA_LAYOUT_TILED) 181b8e80941Smrg return false; 182b8e80941Smrg 183b8e80941Smrg /* If we have HALIGN support, we can allow for the RS padding */ 184b8e80941Smrg if (VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN)) 185b8e80941Smrg return true; 186b8e80941Smrg 187b8e80941Smrg /* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */ 188b8e80941Smrg if (res->halign != TEXTURE_HALIGN_FOUR) 189b8e80941Smrg return false; 190b8e80941Smrg 191b8e80941Smrg return true; 192b8e80941Smrg} 193b8e80941Smrg 194b8e80941Smrgstruct etna_resource * 195b8e80941Smrgetna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc) 196b8e80941Smrg{ 197b8e80941Smrg struct etna_resource *res = etna_resource(prsc); 198b8e80941Smrg if (!etna_resource_sampler_compatible(res)) { 199b8e80941Smrg /* The original resource is not compatible with the sampler. 200b8e80941Smrg * Allocate an appropriately tiled texture. */ 201b8e80941Smrg if (!res->texture) { 202b8e80941Smrg struct pipe_resource templat = *prsc; 203b8e80941Smrg 204b8e80941Smrg templat.bind &= ~(PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET | 205b8e80941Smrg PIPE_BIND_BLENDABLE); 206b8e80941Smrg res->texture = 207b8e80941Smrg etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED, 208b8e80941Smrg ETNA_ADDRESSING_MODE_TILED, 209b8e80941Smrg DRM_FORMAT_MOD_LINEAR, &templat); 210b8e80941Smrg } 211b8e80941Smrg 212b8e80941Smrg if (!res->texture) { 213b8e80941Smrg return NULL; 214b8e80941Smrg } 215b8e80941Smrg res = etna_resource(res->texture); 216b8e80941Smrg } 217b8e80941Smrg return res; 218b8e80941Smrg} 219b8e80941Smrg 220b8e80941Smrgstatic void 221b8e80941Smrgset_sampler_views(struct etna_context *ctx, unsigned start, unsigned end, 222b8e80941Smrg unsigned nr, struct pipe_sampler_view **views) 223b8e80941Smrg{ 224b8e80941Smrg unsigned i, j; 225b8e80941Smrg uint32_t mask = 1 << start; 226b8e80941Smrg uint32_t prev_active_sampler_views = ctx->active_sampler_views; 227b8e80941Smrg 228b8e80941Smrg for (i = start, j = 0; j < nr; i++, j++, mask <<= 1) { 229b8e80941Smrg pipe_sampler_view_reference(&ctx->sampler_view[i], views[j]); 230b8e80941Smrg if (views[j]) { 231b8e80941Smrg ctx->active_sampler_views |= mask; 232b8e80941Smrg ctx->dirty_sampler_views |= mask; 233b8e80941Smrg } else 234b8e80941Smrg ctx->active_sampler_views &= ~mask; 235b8e80941Smrg } 236b8e80941Smrg 237b8e80941Smrg for (; i < end; i++, mask <<= 1) { 238b8e80941Smrg pipe_sampler_view_reference(&ctx->sampler_view[i], NULL); 239b8e80941Smrg ctx->active_sampler_views &= ~mask; 240b8e80941Smrg } 241b8e80941Smrg 242b8e80941Smrg /* sampler views that changed state (even to inactive) are also dirty */ 243b8e80941Smrg ctx->dirty_sampler_views |= ctx->active_sampler_views ^ prev_active_sampler_views; 244b8e80941Smrg} 245b8e80941Smrg 246b8e80941Smrgstatic inline void 247b8e80941Smrgetna_fragtex_set_sampler_views(struct etna_context *ctx, unsigned nr, 248b8e80941Smrg struct pipe_sampler_view **views) 249b8e80941Smrg{ 250b8e80941Smrg unsigned start = 0; 251b8e80941Smrg unsigned end = start + ctx->specs.fragment_sampler_count; 252b8e80941Smrg 253b8e80941Smrg set_sampler_views(ctx, start, end, nr, views); 254b8e80941Smrg ctx->num_fragment_sampler_views = nr; 255b8e80941Smrg} 256b8e80941Smrg 257b8e80941Smrg 258b8e80941Smrgstatic inline void 259b8e80941Smrgetna_vertex_set_sampler_views(struct etna_context *ctx, unsigned nr, 260b8e80941Smrg struct pipe_sampler_view **views) 261b8e80941Smrg{ 262b8e80941Smrg unsigned start = ctx->specs.vertex_sampler_offset; 263b8e80941Smrg unsigned end = start + ctx->specs.vertex_sampler_count; 264b8e80941Smrg 265b8e80941Smrg set_sampler_views(ctx, start, end, nr, views); 266b8e80941Smrg} 267b8e80941Smrg 268b8e80941Smrgstatic void 269b8e80941Smrgetna_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader, 270b8e80941Smrg unsigned start_slot, unsigned num_views, 271b8e80941Smrg struct pipe_sampler_view **views) 272b8e80941Smrg{ 273b8e80941Smrg struct etna_context *ctx = etna_context(pctx); 274b8e80941Smrg assert(start_slot == 0); 275b8e80941Smrg 276b8e80941Smrg ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES; 277b8e80941Smrg 278b8e80941Smrg for (unsigned idx = 0; idx < num_views; ++idx) { 279b8e80941Smrg if (views[idx]) 280b8e80941Smrg etna_update_sampler_source(views[idx], idx); 281b8e80941Smrg } 282b8e80941Smrg 283b8e80941Smrg switch (shader) { 284b8e80941Smrg case PIPE_SHADER_FRAGMENT: 285b8e80941Smrg etna_fragtex_set_sampler_views(ctx, num_views, views); 286b8e80941Smrg break; 287b8e80941Smrg case PIPE_SHADER_VERTEX: 288b8e80941Smrg etna_vertex_set_sampler_views(ctx, num_views, views); 289b8e80941Smrg break; 290b8e80941Smrg default:; 291b8e80941Smrg } 292b8e80941Smrg} 293b8e80941Smrg 294b8e80941Smrgstatic void 295b8e80941Smrgetna_texture_barrier(struct pipe_context *pctx, unsigned flags) 296b8e80941Smrg{ 297b8e80941Smrg struct etna_context *ctx = etna_context(pctx); 298b8e80941Smrg /* clear color and texture cache to make sure that texture unit reads 299b8e80941Smrg * what has been written */ 300b8e80941Smrg etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_TEXTURE); 301b8e80941Smrg} 302b8e80941Smrg 303b8e80941Smrguint32_t 304b8e80941Smrgactive_samplers_bits(struct etna_context *ctx) 305b8e80941Smrg{ 306b8e80941Smrg return ctx->active_sampler_views & ctx->active_samplers; 307b8e80941Smrg} 308b8e80941Smrg 309b8e80941Smrgvoid 310b8e80941Smrgetna_texture_init(struct pipe_context *pctx) 311b8e80941Smrg{ 312b8e80941Smrg pctx->bind_sampler_states = etna_bind_sampler_states; 313b8e80941Smrg pctx->set_sampler_views = etna_set_sampler_views; 314b8e80941Smrg pctx->texture_barrier = etna_texture_barrier; 315b8e80941Smrg etna_texture_state_init(pctx); 316b8e80941Smrg} 317