1848b8605Smrg /**************************************************************************
2848b8605Smrg *
3848b8605Smrg * Copyright 2003 VMware, Inc.
4848b8605Smrg * All Rights Reserved.
5848b8605Smrg *
6848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
7848b8605Smrg * copy of this software and associated documentation files (the
8848b8605Smrg * "Software"), to deal in the Software without restriction, including
9848b8605Smrg * without limitation the rights to use, copy, modify, merge, publish,
10848b8605Smrg * distribute, sub license, and/or sell copies of the Software, and to
11848b8605Smrg * permit persons to whom the Software is furnished to do so, subject to
12848b8605Smrg * the following conditions:
13848b8605Smrg *
14848b8605Smrg * The above copyright notice and this permission notice (including the
15848b8605Smrg * next paragraph) shall be included in all copies or substantial portions
16848b8605Smrg * of the Software.
17848b8605Smrg *
18848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19848b8605Smrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20848b8605Smrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21848b8605Smrg * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22848b8605Smrg * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23848b8605Smrg * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24848b8605Smrg * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25848b8605Smrg *
26848b8605Smrg **************************************************************************/
27848b8605Smrg
28848b8605Smrg#ifndef I915_CONTEXT_H
29848b8605Smrg#define I915_CONTEXT_H
30848b8605Smrg
31848b8605Smrg
32848b8605Smrg#include "pipe/p_context.h"
33848b8605Smrg#include "pipe/p_defines.h"
34848b8605Smrg#include "pipe/p_state.h"
35848b8605Smrg
36848b8605Smrg#include "draw/draw_vertex.h"
37848b8605Smrg
38848b8605Smrg#include "tgsi/tgsi_scan.h"
39848b8605Smrg
40b8e80941Smrg#include "util/slab.h"
41848b8605Smrg#include "util/u_blitter.h"
42848b8605Smrg
43848b8605Smrg
44848b8605Smrgstruct i915_winsys;
45848b8605Smrgstruct i915_winsys_buffer;
46848b8605Smrgstruct i915_winsys_batchbuffer;
47848b8605Smrg
48848b8605Smrg
49848b8605Smrg#define I915_TEX_UNITS 8
50848b8605Smrg
51848b8605Smrg#define I915_DYNAMIC_MODES4       0
52848b8605Smrg#define I915_DYNAMIC_DEPTHSCALE_0 1 /* just the header */
53848b8605Smrg#define I915_DYNAMIC_DEPTHSCALE_1 2
54848b8605Smrg#define I915_DYNAMIC_IAB          3
55848b8605Smrg#define I915_DYNAMIC_BC_0         4 /* just the header */
56848b8605Smrg#define I915_DYNAMIC_BC_1         5
57848b8605Smrg#define I915_DYNAMIC_BFO_0        6
58848b8605Smrg#define I915_DYNAMIC_BFO_1        7
59848b8605Smrg#define I915_DYNAMIC_STP_0        8
60848b8605Smrg#define I915_DYNAMIC_STP_1        9
61848b8605Smrg#define I915_DYNAMIC_SC_ENA_0     10
62848b8605Smrg#define I915_DYNAMIC_SC_RECT_0    11
63848b8605Smrg#define I915_DYNAMIC_SC_RECT_1    12
64848b8605Smrg#define I915_DYNAMIC_SC_RECT_2    13
65848b8605Smrg#define I915_MAX_DYNAMIC          14
66848b8605Smrg
67848b8605Smrg
68848b8605Smrg#define I915_IMMEDIATE_S0         0
69848b8605Smrg#define I915_IMMEDIATE_S1         1
70848b8605Smrg#define I915_IMMEDIATE_S2         2
71848b8605Smrg#define I915_IMMEDIATE_S3         3
72848b8605Smrg#define I915_IMMEDIATE_S4         4
73848b8605Smrg#define I915_IMMEDIATE_S5         5
74848b8605Smrg#define I915_IMMEDIATE_S6         6
75848b8605Smrg#define I915_IMMEDIATE_S7         7
76848b8605Smrg#define I915_MAX_IMMEDIATE        8
77848b8605Smrg
78848b8605Smrg/* These must mach the order of LI0_STATE_* bits, as they will be used
79848b8605Smrg * to generate hardware packets:
80848b8605Smrg */
81848b8605Smrg#define I915_CACHE_STATIC         0
82848b8605Smrg#define I915_CACHE_DYNAMIC        1 /* handled specially */
83848b8605Smrg#define I915_CACHE_SAMPLER        2
84848b8605Smrg#define I915_CACHE_MAP            3
85848b8605Smrg#define I915_CACHE_PROGRAM        4
86848b8605Smrg#define I915_CACHE_CONSTANTS      5
87848b8605Smrg#define I915_MAX_CACHE            6
88848b8605Smrg
89848b8605Smrg#define I915_MAX_CONSTANT  32
90848b8605Smrg
91848b8605Smrg
92848b8605Smrg/** See constant_flags[] below */
93848b8605Smrg#define I915_CONSTFLAG_USER 0x1f
94848b8605Smrg
95848b8605Smrg
96848b8605Smrg/**
97848b8605Smrg * Subclass of pipe_shader_state
98848b8605Smrg */
99848b8605Smrgstruct i915_fragment_shader
100848b8605Smrg{
101848b8605Smrg   struct pipe_shader_state state;
102848b8605Smrg
103848b8605Smrg   struct tgsi_shader_info info;
104848b8605Smrg
105848b8605Smrg   struct draw_fragment_shader *draw_data;
106848b8605Smrg
107848b8605Smrg   uint *decl;
108848b8605Smrg   uint decl_len;
109848b8605Smrg
110848b8605Smrg   uint *program;
111848b8605Smrg   uint program_len;
112848b8605Smrg
113848b8605Smrg   /**
114848b8605Smrg    * constants introduced during translation.
115848b8605Smrg    * These are placed at the end of the constant buffer and grow toward
116848b8605Smrg    * the beginning (eg: slot 31, 30 29, ...)
117848b8605Smrg    * User-provided constants start at 0.
118848b8605Smrg    * This allows both types of constants to co-exist (until there's too many)
119848b8605Smrg    * and doesn't require regenerating/changing the fragment program to
120848b8605Smrg    * shuffle constants around.
121848b8605Smrg    */
122848b8605Smrg   uint num_constants;
123848b8605Smrg   float constants[I915_MAX_CONSTANT][4];
124848b8605Smrg
125848b8605Smrg   /**
126848b8605Smrg    * Status of each constant
127848b8605Smrg    * if I915_CONSTFLAG_PARAM, the value must be taken from the corresponding
128848b8605Smrg    * slot of the user's constant buffer. (set by pipe->set_constant_buffer())
129848b8605Smrg    * Else, the bitmask indicates which components are occupied by immediates.
130848b8605Smrg    */
131848b8605Smrg   ubyte constant_flags[I915_MAX_CONSTANT];
132848b8605Smrg
133848b8605Smrg   /**
134848b8605Smrg    * The mapping between generics and hw texture coords.
135848b8605Smrg    * We need to share this between the vertex and fragment stages.
136848b8605Smrg    **/
137848b8605Smrg   int generic_mapping[I915_TEX_UNITS];
138848b8605Smrg};
139848b8605Smrg
140848b8605Smrg
141848b8605Smrgstruct i915_cache_context;
142848b8605Smrg
143848b8605Smrg/* Use to calculate differences between state emitted to hardware and
144848b8605Smrg * current driver-calculated state.
145848b8605Smrg */
146848b8605Smrgstruct i915_state
147848b8605Smrg{
148848b8605Smrg   unsigned immediate[I915_MAX_IMMEDIATE];
149848b8605Smrg   unsigned dynamic[I915_MAX_DYNAMIC];
150848b8605Smrg
151848b8605Smrg   /** number of constants passed in through a constant buffer */
152848b8605Smrg   uint num_user_constants[PIPE_SHADER_TYPES];
153848b8605Smrg
154848b8605Smrg   /* texture sampler state */
155848b8605Smrg   unsigned sampler[I915_TEX_UNITS][3];
156848b8605Smrg   unsigned sampler_enable_flags;
157848b8605Smrg   unsigned sampler_enable_nr;
158848b8605Smrg
159848b8605Smrg   /* texture image buffers */
160b8e80941Smrg   unsigned texbuffer[I915_TEX_UNITS][3];
161848b8605Smrg
162848b8605Smrg   /** Describes the current hardware vertex layout */
163848b8605Smrg   struct vertex_info vertex_info;
164848b8605Smrg
165848b8605Smrg   /* static state (dst/depth buffer state) */
166848b8605Smrg   struct i915_winsys_buffer *cbuf_bo;
167848b8605Smrg   unsigned cbuf_flags;
168848b8605Smrg   struct i915_winsys_buffer *depth_bo;
169848b8605Smrg   unsigned depth_flags;
170848b8605Smrg   unsigned dst_buf_vars;
171848b8605Smrg   uint32_t draw_offset;
172848b8605Smrg   uint32_t draw_size;
173848b8605Smrg   uint32_t target_fixup_format;
174848b8605Smrg   uint32_t fixup_swizzle;
175848b8605Smrg
176848b8605Smrg   unsigned id;			/* track lost context events */
177848b8605Smrg};
178848b8605Smrg
179848b8605Smrgstruct i915_blend_state {
180848b8605Smrg   unsigned iab;
181848b8605Smrg   unsigned modes4;
182848b8605Smrg   unsigned LIS5;
183848b8605Smrg   unsigned LIS6;
184848b8605Smrg};
185848b8605Smrg
186848b8605Smrgstruct i915_depth_stencil_state {
187848b8605Smrg   unsigned stencil_modes4;
188848b8605Smrg   unsigned bfo[2];
189848b8605Smrg   unsigned stencil_LIS5;
190848b8605Smrg   unsigned depth_LIS6;
191848b8605Smrg};
192848b8605Smrg
193848b8605Smrgstruct i915_rasterizer_state {
194848b8605Smrg   struct pipe_rasterizer_state templ;
195848b8605Smrg
196848b8605Smrg   unsigned light_twoside : 1;
197848b8605Smrg   unsigned st;
198848b8605Smrg
199848b8605Smrg   unsigned LIS4;
200848b8605Smrg   unsigned LIS7;
201848b8605Smrg   unsigned sc[1];
202848b8605Smrg
203848b8605Smrg   union { float f; unsigned u; } ds[2];
204848b8605Smrg};
205848b8605Smrg
206848b8605Smrgstruct i915_sampler_state {
207848b8605Smrg   struct pipe_sampler_state templ;
208848b8605Smrg   unsigned state[3];
209848b8605Smrg   unsigned minlod;
210848b8605Smrg   unsigned maxlod;
211848b8605Smrg};
212848b8605Smrg
213848b8605Smrgstruct i915_velems_state {
214848b8605Smrg   unsigned count;
215848b8605Smrg   struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
216848b8605Smrg};
217848b8605Smrg
218848b8605Smrg
219848b8605Smrgstruct i915_context {
220848b8605Smrg   struct pipe_context base;
221848b8605Smrg
222848b8605Smrg   struct i915_winsys *iws;
223848b8605Smrg
224848b8605Smrg   struct draw_context *draw;
225848b8605Smrg
226848b8605Smrg   /* The most recent drawing state as set by the driver:
227848b8605Smrg    */
228848b8605Smrg   const struct i915_blend_state           *blend;
229848b8605Smrg   const struct i915_sampler_state         *fragment_sampler[PIPE_MAX_SAMPLERS];
230848b8605Smrg   struct pipe_sampler_state               *vertex_samplers[PIPE_MAX_SAMPLERS];
231848b8605Smrg   const struct i915_depth_stencil_state   *depth_stencil;
232848b8605Smrg   const struct i915_rasterizer_state      *rasterizer;
233848b8605Smrg
234848b8605Smrg   struct i915_fragment_shader *fs;
235848b8605Smrg
236848b8605Smrg   void *vs;
237848b8605Smrg
238848b8605Smrg   struct i915_velems_state *velems;
239848b8605Smrg   unsigned nr_vertex_buffers;
240848b8605Smrg   struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
241848b8605Smrg
242848b8605Smrg   struct pipe_blend_color blend_color;
243848b8605Smrg   struct pipe_stencil_ref stencil_ref;
244848b8605Smrg   struct pipe_clip_state clip;
245848b8605Smrg   struct pipe_resource *constants[PIPE_SHADER_TYPES];
246848b8605Smrg   struct pipe_framebuffer_state framebuffer;
247848b8605Smrg   struct pipe_poly_stipple poly_stipple;
248848b8605Smrg   struct pipe_scissor_state scissor;
249848b8605Smrg   struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
250848b8605Smrg   struct pipe_sampler_view *vertex_sampler_views[PIPE_MAX_SAMPLERS];
251848b8605Smrg   struct pipe_viewport_state viewport;
252848b8605Smrg
253848b8605Smrg   unsigned dirty;
254848b8605Smrg
255848b8605Smrg   struct pipe_resource *mapped_vs_tex[PIPE_MAX_SAMPLERS];
256848b8605Smrg   struct i915_winsys_buffer* mapped_vs_tex_buffer[PIPE_MAX_SAMPLERS];
257848b8605Smrg
258848b8605Smrg   unsigned num_samplers;
259848b8605Smrg   unsigned num_fragment_sampler_views;
260848b8605Smrg   unsigned num_vertex_samplers;
261848b8605Smrg   unsigned num_vertex_sampler_views;
262848b8605Smrg
263848b8605Smrg   struct i915_winsys_batchbuffer *batch;
264848b8605Smrg
265848b8605Smrg   /** Vertex buffer */
266848b8605Smrg   struct i915_winsys_buffer *vbo;
267848b8605Smrg   size_t vbo_offset;
268848b8605Smrg   unsigned vbo_flushed;
269848b8605Smrg
270848b8605Smrg   struct i915_state current;
271848b8605Smrg   unsigned hardware_dirty;
272848b8605Smrg   unsigned immediate_dirty : I915_MAX_IMMEDIATE;
273848b8605Smrg   unsigned dynamic_dirty : I915_MAX_DYNAMIC;
274848b8605Smrg   unsigned static_dirty : 4;
275848b8605Smrg   unsigned flush_dirty : 2;
276848b8605Smrg
277848b8605Smrg   struct i915_winsys_buffer *validation_buffers[2 + 1 + I915_TEX_UNITS];
278848b8605Smrg   int num_validation_buffers;
279848b8605Smrg
280b8e80941Smrg   struct slab_mempool transfer_pool;
281b8e80941Smrg   struct slab_mempool texture_transfer_pool;
282848b8605Smrg
283848b8605Smrg   /* state for tracking flushes */
284848b8605Smrg   int last_fired_vertices;
285848b8605Smrg   int fired_vertices;
286848b8605Smrg   int queued_vertices;
287848b8605Smrg
288848b8605Smrg   /** blitter/hw-clear */
289848b8605Smrg   struct blitter_context* blitter;
290848b8605Smrg};
291848b8605Smrg
292848b8605Smrg/* A flag for each state_tracker state object:
293848b8605Smrg */
294848b8605Smrg#define I915_NEW_VIEWPORT      0x1
295848b8605Smrg#define I915_NEW_RASTERIZER    0x2
296848b8605Smrg#define I915_NEW_FS            0x4
297848b8605Smrg#define I915_NEW_BLEND         0x8
298848b8605Smrg#define I915_NEW_CLIP          0x10
299848b8605Smrg#define I915_NEW_SCISSOR       0x20
300848b8605Smrg#define I915_NEW_STIPPLE       0x40
301848b8605Smrg#define I915_NEW_FRAMEBUFFER   0x80
302848b8605Smrg#define I915_NEW_ALPHA_TEST    0x100
303848b8605Smrg#define I915_NEW_DEPTH_STENCIL 0x200
304848b8605Smrg#define I915_NEW_SAMPLER       0x400
305848b8605Smrg#define I915_NEW_SAMPLER_VIEW  0x800
306848b8605Smrg#define I915_NEW_VS_CONSTANTS  0x1000
307848b8605Smrg#define I915_NEW_FS_CONSTANTS  0x2000
308848b8605Smrg#define I915_NEW_GS_CONSTANTS  0x4000
309848b8605Smrg#define I915_NEW_VBO           0x8000
310848b8605Smrg#define I915_NEW_VS            0x10000
311848b8605Smrg
312848b8605Smrg
313848b8605Smrg/* Driver's internally generated state flags:
314848b8605Smrg */
315848b8605Smrg#define I915_NEW_VERTEX_FORMAT    0x10000
316848b8605Smrg
317848b8605Smrg
318848b8605Smrg/* Dirty flags for hardware emit
319848b8605Smrg */
320848b8605Smrg#define I915_HW_STATIC            (1<<I915_CACHE_STATIC)
321848b8605Smrg#define I915_HW_DYNAMIC           (1<<I915_CACHE_DYNAMIC)
322848b8605Smrg#define I915_HW_SAMPLER           (1<<I915_CACHE_SAMPLER)
323848b8605Smrg#define I915_HW_MAP               (1<<I915_CACHE_MAP)
324848b8605Smrg#define I915_HW_PROGRAM           (1<<I915_CACHE_PROGRAM)
325848b8605Smrg#define I915_HW_CONSTANTS         (1<<I915_CACHE_CONSTANTS)
326848b8605Smrg#define I915_HW_IMMEDIATE         (1<<(I915_MAX_CACHE+0))
327848b8605Smrg#define I915_HW_INVARIANT         (1<<(I915_MAX_CACHE+1))
328848b8605Smrg#define I915_HW_FLUSH             (1<<(I915_MAX_CACHE+1))
329848b8605Smrg
330848b8605Smrg/* hw flush handling */
331848b8605Smrg#define I915_FLUSH_CACHE		1
332848b8605Smrg#define I915_PIPELINE_FLUSH		2
333848b8605Smrg
334848b8605Smrg/* split up static state */
335848b8605Smrg#define I915_DST_BUF_COLOR              1
336848b8605Smrg#define I915_DST_BUF_DEPTH              2
337848b8605Smrg#define I915_DST_VARS                   4
338848b8605Smrg#define I915_DST_RECT                   8
339848b8605Smrg
340b8e80941Smrgstatic inline
341848b8605Smrgvoid i915_set_flush_dirty(struct i915_context *i915, unsigned flush)
342848b8605Smrg{
343848b8605Smrg   i915->hardware_dirty |= I915_HW_FLUSH;
344848b8605Smrg   i915->flush_dirty |= flush;
345848b8605Smrg}
346848b8605Smrg
347848b8605Smrg
348848b8605Smrg/***********************************************************************
349848b8605Smrg * i915_prim_emit.c:
350848b8605Smrg */
351848b8605Smrgstruct draw_stage *i915_draw_render_stage( struct i915_context *i915 );
352848b8605Smrg
353848b8605Smrg
354848b8605Smrg/***********************************************************************
355848b8605Smrg * i915_prim_vbuf.c:
356848b8605Smrg */
357848b8605Smrgstruct draw_stage *i915_draw_vbuf_stage( struct i915_context *i915 );
358848b8605Smrg
359848b8605Smrg
360848b8605Smrg/***********************************************************************
361848b8605Smrg * i915_state.c:
362848b8605Smrg */
363848b8605Smrgvoid i915_prepare_vertex_sampling(struct i915_context *i915);
364848b8605Smrgvoid i915_cleanup_vertex_sampling(struct i915_context *i915);
365848b8605Smrg
366848b8605Smrg
367848b8605Smrg
368848b8605Smrg/***********************************************************************
369848b8605Smrg * i915_state_emit.c:
370848b8605Smrg */
371848b8605Smrgvoid i915_emit_hardware_state(struct i915_context *i915 );
372848b8605Smrg
373848b8605Smrg
374848b8605Smrg
375848b8605Smrg/***********************************************************************
376848b8605Smrg * i915_clear.c:
377848b8605Smrg */
378848b8605Smrgvoid i915_clear_blitter(struct pipe_context *pipe, unsigned buffers,
379848b8605Smrg                        const union pipe_color_union *color,
380848b8605Smrg                        double depth, unsigned stencil);
381848b8605Smrgvoid i915_clear_render(struct pipe_context *pipe, unsigned buffers,
382848b8605Smrg                       const union pipe_color_union *color,
383848b8605Smrg                       double depth, unsigned stencil);
384848b8605Smrgvoid i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
385848b8605Smrg                     const union pipe_color_union *color,
386848b8605Smrg                     double depth, unsigned stencil,
387848b8605Smrg                     unsigned destx, unsigned desty, unsigned width, unsigned height);
388848b8605Smrg
389848b8605Smrg
390848b8605Smrg/***********************************************************************
391848b8605Smrg *
392848b8605Smrg */
393848b8605Smrgvoid i915_init_state_functions( struct i915_context *i915 );
394848b8605Smrgvoid i915_init_flush_functions( struct i915_context *i915 );
395848b8605Smrgvoid i915_init_string_functions( struct i915_context *i915 );
396848b8605Smrg
397848b8605Smrg
398848b8605Smrg/************************************************************************
399848b8605Smrg * i915_context.c
400848b8605Smrg */
401848b8605Smrgstruct pipe_context *i915_create_context(struct pipe_screen *screen,
402b8e80941Smrg					 void *priv, unsigned flags);
403848b8605Smrg
404848b8605Smrg
405848b8605Smrg/***********************************************************************
406848b8605Smrg * Inline conversion functions.  These are better-typed than the
407848b8605Smrg * macros used previously:
408848b8605Smrg */
409b8e80941Smrgstatic inline struct i915_context *
410848b8605Smrgi915_context( struct pipe_context *pipe )
411848b8605Smrg{
412848b8605Smrg   return (struct i915_context *)pipe;
413848b8605Smrg}
414848b8605Smrg
415848b8605Smrg
416848b8605Smrg#endif
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