1848b8605Smrg#ifndef __NOUVEAU_SCREEN_H__
2848b8605Smrg#define __NOUVEAU_SCREEN_H__
3848b8605Smrg
4848b8605Smrg#include "pipe/p_screen.h"
5b8e80941Smrg#include "util/disk_cache.h"
6b8e80941Smrg#include "util/u_atomic.h"
7848b8605Smrg#include "util/u_memory.h"
8848b8605Smrg
9848b8605Smrg#ifdef DEBUG
10848b8605Smrg# define NOUVEAU_ENABLE_DRIVER_STATISTICS
11848b8605Smrg#endif
12848b8605Smrg
13848b8605Smrgtypedef uint32_t u32;
14848b8605Smrgtypedef uint16_t u16;
15848b8605Smrg
16848b8605Smrgextern int nouveau_mesa_debug;
17848b8605Smrg
18848b8605Smrgstruct nouveau_bo;
19848b8605Smrg
20b8e80941Smrg#define NOUVEAU_SHADER_CACHE_FLAGS_IR_TGSI 0 << 0
21b8e80941Smrg#define NOUVEAU_SHADER_CACHE_FLAGS_IR_NIR  1 << 0
22b8e80941Smrg
23848b8605Smrgstruct nouveau_screen {
24b8e80941Smrg   struct pipe_screen base;
25b8e80941Smrg   struct nouveau_drm *drm;
26b8e80941Smrg   struct nouveau_device *device;
27b8e80941Smrg   struct nouveau_object *channel;
28b8e80941Smrg   struct nouveau_client *client;
29b8e80941Smrg   struct nouveau_pushbuf *pushbuf;
30b8e80941Smrg
31b8e80941Smrg   int refcount;
32b8e80941Smrg
33b8e80941Smrg   unsigned transfer_pushbuf_threshold;
34b8e80941Smrg
35b8e80941Smrg   unsigned vidmem_bindings; /* PIPE_BIND_* where VRAM placement is desired */
36b8e80941Smrg   unsigned sysmem_bindings; /* PIPE_BIND_* where GART placement is desired */
37b8e80941Smrg   unsigned lowmem_bindings; /* PIPE_BIND_* that require an address < 4 GiB */
38b8e80941Smrg   /*
39b8e80941Smrg    * For bindings with (vidmem & sysmem) bits set, PIPE_USAGE_* decides
40b8e80941Smrg    * placement.
41b8e80941Smrg    */
42b8e80941Smrg
43b8e80941Smrg   uint16_t class_3d;
44b8e80941Smrg
45b8e80941Smrg   struct {
46b8e80941Smrg      struct nouveau_fence *head;
47b8e80941Smrg      struct nouveau_fence *tail;
48b8e80941Smrg      struct nouveau_fence *current;
49b8e80941Smrg      u32 sequence;
50b8e80941Smrg      u32 sequence_ack;
51b8e80941Smrg      void (*emit)(struct pipe_screen *, u32 *sequence);
52b8e80941Smrg      u32  (*update)(struct pipe_screen *);
53b8e80941Smrg   } fence;
54b8e80941Smrg
55b8e80941Smrg   struct nouveau_mman *mm_VRAM;
56b8e80941Smrg   struct nouveau_mman *mm_GART;
57b8e80941Smrg
58b8e80941Smrg   int64_t cpu_gpu_time_delta;
59b8e80941Smrg
60b8e80941Smrg   bool hint_buf_keep_sysmem_copy;
61b8e80941Smrg
62b8e80941Smrg   unsigned vram_domain;
63b8e80941Smrg
64b8e80941Smrg   struct {
65b8e80941Smrg      unsigned profiles_checked;
66b8e80941Smrg      unsigned profiles_present;
67b8e80941Smrg   } firmware_info;
68b8e80941Smrg
69b8e80941Smrg   struct disk_cache *disk_shader_cache;
70b8e80941Smrg
71b8e80941Smrg   bool prefer_nir;
72848b8605Smrg
73848b8605Smrg#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
74848b8605Smrg   union {
75848b8605Smrg      uint64_t v[29];
76848b8605Smrg      struct {
77848b8605Smrg         uint64_t tex_obj_current_count;
78848b8605Smrg         uint64_t tex_obj_current_bytes;
79848b8605Smrg         uint64_t buf_obj_current_count;
80848b8605Smrg         uint64_t buf_obj_current_bytes_vid;
81848b8605Smrg         uint64_t buf_obj_current_bytes_sys;
82848b8605Smrg         uint64_t tex_transfers_rd;
83848b8605Smrg         uint64_t tex_transfers_wr;
84848b8605Smrg         uint64_t tex_copy_count;
85848b8605Smrg         uint64_t tex_blit_count;
86848b8605Smrg         uint64_t tex_cache_flush_count;
87848b8605Smrg         uint64_t buf_transfers_rd;
88848b8605Smrg         uint64_t buf_transfers_wr;
89848b8605Smrg         uint64_t buf_read_bytes_staging_vid;
90848b8605Smrg         uint64_t buf_write_bytes_direct;
91848b8605Smrg         uint64_t buf_write_bytes_staging_vid;
92848b8605Smrg         uint64_t buf_write_bytes_staging_sys;
93848b8605Smrg         uint64_t buf_copy_bytes;
94848b8605Smrg         uint64_t buf_non_kernel_fence_sync_count;
95848b8605Smrg         uint64_t any_non_kernel_fence_sync_count;
96848b8605Smrg         uint64_t query_sync_count;
97848b8605Smrg         uint64_t gpu_serialize_count;
98848b8605Smrg         uint64_t draw_calls_array;
99848b8605Smrg         uint64_t draw_calls_indexed;
100848b8605Smrg         uint64_t draw_calls_fallback_count;
101848b8605Smrg         uint64_t user_buffer_upload_bytes;
102848b8605Smrg         uint64_t constbuf_upload_count;
103848b8605Smrg         uint64_t constbuf_upload_bytes;
104848b8605Smrg         uint64_t pushbuf_count;
105848b8605Smrg         uint64_t resource_validate_count;
106848b8605Smrg      } named;
107848b8605Smrg   } stats;
108848b8605Smrg#endif
109848b8605Smrg};
110848b8605Smrg
111b8e80941Smrg#define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain)
112b8e80941Smrg
113848b8605Smrg#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
114848b8605Smrg# define NOUVEAU_DRV_STAT(s, n, v) do {         \
115b8e80941Smrg      p_atomic_add(&(s)->stats.named.n, (v));   \
116848b8605Smrg   } while(0)
117b8e80941Smrg# define NOUVEAU_DRV_STAT_RES(r, n, v) do {                                \
118b8e80941Smrg      p_atomic_add(&nouveau_screen((r)->base.screen)->stats.named.n, v);   \
119848b8605Smrg   } while(0)
120848b8605Smrg# define NOUVEAU_DRV_STAT_IFD(x) x
121848b8605Smrg#else
122848b8605Smrg# define NOUVEAU_DRV_STAT(s, n, v)     do { } while(0)
123848b8605Smrg# define NOUVEAU_DRV_STAT_RES(r, n, v) do { } while(0)
124848b8605Smrg# define NOUVEAU_DRV_STAT_IFD(x)
125848b8605Smrg#endif
126848b8605Smrg
127b8e80941Smrgstatic inline struct nouveau_screen *
128848b8605Smrgnouveau_screen(struct pipe_screen *pscreen)
129848b8605Smrg{
130b8e80941Smrg   return (struct nouveau_screen *)pscreen;
131848b8605Smrg}
132848b8605Smrg
133b8e80941Smrgbool nouveau_drm_screen_unref(struct nouveau_screen *screen);
134848b8605Smrg
135b8e80941Smrgbool
136848b8605Smrgnouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
137b8e80941Smrg                             struct nouveau_bo *bo,
138b8e80941Smrg                             unsigned stride,
139b8e80941Smrg                             struct winsys_handle *whandle);
140848b8605Smrgstruct nouveau_bo *
141848b8605Smrgnouveau_screen_bo_from_handle(struct pipe_screen *pscreen,
142b8e80941Smrg                              struct winsys_handle *whandle,
143b8e80941Smrg                              unsigned *out_stride);
144848b8605Smrg
145848b8605Smrg
146848b8605Smrgint nouveau_screen_init(struct nouveau_screen *, struct nouveau_device *);
147848b8605Smrgvoid nouveau_screen_fini(struct nouveau_screen *);
148848b8605Smrg
149848b8605Smrgvoid nouveau_screen_init_vdec(struct nouveau_screen *);
150848b8605Smrg
151848b8605Smrg#endif
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