r700_asm.c revision 848b8605 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_asm.h"
24#include "r700_sq.h"
25
26void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
27{
28	unsigned count = (cf->ndw / 4) - 1;
29	*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
30	*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
31			S_SQ_CF_WORD1_BARRIER(1) |
32			S_SQ_CF_WORD1_COUNT(count) |
33			S_SQ_CF_WORD1_COUNT_3(count >> 3);
34}
35
36int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
37{
38	bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
39		S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
40		S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
41		S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
42		S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
43		S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
44		S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
45		S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
46		S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
47		S_SQ_ALU_WORD0_LAST(alu->last);
48
49	/* don't replace gpr by pv or ps for destination register */
50	if (alu->is_op3) {
51		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
52					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
53			                S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
54			                S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
55					S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
56					S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
57					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
58					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
59					S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
60					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
61	} else {
62		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
63					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
64			                S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
65			                S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
66					S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
67					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
68					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
69					S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
70					S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
71					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
72			                S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
73			                S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
74	}
75	return 0;
76}
77
78void r700_bytecode_alu_read(struct r600_bytecode *bc,
79		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
80{
81	/* WORD0 */
82	alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
83	alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
84	alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
85	alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
86	alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
87	alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
88	alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
89	alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
90	alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
91	alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
92	alu->last = G_SQ_ALU_WORD0_LAST(word0);
93
94	/* WORD1 */
95	alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
96	if (alu->bank_swizzle)
97		alu->bank_swizzle_force = alu->bank_swizzle;
98	alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
99	alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
100	alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
101	alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
102	if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
103	{
104		alu->is_op3 = 1;
105		alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
106		alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
107		alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
108		alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
109		alu->op = r600_isa_alu_by_opcode(bc->isa,
110				G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1);
111	}
112	else /*ALU_DWORD1_OP2*/
113	{
114		alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
115		alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
116		alu->op = r600_isa_alu_by_opcode(bc->isa,
117				G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0);
118		alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
119		alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
120		alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
121		alu->execute_mask =
122			G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
123	}
124}
125