1b8e80941Smrg/* 2b8e80941Smrg * Copyright © 2011 Intel Corporation 3b8e80941Smrg * 4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 6b8e80941Smrg * to deal in the Software without restriction, including without limitation 7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 9b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 10b8e80941Smrg * 11b8e80941Smrg * The above copyright notice and this permission notice (including the next 12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 13b8e80941Smrg * Software. 14b8e80941Smrg * 15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21b8e80941Smrg * IN THE SOFTWARE. 22b8e80941Smrg */ 23b8e80941Smrg 24b8e80941Smrg/** 25b8e80941Smrg * @file brw_vue_map.c 26b8e80941Smrg * 27b8e80941Smrg * This file computes the "VUE map" for a (non-fragment) shader stage, which 28b8e80941Smrg * describes the layout of its output varyings. The VUE map is used to match 29b8e80941Smrg * outputs from one stage with the inputs of the next. 30b8e80941Smrg * 31b8e80941Smrg * Largely, varyings can be placed however we like - producers/consumers simply 32b8e80941Smrg * have to agree on the layout. However, there is also a "VUE Header" that 33b8e80941Smrg * prescribes a fixed-layout for items that interact with fixed function 34b8e80941Smrg * hardware, such as the clipper and rasterizer. 35b8e80941Smrg * 36b8e80941Smrg * Authors: 37b8e80941Smrg * Paul Berry <stereotype441@gmail.com> 38b8e80941Smrg * Chris Forbes <chrisf@ijw.co.nz> 39b8e80941Smrg * Eric Anholt <eric@anholt.net> 40b8e80941Smrg */ 41b8e80941Smrg 42b8e80941Smrg 43b8e80941Smrg#include "brw_compiler.h" 44b8e80941Smrg#include "dev/gen_debug.h" 45b8e80941Smrg 46b8e80941Smrgstatic inline void 47b8e80941Smrgassign_vue_slot(struct brw_vue_map *vue_map, int varying, int slot) 48b8e80941Smrg{ 49b8e80941Smrg /* Make sure this varying hasn't been assigned a slot already */ 50b8e80941Smrg assert (vue_map->varying_to_slot[varying] == -1); 51b8e80941Smrg 52b8e80941Smrg vue_map->varying_to_slot[varying] = slot; 53b8e80941Smrg vue_map->slot_to_varying[slot] = varying; 54b8e80941Smrg} 55b8e80941Smrg 56b8e80941Smrg/** 57b8e80941Smrg * Compute the VUE map for a shader stage. 58b8e80941Smrg */ 59b8e80941Smrgvoid 60b8e80941Smrgbrw_compute_vue_map(const struct gen_device_info *devinfo, 61b8e80941Smrg struct brw_vue_map *vue_map, 62b8e80941Smrg uint64_t slots_valid, 63b8e80941Smrg bool separate) 64b8e80941Smrg{ 65b8e80941Smrg /* Keep using the packed/contiguous layout on old hardware - we only need 66b8e80941Smrg * the SSO layout when using geometry/tessellation shaders or 32 FS input 67b8e80941Smrg * varyings, which only exist on Gen >= 6. It's also a bit more efficient. 68b8e80941Smrg */ 69b8e80941Smrg if (devinfo->gen < 6) 70b8e80941Smrg separate = false; 71b8e80941Smrg 72b8e80941Smrg if (separate) { 73b8e80941Smrg /* In SSO mode, we don't know whether the adjacent stage will 74b8e80941Smrg * read/write gl_ClipDistance, which has a fixed slot location. 75b8e80941Smrg * We have to assume the worst and reserve a slot for it, or else 76b8e80941Smrg * the rest of our varyings will be off by a slot. 77b8e80941Smrg * 78b8e80941Smrg * Note that we don't have to worry about COL/BFC, as those built-in 79b8e80941Smrg * variables only exist in legacy GL, which only supports VS and FS. 80b8e80941Smrg */ 81b8e80941Smrg slots_valid |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0); 82b8e80941Smrg slots_valid |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1); 83b8e80941Smrg } 84b8e80941Smrg 85b8e80941Smrg vue_map->slots_valid = slots_valid; 86b8e80941Smrg vue_map->separate = separate; 87b8e80941Smrg 88b8e80941Smrg /* gl_Layer and gl_ViewportIndex don't get their own varying slots -- they 89b8e80941Smrg * are stored in the first VUE slot (VARYING_SLOT_PSIZ). 90b8e80941Smrg */ 91b8e80941Smrg slots_valid &= ~(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT); 92b8e80941Smrg 93b8e80941Smrg /* Make sure that the values we store in vue_map->varying_to_slot and 94b8e80941Smrg * vue_map->slot_to_varying won't overflow the signed chars that are used 95b8e80941Smrg * to store them. Note that since vue_map->slot_to_varying sometimes holds 96b8e80941Smrg * values equal to BRW_VARYING_SLOT_COUNT, we need to ensure that 97b8e80941Smrg * BRW_VARYING_SLOT_COUNT is <= 127, not 128. 98b8e80941Smrg */ 99b8e80941Smrg STATIC_ASSERT(BRW_VARYING_SLOT_COUNT <= 127); 100b8e80941Smrg 101b8e80941Smrg for (int i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) { 102b8e80941Smrg vue_map->varying_to_slot[i] = -1; 103b8e80941Smrg vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_PAD; 104b8e80941Smrg } 105b8e80941Smrg 106b8e80941Smrg int slot = 0; 107b8e80941Smrg 108b8e80941Smrg /* VUE header: format depends on chip generation and whether clipping is 109b8e80941Smrg * enabled. 110b8e80941Smrg * 111b8e80941Smrg * See the Sandybridge PRM, Volume 2 Part 1, section 1.5.1 (page 30), 112b8e80941Smrg * "Vertex URB Entry (VUE) Formats" which describes the VUE header layout. 113b8e80941Smrg */ 114b8e80941Smrg if (devinfo->gen < 6) { 115b8e80941Smrg /* There are 8 dwords in VUE header pre-Ironlake: 116b8e80941Smrg * dword 0-3 is indices, point width, clip flags. 117b8e80941Smrg * dword 4-7 is ndc position 118b8e80941Smrg * dword 8-11 is the first vertex data. 119b8e80941Smrg * 120b8e80941Smrg * On Ironlake the VUE header is nominally 20 dwords, but the hardware 121b8e80941Smrg * will accept the same header layout as Gen4 [and should be a bit faster] 122b8e80941Smrg */ 123b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_PSIZ, slot++); 124b8e80941Smrg assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC, slot++); 125b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_POS, slot++); 126b8e80941Smrg } else { 127b8e80941Smrg /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge: 128b8e80941Smrg * dword 0-3 of the header is indices, point width, clip flags. 129b8e80941Smrg * dword 4-7 is the 4D space position 130b8e80941Smrg * dword 8-15 of the vertex header is the user clip distance if 131b8e80941Smrg * enabled. 132b8e80941Smrg * dword 8-11 or 16-19 is the first vertex element data we fill. 133b8e80941Smrg */ 134b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_PSIZ, slot++); 135b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_POS, slot++); 136b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0)) 137b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0, slot++); 138b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1)) 139b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1, slot++); 140b8e80941Smrg 141b8e80941Smrg /* front and back colors need to be consecutive so that we can use 142b8e80941Smrg * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing 143b8e80941Smrg * two-sided color. 144b8e80941Smrg */ 145b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0)) 146b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_COL0, slot++); 147b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0)) 148b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_BFC0, slot++); 149b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1)) 150b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_COL1, slot++); 151b8e80941Smrg if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1)) 152b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_BFC1, slot++); 153b8e80941Smrg } 154b8e80941Smrg 155b8e80941Smrg /* The hardware doesn't care about the rest of the vertex outputs, so we 156b8e80941Smrg * can assign them however we like. For normal programs, we simply assign 157b8e80941Smrg * them contiguously. 158b8e80941Smrg * 159b8e80941Smrg * For separate shader pipelines, we first assign built-in varyings 160b8e80941Smrg * contiguous slots. This works because ARB_separate_shader_objects 161b8e80941Smrg * requires that all shaders have matching built-in varying interface 162b8e80941Smrg * blocks. Next, we assign generic varyings based on their location 163b8e80941Smrg * (either explicit or linker assigned). This guarantees a fixed layout. 164b8e80941Smrg * 165b8e80941Smrg * We generally don't need to assign a slot for VARYING_SLOT_CLIP_VERTEX, 166b8e80941Smrg * since it's encoded as the clip distances by emit_clip_distances(). 167b8e80941Smrg * However, it may be output by transform feedback, and we'd rather not 168b8e80941Smrg * recompute state when TF changes, so we just always include it. 169b8e80941Smrg */ 170b8e80941Smrg uint64_t builtins = slots_valid & BITFIELD64_MASK(VARYING_SLOT_VAR0); 171b8e80941Smrg while (builtins != 0) { 172b8e80941Smrg const int varying = ffsll(builtins) - 1; 173b8e80941Smrg if (vue_map->varying_to_slot[varying] == -1) { 174b8e80941Smrg assign_vue_slot(vue_map, varying, slot++); 175b8e80941Smrg } 176b8e80941Smrg builtins &= ~BITFIELD64_BIT(varying); 177b8e80941Smrg } 178b8e80941Smrg 179b8e80941Smrg const int first_generic_slot = slot; 180b8e80941Smrg uint64_t generics = slots_valid & ~BITFIELD64_MASK(VARYING_SLOT_VAR0); 181b8e80941Smrg while (generics != 0) { 182b8e80941Smrg const int varying = ffsll(generics) - 1; 183b8e80941Smrg if (separate) { 184b8e80941Smrg slot = first_generic_slot + varying - VARYING_SLOT_VAR0; 185b8e80941Smrg } 186b8e80941Smrg assign_vue_slot(vue_map, varying, slot++); 187b8e80941Smrg generics &= ~BITFIELD64_BIT(varying); 188b8e80941Smrg } 189b8e80941Smrg 190b8e80941Smrg vue_map->num_slots = slot; 191b8e80941Smrg vue_map->num_per_vertex_slots = 0; 192b8e80941Smrg vue_map->num_per_patch_slots = 0; 193b8e80941Smrg} 194b8e80941Smrg 195b8e80941Smrg/** 196b8e80941Smrg * Compute the VUE map for tessellation control shader outputs and 197b8e80941Smrg * tessellation evaluation shader inputs. 198b8e80941Smrg */ 199b8e80941Smrgvoid 200b8e80941Smrgbrw_compute_tess_vue_map(struct brw_vue_map *vue_map, 201b8e80941Smrg uint64_t vertex_slots, 202b8e80941Smrg uint32_t patch_slots) 203b8e80941Smrg{ 204b8e80941Smrg /* I don't think anything actually uses this... */ 205b8e80941Smrg vue_map->slots_valid = vertex_slots; 206b8e80941Smrg 207b8e80941Smrg /* separate isn't really meaningful, but make sure it's initialized */ 208b8e80941Smrg vue_map->separate = false; 209b8e80941Smrg 210b8e80941Smrg vertex_slots &= ~(VARYING_BIT_TESS_LEVEL_OUTER | 211b8e80941Smrg VARYING_BIT_TESS_LEVEL_INNER); 212b8e80941Smrg 213b8e80941Smrg /* Make sure that the values we store in vue_map->varying_to_slot and 214b8e80941Smrg * vue_map->slot_to_varying won't overflow the signed chars that are used 215b8e80941Smrg * to store them. Note that since vue_map->slot_to_varying sometimes holds 216b8e80941Smrg * values equal to VARYING_SLOT_TESS_MAX , we need to ensure that 217b8e80941Smrg * VARYING_SLOT_TESS_MAX is <= 127, not 128. 218b8e80941Smrg */ 219b8e80941Smrg STATIC_ASSERT(VARYING_SLOT_TESS_MAX <= 127); 220b8e80941Smrg 221b8e80941Smrg for (int i = 0; i < VARYING_SLOT_TESS_MAX ; ++i) { 222b8e80941Smrg vue_map->varying_to_slot[i] = -1; 223b8e80941Smrg vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_PAD; 224b8e80941Smrg } 225b8e80941Smrg 226b8e80941Smrg int slot = 0; 227b8e80941Smrg 228b8e80941Smrg /* The first 8 DWords are reserved for the "Patch Header". 229b8e80941Smrg * 230b8e80941Smrg * VARYING_SLOT_TESS_LEVEL_OUTER / INNER live here, but the exact layout 231b8e80941Smrg * depends on the domain type. They might not be in slots 0 and 1 as 232b8e80941Smrg * described here, but pretending they're separate allows us to uniquely 233b8e80941Smrg * identify them by distinct slot locations. 234b8e80941Smrg */ 235b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_TESS_LEVEL_INNER, slot++); 236b8e80941Smrg assign_vue_slot(vue_map, VARYING_SLOT_TESS_LEVEL_OUTER, slot++); 237b8e80941Smrg 238b8e80941Smrg /* first assign per-patch varyings */ 239b8e80941Smrg while (patch_slots != 0) { 240b8e80941Smrg const int varying = ffsll(patch_slots) - 1; 241b8e80941Smrg if (vue_map->varying_to_slot[varying + VARYING_SLOT_PATCH0] == -1) { 242b8e80941Smrg assign_vue_slot(vue_map, varying + VARYING_SLOT_PATCH0, slot++); 243b8e80941Smrg } 244b8e80941Smrg patch_slots &= ~BITFIELD64_BIT(varying); 245b8e80941Smrg } 246b8e80941Smrg 247b8e80941Smrg /* apparently, including the patch header... */ 248b8e80941Smrg vue_map->num_per_patch_slots = slot; 249b8e80941Smrg 250b8e80941Smrg /* then assign per-vertex varyings for each vertex in our patch */ 251b8e80941Smrg while (vertex_slots != 0) { 252b8e80941Smrg const int varying = ffsll(vertex_slots) - 1; 253b8e80941Smrg if (vue_map->varying_to_slot[varying] == -1) { 254b8e80941Smrg assign_vue_slot(vue_map, varying, slot++); 255b8e80941Smrg } 256b8e80941Smrg vertex_slots &= ~BITFIELD64_BIT(varying); 257b8e80941Smrg } 258b8e80941Smrg 259b8e80941Smrg vue_map->num_per_vertex_slots = slot - vue_map->num_per_patch_slots; 260b8e80941Smrg vue_map->num_slots = slot; 261b8e80941Smrg} 262b8e80941Smrg 263b8e80941Smrgstatic const char * 264b8e80941Smrgvarying_name(brw_varying_slot slot) 265b8e80941Smrg{ 266b8e80941Smrg assume(slot < BRW_VARYING_SLOT_COUNT); 267b8e80941Smrg 268b8e80941Smrg if (slot < VARYING_SLOT_MAX) 269b8e80941Smrg return gl_varying_slot_name((gl_varying_slot) slot); 270b8e80941Smrg 271b8e80941Smrg static const char *brw_names[] = { 272b8e80941Smrg [BRW_VARYING_SLOT_NDC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_NDC", 273b8e80941Smrg [BRW_VARYING_SLOT_PAD - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PAD", 274b8e80941Smrg [BRW_VARYING_SLOT_PNTC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PNTC", 275b8e80941Smrg }; 276b8e80941Smrg 277b8e80941Smrg return brw_names[slot - VARYING_SLOT_MAX]; 278b8e80941Smrg} 279b8e80941Smrg 280b8e80941Smrgvoid 281b8e80941Smrgbrw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map) 282b8e80941Smrg{ 283b8e80941Smrg if (vue_map->num_per_vertex_slots > 0 || vue_map->num_per_patch_slots > 0) { 284b8e80941Smrg fprintf(fp, "PUE map (%d slots, %d/patch, %d/vertex, %s)\n", 285b8e80941Smrg vue_map->num_slots, 286b8e80941Smrg vue_map->num_per_patch_slots, 287b8e80941Smrg vue_map->num_per_vertex_slots, 288b8e80941Smrg vue_map->separate ? "SSO" : "non-SSO"); 289b8e80941Smrg for (int i = 0; i < vue_map->num_slots; i++) { 290b8e80941Smrg if (vue_map->slot_to_varying[i] >= VARYING_SLOT_PATCH0) { 291b8e80941Smrg fprintf(fp, " [%d] VARYING_SLOT_PATCH%d\n", i, 292b8e80941Smrg vue_map->slot_to_varying[i] - VARYING_SLOT_PATCH0); 293b8e80941Smrg } else { 294b8e80941Smrg fprintf(fp, " [%d] %s\n", i, 295b8e80941Smrg varying_name(vue_map->slot_to_varying[i])); 296b8e80941Smrg } 297b8e80941Smrg } 298b8e80941Smrg } else { 299b8e80941Smrg fprintf(fp, "VUE map (%d slots, %s)\n", 300b8e80941Smrg vue_map->num_slots, vue_map->separate ? "SSO" : "non-SSO"); 301b8e80941Smrg for (int i = 0; i < vue_map->num_slots; i++) { 302b8e80941Smrg fprintf(fp, " [%d] %s\n", i, 303b8e80941Smrg varying_name(vue_map->slot_to_varying[i])); 304b8e80941Smrg } 305b8e80941Smrg } 306b8e80941Smrg fprintf(fp, "\n"); 307b8e80941Smrg} 308