1b8e80941Smrg/*
2b8e80941Smrg * Copyright © 2012 Intel Corporation
3b8e80941Smrg *
4b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5b8e80941Smrg * copy of this software and associated documentation files (the "Software"),
6b8e80941Smrg * to deal in the Software without restriction, including without limitation
7b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the
9b8e80941Smrg * Software is furnished to do so, subject to the following conditions:
10b8e80941Smrg *
11b8e80941Smrg * The above copyright notice and this permission notice (including the next
12b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the
13b8e80941Smrg * Software.
14b8e80941Smrg *
15b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21b8e80941Smrg * IN THE SOFTWARE.
22b8e80941Smrg */
23b8e80941Smrg
24b8e80941Smrg#include <stdlib.h>
25b8e80941Smrg#include <stdio.h>
26b8e80941Smrg#include <stdbool.h>
27b8e80941Smrg#include "util/ralloc.h"
28b8e80941Smrg#include "brw_eu.h"
29b8e80941Smrg
30b8e80941Smrgstatic bool
31b8e80941Smrgtest_compact_instruction(struct brw_codegen *p, brw_inst src)
32b8e80941Smrg{
33b8e80941Smrg   brw_compact_inst dst;
34b8e80941Smrg   memset(&dst, 0xd0, sizeof(dst));
35b8e80941Smrg
36b8e80941Smrg   if (brw_try_compact_instruction(p->devinfo, &dst, &src)) {
37b8e80941Smrg      brw_inst uncompacted;
38b8e80941Smrg
39b8e80941Smrg      brw_uncompact_instruction(p->devinfo, &uncompacted, &dst);
40b8e80941Smrg      if (memcmp(&uncompacted, &src, sizeof(src))) {
41b8e80941Smrg	 brw_debug_compact_uncompact(p->devinfo, &src, &uncompacted);
42b8e80941Smrg	 return false;
43b8e80941Smrg      }
44b8e80941Smrg   } else {
45b8e80941Smrg      brw_compact_inst unchanged;
46b8e80941Smrg      memset(&unchanged, 0xd0, sizeof(unchanged));
47b8e80941Smrg      /* It's not supposed to change dst unless it compacted. */
48b8e80941Smrg      if (memcmp(&unchanged, &dst, sizeof(dst))) {
49b8e80941Smrg	 fprintf(stderr, "Failed to compact, but dst changed\n");
50b8e80941Smrg	 fprintf(stderr, "  Instruction: ");
51b8e80941Smrg	 brw_disassemble_inst(stderr, p->devinfo, &src, false);
52b8e80941Smrg	 return false;
53b8e80941Smrg      }
54b8e80941Smrg   }
55b8e80941Smrg
56b8e80941Smrg   return true;
57b8e80941Smrg}
58b8e80941Smrg
59b8e80941Smrg/**
60b8e80941Smrg * When doing fuzz testing, pad bits won't round-trip.
61b8e80941Smrg *
62b8e80941Smrg * This sort of a superset of skip_bit, which is testing for changing bits that
63b8e80941Smrg * aren't worth testing for fuzzing.  We also just want to clear bits that
64b8e80941Smrg * become meaningless once fuzzing twiddles a related bit.
65b8e80941Smrg */
66b8e80941Smrgstatic void
67b8e80941Smrgclear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
68b8e80941Smrg{
69b8e80941Smrg   if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND &&
70b8e80941Smrg       brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC &&
71b8e80941Smrg       brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
72b8e80941Smrg       brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
73b8e80941Smrg      brw_inst_set_bits(inst, 127, 111, 0);
74b8e80941Smrg   }
75b8e80941Smrg
76b8e80941Smrg   if (devinfo->gen == 8 && !devinfo->is_cherryview &&
77b8e80941Smrg       is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, inst))) {
78b8e80941Smrg      brw_inst_set_bits(inst, 105, 105, 0);
79b8e80941Smrg      brw_inst_set_bits(inst, 84, 84, 0);
80b8e80941Smrg      brw_inst_set_bits(inst, 36, 35, 0);
81b8e80941Smrg   }
82b8e80941Smrg}
83b8e80941Smrg
84b8e80941Smrgstatic bool
85b8e80941Smrgskip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
86b8e80941Smrg{
87b8e80941Smrg   /* pad bit */
88b8e80941Smrg   if (bit == 7)
89b8e80941Smrg      return true;
90b8e80941Smrg
91b8e80941Smrg   /* The compact bit -- uncompacted can't have it set. */
92b8e80941Smrg   if (bit == 29)
93b8e80941Smrg      return true;
94b8e80941Smrg
95b8e80941Smrg   if (is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, src))) {
96b8e80941Smrg      if (devinfo->gen >= 9 || devinfo->is_cherryview) {
97b8e80941Smrg         if (bit == 127)
98b8e80941Smrg            return true;
99b8e80941Smrg      } else {
100b8e80941Smrg         if (bit >= 126 && bit <= 127)
101b8e80941Smrg            return true;
102b8e80941Smrg
103b8e80941Smrg         if (bit == 105)
104b8e80941Smrg            return true;
105b8e80941Smrg
106b8e80941Smrg         if (bit == 84)
107b8e80941Smrg            return true;
108b8e80941Smrg
109b8e80941Smrg         if (bit >= 35 && bit <= 36)
110b8e80941Smrg            return true;
111b8e80941Smrg      }
112b8e80941Smrg   } else {
113b8e80941Smrg      if (bit == 47)
114b8e80941Smrg         return true;
115b8e80941Smrg
116b8e80941Smrg      if (devinfo->gen >= 8) {
117b8e80941Smrg         if (bit == 11)
118b8e80941Smrg            return true;
119b8e80941Smrg
120b8e80941Smrg         if (bit == 95)
121b8e80941Smrg            return true;
122b8e80941Smrg      } else {
123b8e80941Smrg         if (devinfo->gen < 7 && bit == 90)
124b8e80941Smrg            return true;
125b8e80941Smrg
126b8e80941Smrg         if (bit >= 91 && bit <= 95)
127b8e80941Smrg            return true;
128b8e80941Smrg      }
129b8e80941Smrg   }
130b8e80941Smrg
131b8e80941Smrg   /* sometimes these are pad bits. */
132b8e80941Smrg   if (brw_inst_opcode(devinfo, src) != BRW_OPCODE_SEND &&
133b8e80941Smrg       brw_inst_opcode(devinfo, src) != BRW_OPCODE_SENDC &&
134b8e80941Smrg       brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
135b8e80941Smrg       brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
136b8e80941Smrg       bit >= 121) {
137b8e80941Smrg      return true;
138b8e80941Smrg   }
139b8e80941Smrg
140b8e80941Smrg   return false;
141b8e80941Smrg}
142b8e80941Smrg
143b8e80941Smrgstatic bool
144b8e80941Smrgtest_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
145b8e80941Smrg{
146b8e80941Smrg   for (int bit0 = 0; bit0 < 128; bit0++) {
147b8e80941Smrg      if (skip_bit(p->devinfo, &src, bit0))
148b8e80941Smrg	 continue;
149b8e80941Smrg
150b8e80941Smrg      for (int bit1 = 0; bit1 < 128; bit1++) {
151b8e80941Smrg         brw_inst instr = src;
152b8e80941Smrg	 uint64_t *bits = instr.data;
153b8e80941Smrg
154b8e80941Smrg         if (skip_bit(p->devinfo, &src, bit1))
155b8e80941Smrg	    continue;
156b8e80941Smrg
157b8e80941Smrg	 bits[bit0 / 64] ^= (1ull << (bit0 & 63));
158b8e80941Smrg	 bits[bit1 / 64] ^= (1ull << (bit1 & 63));
159b8e80941Smrg
160b8e80941Smrg         clear_pad_bits(p->devinfo, &instr);
161b8e80941Smrg
162b8e80941Smrg	 if (!test_compact_instruction(p, instr)) {
163b8e80941Smrg	    printf("  twiddled bits for fuzzing %d, %d\n", bit0, bit1);
164b8e80941Smrg	    return false;
165b8e80941Smrg	 }
166b8e80941Smrg      }
167b8e80941Smrg   }
168b8e80941Smrg
169b8e80941Smrg   return true;
170b8e80941Smrg}
171b8e80941Smrg
172b8e80941Smrgstatic void
173b8e80941Smrggen_ADD_GRF_GRF_GRF(struct brw_codegen *p)
174b8e80941Smrg{
175b8e80941Smrg   struct brw_reg g0 = brw_vec8_grf(0, 0);
176b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
177b8e80941Smrg   struct brw_reg g4 = brw_vec8_grf(4, 0);
178b8e80941Smrg
179b8e80941Smrg   brw_ADD(p, g0, g2, g4);
180b8e80941Smrg}
181b8e80941Smrg
182b8e80941Smrgstatic void
183b8e80941Smrggen_ADD_GRF_GRF_IMM(struct brw_codegen *p)
184b8e80941Smrg{
185b8e80941Smrg   struct brw_reg g0 = brw_vec8_grf(0, 0);
186b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
187b8e80941Smrg
188b8e80941Smrg   brw_ADD(p, g0, g2, brw_imm_f(1.0));
189b8e80941Smrg}
190b8e80941Smrg
191b8e80941Smrgstatic void
192b8e80941Smrggen_ADD_GRF_GRF_IMM_d(struct brw_codegen *p)
193b8e80941Smrg{
194b8e80941Smrg   struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
195b8e80941Smrg   struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
196b8e80941Smrg
197b8e80941Smrg   brw_ADD(p, g0, g2, brw_imm_d(1));
198b8e80941Smrg}
199b8e80941Smrg
200b8e80941Smrgstatic void
201b8e80941Smrggen_MOV_GRF_GRF(struct brw_codegen *p)
202b8e80941Smrg{
203b8e80941Smrg   struct brw_reg g0 = brw_vec8_grf(0, 0);
204b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
205b8e80941Smrg
206b8e80941Smrg   brw_MOV(p, g0, g2);
207b8e80941Smrg}
208b8e80941Smrg
209b8e80941Smrgstatic void
210b8e80941Smrggen_ADD_MRF_GRF_GRF(struct brw_codegen *p)
211b8e80941Smrg{
212b8e80941Smrg   struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
213b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
214b8e80941Smrg   struct brw_reg g4 = brw_vec8_grf(4, 0);
215b8e80941Smrg
216b8e80941Smrg   brw_ADD(p, m6, g2, g4);
217b8e80941Smrg}
218b8e80941Smrg
219b8e80941Smrgstatic void
220b8e80941Smrggen_ADD_vec1_GRF_GRF_GRF(struct brw_codegen *p)
221b8e80941Smrg{
222b8e80941Smrg   struct brw_reg g0 = brw_vec1_grf(0, 0);
223b8e80941Smrg   struct brw_reg g2 = brw_vec1_grf(2, 0);
224b8e80941Smrg   struct brw_reg g4 = brw_vec1_grf(4, 0);
225b8e80941Smrg
226b8e80941Smrg   brw_ADD(p, g0, g2, g4);
227b8e80941Smrg}
228b8e80941Smrg
229b8e80941Smrgstatic void
230b8e80941Smrggen_PLN_MRF_GRF_GRF(struct brw_codegen *p)
231b8e80941Smrg{
232b8e80941Smrg   struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
233b8e80941Smrg   struct brw_reg interp = brw_vec1_grf(2, 0);
234b8e80941Smrg   struct brw_reg g4 = brw_vec8_grf(4, 0);
235b8e80941Smrg
236b8e80941Smrg   brw_PLN(p, m6, interp, g4);
237b8e80941Smrg}
238b8e80941Smrg
239b8e80941Smrgstatic void
240b8e80941Smrggen_f0_0_MOV_GRF_GRF(struct brw_codegen *p)
241b8e80941Smrg{
242b8e80941Smrg   struct brw_reg g0 = brw_vec8_grf(0, 0);
243b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
244b8e80941Smrg
245b8e80941Smrg   brw_push_insn_state(p);
246b8e80941Smrg   brw_set_default_predicate_control(p, true);
247b8e80941Smrg   brw_MOV(p, g0, g2);
248b8e80941Smrg   brw_pop_insn_state(p);
249b8e80941Smrg}
250b8e80941Smrg
251b8e80941Smrg/* The handling of f0.1 vs f0.0 changes between gen6 and gen7.  Explicitly test
252b8e80941Smrg * it, so that we run the fuzzing can run over all the other bits that might
253b8e80941Smrg * interact with it.
254b8e80941Smrg */
255b8e80941Smrgstatic void
256b8e80941Smrggen_f0_1_MOV_GRF_GRF(struct brw_codegen *p)
257b8e80941Smrg{
258b8e80941Smrg   struct brw_reg g0 = brw_vec8_grf(0, 0);
259b8e80941Smrg   struct brw_reg g2 = brw_vec8_grf(2, 0);
260b8e80941Smrg
261b8e80941Smrg   brw_push_insn_state(p);
262b8e80941Smrg   brw_set_default_predicate_control(p, true);
263b8e80941Smrg   brw_inst *mov = brw_MOV(p, g0, g2);
264b8e80941Smrg   brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
265b8e80941Smrg   brw_pop_insn_state(p);
266b8e80941Smrg}
267b8e80941Smrg
268b8e80941Smrgstruct {
269b8e80941Smrg   void (*func)(struct brw_codegen *p);
270b8e80941Smrg} tests[] = {
271b8e80941Smrg   { gen_MOV_GRF_GRF },
272b8e80941Smrg   { gen_ADD_GRF_GRF_GRF },
273b8e80941Smrg   { gen_ADD_GRF_GRF_IMM },
274b8e80941Smrg   { gen_ADD_GRF_GRF_IMM_d },
275b8e80941Smrg   { gen_ADD_MRF_GRF_GRF },
276b8e80941Smrg   { gen_ADD_vec1_GRF_GRF_GRF },
277b8e80941Smrg   { gen_PLN_MRF_GRF_GRF },
278b8e80941Smrg   { gen_f0_0_MOV_GRF_GRF },
279b8e80941Smrg   { gen_f0_1_MOV_GRF_GRF },
280b8e80941Smrg};
281b8e80941Smrg
282b8e80941Smrgstatic bool
283b8e80941Smrgrun_tests(const struct gen_device_info *devinfo)
284b8e80941Smrg{
285b8e80941Smrg   brw_init_compaction_tables(devinfo);
286b8e80941Smrg   bool fail = false;
287b8e80941Smrg
288b8e80941Smrg   for (unsigned i = 0; i < ARRAY_SIZE(tests); i++) {
289b8e80941Smrg      for (int align_16 = 0; align_16 <= 1; align_16++) {
290b8e80941Smrg	 struct brw_codegen *p = rzalloc(NULL, struct brw_codegen);
291b8e80941Smrg	 brw_init_codegen(devinfo, p, p);
292b8e80941Smrg
293b8e80941Smrg	 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
294b8e80941Smrg	 if (align_16)
295b8e80941Smrg	    brw_set_default_access_mode(p, BRW_ALIGN_16);
296b8e80941Smrg	 else
297b8e80941Smrg	    brw_set_default_access_mode(p, BRW_ALIGN_1);
298b8e80941Smrg
299b8e80941Smrg	 tests[i].func(p);
300b8e80941Smrg	 assert(p->nr_insn == 1);
301b8e80941Smrg
302b8e80941Smrg	 if (!test_compact_instruction(p, p->store[0])) {
303b8e80941Smrg	    fail = true;
304b8e80941Smrg	    continue;
305b8e80941Smrg	 }
306b8e80941Smrg
307b8e80941Smrg	 if (!test_fuzz_compact_instruction(p, p->store[0])) {
308b8e80941Smrg	    fail = true;
309b8e80941Smrg	    continue;
310b8e80941Smrg	 }
311b8e80941Smrg
312b8e80941Smrg	 ralloc_free(p);
313b8e80941Smrg      }
314b8e80941Smrg   }
315b8e80941Smrg
316b8e80941Smrg   return fail;
317b8e80941Smrg}
318b8e80941Smrg
319b8e80941Smrgint
320b8e80941Smrgmain(int argc, char **argv)
321b8e80941Smrg{
322b8e80941Smrg   struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
323b8e80941Smrg   bool fail = false;
324b8e80941Smrg
325b8e80941Smrg   for (devinfo->gen = 5; devinfo->gen <= 9; devinfo->gen++) {
326b8e80941Smrg      fail |= run_tests(devinfo);
327b8e80941Smrg   }
328b8e80941Smrg
329b8e80941Smrg   return fail;
330b8e80941Smrg}
331