gen8_cmd_buffer.c revision b8e80941
1/* 2 * Copyright © 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <assert.h> 25#include <stdbool.h> 26#include <string.h> 27#include <unistd.h> 28#include <fcntl.h> 29 30#include "anv_private.h" 31 32#include "genxml/gen_macros.h" 33#include "genxml/genX_pack.h" 34 35#if GEN_GEN == 8 36void 37gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) 38{ 39 uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count; 40 const VkViewport *viewports = 41 cmd_buffer->state.gfx.dynamic.viewport.viewports; 42 struct anv_state sf_clip_state = 43 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64); 44 45 for (uint32_t i = 0; i < count; i++) { 46 const VkViewport *vp = &viewports[i]; 47 48 /* The gen7 state struct has just the matrix and guardband fields, the 49 * gen8 struct adds the min/max viewport fields. */ 50 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = { 51 .ViewportMatrixElementm00 = vp->width / 2, 52 .ViewportMatrixElementm11 = vp->height / 2, 53 .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth, 54 .ViewportMatrixElementm30 = vp->x + vp->width / 2, 55 .ViewportMatrixElementm31 = vp->y + vp->height / 2, 56 .ViewportMatrixElementm32 = vp->minDepth, 57 .XMinClipGuardband = -1.0f, 58 .XMaxClipGuardband = 1.0f, 59 .YMinClipGuardband = -1.0f, 60 .YMaxClipGuardband = 1.0f, 61 .XMinViewPort = vp->x, 62 .XMaxViewPort = vp->x + vp->width - 1, 63 .YMinViewPort = MIN2(vp->y, vp->y + vp->height), 64 .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1, 65 }; 66 67 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, 68 &sf_clip_viewport); 69 } 70 71 anv_batch_emit(&cmd_buffer->batch, 72 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) { 73 clip.SFClipViewportPointer = sf_clip_state.offset; 74 } 75} 76 77void 78gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, 79 bool depth_clamp_enable) 80{ 81 uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count; 82 const VkViewport *viewports = 83 cmd_buffer->state.gfx.dynamic.viewport.viewports; 84 struct anv_state cc_state = 85 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32); 86 87 for (uint32_t i = 0; i < count; i++) { 88 const VkViewport *vp = &viewports[i]; 89 90 struct GENX(CC_VIEWPORT) cc_viewport = { 91 .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f, 92 .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f, 93 }; 94 95 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport); 96 } 97 98 anv_batch_emit(&cmd_buffer->batch, 99 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) { 100 cc.CCViewportPointer = cc_state.offset; 101 } 102} 103#endif 104 105void 106genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) 107{ 108 if (cmd_buffer->state.pma_fix_enabled == enable) 109 return; 110 111 cmd_buffer->state.pma_fix_enabled = enable; 112 113 /* According to the Broadwell PIPE_CONTROL documentation, software should 114 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set 115 * prior to the LRI. If stencil buffer writes are enabled, then a Render 116 * Cache Flush is also necessary. 117 * 118 * The Skylake docs say to use a depth stall rather than a command 119 * streamer stall. However, the hardware seems to violently disagree. 120 * A full command streamer stall seems to be needed in both cases. 121 */ 122 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { 123 pc.DepthCacheFlushEnable = true; 124 pc.CommandStreamerStallEnable = true; 125 pc.RenderTargetCacheFlushEnable = true; 126 } 127 128#if GEN_GEN == 9 129 130 uint32_t cache_mode; 131 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), 132 .STCPMAOptimizationEnable = enable, 133 .STCPMAOptimizationEnableMask = true); 134 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { 135 lri.RegisterOffset = GENX(CACHE_MODE_0_num); 136 lri.DataDWord = cache_mode; 137 } 138 139#elif GEN_GEN == 8 140 141 uint32_t cache_mode; 142 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1), 143 .NPPMAFixEnable = enable, 144 .NPEarlyZFailsDisable = enable, 145 .NPPMAFixEnableMask = true, 146 .NPEarlyZFailsDisableMask = true); 147 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { 148 lri.RegisterOffset = GENX(CACHE_MODE_1_num); 149 lri.DataDWord = cache_mode; 150 } 151 152#endif /* GEN_GEN == 8 */ 153 154 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache 155 * Flush bits is often necessary. We do it regardless because it's easier. 156 * The render cache flush is also necessary if stencil writes are enabled. 157 * 158 * Again, the Skylake docs give a different set of flushes but the BDW 159 * flushes seem to work just as well. 160 */ 161 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { 162 pc.DepthStallEnable = true; 163 pc.DepthCacheFlushEnable = true; 164 pc.RenderTargetCacheFlushEnable = true; 165 } 166} 167 168UNUSED static bool 169want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer) 170{ 171 assert(GEN_GEN == 8); 172 173 /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE: 174 * 175 * SW must set this bit in order to enable this fix when following 176 * expression is TRUE. 177 * 178 * 3DSTATE_WM::ForceThreadDispatch != 1 && 179 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) && 180 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) && 181 * (3DSTATE_DEPTH_BUFFER::HIZ Enable) && 182 * !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) && 183 * (3DSTATE_PS_EXTRA::PixelShaderValid) && 184 * !(3DSTATE_WM_HZ_OP::DepthBufferClear || 185 * 3DSTATE_WM_HZ_OP::DepthBufferResolve || 186 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable || 187 * 3DSTATE_WM_HZ_OP::StencilBufferClear) && 188 * (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) && 189 * (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels || 190 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget || 191 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable || 192 * 3DSTATE_PS_BLEND::AlphaTestEnable || 193 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) && 194 * 3DSTATE_WM::ForceKillPix != ForceOff && 195 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable && 196 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) || 197 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable && 198 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE && 199 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) || 200 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF)) 201 */ 202 203 /* These are always true: 204 * 3DSTATE_WM::ForceThreadDispatch != 1 && 205 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) 206 */ 207 208 /* We only enable the PMA fix if we know for certain that HiZ is enabled. 209 * If we don't know whether HiZ is enabled or not, we disable the PMA fix 210 * and there is no harm. 211 * 212 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) && 213 * 3DSTATE_DEPTH_BUFFER::HIZ Enable 214 */ 215 if (!cmd_buffer->state.hiz_enabled) 216 return false; 217 218 /* 3DSTATE_PS_EXTRA::PixelShaderValid */ 219 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; 220 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) 221 return false; 222 223 /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */ 224 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); 225 if (wm_prog_data->early_fragment_tests) 226 return false; 227 228 /* We never use anv_pipeline for HiZ ops so this is trivially true: 229 * !(3DSTATE_WM_HZ_OP::DepthBufferClear || 230 * 3DSTATE_WM_HZ_OP::DepthBufferResolve || 231 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable || 232 * 3DSTATE_WM_HZ_OP::StencilBufferClear) 233 */ 234 235 /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */ 236 if (!pipeline->depth_test_enable) 237 return false; 238 239 /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels || 240 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget || 241 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable || 242 * 3DSTATE_PS_BLEND::AlphaTestEnable || 243 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) && 244 * 3DSTATE_WM::ForceKillPix != ForceOff && 245 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable && 246 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) || 247 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable && 248 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE && 249 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) || 250 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF)) 251 */ 252 return (pipeline->kill_pixel && (pipeline->writes_depth || 253 pipeline->writes_stencil)) || 254 wm_prog_data->computed_depth_mode != PSCDEPTH_OFF; 255} 256 257UNUSED static bool 258want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer) 259{ 260 if (GEN_GEN > 9) 261 return false; 262 assert(GEN_GEN == 9); 263 264 /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable: 265 * 266 * Clearing this bit will force the STC cache to wait for pending 267 * retirement of pixels at the HZ-read stage and do the STC-test for 268 * Non-promoted, R-computed and Computed depth modes instead of 269 * postponing the STC-test to RCPFE. 270 * 271 * STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE && 272 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable 273 * 274 * STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE && 275 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable && 276 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE) 277 * 278 * COMP_STC_EN = STC_TEST_EN && 279 * 3DSTATE_PS_EXTRA::PixelShaderComputesStencil 280 * 281 * SW parses the pipeline states to generate the following logical 282 * signal indicating if PMA FIX can be enabled. 283 * 284 * STC_PMA_OPT = 285 * 3DSTATE_WM::ForceThreadDispatch != 1 && 286 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) && 287 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL && 288 * 3DSTATE_DEPTH_BUFFER::HIZ Enable && 289 * !(3DSTATE_WM::EDSC_Mode == 2) && 290 * 3DSTATE_PS_EXTRA::PixelShaderValid && 291 * !(3DSTATE_WM_HZ_OP::DepthBufferClear || 292 * 3DSTATE_WM_HZ_OP::DepthBufferResolve || 293 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable || 294 * 3DSTATE_WM_HZ_OP::StencilBufferClear) && 295 * (COMP_STC_EN || STC_WRITE_EN) && 296 * ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels || 297 * 3DSTATE_WM::ForceKillPix == ON || 298 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget || 299 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable || 300 * 3DSTATE_PS_BLEND::AlphaTestEnable || 301 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) || 302 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)) 303 */ 304 305 /* These are always true: 306 * 3DSTATE_WM::ForceThreadDispatch != 1 && 307 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) 308 */ 309 310 /* We only enable the PMA fix if we know for certain that HiZ is enabled. 311 * If we don't know whether HiZ is enabled or not, we disable the PMA fix 312 * and there is no harm. 313 * 314 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) && 315 * 3DSTATE_DEPTH_BUFFER::HIZ Enable 316 */ 317 if (!cmd_buffer->state.hiz_enabled) 318 return false; 319 320 /* We can't possibly know if HiZ is enabled without the framebuffer */ 321 assert(cmd_buffer->state.framebuffer); 322 323 /* HiZ is enabled so we had better have a depth buffer with HiZ */ 324 const struct anv_image_view *ds_iview = 325 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer); 326 assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ); 327 328 /* 3DSTATE_PS_EXTRA::PixelShaderValid */ 329 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; 330 if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) 331 return false; 332 333 /* !(3DSTATE_WM::EDSC_Mode == 2) */ 334 const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); 335 if (wm_prog_data->early_fragment_tests) 336 return false; 337 338 /* We never use anv_pipeline for HiZ ops so this is trivially true: 339 * !(3DSTATE_WM_HZ_OP::DepthBufferClear || 340 * 3DSTATE_WM_HZ_OP::DepthBufferResolve || 341 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable || 342 * 3DSTATE_WM_HZ_OP::StencilBufferClear) 343 */ 344 345 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE && 346 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable 347 */ 348 const bool stc_test_en = 349 (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && 350 pipeline->stencil_test_enable; 351 352 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE && 353 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable && 354 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE) 355 */ 356 const bool stc_write_en = 357 (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && 358 (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front || 359 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) && 360 pipeline->writes_stencil; 361 362 /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */ 363 const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil; 364 365 /* COMP_STC_EN || STC_WRITE_EN */ 366 if (!(comp_stc_en || stc_write_en)) 367 return false; 368 369 /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels || 370 * 3DSTATE_WM::ForceKillPix == ON || 371 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget || 372 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable || 373 * 3DSTATE_PS_BLEND::AlphaTestEnable || 374 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) || 375 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF) 376 */ 377 return pipeline->kill_pixel || 378 wm_prog_data->computed_depth_mode != PSCDEPTH_OFF; 379} 380 381void 382genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) 383{ 384 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline; 385 struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic; 386 387 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | 388 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) { 389 uint32_t sf_dw[GENX(3DSTATE_SF_length)]; 390 struct GENX(3DSTATE_SF) sf = { 391 GENX(3DSTATE_SF_header), 392 }; 393#if GEN_GEN == 8 394 if (cmd_buffer->device->info.is_cherryview) { 395 sf.CHVLineWidth = d->line_width; 396 } else { 397 sf.LineWidth = d->line_width; 398 } 399#else 400 sf.LineWidth = d->line_width, 401#endif 402 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); 403 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf); 404 } 405 406 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | 407 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){ 408 uint32_t raster_dw[GENX(3DSTATE_RASTER_length)]; 409 struct GENX(3DSTATE_RASTER) raster = { 410 GENX(3DSTATE_RASTER_header), 411 .GlobalDepthOffsetConstant = d->depth_bias.bias, 412 .GlobalDepthOffsetScale = d->depth_bias.slope, 413 .GlobalDepthOffsetClamp = d->depth_bias.clamp 414 }; 415 GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster); 416 anv_batch_emit_merge(&cmd_buffer->batch, raster_dw, 417 pipeline->gen8.raster); 418 } 419 420 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to 421 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split 422 * across different state packets for gen8 and gen9. We handle that by 423 * using a big old #if switch here. 424 */ 425#if GEN_GEN == 8 426 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | 427 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) { 428 struct anv_state cc_state = 429 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 430 GENX(COLOR_CALC_STATE_length) * 4, 431 64); 432 struct GENX(COLOR_CALC_STATE) cc = { 433 .BlendConstantColorRed = d->blend_constants[0], 434 .BlendConstantColorGreen = d->blend_constants[1], 435 .BlendConstantColorBlue = d->blend_constants[2], 436 .BlendConstantColorAlpha = d->blend_constants[3], 437 .StencilReferenceValue = d->stencil_reference.front & 0xff, 438 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff, 439 }; 440 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); 441 442 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { 443 ccp.ColorCalcStatePointer = cc_state.offset; 444 ccp.ColorCalcStatePointerValid = true; 445 } 446 } 447 448 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | 449 ANV_CMD_DIRTY_RENDER_TARGETS | 450 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | 451 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) { 452 uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; 453 454 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = { 455 GENX(3DSTATE_WM_DEPTH_STENCIL_header), 456 457 .StencilTestMask = d->stencil_compare_mask.front & 0xff, 458 .StencilWriteMask = d->stencil_write_mask.front & 0xff, 459 460 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff, 461 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, 462 463 .StencilBufferWriteEnable = 464 (d->stencil_write_mask.front || d->stencil_write_mask.back) && 465 pipeline->writes_stencil, 466 }; 467 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw, 468 &wm_depth_stencil); 469 470 anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw, 471 pipeline->gen8.wm_depth_stencil); 472 473 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, 474 want_depth_pma_fix(cmd_buffer)); 475 } 476#else 477 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) { 478 struct anv_state cc_state = 479 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 480 GENX(COLOR_CALC_STATE_length) * 4, 481 64); 482 struct GENX(COLOR_CALC_STATE) cc = { 483 .BlendConstantColorRed = d->blend_constants[0], 484 .BlendConstantColorGreen = d->blend_constants[1], 485 .BlendConstantColorBlue = d->blend_constants[2], 486 .BlendConstantColorAlpha = d->blend_constants[3], 487 }; 488 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); 489 490 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { 491 ccp.ColorCalcStatePointer = cc_state.offset; 492 ccp.ColorCalcStatePointerValid = true; 493 } 494 } 495 496 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | 497 ANV_CMD_DIRTY_RENDER_TARGETS | 498 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | 499 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | 500 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) { 501 uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; 502 struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = { 503 GENX(3DSTATE_WM_DEPTH_STENCIL_header), 504 505 .StencilTestMask = d->stencil_compare_mask.front & 0xff, 506 .StencilWriteMask = d->stencil_write_mask.front & 0xff, 507 508 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff, 509 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, 510 511 .StencilReferenceValue = d->stencil_reference.front & 0xff, 512 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff, 513 514 .StencilBufferWriteEnable = 515 (d->stencil_write_mask.front || d->stencil_write_mask.back) && 516 pipeline->writes_stencil, 517 }; 518 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil); 519 520 anv_batch_emit_merge(&cmd_buffer->batch, dwords, 521 pipeline->gen9.wm_depth_stencil); 522 523 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, 524 want_stencil_pma_fix(cmd_buffer)); 525 } 526#endif 527 528 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | 529 ANV_CMD_DIRTY_INDEX_BUFFER)) { 530 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) { 531 vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart; 532 vf.CutIndex = cmd_buffer->state.restart_index; 533 } 534 } 535 536 cmd_buffer->state.gfx.dirty = 0; 537} 538 539void genX(CmdBindIndexBuffer)( 540 VkCommandBuffer commandBuffer, 541 VkBuffer _buffer, 542 VkDeviceSize offset, 543 VkIndexType indexType) 544{ 545 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); 546 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); 547 548 static const uint32_t vk_to_gen_index_type[] = { 549 [VK_INDEX_TYPE_UINT16] = INDEX_WORD, 550 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD, 551 }; 552 553 static const uint32_t restart_index_for_type[] = { 554 [VK_INDEX_TYPE_UINT16] = UINT16_MAX, 555 [VK_INDEX_TYPE_UINT32] = UINT32_MAX, 556 }; 557 558 cmd_buffer->state.restart_index = restart_index_for_type[indexType]; 559 560 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) { 561 ib.IndexFormat = vk_to_gen_index_type[indexType]; 562 ib.MOCS = anv_mocs_for_bo(cmd_buffer->device, 563 buffer->address.bo); 564 ib.BufferStartingAddress = anv_address_add(buffer->address, offset); 565 ib.BufferSize = buffer->size - offset; 566 } 567 568 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; 569} 570