1848b8605Smrg#ifndef _PCI_ID_DRIVER_MAP_H_ 2848b8605Smrg#define _PCI_ID_DRIVER_MAP_H_ 3848b8605Smrg 4848b8605Smrg#include <stddef.h> 5848b8605Smrg 6848b8605Smrg#ifndef ARRAY_SIZE 7848b8605Smrg#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 8848b8605Smrg#endif 9848b8605Smrg 10848b8605Smrg#ifndef __IS_LOADER 11848b8605Smrg# error "Only include from loader.c" 12848b8605Smrg#endif 13848b8605Smrg 14848b8605Smrgstatic const int i915_chip_ids[] = { 15848b8605Smrg#define CHIPSET(chip, desc, name) chip, 16848b8605Smrg#include "pci_ids/i915_pci_ids.h" 17848b8605Smrg#undef CHIPSET 18848b8605Smrg}; 19848b8605Smrg 20848b8605Smrgstatic const int i965_chip_ids[] = { 21848b8605Smrg#define CHIPSET(chip, family, name) chip, 22848b8605Smrg#include "pci_ids/i965_pci_ids.h" 23848b8605Smrg#undef CHIPSET 24848b8605Smrg}; 25848b8605Smrg 26b8e80941Smrgstatic const int iris_chip_ids[] = { 27b8e80941Smrg#define CHIPSET(chip, family, name) chip, 28b8e80941Smrg#define IRIS 1 29b8e80941Smrg#include "pci_ids/i965_pci_ids.h" 30b8e80941Smrg#undef IRIS 31b8e80941Smrg#undef CHIPSET 32b8e80941Smrg}; 33b8e80941Smrg 34848b8605Smrgstatic const int r100_chip_ids[] = { 35848b8605Smrg#define CHIPSET(chip, name, family) chip, 36848b8605Smrg#include "pci_ids/radeon_pci_ids.h" 37848b8605Smrg#undef CHIPSET 38848b8605Smrg}; 39848b8605Smrg 40848b8605Smrgstatic const int r200_chip_ids[] = { 41848b8605Smrg#define CHIPSET(chip, name, family) chip, 42848b8605Smrg#include "pci_ids/r200_pci_ids.h" 43848b8605Smrg#undef CHIPSET 44848b8605Smrg}; 45848b8605Smrg 46848b8605Smrgstatic const int r300_chip_ids[] = { 47848b8605Smrg#define CHIPSET(chip, name, family) chip, 48848b8605Smrg#include "pci_ids/r300_pci_ids.h" 49848b8605Smrg#undef CHIPSET 50848b8605Smrg}; 51848b8605Smrg 52848b8605Smrgstatic const int r600_chip_ids[] = { 53848b8605Smrg#define CHIPSET(chip, name, family) chip, 54848b8605Smrg#include "pci_ids/r600_pci_ids.h" 55848b8605Smrg#undef CHIPSET 56848b8605Smrg}; 57848b8605Smrg 58848b8605Smrgstatic const int radeonsi_chip_ids[] = { 59b8e80941Smrg#define CHIPSET(chip, family) chip, 60848b8605Smrg#include "pci_ids/radeonsi_pci_ids.h" 61848b8605Smrg#undef CHIPSET 62848b8605Smrg}; 63848b8605Smrg 64b8e80941Smrgstatic const int virtio_gpu_chip_ids[] = { 65b8e80941Smrg#define CHIPSET(chip, name, family) chip, 66b8e80941Smrg#include "pci_ids/virtio_gpu_pci_ids.h" 67b8e80941Smrg#undef CHIPSET 68b8e80941Smrg}; 69b8e80941Smrg 70848b8605Smrgstatic const int vmwgfx_chip_ids[] = { 71848b8605Smrg#define CHIPSET(chip, name, family) chip, 72848b8605Smrg#include "pci_ids/vmwgfx_pci_ids.h" 73848b8605Smrg#undef CHIPSET 74848b8605Smrg}; 75848b8605Smrg 76848b8605Smrgint is_nouveau_vieux(int fd); 77848b8605Smrg 78848b8605Smrgstatic const struct { 79848b8605Smrg int vendor_id; 80848b8605Smrg const char *driver; 81848b8605Smrg const int *chip_ids; 82848b8605Smrg int num_chips_ids; 83848b8605Smrg int (*predicate)(int fd); 84848b8605Smrg} driver_map[] = { 85b8e80941Smrg { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) }, 86b8e80941Smrg { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) }, 87b8e80941Smrg { 0x8086, "iris", iris_chip_ids, ARRAY_SIZE(iris_chip_ids) }, 88b8e80941Smrg { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) }, 89b8e80941Smrg { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids) }, 90b8e80941Smrg { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids) }, 91b8e80941Smrg { 0x1002, "r600", r600_chip_ids, ARRAY_SIZE(r600_chip_ids) }, 92b8e80941Smrg { 0x1002, "radeonsi", radeonsi_chip_ids, ARRAY_SIZE(radeonsi_chip_ids) }, 93b8e80941Smrg { 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux }, 94b8e80941Smrg { 0x10de, "nouveau", NULL, -1, }, 95b8e80941Smrg { 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) }, 96b8e80941Smrg { 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) }, 97848b8605Smrg { 0x0000, NULL, NULL, 0 }, 98848b8605Smrg}; 99848b8605Smrg 100848b8605Smrg#endif /* _PCI_ID_DRIVER_MAP_H_ */ 101