v3d_drm.h revision 53c12917
101e04c3fSmrg/*
201e04c3fSmrg * Copyright © 2014-2018 Broadcom
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the next
1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg * Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2101e04c3fSmrg * IN THE SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#ifndef _V3D_DRM_H_
2501e04c3fSmrg#define _V3D_DRM_H_
2601e04c3fSmrg
2701e04c3fSmrg#include "drm.h"
2801e04c3fSmrg
2901e04c3fSmrg#if defined(__cplusplus)
3001e04c3fSmrgextern "C" {
3101e04c3fSmrg#endif
3201e04c3fSmrg
3301e04c3fSmrg#define DRM_V3D_SUBMIT_CL                         0x00
3401e04c3fSmrg#define DRM_V3D_WAIT_BO                           0x01
3501e04c3fSmrg#define DRM_V3D_CREATE_BO                         0x02
3601e04c3fSmrg#define DRM_V3D_MMAP_BO                           0x03
3701e04c3fSmrg#define DRM_V3D_GET_PARAM                         0x04
3801e04c3fSmrg#define DRM_V3D_GET_BO_OFFSET                     0x05
3953c12917Smaya#define DRM_V3D_SUBMIT_TFU                        0x06
4001e04c3fSmrg
4101e04c3fSmrg#define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
4201e04c3fSmrg#define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
4301e04c3fSmrg#define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
4401e04c3fSmrg#define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
4501e04c3fSmrg#define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
4601e04c3fSmrg#define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
4753c12917Smaya#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
4801e04c3fSmrg
4901e04c3fSmrg/**
5001e04c3fSmrg * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
5101e04c3fSmrg * engine.
5201e04c3fSmrg *
5301e04c3fSmrg * This asks the kernel to have the GPU execute an optional binner
5401e04c3fSmrg * command list, and a render command list.
5553c12917Smaya *
5653c12917Smaya * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
5753c12917Smaya * each CL executes.  The VCD cache should be flushed (if necessary)
5853c12917Smaya * by the submitted CLs.  The TLB writes are guaranteed to have been
5953c12917Smaya * flushed by the time the render done IRQ happens, which is the
6053c12917Smaya * trigger for out_sync.  Any dirtying of cachelines by the job (only
6153c12917Smaya * possible using TMU writes) must be flushed by the caller using the
6253c12917Smaya * CL's cache flush commands.
6301e04c3fSmrg */
6401e04c3fSmrgstruct drm_v3d_submit_cl {
6501e04c3fSmrg	/* Pointer to the binner command list.
6601e04c3fSmrg	 *
6701e04c3fSmrg	 * This is the first set of commands executed, which runs the
6801e04c3fSmrg	 * coordinate shader to determine where primitives land on the screen,
6901e04c3fSmrg	 * then writes out the state updates and draw calls necessary per tile
7001e04c3fSmrg	 * to the tile allocation BO.
7153c12917Smaya	 *
7253c12917Smaya	 * This BCL will block on any previous BCL submitted on the
7353c12917Smaya	 * same FD, but not on any RCL or BCLs submitted by other
7453c12917Smaya	 * clients -- that is left up to the submitter to control
7553c12917Smaya	 * using in_sync_bcl if necessary.
7601e04c3fSmrg	 */
7701e04c3fSmrg	__u32 bcl_start;
7801e04c3fSmrg
7953c12917Smaya	/** End address of the BCL (first byte after the BCL) */
8001e04c3fSmrg	__u32 bcl_end;
8101e04c3fSmrg
8201e04c3fSmrg	/* Offset of the render command list.
8301e04c3fSmrg	 *
8401e04c3fSmrg	 * This is the second set of commands executed, which will either
8501e04c3fSmrg	 * execute the tiles that have been set up by the BCL, or a fixed set
8601e04c3fSmrg	 * of tiles (in the case of RCL-only blits).
8753c12917Smaya	 *
8853c12917Smaya	 * This RCL will block on this submit's BCL, and any previous
8953c12917Smaya	 * RCL submitted on the same FD, but not on any RCL or BCLs
9053c12917Smaya	 * submitted by other clients -- that is left up to the
9153c12917Smaya	 * submitter to control using in_sync_rcl if necessary.
9201e04c3fSmrg	 */
9301e04c3fSmrg	__u32 rcl_start;
9401e04c3fSmrg
9553c12917Smaya	/** End address of the RCL (first byte after the RCL) */
9601e04c3fSmrg	__u32 rcl_end;
9701e04c3fSmrg
9801e04c3fSmrg	/** An optional sync object to wait on before starting the BCL. */
9901e04c3fSmrg	__u32 in_sync_bcl;
10001e04c3fSmrg	/** An optional sync object to wait on before starting the RCL. */
10101e04c3fSmrg	__u32 in_sync_rcl;
10201e04c3fSmrg	/** An optional sync object to place the completion fence in. */
10301e04c3fSmrg	__u32 out_sync;
10401e04c3fSmrg
10501e04c3fSmrg	/* Offset of the tile alloc memory
10601e04c3fSmrg	 *
10701e04c3fSmrg	 * This is optional on V3D 3.3 (where the CL can set the value) but
10801e04c3fSmrg	 * required on V3D 4.1.
10901e04c3fSmrg	 */
11001e04c3fSmrg	__u32 qma;
11101e04c3fSmrg
11201e04c3fSmrg	/** Size of the tile alloc memory. */
11301e04c3fSmrg	__u32 qms;
11401e04c3fSmrg
11501e04c3fSmrg	/** Offset of the tile state data array. */
11601e04c3fSmrg	__u32 qts;
11701e04c3fSmrg
11801e04c3fSmrg	/* Pointer to a u32 array of the BOs that are referenced by the job.
11901e04c3fSmrg	 */
12001e04c3fSmrg	__u64 bo_handles;
12101e04c3fSmrg
12201e04c3fSmrg	/* Number of BO handles passed in (size is that times 4). */
12301e04c3fSmrg	__u32 bo_handle_count;
12401e04c3fSmrg
12501e04c3fSmrg	/* Pad, must be zero-filled. */
12601e04c3fSmrg	__u32 pad;
12701e04c3fSmrg};
12801e04c3fSmrg
12901e04c3fSmrg/**
13001e04c3fSmrg * struct drm_v3d_wait_bo - ioctl argument for waiting for
13101e04c3fSmrg * completion of the last DRM_V3D_SUBMIT_CL on a BO.
13201e04c3fSmrg *
13301e04c3fSmrg * This is useful for cases where multiple processes might be
13401e04c3fSmrg * rendering to a BO and you want to wait for all rendering to be
13501e04c3fSmrg * completed.
13601e04c3fSmrg */
13701e04c3fSmrgstruct drm_v3d_wait_bo {
13801e04c3fSmrg	__u32 handle;
13901e04c3fSmrg	__u32 pad;
14001e04c3fSmrg	__u64 timeout_ns;
14101e04c3fSmrg};
14201e04c3fSmrg
14301e04c3fSmrg/**
14401e04c3fSmrg * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
14501e04c3fSmrg *
14601e04c3fSmrg * There are currently no values for the flags argument, but it may be
14701e04c3fSmrg * used in a future extension.
14801e04c3fSmrg */
14901e04c3fSmrgstruct drm_v3d_create_bo {
15001e04c3fSmrg	__u32 size;
15101e04c3fSmrg	__u32 flags;
15201e04c3fSmrg	/** Returned GEM handle for the BO. */
15301e04c3fSmrg	__u32 handle;
15401e04c3fSmrg	/**
15501e04c3fSmrg	 * Returned offset for the BO in the V3D address space.  This offset
15601e04c3fSmrg	 * is private to the DRM fd and is valid for the lifetime of the GEM
15701e04c3fSmrg	 * handle.
15801e04c3fSmrg	 *
15901e04c3fSmrg	 * This offset value will always be nonzero, since various HW
16001e04c3fSmrg	 * units treat 0 specially.
16101e04c3fSmrg	 */
16201e04c3fSmrg	__u32 offset;
16301e04c3fSmrg};
16401e04c3fSmrg
16501e04c3fSmrg/**
16601e04c3fSmrg * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
16701e04c3fSmrg *
16801e04c3fSmrg * This doesn't actually perform an mmap.  Instead, it returns the
16901e04c3fSmrg * offset you need to use in an mmap on the DRM device node.  This
17001e04c3fSmrg * means that tools like valgrind end up knowing about the mapped
17101e04c3fSmrg * memory.
17201e04c3fSmrg *
17301e04c3fSmrg * There are currently no values for the flags argument, but it may be
17401e04c3fSmrg * used in a future extension.
17501e04c3fSmrg */
17601e04c3fSmrgstruct drm_v3d_mmap_bo {
17701e04c3fSmrg	/** Handle for the object being mapped. */
17801e04c3fSmrg	__u32 handle;
17901e04c3fSmrg	__u32 flags;
18001e04c3fSmrg	/** offset into the drm node to use for subsequent mmap call. */
18101e04c3fSmrg	__u64 offset;
18201e04c3fSmrg};
18301e04c3fSmrg
18401e04c3fSmrgenum drm_v3d_param {
18501e04c3fSmrg	DRM_V3D_PARAM_V3D_UIFCFG,
18601e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT1,
18701e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT2,
18801e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT3,
18901e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
19001e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
19101e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
19253c12917Smaya	DRM_V3D_PARAM_SUPPORTS_TFU,
19301e04c3fSmrg};
19401e04c3fSmrg
19501e04c3fSmrgstruct drm_v3d_get_param {
19601e04c3fSmrg	__u32 param;
19701e04c3fSmrg	__u32 pad;
19801e04c3fSmrg	__u64 value;
19901e04c3fSmrg};
20001e04c3fSmrg
20101e04c3fSmrg/**
20201e04c3fSmrg * Returns the offset for the BO in the V3D address space for this DRM fd.
20301e04c3fSmrg * This is the same value returned by drm_v3d_create_bo, if that was called
20401e04c3fSmrg * from this DRM fd.
20501e04c3fSmrg */
20601e04c3fSmrgstruct drm_v3d_get_bo_offset {
20701e04c3fSmrg	__u32 handle;
20801e04c3fSmrg	__u32 offset;
20901e04c3fSmrg};
21001e04c3fSmrg
21153c12917Smayastruct drm_v3d_submit_tfu {
21253c12917Smaya	__u32 icfg;
21353c12917Smaya	__u32 iia;
21453c12917Smaya	__u32 iis;
21553c12917Smaya	__u32 ica;
21653c12917Smaya	__u32 iua;
21753c12917Smaya	__u32 ioa;
21853c12917Smaya	__u32 ios;
21953c12917Smaya	__u32 coef[4];
22053c12917Smaya	/* First handle is the output BO, following are other inputs.
22153c12917Smaya	 * 0 for unused.
22253c12917Smaya	 */
22353c12917Smaya	__u32 bo_handles[4];
22453c12917Smaya	/* sync object to block on before running the TFU job.  Each TFU
22553c12917Smaya	 * job will execute in the order submitted to its FD.  Synchronization
22653c12917Smaya	 * against rendering jobs requires using sync objects.
22753c12917Smaya	 */
22853c12917Smaya	__u32 in_sync;
22953c12917Smaya	/* Sync object to signal when the TFU job is done. */
23053c12917Smaya	__u32 out_sync;
23153c12917Smaya};
23253c12917Smaya
23301e04c3fSmrg#if defined(__cplusplus)
23401e04c3fSmrg}
23501e04c3fSmrg#endif
23601e04c3fSmrg
23701e04c3fSmrg#endif /* _V3D_DRM_H_ */
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