101e04c3fSmrg/*
201e04c3fSmrg * Copyright 2014 Advanced Micro Devices, Inc.
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the next
1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg * Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2001e04c3fSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2101e04c3fSmrg * SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#ifndef AC_BINARY_H
2501e04c3fSmrg#define AC_BINARY_H
2601e04c3fSmrg
2701e04c3fSmrg#include <stdbool.h>
287ec681f3Smrg#include <stddef.h>
297ec681f3Smrg#include <stdint.h>
3001e04c3fSmrg
3101e04c3fSmrg#ifdef __cplusplus
3201e04c3fSmrgextern "C" {
3301e04c3fSmrg#endif
3401e04c3fSmrg
357ec681f3Smrgstruct radeon_info;
3601e04c3fSmrg
3701e04c3fSmrgstruct ac_shader_config {
387ec681f3Smrg   unsigned num_sgprs;
397ec681f3Smrg   unsigned num_vgprs;
407ec681f3Smrg   unsigned num_shared_vgprs; /* GFX10: number of VGPRs shared between half-waves */
417ec681f3Smrg   unsigned spilled_sgprs;
427ec681f3Smrg   unsigned spilled_vgprs;
437ec681f3Smrg   unsigned lds_size; /* in HW allocation units; i.e 256 bytes on SI, 512 bytes on CI+ */
447ec681f3Smrg   unsigned spi_ps_input_ena;
457ec681f3Smrg   unsigned spi_ps_input_addr;
467ec681f3Smrg   unsigned float_mode;
477ec681f3Smrg   unsigned scratch_bytes_per_wave;
487ec681f3Smrg   unsigned rsrc1;
497ec681f3Smrg   unsigned rsrc2;
507ec681f3Smrg   unsigned rsrc3;
5101e04c3fSmrg};
5201e04c3fSmrg
537ec681f3Smrgvoid ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wave_size,
547ec681f3Smrg                                   bool really_needs_scratch, const struct radeon_info *info,
557ec681f3Smrg                                   struct ac_shader_config *conf);
5601e04c3fSmrg
5701e04c3fSmrg#ifdef __cplusplus
5801e04c3fSmrg}
5901e04c3fSmrg#endif
6001e04c3fSmrg
6101e04c3fSmrg#endif /* AC_BINARY_H */
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