ac_drm_fourcc.h revision 7ec681f3 
1/*
2 * Copyright © 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26#ifndef AC_DRM_FOURCC_H
27#define AC_DRM_FOURCC_H
28
29#ifdef _WIN32
30#include <stdint.h>
31typedef uint64_t __u64;
32#define DRM_FORMAT_MOD_VENDOR_NONE    0
33#define DRM_FORMAT_MOD_VENDOR_AMD     0x02
34#define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
35#define fourcc_mod_code(vendor, val) \
36	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
37#define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
38#define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
39#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
40#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
41#define AMD_FMT_MOD_TILE_VER_GFX9 1
42#define AMD_FMT_MOD_TILE_VER_GFX10 2
43#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
44#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
45#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
46#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
47#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
48#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
49#define AMD_FMT_MOD_DCC_BLOCK_64B 0
50#define AMD_FMT_MOD_DCC_BLOCK_128B 1
51#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
52#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
53#define AMD_FMT_MOD_TILE_SHIFT 8
54#define AMD_FMT_MOD_TILE_MASK 0x1F
55#define AMD_FMT_MOD_DCC_SHIFT 13
56#define AMD_FMT_MOD_DCC_MASK 0x1
57#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
58#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
59#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
60#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
61#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
62#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
63#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
64#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
65#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
66#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
67#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
68#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
69#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
70#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
71#define AMD_FMT_MOD_RB_SHIFT 30
72#define AMD_FMT_MOD_RB_MASK 0x7
73#define AMD_FMT_MOD_PIPE_SHIFT 33
74#define AMD_FMT_MOD_SET(field, value) \
75	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
76#define AMD_FMT_MOD_GET(field, value) \
77	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
78#else
79#include "drm-uapi/drm_fourcc.h"
80#endif
81
82#endif /* AC_DRM_FOURCC_H */
83