17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2021 Valve Corporation 37ec681f3Smrg * 47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 57ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 67ec681f3Smrg * to deal in the Software without restriction, including without limitation 77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 97ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 107ec681f3Smrg * 117ec681f3Smrg * The above copyright notice and this permission notice (including the next 127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 137ec681f3Smrg * Software. 147ec681f3Smrg * 157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 217ec681f3Smrg * IN THE SOFTWARE. 227ec681f3Smrg * 237ec681f3Smrg */ 247ec681f3Smrg 257ec681f3Smrg 267ec681f3Smrg#ifndef AC_NIR_H 277ec681f3Smrg#define AC_NIR_H 287ec681f3Smrg 297ec681f3Smrg#include "nir.h" 307ec681f3Smrg#include "ac_shader_args.h" 317ec681f3Smrg#include "ac_shader_util.h" 327ec681f3Smrg#include "amd_family.h" 337ec681f3Smrg 347ec681f3Smrg#ifdef __cplusplus 357ec681f3Smrgextern "C" { 367ec681f3Smrg#endif 377ec681f3Smrg 387ec681f3Smrg/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */ 397ec681f3Smrgstruct nir_builder; 407ec681f3Smrgtypedef struct nir_builder nir_builder; 417ec681f3Smrg 427ec681f3Smrgvoid 437ec681f3Smrgac_nir_lower_ls_outputs_to_mem(nir_shader *ls, 447ec681f3Smrg bool tcs_in_out_eq, 457ec681f3Smrg uint64_t tcs_temp_only_inputs, 467ec681f3Smrg unsigned num_reserved_ls_outputs); 477ec681f3Smrg 487ec681f3Smrgvoid 497ec681f3Smrgac_nir_lower_hs_inputs_to_mem(nir_shader *shader, 507ec681f3Smrg bool tcs_in_out_eq, 517ec681f3Smrg unsigned num_reserved_tcs_inputs); 527ec681f3Smrg 537ec681f3Smrgvoid 547ec681f3Smrgac_nir_lower_hs_outputs_to_mem(nir_shader *shader, 557ec681f3Smrg enum chip_class chip_class, 567ec681f3Smrg bool tes_reads_tessfactors, 577ec681f3Smrg uint64_t tes_inputs_read, 587ec681f3Smrg uint64_t tes_patch_inputs_read, 597ec681f3Smrg unsigned num_reserved_tcs_inputs, 607ec681f3Smrg unsigned num_reserved_tcs_outputs, 617ec681f3Smrg unsigned num_reserved_tcs_patch_outputs, 627ec681f3Smrg bool emit_tess_factor_write); 637ec681f3Smrg 647ec681f3Smrgvoid 657ec681f3Smrgac_nir_lower_tes_inputs_to_mem(nir_shader *shader, 667ec681f3Smrg unsigned num_reserved_tcs_outputs, 677ec681f3Smrg unsigned num_reserved_tcs_patch_outputs); 687ec681f3Smrg 697ec681f3Smrgenum ac_nir_tess_to_const_options { 707ec681f3Smrg ac_nir_lower_patch_vtx_in = 1 << 0, 717ec681f3Smrg ac_nir_lower_num_patches = 1 << 1, 727ec681f3Smrg}; 737ec681f3Smrg 747ec681f3Smrgvoid 757ec681f3Smrgac_nir_lower_tess_to_const(nir_shader *shader, 767ec681f3Smrg unsigned patch_vtx_in, 777ec681f3Smrg unsigned tcs_num_patches, 787ec681f3Smrg unsigned options); 797ec681f3Smrg 807ec681f3Smrgvoid 817ec681f3Smrgac_nir_lower_es_outputs_to_mem(nir_shader *shader, 827ec681f3Smrg enum chip_class chip_class, 837ec681f3Smrg unsigned num_reserved_es_outputs); 847ec681f3Smrg 857ec681f3Smrgvoid 867ec681f3Smrgac_nir_lower_gs_inputs_to_mem(nir_shader *shader, 877ec681f3Smrg enum chip_class chip_class, 887ec681f3Smrg unsigned num_reserved_es_outputs); 897ec681f3Smrg 907ec681f3Smrgbool 917ec681f3Smrgac_nir_lower_indirect_derefs(nir_shader *shader, 927ec681f3Smrg enum chip_class chip_class); 937ec681f3Smrg 947ec681f3Smrgvoid 957ec681f3Smrgac_nir_lower_ngg_nogs(nir_shader *shader, 967ec681f3Smrg unsigned max_num_es_vertices, 977ec681f3Smrg unsigned num_vertices_per_primitive, 987ec681f3Smrg unsigned max_workgroup_size, 997ec681f3Smrg unsigned wave_size, 1007ec681f3Smrg bool can_cull, 1017ec681f3Smrg bool early_prim_export, 1027ec681f3Smrg bool passthrough, 1037ec681f3Smrg bool export_prim_id, 1047ec681f3Smrg bool provoking_vtx_last, 1057ec681f3Smrg bool use_edgeflags, 1067ec681f3Smrg uint32_t instance_rate_inputs); 1077ec681f3Smrg 1087ec681f3Smrgvoid 1097ec681f3Smrgac_nir_lower_ngg_gs(nir_shader *shader, 1107ec681f3Smrg unsigned wave_size, 1117ec681f3Smrg unsigned max_workgroup_size, 1127ec681f3Smrg unsigned esgs_ring_lds_bytes, 1137ec681f3Smrg unsigned gs_out_vtx_bytes, 1147ec681f3Smrg unsigned gs_total_out_vtx_bytes, 1157ec681f3Smrg bool provoking_vtx_last); 1167ec681f3Smrg 1177ec681f3Smrgnir_ssa_def * 1187ec681f3Smrgac_nir_cull_triangle(nir_builder *b, 1197ec681f3Smrg nir_ssa_def *initially_accepted, 1207ec681f3Smrg nir_ssa_def *pos[3][4]); 1217ec681f3Smrg 1227ec681f3Smrg#ifdef __cplusplus 1237ec681f3Smrg} 1247ec681f3Smrg#endif 1257ec681f3Smrg 1267ec681f3Smrg#endif /* AC_NIR_H */ 127