17ec681f3Smrg/*
27ec681f3Smrg * Copyright © 2020 Valve Corporation
37ec681f3Smrg *
47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
57ec681f3Smrg * copy of this software and associated documentation files (the "Software"),
67ec681f3Smrg * to deal in the Software without restriction, including without limitation
77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the
97ec681f3Smrg * Software is furnished to do so, subject to the following conditions:
107ec681f3Smrg *
117ec681f3Smrg * The above copyright notice and this permission notice (including the next
127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the
137ec681f3Smrg * Software.
147ec681f3Smrg *
157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
217ec681f3Smrg * IN THE SOFTWARE.
227ec681f3Smrg *
237ec681f3Smrg */
247ec681f3Smrg#include "helpers.h"
257ec681f3Smrg#include "test_isel-spirv.h"
267ec681f3Smrg
277ec681f3Smrg#include <llvm/Config/llvm-config.h>
287ec681f3Smrg
297ec681f3Smrgusing namespace aco;
307ec681f3Smrg
317ec681f3SmrgBEGIN_TEST(isel.interp.simple)
327ec681f3Smrg   QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
337ec681f3Smrg      layout(location = 0) in vec4 in_color;
347ec681f3Smrg      layout(location = 0) out vec4 out_color;
357ec681f3Smrg      void main() {
367ec681f3Smrg         out_color = in_color;
377ec681f3Smrg      }
387ec681f3Smrg   );
397ec681f3Smrg   QoShaderModuleCreateInfo fs = qoShaderModuleCreateInfoGLSL(FRAGMENT,
407ec681f3Smrg      layout(location = 0) in vec4 in_color;
417ec681f3Smrg      layout(location = 0) out vec4 out_color;
427ec681f3Smrg      void main() {
437ec681f3Smrg         //>> v1: %a_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.w
447ec681f3Smrg         //! v1: %a = v_interp_p2_f32 %by, %pm:m0, (kill)%a_tmp attr0.w
457ec681f3Smrg         //! v1: %b_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.z
467ec681f3Smrg         //! v1: %b = v_interp_p2_f32 %by, %pm:m0, (kill)%b_tmp attr0.z
477ec681f3Smrg         //! v1: %g_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.y
487ec681f3Smrg         //! v1: %g = v_interp_p2_f32 %by, %pm:m0, (kill)%g_tmp attr0.y
497ec681f3Smrg         //! v1: %r_tmp = v_interp_p1_f32 (kill)%bx, %pm:m0 attr0.x
507ec681f3Smrg         //! v1: %r = v_interp_p2_f32 (kill)%by, (kill)%pm:m0, (kill)%r_tmp attr0.x
517ec681f3Smrg         //! exp (kill)%r, (kill)%g, (kill)%b, (kill)%a mrt0
527ec681f3Smrg         out_color = in_color;
537ec681f3Smrg      }
547ec681f3Smrg   );
557ec681f3Smrg
567ec681f3Smrg   PipelineBuilder pbld(get_vk_device(GFX9));
577ec681f3Smrg   pbld.add_vsfs(vs, fs);
587ec681f3Smrg   pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR");
597ec681f3SmrgEND_TEST
607ec681f3Smrg
617ec681f3SmrgBEGIN_TEST(isel.compute.simple)
627ec681f3Smrg   for (unsigned i = GFX7; i <= GFX8; i++) {
637ec681f3Smrg      if (!set_variant((chip_class)i))
647ec681f3Smrg         continue;
657ec681f3Smrg
667ec681f3Smrg      QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
677ec681f3Smrg         layout(local_size_x=1) in;
687ec681f3Smrg         layout(binding=0) buffer Buf {
697ec681f3Smrg            uint res;
707ec681f3Smrg         };
717ec681f3Smrg         void main() {
727ec681f3Smrg            //>> v1: %data = p_parallelcopy 42
737ec681f3Smrg            //buffer_store_dword %_, v1: undef, 0, %data disable_wqm storage:buffer semantics: scope:invocation
747ec681f3Smrg            res = 42;
757ec681f3Smrg         }
767ec681f3Smrg      );
777ec681f3Smrg
787ec681f3Smrg      PipelineBuilder pbld(get_vk_device((chip_class)i));
797ec681f3Smrg      pbld.add_cs(cs);
807ec681f3Smrg      pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
817ec681f3Smrg   }
827ec681f3SmrgEND_TEST
837ec681f3Smrg
847ec681f3SmrgBEGIN_TEST(isel.gs.no_outputs)
857ec681f3Smrg   for (unsigned i = GFX8; i <= GFX10; i++) {
867ec681f3Smrg      if (!set_variant((chip_class)i))
877ec681f3Smrg         continue;
887ec681f3Smrg
897ec681f3Smrg      QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
907ec681f3Smrg         void main() {}
917ec681f3Smrg      );
927ec681f3Smrg
937ec681f3Smrg      QoShaderModuleCreateInfo gs = qoShaderModuleCreateInfoGLSL(GEOMETRY,
947ec681f3Smrg         layout(points) in;
957ec681f3Smrg         layout(points, max_vertices = 1) out;
967ec681f3Smrg
977ec681f3Smrg         void main() {
987ec681f3Smrg            EmitVertex();
997ec681f3Smrg            EndPrimitive();
1007ec681f3Smrg         }
1017ec681f3Smrg      );
1027ec681f3Smrg
1037ec681f3Smrg      PipelineBuilder pbld(get_vk_device((chip_class)i));
1047ec681f3Smrg      pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
1057ec681f3Smrg      pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs);
1067ec681f3Smrg      pbld.create_pipeline();
1077ec681f3Smrg
1087ec681f3Smrg      //! success
1097ec681f3Smrg      fprintf(output, "success\n");
1107ec681f3Smrg   }
1117ec681f3SmrgEND_TEST
1127ec681f3Smrg
1137ec681f3SmrgBEGIN_TEST(isel.gs.no_verts)
1147ec681f3Smrg   for (unsigned i = GFX8; i <= GFX10; i++) {
1157ec681f3Smrg      if (!set_variant((chip_class)i))
1167ec681f3Smrg         continue;
1177ec681f3Smrg
1187ec681f3Smrg      QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
1197ec681f3Smrg         void main() {}
1207ec681f3Smrg      );
1217ec681f3Smrg
1227ec681f3Smrg      QoShaderModuleCreateInfo gs = qoShaderModuleCreateInfoGLSL(GEOMETRY,
1237ec681f3Smrg         layout(points) in;
1247ec681f3Smrg         layout(points, max_vertices = 0) out;
1257ec681f3Smrg
1267ec681f3Smrg         void main() {}
1277ec681f3Smrg      );
1287ec681f3Smrg
1297ec681f3Smrg      PipelineBuilder pbld(get_vk_device((chip_class)i));
1307ec681f3Smrg      pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
1317ec681f3Smrg      pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs);
1327ec681f3Smrg      pbld.create_pipeline();
1337ec681f3Smrg
1347ec681f3Smrg      //! success
1357ec681f3Smrg      fprintf(output, "success\n");
1367ec681f3Smrg   }
1377ec681f3SmrgEND_TEST
1387ec681f3Smrg
1397ec681f3SmrgBEGIN_TEST(isel.sparse.clause)
1407ec681f3Smrg   for (unsigned i = GFX10_3; i <= GFX10_3; i++) {
1417ec681f3Smrg      if (!set_variant((chip_class)i))
1427ec681f3Smrg         continue;
1437ec681f3Smrg
1447ec681f3Smrg      QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
1457ec681f3Smrg         QO_EXTENSION GL_ARB_sparse_texture2 : require
1467ec681f3Smrg         layout(local_size_x=1) in;
1477ec681f3Smrg         layout(binding=0) uniform sampler2D tex;
1487ec681f3Smrg         layout(binding=1) buffer Buf {
1497ec681f3Smrg            vec4 res[4];
1507ec681f3Smrg            uint code[4];
1517ec681f3Smrg         };
1527ec681f3Smrg         void main() {
1537ec681f3Smrg            //! llvm_version: #llvm_ver
1547ec681f3Smrg            //; if llvm_ver >= 12:
1557ec681f3Smrg            //;    funcs['sample_res'] = lambda _: 'v[#_:#_]'
1567ec681f3Smrg            //;    funcs['sample_coords'] = lambda _: '[v#_, v#_, v#_]'
1577ec681f3Smrg            //; else:
1587ec681f3Smrg            //;    funcs['sample_res'] = lambda _: 'v#_'
1597ec681f3Smrg            //;    funcs['sample_coords'] = lambda _: '[v#_, v#_, v#_, v#_]'
1607ec681f3Smrg            //>> v5: (noCSE)%zero0 = p_create_vector 0, 0, 0, 0, 0
1617ec681f3Smrg            //>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero0, (kill)%_, %_, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
1627ec681f3Smrg            //>> v5: (noCSE)%zero1 = p_create_vector 0, 0, 0, 0, 0
1637ec681f3Smrg            //>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero1, (kill)%_, %_, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
1647ec681f3Smrg            //>> v5: (noCSE)%zero2 = p_create_vector 0, 0, 0, 0, 0
1657ec681f3Smrg            //>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero2, (kill)%_, %_, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
1667ec681f3Smrg            //>> v5: (noCSE)%zero3 = p_create_vector 0, 0, 0, 0, 0
1677ec681f3Smrg            //>> v5: %_ = image_sample_lz_o (kill)%_, (kill)%_, (kill)%zero3, (kill)%_, (kill)%_, (kill)%_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
1687ec681f3Smrg            //>> s_clause 0x3
1697ec681f3Smrg            //! image_sample_lz_o @sample_res, @sample_coords, @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
1707ec681f3Smrg            //! image_sample_lz_o @sample_res, @sample_coords, @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
1717ec681f3Smrg            //! image_sample_lz_o @sample_res, @sample_coords, @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
1727ec681f3Smrg            //! image_sample_lz_o @sample_res, @sample_coords, @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
1737ec681f3Smrg            code[0] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(1, 0), res[0]);
1747ec681f3Smrg            code[1] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(2, 0), res[1]);
1757ec681f3Smrg            code[2] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(3, 0), res[2]);
1767ec681f3Smrg            code[3] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(4, 0), res[3]);
1777ec681f3Smrg         }
1787ec681f3Smrg      );
1797ec681f3Smrg
1807ec681f3Smrg      fprintf(output, "llvm_version: %u\n", LLVM_VERSION_MAJOR);
1817ec681f3Smrg
1827ec681f3Smrg      PipelineBuilder pbld(get_vk_device((chip_class)i));
1837ec681f3Smrg      pbld.add_cs(cs);
1847ec681f3Smrg      pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
1857ec681f3Smrg      pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "Assembly", true);
1867ec681f3Smrg   }
1877ec681f3SmrgEND_TEST
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