gfx103.json revision 7ec681f3 
1{
2 "enums": {
3  "BinMapMode": {
4   "entries": [
5    {"name": "BIN_MAP_MODE_NONE", "value": 0},
6    {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
7    {"name": "BIN_MAP_MODE_POPS", "value": 2}
8   ]
9  },
10  "BinSizeExtend": {
11   "entries": [
12    {"name": "BIN_SIZE_32_PIXELS", "value": 0},
13    {"name": "BIN_SIZE_64_PIXELS", "value": 1},
14    {"name": "BIN_SIZE_128_PIXELS", "value": 2},
15    {"name": "BIN_SIZE_256_PIXELS", "value": 3},
16    {"name": "BIN_SIZE_512_PIXELS", "value": 4}
17   ]
18  },
19  "BinningMode": {
20   "entries": [
21    {"name": "BINNING_ALLOWED", "value": 0},
22    {"name": "FORCE_BINNING_ON", "value": 1},
23    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
24    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
25   ]
26  },
27  "BlendOp": {
28   "entries": [
29    {"name": "BLEND_ZERO", "value": 0},
30    {"name": "BLEND_ONE", "value": 1},
31    {"name": "BLEND_SRC_COLOR", "value": 2},
32    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
33    {"name": "BLEND_SRC_ALPHA", "value": 4},
34    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
35    {"name": "BLEND_DST_ALPHA", "value": 6},
36    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
37    {"name": "BLEND_DST_COLOR", "value": 8},
38    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
39    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
40    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
41    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
42    {"name": "BLEND_CONSTANT_COLOR", "value": 13},
43    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
44    {"name": "BLEND_SRC1_COLOR", "value": 15},
45    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
46    {"name": "BLEND_SRC1_ALPHA", "value": 17},
47    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
48    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
49    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
50   ]
51  },
52  "BlendOpt": {
53   "entries": [
54    {"name": "FORCE_OPT_AUTO", "value": 0},
55    {"name": "FORCE_OPT_DISABLE", "value": 1},
56    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
57    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
58    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
59    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
60    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
61    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
62   ]
63  },
64  "CBMode": {
65   "entries": [
66    {"name": "CB_DISABLE", "value": 0},
67    {"name": "CB_NORMAL", "value": 1},
68    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
69    {"name": "CB_RESOLVE", "value": 3},
70    {"name": "CB_DECOMPRESS", "value": 4},
71    {"name": "CB_FMASK_DECOMPRESS", "value": 5},
72    {"name": "CB_DCC_DECOMPRESS", "value": 6},
73    {"name": "CB_RESERVED", "value": 7}
74   ]
75  },
76  "CBPerfClearFilterSel": {
77   "entries": [
78    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
79    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
80   ]
81  },
82  "CBPerfOpFilterSel": {
83   "entries": [
84    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
85    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
86    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
87    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
88    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
89    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
90   ]
91  },
92  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
93   "entries": [
94    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
95    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
96    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
97   ]
98  },
99  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
100   "entries": [
101    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
102    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
103   ]
104  },
105  "CLIP_RULE": {
106   "entries": [
107    {"name": "OUT", "value": 1},
108    {"name": "IN_0", "value": 2},
109    {"name": "IN_1", "value": 4},
110    {"name": "IN_10", "value": 8},
111    {"name": "IN_2", "value": 16},
112    {"name": "IN_20", "value": 32},
113    {"name": "IN_21", "value": 64},
114    {"name": "IN_210", "value": 128},
115    {"name": "IN_3", "value": 256},
116    {"name": "IN_30", "value": 512},
117    {"name": "IN_31", "value": 1024},
118    {"name": "IN_310", "value": 2048},
119    {"name": "IN_32", "value": 4096},
120    {"name": "IN_320", "value": 8192},
121    {"name": "IN_321", "value": 16384},
122    {"name": "IN_3210", "value": 32768}
123   ]
124  },
125  "CP_PERFMON_ENABLE_MODE": {
126   "entries": [
127    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
128    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
129    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
130    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
131   ]
132  },
133  "CP_PERFMON_STATE": {
134   "entries": [
135    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
136    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
137    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
138    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
139    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
140    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
141   ]
142  },
143  "CmaskAddr": {
144   "entries": [
145    {"name": "CMASK_ADDR_TILED", "value": 0},
146    {"name": "CMASK_ADDR_LINEAR", "value": 1},
147    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
148   ]
149  },
150  "ColorFormat": {
151   "entries": [
152    {"name": "COLOR_INVALID", "value": 0},
153    {"name": "COLOR_8", "value": 1},
154    {"name": "COLOR_16", "value": 2},
155    {"name": "COLOR_8_8", "value": 3},
156    {"name": "COLOR_32", "value": 4},
157    {"name": "COLOR_16_16", "value": 5},
158    {"name": "COLOR_10_11_11", "value": 6},
159    {"name": "COLOR_11_11_10", "value": 7},
160    {"name": "COLOR_10_10_10_2", "value": 8},
161    {"name": "COLOR_2_10_10_10", "value": 9},
162    {"name": "COLOR_8_8_8_8", "value": 10},
163    {"name": "COLOR_32_32", "value": 11},
164    {"name": "COLOR_16_16_16_16", "value": 12},
165    {"name": "COLOR_32_32_32_32", "value": 14},
166    {"name": "COLOR_5_6_5", "value": 16},
167    {"name": "COLOR_1_5_5_5", "value": 17},
168    {"name": "COLOR_5_5_5_1", "value": 18},
169    {"name": "COLOR_4_4_4_4", "value": 19},
170    {"name": "COLOR_8_24", "value": 20},
171    {"name": "COLOR_24_8", "value": 21},
172    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
173    {"name": "COLOR_5_9_9_9", "value": 24}
174   ]
175  },
176  "CombFunc": {
177   "entries": [
178    {"name": "COMB_DST_PLUS_SRC", "value": 0},
179    {"name": "COMB_SRC_MINUS_DST", "value": 1},
180    {"name": "COMB_MIN_DST_SRC", "value": 2},
181    {"name": "COMB_MAX_DST_SRC", "value": 3},
182    {"name": "COMB_DST_MINUS_SRC", "value": 4}
183   ]
184  },
185  "CompareFrag": {
186   "entries": [
187    {"name": "FRAG_NEVER", "value": 0},
188    {"name": "FRAG_LESS", "value": 1},
189    {"name": "FRAG_EQUAL", "value": 2},
190    {"name": "FRAG_LEQUAL", "value": 3},
191    {"name": "FRAG_GREATER", "value": 4},
192    {"name": "FRAG_NOTEQUAL", "value": 5},
193    {"name": "FRAG_GEQUAL", "value": 6},
194    {"name": "FRAG_ALWAYS", "value": 7}
195   ]
196  },
197  "ConservativeZExport": {
198   "entries": [
199    {"name": "EXPORT_ANY_Z", "value": 0},
200    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
201    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
202    {"name": "EXPORT_RESERVED", "value": 3}
203   ]
204  },
205  "CovToShaderSel": {
206   "entries": [
207    {"name": "INPUT_COVERAGE", "value": 0},
208    {"name": "INPUT_INNER_COVERAGE", "value": 1},
209    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
210    {"name": "RAW", "value": 3}
211   ]
212  },
213  "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
214   "entries": [
215    {"name": "AUTO", "value": 0},
216    {"name": "FORCE_ON", "value": 1},
217    {"name": "FORCE_OFF", "value": 2},
218    {"name": "RESERVED", "value": 3}
219   ]
220  },
221  "DbPRTFaultBehavior": {
222   "entries": [
223    {"name": "FAULT_ZERO", "value": 0},
224    {"name": "FAULT_ONE", "value": 1},
225    {"name": "FAULT_FAIL", "value": 2},
226    {"name": "FAULT_PASS", "value": 3}
227   ]
228  },
229  "DbPSLControl": {
230   "entries": [
231    {"name": "PSLC_AUTO", "value": 0},
232    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
233    {"name": "PSLC_ASAP", "value": 2},
234    {"name": "PSLC_COUNTDOWN", "value": 3}
235   ]
236  },
237  "EXCP_EN": {
238   "entries": [
239    {"name": "INVALID", "value": 1},
240    {"name": "INPUT_DENORMAL", "value": 2},
241    {"name": "DIVIDE_BY_ZERO", "value": 4},
242    {"name": "OVERFLOW", "value": 8},
243    {"name": "UNDERFLOW", "value": 16},
244    {"name": "INEXACT", "value": 32},
245    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
246    {"name": "ADDRESS_WATCH", "value": 128},
247    {"name": "MEMORY_VIOLATION", "value": 256}
248   ]
249  },
250  "FLOAT_MODE": {
251   "entries": [
252    {"name": "FP_32_DENORMS", "value": 48},
253    {"name": "FP_64_DENORMS", "value": 192},
254    {"name": "FP_ALL_DENORMS", "value": 240}
255   ]
256  },
257  "ForceControl": {
258   "entries": [
259    {"name": "FORCE_OFF", "value": 0},
260    {"name": "FORCE_ENABLE", "value": 1},
261    {"name": "FORCE_DISABLE", "value": 2},
262    {"name": "FORCE_RESERVED", "value": 3}
263   ]
264  },
265  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
266   "entries": [
267    {"name": "X_DRAW_POINTS", "value": 0},
268    {"name": "X_DRAW_LINES", "value": 1},
269    {"name": "X_DRAW_TRIANGLES", "value": 2}
270   ]
271  },
272  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
273   "entries": [
274    {"name": "X_DISABLE_POLY_MODE", "value": 0},
275    {"name": "X_DUAL_MODE", "value": 1}
276   ]
277  },
278  "PA_SU_VTX_CNTL__ROUND_MODE": {
279   "entries": [
280    {"name": "X_TRUNCATE", "value": 0},
281    {"name": "X_ROUND", "value": 1},
282    {"name": "X_ROUND_TO_EVEN", "value": 2},
283    {"name": "X_ROUND_TO_ODD", "value": 3}
284   ]
285  },
286  "PkrMap": {
287   "entries": [
288    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
289    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
290    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
291    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
292   ]
293  },
294  "PkrXsel": {
295   "entries": [
296    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
297    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
298    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
299    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
300   ]
301  },
302  "PkrXsel2": {
303   "entries": [
304    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
305    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
306    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
307    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
308   ]
309  },
310  "PkrYsel": {
311   "entries": [
312    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
313    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
314    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
315    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
316   ]
317  },
318  "QUANT_MODE": {
319   "entries": [
320    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
321    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
322    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
323    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
324    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
325    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
326    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
327    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
328   ]
329  },
330  "ROP3": {
331   "entries": [
332    {"name": "ROP3_CLEAR", "value": 0},
333    {"name": "X_0X05", "value": 5},
334    {"name": "X_0X0A", "value": 10},
335    {"name": "X_0X0F", "value": 15},
336    {"name": "ROP3_NOR", "value": 17},
337    {"name": "ROP3_AND_INVERTED", "value": 34},
338    {"name": "ROP3_COPY_INVERTED", "value": 51},
339    {"name": "ROP3_AND_REVERSE", "value": 68},
340    {"name": "X_0X50", "value": 80},
341    {"name": "ROP3_INVERT", "value": 85},
342    {"name": "X_0X5A", "value": 90},
343    {"name": "X_0X5F", "value": 95},
344    {"name": "ROP3_XOR", "value": 102},
345    {"name": "ROP3_NAND", "value": 119},
346    {"name": "ROP3_AND", "value": 136},
347    {"name": "ROP3_EQUIVALENT", "value": 153},
348    {"name": "X_0XA0", "value": 160},
349    {"name": "X_0XA5", "value": 165},
350    {"name": "ROP3_NO_OP", "value": 170},
351    {"name": "X_0XAF", "value": 175},
352    {"name": "ROP3_OR_INVERTED", "value": 187},
353    {"name": "ROP3_COPY", "value": 204},
354    {"name": "ROP3_OR_REVERSE", "value": 221},
355    {"name": "ROP3_OR", "value": 238},
356    {"name": "X_0XF0", "value": 240},
357    {"name": "X_0XF5", "value": 245},
358    {"name": "X_0XFA", "value": 250},
359    {"name": "ROP3_SET", "value": 255}
360   ]
361  },
362  "RbMap": {
363   "entries": [
364    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
365    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
366    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
367    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
368   ]
369  },
370  "RbXsel": {
371   "entries": [
372    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
373    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
374   ]
375  },
376  "RbXsel2": {
377   "entries": [
378    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
379    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
380    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
381    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
382   ]
383  },
384  "RbYsel": {
385   "entries": [
386    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
387    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
388   ]
389  },
390  "ReadPolicy": {
391   "entries": [
392    {"name": "CACHE_LRU_RD", "value": 0},
393    {"name": "CACHE_NOA", "value": 1},
394    {"name": "UNCACHED_RD", "value": 2},
395    {"name": "RESERVED_RDPOLICY", "value": 3}
396   ]
397  },
398  "SPI_PNT_SPRITE_OVERRIDE": {
399   "entries": [
400    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
401    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
402    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
403    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
404    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
405   ]
406  },
407  "SPI_SHADER_EX_FORMAT": {
408   "entries": [
409    {"name": "SPI_SHADER_ZERO", "value": 0},
410    {"name": "SPI_SHADER_32_R", "value": 1},
411    {"name": "SPI_SHADER_32_GR", "value": 2},
412    {"name": "SPI_SHADER_32_AR", "value": 3},
413    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
414    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
415    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
416    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
417    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
418    {"name": "SPI_SHADER_32_ABGR", "value": 9}
419   ]
420  },
421  "SPI_SHADER_FORMAT": {
422   "entries": [
423    {"name": "SPI_SHADER_NONE", "value": 0},
424    {"name": "SPI_SHADER_1COMP", "value": 1},
425    {"name": "SPI_SHADER_2COMP", "value": 2},
426    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
427    {"name": "SPI_SHADER_4COMP", "value": 4}
428   ]
429  },
430  "SPM_PERFMON_STATE": {
431   "entries": [
432    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
433    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
434    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
435    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
436    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
437    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
438   ]
439  },
440  "SX_BLEND_OPT": {
441   "entries": [
442    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
443    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
444    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
445    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
446    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
447    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
448    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
449    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
450   ]
451  },
452  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
453   "entries": [
454    {"name": "EXACT", "value": 0},
455    {"name": "11BIT_FORMAT", "value": 1},
456    {"name": "10BIT_FORMAT", "value": 3},
457    {"name": "8BIT_FORMAT", "value": 6},
458    {"name": "6BIT_FORMAT", "value": 11},
459    {"name": "5BIT_FORMAT", "value": 13},
460    {"name": "4BIT_FORMAT", "value": 15}
461   ]
462  },
463  "SX_DOWNCONVERT_FORMAT": {
464   "entries": [
465    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
466    {"name": "SX_RT_EXPORT_32_R", "value": 1},
467    {"name": "SX_RT_EXPORT_32_A", "value": 2},
468    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
469    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
470    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
471    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
472    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
473    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
474    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
475    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
476    {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11}
477   ]
478  },
479  "SX_OPT_COMB_FCN": {
480   "entries": [
481    {"name": "OPT_COMB_NONE", "value": 0},
482    {"name": "OPT_COMB_ADD", "value": 1},
483    {"name": "OPT_COMB_SUBTRACT", "value": 2},
484    {"name": "OPT_COMB_MIN", "value": 3},
485    {"name": "OPT_COMB_MAX", "value": 4},
486    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
487    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
488    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
489   ]
490  },
491  "ScMap": {
492   "entries": [
493    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
494    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
495    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
496    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
497   ]
498  },
499  "ScUncertaintyRegionMode": {
500   "entries": [
501    {"name": "SC_HALF_LSB", "value": 0},
502    {"name": "SC_LSB_ONE_SIDED", "value": 1},
503    {"name": "SC_LSB_TWO_SIDED", "value": 2}
504   ]
505  },
506  "ScXsel": {
507   "entries": [
508    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
509    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
510    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
511    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
512   ]
513  },
514  "ScYsel": {
515   "entries": [
516    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
517    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
518    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
519    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
520   ]
521  },
522  "SeMap": {
523   "entries": [
524    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
525    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
526    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
527    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
528   ]
529  },
530  "SePairMap": {
531   "entries": [
532    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
533    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
534    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
535    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
536   ]
537  },
538  "SePairXsel": {
539   "entries": [
540    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
541    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
542    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
543    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
544   ]
545  },
546  "SePairYsel": {
547   "entries": [
548    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
549    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
550    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
551    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
552   ]
553  },
554  "SeXsel": {
555   "entries": [
556    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
557    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
558    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
559    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
560   ]
561  },
562  "SeYsel": {
563   "entries": [
564    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
565    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
566    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
567    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
568   ]
569  },
570  "StencilFormat": {
571   "entries": [
572    {"name": "STENCIL_INVALID", "value": 0},
573    {"name": "STENCIL_8", "value": 1}
574   ]
575  },
576  "StencilOp": {
577   "entries": [
578    {"name": "STENCIL_KEEP", "value": 0},
579    {"name": "STENCIL_ZERO", "value": 1},
580    {"name": "STENCIL_ONES", "value": 2},
581    {"name": "STENCIL_REPLACE_TEST", "value": 3},
582    {"name": "STENCIL_REPLACE_OP", "value": 4},
583    {"name": "STENCIL_ADD_CLAMP", "value": 5},
584    {"name": "STENCIL_SUB_CLAMP", "value": 6},
585    {"name": "STENCIL_INVERT", "value": 7},
586    {"name": "STENCIL_ADD_WRAP", "value": 8},
587    {"name": "STENCIL_SUB_WRAP", "value": 9},
588    {"name": "STENCIL_AND", "value": 10},
589    {"name": "STENCIL_OR", "value": 11},
590    {"name": "STENCIL_XOR", "value": 12},
591    {"name": "STENCIL_NAND", "value": 13},
592    {"name": "STENCIL_NOR", "value": 14},
593    {"name": "STENCIL_XNOR", "value": 15}
594   ]
595  },
596  "SurfaceEndian": {
597   "entries": [
598    {"name": "ENDIAN_NONE", "value": 0},
599    {"name": "ENDIAN_8IN16", "value": 1},
600    {"name": "ENDIAN_8IN32", "value": 2},
601    {"name": "ENDIAN_8IN64", "value": 3}
602   ]
603  },
604  "SurfaceNumber": {
605   "entries": [
606    {"name": "NUMBER_UNORM", "value": 0},
607    {"name": "NUMBER_SNORM", "value": 1},
608    {"name": "NUMBER_USCALED", "value": 2},
609    {"name": "NUMBER_SSCALED", "value": 3},
610    {"name": "NUMBER_UINT", "value": 4},
611    {"name": "NUMBER_SINT", "value": 5},
612    {"name": "NUMBER_SRGB", "value": 6},
613    {"name": "NUMBER_FLOAT", "value": 7}
614   ]
615  },
616  "SurfaceSwap": {
617   "entries": [
618    {"name": "SWAP_STD", "value": 0},
619    {"name": "SWAP_ALT", "value": 1},
620    {"name": "SWAP_STD_REV", "value": 2},
621    {"name": "SWAP_ALT_REV", "value": 3}
622   ]
623  },
624  "ThreadTraceRegInclude": {
625   "entries": [
626    {"name": "REG_INCLUDE_SQDEC", "value": 1},
627    {"name": "REG_INCLUDE_SHDEC", "value": 2},
628    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
629    {"name": "REG_INCLUDE_COMP", "value": 8},
630    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
631    {"name": "REG_INCLUDE_CONFIG", "value": 32},
632    {"name": "REG_INCLUDE_OTHER", "value": 64},
633    {"name": "REG_INCLUDE_READS", "value": 128}
634   ]
635  },
636  "ThreadTraceTokenExclude": {
637   "entries": [
638    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
639    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
640    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
641    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
642    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
643    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
644    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
645    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
646    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
647    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
648    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
649    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
650   ]
651  },
652  "VGT_DETECT_ONE": {
653   "entries": [
654    {"name": "PRE_CLAMP_TF1", "value": 0},
655    {"name": "POST_CLAMP_TF1", "value": 1},
656    {"name": "DISABLE_TF1", "value": 2}
657   ]
658  },
659  "VGT_DETECT_ZERO": {
660   "entries": [
661    {"name": "PRE_CLAMP_TF0", "value": 0},
662    {"name": "POST_CLAMP_TF0", "value": 1},
663    {"name": "DISABLE_TF0", "value": 2}
664   ]
665  },
666  "VGT_DIST_MODE": {
667   "entries": [
668    {"name": "NO_DIST", "value": 0},
669    {"name": "PATCHES", "value": 1},
670    {"name": "DONUTS", "value": 2},
671    {"name": "TRAPEZOIDS", "value": 3}
672   ]
673  },
674  "VGT_DI_MAJOR_MODE_SELECT": {
675   "entries": [
676    {"name": "DI_MAJOR_MODE_0", "value": 0},
677    {"name": "DI_MAJOR_MODE_1", "value": 1}
678   ]
679  },
680  "VGT_DI_PRIM_TYPE": {
681   "entries": [
682    {"name": "DI_PT_NONE", "value": 0},
683    {"name": "DI_PT_POINTLIST", "value": 1},
684    {"name": "DI_PT_LINELIST", "value": 2},
685    {"name": "DI_PT_LINESTRIP", "value": 3},
686    {"name": "DI_PT_TRILIST", "value": 4},
687    {"name": "DI_PT_TRIFAN", "value": 5},
688    {"name": "DI_PT_TRISTRIP", "value": 6},
689    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
690    {"name": "DI_PT_UNUSED_1", "value": 8},
691    {"name": "DI_PT_PATCH", "value": 9},
692    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
693    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
694    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
695    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
696    {"name": "DI_PT_UNUSED_3", "value": 14},
697    {"name": "DI_PT_UNUSED_4", "value": 15},
698    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
699    {"name": "DI_PT_RECTLIST", "value": 17},
700    {"name": "DI_PT_LINELOOP", "value": 18},
701    {"name": "DI_PT_QUADLIST", "value": 19},
702    {"name": "DI_PT_QUADSTRIP", "value": 20},
703    {"name": "DI_PT_POLYGON", "value": 21}
704   ]
705  },
706  "VGT_DI_SOURCE_SELECT": {
707   "entries": [
708    {"name": "DI_SRC_SEL_DMA", "value": 0},
709    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
710    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
711    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
712   ]
713  },
714  "VGT_DMA_BUF_TYPE": {
715   "entries": [
716    {"name": "VGT_DMA_BUF_MEM", "value": 0},
717    {"name": "VGT_DMA_BUF_RING", "value": 1},
718    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
719    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
720   ]
721  },
722  "VGT_DMA_SWAP_MODE": {
723   "entries": [
724    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
725    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
726    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
727    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
728   ]
729  },
730  "VGT_EVENT_TYPE": {
731   "entries": [
732    {"name": "Reserved_0x00", "value": 0},
733    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
734    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
735    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
736    {"name": "CACHE_FLUSH_TS", "value": 4},
737    {"name": "CONTEXT_DONE", "value": 5},
738    {"name": "CACHE_FLUSH", "value": 6},
739    {"name": "CS_PARTIAL_FLUSH", "value": 7},
740    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
741    {"name": "SET_FE_ID", "value": 9},
742    {"name": "VGT_STREAMOUT_RESET", "value": 10},
743    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
744    {"name": "END_OF_PIPE_IB_END", "value": 12},
745    {"name": "RST_PIX_CNT", "value": 13},
746    {"name": "BREAK_BATCH", "value": 14},
747    {"name": "VS_PARTIAL_FLUSH", "value": 15},
748    {"name": "PS_PARTIAL_FLUSH", "value": 16},
749    {"name": "FLUSH_HS_OUTPUT", "value": 17},
750    {"name": "FLUSH_DFSM", "value": 18},
751    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
752    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
753    {"name": "ZPASS_DONE", "value": 21},
754    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
755    {"name": "PERFCOUNTER_START", "value": 23},
756    {"name": "PERFCOUNTER_STOP", "value": 24},
757    {"name": "PIPELINESTAT_START", "value": 25},
758    {"name": "PIPELINESTAT_STOP", "value": 26},
759    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
760    {"name": "FLUSH_ES_OUTPUT", "value": 28},
761    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
762    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
763    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
764    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
765    {"name": "RESET_VTX_CNT", "value": 33},
766    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
767    {"name": "CS_CONTEXT_DONE", "value": 35},
768    {"name": "VGT_FLUSH", "value": 36},
769    {"name": "TGID_ROLLOVER", "value": 37},
770    {"name": "SQ_NON_EVENT", "value": 38},
771    {"name": "SC_SEND_DB_VPZ", "value": 39},
772    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
773    {"name": "FLUSH_SX_TS", "value": 41},
774    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
775    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
776    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
777    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
778    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
779    {"name": "CS_DONE", "value": 47},
780    {"name": "PS_DONE", "value": 48},
781    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
782    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
783    {"name": "THREAD_TRACE_START", "value": 51},
784    {"name": "THREAD_TRACE_STOP", "value": 52},
785    {"name": "THREAD_TRACE_MARKER", "value": 53},
786    {"name": "THREAD_TRACE_DRAW", "value": 54},
787    {"name": "THREAD_TRACE_FINISH", "value": 55},
788    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
789    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
790    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
791    {"name": "CONTEXT_SUSPEND", "value": 59},
792    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
793    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
794    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
795    {"name": "DRAW_DONE", "value": 63}
796   ]
797  },
798  "VGT_GS_CUT_MODE": {
799   "entries": [
800    {"name": "GS_CUT_1024", "value": 0},
801    {"name": "GS_CUT_512", "value": 1},
802    {"name": "GS_CUT_256", "value": 2},
803    {"name": "GS_CUT_128", "value": 3}
804   ]
805  },
806  "VGT_GS_MODE_TYPE": {
807   "entries": [
808    {"name": "GS_OFF", "value": 0},
809    {"name": "GS_SCENARIO_A", "value": 1},
810    {"name": "GS_SCENARIO_B", "value": 2},
811    {"name": "GS_SCENARIO_G", "value": 3},
812    {"name": "GS_SCENARIO_C", "value": 4},
813    {"name": "SPRITE_EN", "value": 5}
814   ]
815  },
816  "VGT_GS_OUTPRIM_TYPE": {
817   "entries": [
818    {"name": "POINTLIST", "value": 0},
819    {"name": "LINESTRIP", "value": 1},
820    {"name": "TRISTRIP", "value": 2},
821    {"name": "RECTLIST", "value": 3}
822   ]
823  },
824  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
825   "entries": [
826    {"name": "X_8K_DWORDS", "value": 0},
827    {"name": "X_4K_DWORDS", "value": 1},
828    {"name": "X_2K_DWORDS", "value": 2},
829    {"name": "X_1K_DWORDS", "value": 3}
830   ]
831  },
832  "VGT_INDEX_TYPE_MODE": {
833   "entries": [
834    {"name": "VGT_INDEX_16", "value": 0},
835    {"name": "VGT_INDEX_32", "value": 1},
836    {"name": "VGT_INDEX_8", "value": 2}
837   ]
838  },
839  "VGT_RDREQ_POLICY": {
840   "entries": [
841    {"name": "VGT_POLICY_LRU", "value": 0},
842    {"name": "VGT_POLICY_STREAM", "value": 1},
843    {"name": "VGT_POLICY_BYPASS", "value": 2}
844   ]
845  },
846  "VGT_STAGES_ES_EN": {
847   "entries": [
848    {"name": "ES_STAGE_OFF", "value": 0},
849    {"name": "ES_STAGE_DS", "value": 1},
850    {"name": "ES_STAGE_REAL", "value": 2},
851    {"name": "RESERVED_ES", "value": 3}
852   ]
853  },
854  "VGT_STAGES_GS_EN": {
855   "entries": [
856    {"name": "GS_STAGE_OFF", "value": 0},
857    {"name": "GS_STAGE_ON", "value": 1}
858   ]
859  },
860  "VGT_STAGES_HS_EN": {
861   "entries": [
862    {"name": "HS_STAGE_OFF", "value": 0},
863    {"name": "HS_STAGE_ON", "value": 1}
864   ]
865  },
866  "VGT_STAGES_LS_EN": {
867   "entries": [
868    {"name": "LS_STAGE_OFF", "value": 0},
869    {"name": "LS_STAGE_ON", "value": 1},
870    {"name": "CS_STAGE_ON", "value": 2},
871    {"name": "RESERVED_LS", "value": 3}
872   ]
873  },
874  "VGT_STAGES_VS_EN": {
875   "entries": [
876    {"name": "VS_STAGE_REAL", "value": 0},
877    {"name": "VS_STAGE_DS", "value": 1},
878    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
879    {"name": "RESERVED_VS", "value": 3}
880   ]
881  },
882  "VGT_TESS_PARTITION": {
883   "entries": [
884    {"name": "PART_INTEGER", "value": 0},
885    {"name": "PART_POW2", "value": 1},
886    {"name": "PART_FRAC_ODD", "value": 2},
887    {"name": "PART_FRAC_EVEN", "value": 3}
888   ]
889  },
890  "VGT_TESS_TOPOLOGY": {
891   "entries": [
892    {"name": "OUTPUT_POINT", "value": 0},
893    {"name": "OUTPUT_LINE", "value": 1},
894    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
895    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
896   ]
897  },
898  "VGT_TESS_TYPE": {
899   "entries": [
900    {"name": "TESS_ISOLINE", "value": 0},
901    {"name": "TESS_TRIANGLE", "value": 1},
902    {"name": "TESS_QUAD", "value": 2}
903   ]
904  },
905  "VRSCombinerMode": {
906   "entries": [
907    {"name": "VRS_COMB_MODE_PASSTHRU", "value": 0},
908    {"name": "VRS_COMB_MODE_OVERRIDE", "value": 1},
909    {"name": "VRS_COMB_MODE_MIN", "value": 2},
910    {"name": "VRS_COMB_MODE_MAX", "value": 3},
911    {"name": "VRS_COMB_MODE_SATURATE", "value": 4}
912   ]
913  },
914  "VRSHtileEncoding": {
915   "entries": [
916    {"name": "VRS_HTILE_DISABLE", "value": 0},
917    {"name": "VRS_HTILE_2BIT_ENCODING", "value": 1},
918    {"name": "VRS_HTILE_4BIT_ENCODING", "value": 2}
919   ]
920  },
921  "WritePolicy": {
922   "entries": [
923    {"name": "CACHE_LRU_WR", "value": 0},
924    {"name": "CACHE_STREAM", "value": 1},
925    {"name": "CACHE_BYPASS", "value": 2},
926    {"name": "UNCACHED_WR", "value": 3}
927   ]
928  },
929  "ZFormat": {
930   "entries": [
931    {"name": "Z_INVALID", "value": 0},
932    {"name": "Z_16", "value": 1},
933    {"name": "Z_24", "value": 2},
934    {"name": "Z_32_FLOAT", "value": 3}
935   ]
936  },
937  "ZLimitSumm": {
938   "entries": [
939    {"name": "FORCE_SUMM_OFF", "value": 0},
940    {"name": "FORCE_SUMM_MINZ", "value": 1},
941    {"name": "FORCE_SUMM_MAXZ", "value": 2},
942    {"name": "FORCE_SUMM_BOTH", "value": 3}
943   ]
944  },
945  "ZOrder": {
946   "entries": [
947    {"name": "LATE_Z", "value": 0},
948    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
949    {"name": "RE_Z", "value": 2},
950    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
951   ]
952  }
953 },
954 "register_mappings": [
955  {
956   "chips": ["gfx103"],
957   "map": {"at": 40, "to": "mm"},
958   "name": "SQ_WAVE_ACTIVE",
959   "type_ref": "SQ_WAVE_ACTIVE"
960  },
961  {
962   "chips": ["gfx103"],
963   "map": {"at": 44, "to": "mm"},
964   "name": "SQ_WAVE_VALID_AND_IDLE",
965   "type_ref": "SQ_WAVE_ACTIVE"
966  },
967  {
968   "chips": ["gfx103"],
969   "map": {"at": 1028, "to": "mm"},
970   "name": "SQ_WAVE_MODE",
971   "type_ref": "SQ_WAVE_MODE"
972  },
973  {
974   "chips": ["gfx103"],
975   "map": {"at": 1032, "to": "mm"},
976   "name": "SQ_WAVE_STATUS",
977   "type_ref": "SQ_WAVE_STATUS"
978  },
979  {
980   "chips": ["gfx103"],
981   "map": {"at": 1036, "to": "mm"},
982   "name": "SQ_WAVE_TRAPSTS",
983   "type_ref": "SQ_WAVE_TRAPSTS"
984  },
985  {
986   "chips": ["gfx103"],
987   "map": {"at": 1040, "to": "mm"},
988   "name": "SQ_WAVE_HW_ID_LEGACY",
989   "type_ref": "SQ_WAVE_HW_ID_LEGACY"
990  },
991  {
992   "chips": ["gfx103"],
993   "map": {"at": 1044, "to": "mm"},
994   "name": "SQ_WAVE_GPR_ALLOC",
995   "type_ref": "SQ_WAVE_GPR_ALLOC"
996  },
997  {
998   "chips": ["gfx103"],
999   "map": {"at": 1048, "to": "mm"},
1000   "name": "SQ_WAVE_LDS_ALLOC",
1001   "type_ref": "SQ_WAVE_LDS_ALLOC"
1002  },
1003  {
1004   "chips": ["gfx103"],
1005   "map": {"at": 1052, "to": "mm"},
1006   "name": "SQ_WAVE_IB_STS",
1007   "type_ref": "SQ_WAVE_IB_STS"
1008  },
1009  {
1010   "chips": ["gfx103"],
1011   "map": {"at": 1056, "to": "mm"},
1012   "name": "SQ_WAVE_PC_LO"
1013  },
1014  {
1015   "chips": ["gfx103"],
1016   "map": {"at": 1060, "to": "mm"},
1017   "name": "SQ_WAVE_PC_HI",
1018   "type_ref": "SQ_WAVE_PC_HI"
1019  },
1020  {
1021   "chips": ["gfx103"],
1022   "map": {"at": 1064, "to": "mm"},
1023   "name": "SQ_WAVE_INST_DW0"
1024  },
1025  {
1026   "chips": ["gfx103"],
1027   "map": {"at": 1076, "to": "mm"},
1028   "name": "SQ_WAVE_IB_DBG1",
1029   "type_ref": "SQ_WAVE_IB_DBG1"
1030  },
1031  {
1032   "chips": ["gfx103"],
1033   "map": {"at": 1080, "to": "mm"},
1034   "name": "SQ_WAVE_FLUSH_IB"
1035  },
1036  {
1037   "chips": ["gfx103"],
1038   "map": {"at": 1104, "to": "mm"},
1039   "name": "SQ_WAVE_FLAT_SCRATCH_LO"
1040  },
1041  {
1042   "chips": ["gfx103"],
1043   "map": {"at": 1108, "to": "mm"},
1044   "name": "SQ_WAVE_FLAT_SCRATCH_HI"
1045  },
1046  {
1047   "chips": ["gfx103"],
1048   "map": {"at": 1116, "to": "mm"},
1049   "name": "SQ_WAVE_HW_ID1",
1050   "type_ref": "SQ_WAVE_HW_ID1"
1051  },
1052  {
1053   "chips": ["gfx103"],
1054   "map": {"at": 1120, "to": "mm"},
1055   "name": "SQ_WAVE_HW_ID2",
1056   "type_ref": "SQ_WAVE_HW_ID2"
1057  },
1058  {
1059   "chips": ["gfx103"],
1060   "map": {"at": 1124, "to": "mm"},
1061   "name": "SQ_WAVE_POPS_PACKER",
1062   "type_ref": "SQ_WAVE_POPS_PACKER"
1063  },
1064  {
1065   "chips": ["gfx103"],
1066   "map": {"at": 1128, "to": "mm"},
1067   "name": "SQ_WAVE_SCHED_MODE",
1068   "type_ref": "SQ_WAVE_SCHED_MODE"
1069  },
1070  {
1071   "chips": ["gfx103"],
1072   "map": {"at": 1132, "to": "mm"},
1073   "name": "SQ_WAVE_VGPR_OFFSET",
1074   "type_ref": "SQ_WAVE_VGPR_OFFSET"
1075  },
1076  {
1077   "chips": ["gfx103"],
1078   "map": {"at": 1136, "to": "mm"},
1079   "name": "SQ_WAVE_IB_STS2",
1080   "type_ref": "SQ_WAVE_IB_STS2"
1081  },
1082  {
1083   "chips": ["gfx103"],
1084   "map": {"at": 1140, "to": "mm"},
1085   "name": "SQ_WAVE_SHADER_CYCLES",
1086   "type_ref": "SQ_WAVE_SHADER_CYCLES"
1087  },
1088  {
1089   "chips": ["gfx103"],
1090   "map": {"at": 2480, "to": "mm"},
1091   "name": "SQ_WAVE_TTMP0"
1092  },
1093  {
1094   "chips": ["gfx103"],
1095   "map": {"at": 2484, "to": "mm"},
1096   "name": "SQ_WAVE_TTMP1"
1097  },
1098  {
1099   "chips": ["gfx103"],
1100   "map": {"at": 2488, "to": "mm"},
1101   "name": "SQ_WAVE_TTMP2"
1102  },
1103  {
1104   "chips": ["gfx103"],
1105   "map": {"at": 2492, "to": "mm"},
1106   "name": "SQ_WAVE_TTMP3"
1107  },
1108  {
1109   "chips": ["gfx103"],
1110   "map": {"at": 2496, "to": "mm"},
1111   "name": "SQ_WAVE_TTMP4"
1112  },
1113  {
1114   "chips": ["gfx103"],
1115   "map": {"at": 2500, "to": "mm"},
1116   "name": "SQ_WAVE_TTMP5"
1117  },
1118  {
1119   "chips": ["gfx103"],
1120   "map": {"at": 2504, "to": "mm"},
1121   "name": "SQ_WAVE_TTMP6"
1122  },
1123  {
1124   "chips": ["gfx103"],
1125   "map": {"at": 2508, "to": "mm"},
1126   "name": "SQ_WAVE_TTMP7"
1127  },
1128  {
1129   "chips": ["gfx103"],
1130   "map": {"at": 2512, "to": "mm"},
1131   "name": "SQ_WAVE_TTMP8"
1132  },
1133  {
1134   "chips": ["gfx103"],
1135   "map": {"at": 2516, "to": "mm"},
1136   "name": "SQ_WAVE_TTMP9"
1137  },
1138  {
1139   "chips": ["gfx103"],
1140   "map": {"at": 2520, "to": "mm"},
1141   "name": "SQ_WAVE_TTMP10"
1142  },
1143  {
1144   "chips": ["gfx103"],
1145   "map": {"at": 2524, "to": "mm"},
1146   "name": "SQ_WAVE_TTMP11"
1147  },
1148  {
1149   "chips": ["gfx103"],
1150   "map": {"at": 2528, "to": "mm"},
1151   "name": "SQ_WAVE_TTMP12"
1152  },
1153  {
1154   "chips": ["gfx103"],
1155   "map": {"at": 2532, "to": "mm"},
1156   "name": "SQ_WAVE_TTMP13"
1157  },
1158  {
1159   "chips": ["gfx103"],
1160   "map": {"at": 2536, "to": "mm"},
1161   "name": "SQ_WAVE_TTMP14"
1162  },
1163  {
1164   "chips": ["gfx103"],
1165   "map": {"at": 2540, "to": "mm"},
1166   "name": "SQ_WAVE_TTMP15"
1167  },
1168  {
1169   "chips": ["gfx103"],
1170   "map": {"at": 2544, "to": "mm"},
1171   "name": "SQ_WAVE_M0"
1172  },
1173  {
1174   "chips": ["gfx103"],
1175   "map": {"at": 2552, "to": "mm"},
1176   "name": "SQ_WAVE_EXEC_LO"
1177  },
1178  {
1179   "chips": ["gfx103"],
1180   "map": {"at": 2556, "to": "mm"},
1181   "name": "SQ_WAVE_EXEC_HI"
1182  },
1183  {
1184   "chips": ["gfx103"],
1185   "map": {"at": 32776, "to": "mm"},
1186   "name": "GRBM_STATUS2",
1187   "type_ref": "GRBM_STATUS2"
1188  },
1189  {
1190   "chips": ["gfx103"],
1191   "map": {"at": 32784, "to": "mm"},
1192   "name": "GRBM_STATUS",
1193   "type_ref": "GRBM_STATUS"
1194  },
1195  {
1196   "chips": ["gfx103"],
1197   "map": {"at": 32788, "to": "mm"},
1198   "name": "GRBM_STATUS_SE0",
1199   "type_ref": "GRBM_STATUS_SE0"
1200  },
1201  {
1202   "chips": ["gfx103"],
1203   "map": {"at": 32792, "to": "mm"},
1204   "name": "GRBM_STATUS_SE1",
1205   "type_ref": "GRBM_STATUS_SE0"
1206  },
1207  {
1208   "chips": ["gfx103"],
1209   "map": {"at": 32796, "to": "mm"},
1210   "name": "GRBM_STATUS3",
1211   "type_ref": "GRBM_STATUS3"
1212  },
1213  {
1214   "chips": ["gfx103"],
1215   "map": {"at": 32824, "to": "mm"},
1216   "name": "GRBM_STATUS_SE2",
1217   "type_ref": "GRBM_STATUS_SE0"
1218  },
1219  {
1220   "chips": ["gfx103"],
1221   "map": {"at": 32828, "to": "mm"},
1222   "name": "GRBM_STATUS_SE3",
1223   "type_ref": "GRBM_STATUS_SE0"
1224  },
1225  {
1226   "chips": ["gfx103"],
1227   "map": {"at": 33296, "to": "mm"},
1228   "name": "CP_CPC_STATUS",
1229   "type_ref": "CP_CPC_STATUS"
1230  },
1231  {
1232   "chips": ["gfx103"],
1233   "map": {"at": 33300, "to": "mm"},
1234   "name": "CP_CPC_BUSY_STAT",
1235   "type_ref": "CP_CPC_BUSY_STAT"
1236  },
1237  {
1238   "chips": ["gfx103"],
1239   "map": {"at": 33304, "to": "mm"},
1240   "name": "CP_CPC_STALLED_STAT1",
1241   "type_ref": "CP_CPC_STALLED_STAT1"
1242  },
1243  {
1244   "chips": ["gfx103"],
1245   "map": {"at": 33308, "to": "mm"},
1246   "name": "CP_CPF_STATUS",
1247   "type_ref": "CP_CPF_STATUS"
1248  },
1249  {
1250   "chips": ["gfx103"],
1251   "map": {"at": 33312, "to": "mm"},
1252   "name": "CP_CPF_BUSY_STAT",
1253   "type_ref": "CP_CPF_BUSY_STAT"
1254  },
1255  {
1256   "chips": ["gfx103"],
1257   "map": {"at": 33316, "to": "mm"},
1258   "name": "CP_CPF_STALLED_STAT1",
1259   "type_ref": "CP_CPF_STALLED_STAT1"
1260  },
1261  {
1262   "chips": ["gfx103"],
1263   "map": {"at": 33320, "to": "mm"},
1264   "name": "CP_CPC_BUSY_STAT2",
1265   "type_ref": "CP_CPC_BUSY_STAT2"
1266  },
1267  {
1268   "chips": ["gfx103"],
1269   "map": {"at": 33324, "to": "mm"},
1270   "name": "CP_CPC_GRBM_FREE_COUNT",
1271   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1272  },
1273  {
1274   "chips": ["gfx103"],
1275   "map": {"at": 33328, "to": "mm"},
1276   "name": "CP_CPC_PRIV_VIOLATION_ADDR",
1277   "type_ref": "CP_CPC_PRIV_VIOLATION_ADDR"
1278  },
1279  {
1280   "chips": ["gfx103"],
1281   "map": {"at": 33344, "to": "mm"},
1282   "name": "CP_CPC_SCRATCH_INDEX",
1283   "type_ref": "CP_CPC_SCRATCH_INDEX"
1284  },
1285  {
1286   "chips": ["gfx103"],
1287   "map": {"at": 33348, "to": "mm"},
1288   "name": "CP_CPC_SCRATCH_DATA"
1289  },
1290  {
1291   "chips": ["gfx103"],
1292   "map": {"at": 33352, "to": "mm"},
1293   "name": "CP_CPF_GRBM_FREE_COUNT",
1294   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1295  },
1296  {
1297   "chips": ["gfx103"],
1298   "map": {"at": 33356, "to": "mm"},
1299   "name": "CP_CPF_BUSY_STAT2",
1300   "type_ref": "CP_CPF_BUSY_STAT2"
1301  },
1302  {
1303   "chips": ["gfx103"],
1304   "map": {"at": 33436, "to": "mm"},
1305   "name": "CP_CPC_HALT_HYST_COUNT",
1306   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1307  },
1308  {
1309   "chips": ["gfx103"],
1310   "map": {"at": 36096, "to": "mm"},
1311   "name": "SQ_THREAD_TRACE_BUF0_BASE"
1312  },
1313  {
1314   "chips": ["gfx103"],
1315   "map": {"at": 36100, "to": "mm"},
1316   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1317   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1318  },
1319  {
1320   "chips": ["gfx103"],
1321   "map": {"at": 36104, "to": "mm"},
1322   "name": "SQ_THREAD_TRACE_BUF1_BASE"
1323  },
1324  {
1325   "chips": ["gfx103"],
1326   "map": {"at": 36108, "to": "mm"},
1327   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1328   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1329  },
1330  {
1331   "chips": ["gfx103"],
1332   "map": {"at": 36112, "to": "mm"},
1333   "name": "SQ_THREAD_TRACE_WPTR",
1334   "type_ref": "SQ_THREAD_TRACE_WPTR"
1335  },
1336  {
1337   "chips": ["gfx103"],
1338   "map": {"at": 36116, "to": "mm"},
1339   "name": "SQ_THREAD_TRACE_MASK",
1340   "type_ref": "SQ_THREAD_TRACE_MASK"
1341  },
1342  {
1343   "chips": ["gfx103"],
1344   "map": {"at": 36120, "to": "mm"},
1345   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1346   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1347  },
1348  {
1349   "chips": ["gfx103"],
1350   "map": {"at": 36124, "to": "mm"},
1351   "name": "SQ_THREAD_TRACE_CTRL",
1352   "type_ref": "SQ_THREAD_TRACE_CTRL"
1353  },
1354  {
1355   "chips": ["gfx103"],
1356   "map": {"at": 36128, "to": "mm"},
1357   "name": "SQ_THREAD_TRACE_STATUS",
1358   "type_ref": "SQ_THREAD_TRACE_STATUS"
1359  },
1360  {
1361   "chips": ["gfx103"],
1362   "map": {"at": 36132, "to": "mm"},
1363   "name": "SQ_THREAD_TRACE_DROPPED_CNTR"
1364  },
1365  {
1366   "chips": ["gfx103"],
1367   "map": {"at": 36140, "to": "mm"},
1368   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR"
1369  },
1370  {
1371   "chips": ["gfx103"],
1372   "map": {"at": 36144, "to": "mm"},
1373   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR"
1374  },
1375  {
1376   "chips": ["gfx103"],
1377   "map": {"at": 36148, "to": "mm"},
1378   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR"
1379  },
1380  {
1381   "chips": ["gfx103"],
1382   "map": {"at": 36152, "to": "mm"},
1383   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
1384  },
1385  {
1386   "chips": ["gfx103"],
1387   "map": {"at": 36156, "to": "mm"},
1388   "name": "SQ_THREAD_TRACE_STATUS2",
1389   "type_ref": "SQ_THREAD_TRACE_STATUS2"
1390  },
1391  {
1392   "chips": ["gfx103"],
1393   "map": {"at": 37168, "to": "mm"},
1394   "name": "SPI_CONFIG_CNTL",
1395   "type_ref": "SPI_CONFIG_CNTL"
1396  },
1397  {
1398   "chips": ["gfx103"],
1399   "map": {"at": 39160, "to": "mm"},
1400   "name": "GB_ADDR_CONFIG",
1401   "type_ref": "GB_ADDR_CONFIG"
1402  },
1403  {
1404   "chips": ["gfx103"],
1405   "map": {"at": 45060, "to": "mm"},
1406   "name": "SPI_SHADER_PGM_RSRC4_PS",
1407   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1408  },
1409  {
1410   "chips": ["gfx103"],
1411   "map": {"at": 45080, "to": "mm"},
1412   "name": "SPI_SHADER_PGM_CHKSUM_PS"
1413  },
1414  {
1415   "chips": ["gfx103"],
1416   "map": {"at": 45084, "to": "mm"},
1417   "name": "SPI_SHADER_PGM_RSRC3_PS",
1418   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1419  },
1420  {
1421   "chips": ["gfx103"],
1422   "map": {"at": 45088, "to": "mm"},
1423   "name": "SPI_SHADER_PGM_LO_PS"
1424  },
1425  {
1426   "chips": ["gfx103"],
1427   "map": {"at": 45092, "to": "mm"},
1428   "name": "SPI_SHADER_PGM_HI_PS",
1429   "type_ref": "SPI_SHADER_PGM_HI_PS"
1430  },
1431  {
1432   "chips": ["gfx103"],
1433   "map": {"at": 45096, "to": "mm"},
1434   "name": "SPI_SHADER_PGM_RSRC1_PS",
1435   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1436  },
1437  {
1438   "chips": ["gfx103"],
1439   "map": {"at": 45100, "to": "mm"},
1440   "name": "SPI_SHADER_PGM_RSRC2_PS",
1441   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1442  },
1443  {
1444   "chips": ["gfx103"],
1445   "map": {"at": 45104, "to": "mm"},
1446   "name": "SPI_SHADER_USER_DATA_PS_0"
1447  },
1448  {
1449   "chips": ["gfx103"],
1450   "map": {"at": 45108, "to": "mm"},
1451   "name": "SPI_SHADER_USER_DATA_PS_1"
1452  },
1453  {
1454   "chips": ["gfx103"],
1455   "map": {"at": 45112, "to": "mm"},
1456   "name": "SPI_SHADER_USER_DATA_PS_2"
1457  },
1458  {
1459   "chips": ["gfx103"],
1460   "map": {"at": 45116, "to": "mm"},
1461   "name": "SPI_SHADER_USER_DATA_PS_3"
1462  },
1463  {
1464   "chips": ["gfx103"],
1465   "map": {"at": 45120, "to": "mm"},
1466   "name": "SPI_SHADER_USER_DATA_PS_4"
1467  },
1468  {
1469   "chips": ["gfx103"],
1470   "map": {"at": 45124, "to": "mm"},
1471   "name": "SPI_SHADER_USER_DATA_PS_5"
1472  },
1473  {
1474   "chips": ["gfx103"],
1475   "map": {"at": 45128, "to": "mm"},
1476   "name": "SPI_SHADER_USER_DATA_PS_6"
1477  },
1478  {
1479   "chips": ["gfx103"],
1480   "map": {"at": 45132, "to": "mm"},
1481   "name": "SPI_SHADER_USER_DATA_PS_7"
1482  },
1483  {
1484   "chips": ["gfx103"],
1485   "map": {"at": 45136, "to": "mm"},
1486   "name": "SPI_SHADER_USER_DATA_PS_8"
1487  },
1488  {
1489   "chips": ["gfx103"],
1490   "map": {"at": 45140, "to": "mm"},
1491   "name": "SPI_SHADER_USER_DATA_PS_9"
1492  },
1493  {
1494   "chips": ["gfx103"],
1495   "map": {"at": 45144, "to": "mm"},
1496   "name": "SPI_SHADER_USER_DATA_PS_10"
1497  },
1498  {
1499   "chips": ["gfx103"],
1500   "map": {"at": 45148, "to": "mm"},
1501   "name": "SPI_SHADER_USER_DATA_PS_11"
1502  },
1503  {
1504   "chips": ["gfx103"],
1505   "map": {"at": 45152, "to": "mm"},
1506   "name": "SPI_SHADER_USER_DATA_PS_12"
1507  },
1508  {
1509   "chips": ["gfx103"],
1510   "map": {"at": 45156, "to": "mm"},
1511   "name": "SPI_SHADER_USER_DATA_PS_13"
1512  },
1513  {
1514   "chips": ["gfx103"],
1515   "map": {"at": 45160, "to": "mm"},
1516   "name": "SPI_SHADER_USER_DATA_PS_14"
1517  },
1518  {
1519   "chips": ["gfx103"],
1520   "map": {"at": 45164, "to": "mm"},
1521   "name": "SPI_SHADER_USER_DATA_PS_15"
1522  },
1523  {
1524   "chips": ["gfx103"],
1525   "map": {"at": 45168, "to": "mm"},
1526   "name": "SPI_SHADER_USER_DATA_PS_16"
1527  },
1528  {
1529   "chips": ["gfx103"],
1530   "map": {"at": 45172, "to": "mm"},
1531   "name": "SPI_SHADER_USER_DATA_PS_17"
1532  },
1533  {
1534   "chips": ["gfx103"],
1535   "map": {"at": 45176, "to": "mm"},
1536   "name": "SPI_SHADER_USER_DATA_PS_18"
1537  },
1538  {
1539   "chips": ["gfx103"],
1540   "map": {"at": 45180, "to": "mm"},
1541   "name": "SPI_SHADER_USER_DATA_PS_19"
1542  },
1543  {
1544   "chips": ["gfx103"],
1545   "map": {"at": 45184, "to": "mm"},
1546   "name": "SPI_SHADER_USER_DATA_PS_20"
1547  },
1548  {
1549   "chips": ["gfx103"],
1550   "map": {"at": 45188, "to": "mm"},
1551   "name": "SPI_SHADER_USER_DATA_PS_21"
1552  },
1553  {
1554   "chips": ["gfx103"],
1555   "map": {"at": 45192, "to": "mm"},
1556   "name": "SPI_SHADER_USER_DATA_PS_22"
1557  },
1558  {
1559   "chips": ["gfx103"],
1560   "map": {"at": 45196, "to": "mm"},
1561   "name": "SPI_SHADER_USER_DATA_PS_23"
1562  },
1563  {
1564   "chips": ["gfx103"],
1565   "map": {"at": 45200, "to": "mm"},
1566   "name": "SPI_SHADER_USER_DATA_PS_24"
1567  },
1568  {
1569   "chips": ["gfx103"],
1570   "map": {"at": 45204, "to": "mm"},
1571   "name": "SPI_SHADER_USER_DATA_PS_25"
1572  },
1573  {
1574   "chips": ["gfx103"],
1575   "map": {"at": 45208, "to": "mm"},
1576   "name": "SPI_SHADER_USER_DATA_PS_26"
1577  },
1578  {
1579   "chips": ["gfx103"],
1580   "map": {"at": 45212, "to": "mm"},
1581   "name": "SPI_SHADER_USER_DATA_PS_27"
1582  },
1583  {
1584   "chips": ["gfx103"],
1585   "map": {"at": 45216, "to": "mm"},
1586   "name": "SPI_SHADER_USER_DATA_PS_28"
1587  },
1588  {
1589   "chips": ["gfx103"],
1590   "map": {"at": 45220, "to": "mm"},
1591   "name": "SPI_SHADER_USER_DATA_PS_29"
1592  },
1593  {
1594   "chips": ["gfx103"],
1595   "map": {"at": 45224, "to": "mm"},
1596   "name": "SPI_SHADER_USER_DATA_PS_30"
1597  },
1598  {
1599   "chips": ["gfx103"],
1600   "map": {"at": 45228, "to": "mm"},
1601   "name": "SPI_SHADER_USER_DATA_PS_31"
1602  },
1603  {
1604   "chips": ["gfx103"],
1605   "map": {"at": 45248, "to": "mm"},
1606   "name": "SPI_SHADER_REQ_CTRL_PS",
1607   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1608  },
1609  {
1610   "chips": ["gfx103"],
1611   "map": {"at": 45256, "to": "mm"},
1612   "name": "SPI_SHADER_USER_ACCUM_PS_0",
1613   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1614  },
1615  {
1616   "chips": ["gfx103"],
1617   "map": {"at": 45260, "to": "mm"},
1618   "name": "SPI_SHADER_USER_ACCUM_PS_1",
1619   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1620  },
1621  {
1622   "chips": ["gfx103"],
1623   "map": {"at": 45264, "to": "mm"},
1624   "name": "SPI_SHADER_USER_ACCUM_PS_2",
1625   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1626  },
1627  {
1628   "chips": ["gfx103"],
1629   "map": {"at": 45268, "to": "mm"},
1630   "name": "SPI_SHADER_USER_ACCUM_PS_3",
1631   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1632  },
1633  {
1634   "chips": ["gfx103"],
1635   "map": {"at": 45316, "to": "mm"},
1636   "name": "SPI_SHADER_PGM_RSRC4_VS",
1637   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1638  },
1639  {
1640   "chips": ["gfx103"],
1641   "map": {"at": 45332, "to": "mm"},
1642   "name": "SPI_SHADER_PGM_CHKSUM_VS"
1643  },
1644  {
1645   "chips": ["gfx103"],
1646   "map": {"at": 45336, "to": "mm"},
1647   "name": "SPI_SHADER_PGM_RSRC3_VS",
1648   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1649  },
1650  {
1651   "chips": ["gfx103"],
1652   "map": {"at": 45340, "to": "mm"},
1653   "name": "SPI_SHADER_LATE_ALLOC_VS",
1654   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
1655  },
1656  {
1657   "chips": ["gfx103"],
1658   "map": {"at": 45344, "to": "mm"},
1659   "name": "SPI_SHADER_PGM_LO_VS"
1660  },
1661  {
1662   "chips": ["gfx103"],
1663   "map": {"at": 45348, "to": "mm"},
1664   "name": "SPI_SHADER_PGM_HI_VS",
1665   "type_ref": "SPI_SHADER_PGM_HI_PS"
1666  },
1667  {
1668   "chips": ["gfx103"],
1669   "map": {"at": 45352, "to": "mm"},
1670   "name": "SPI_SHADER_PGM_RSRC1_VS",
1671   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
1672  },
1673  {
1674   "chips": ["gfx103"],
1675   "map": {"at": 45356, "to": "mm"},
1676   "name": "SPI_SHADER_PGM_RSRC2_VS",
1677   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
1678  },
1679  {
1680   "chips": ["gfx103"],
1681   "map": {"at": 45360, "to": "mm"},
1682   "name": "SPI_SHADER_USER_DATA_VS_0"
1683  },
1684  {
1685   "chips": ["gfx103"],
1686   "map": {"at": 45364, "to": "mm"},
1687   "name": "SPI_SHADER_USER_DATA_VS_1"
1688  },
1689  {
1690   "chips": ["gfx103"],
1691   "map": {"at": 45368, "to": "mm"},
1692   "name": "SPI_SHADER_USER_DATA_VS_2"
1693  },
1694  {
1695   "chips": ["gfx103"],
1696   "map": {"at": 45372, "to": "mm"},
1697   "name": "SPI_SHADER_USER_DATA_VS_3"
1698  },
1699  {
1700   "chips": ["gfx103"],
1701   "map": {"at": 45376, "to": "mm"},
1702   "name": "SPI_SHADER_USER_DATA_VS_4"
1703  },
1704  {
1705   "chips": ["gfx103"],
1706   "map": {"at": 45380, "to": "mm"},
1707   "name": "SPI_SHADER_USER_DATA_VS_5"
1708  },
1709  {
1710   "chips": ["gfx103"],
1711   "map": {"at": 45384, "to": "mm"},
1712   "name": "SPI_SHADER_USER_DATA_VS_6"
1713  },
1714  {
1715   "chips": ["gfx103"],
1716   "map": {"at": 45388, "to": "mm"},
1717   "name": "SPI_SHADER_USER_DATA_VS_7"
1718  },
1719  {
1720   "chips": ["gfx103"],
1721   "map": {"at": 45392, "to": "mm"},
1722   "name": "SPI_SHADER_USER_DATA_VS_8"
1723  },
1724  {
1725   "chips": ["gfx103"],
1726   "map": {"at": 45396, "to": "mm"},
1727   "name": "SPI_SHADER_USER_DATA_VS_9"
1728  },
1729  {
1730   "chips": ["gfx103"],
1731   "map": {"at": 45400, "to": "mm"},
1732   "name": "SPI_SHADER_USER_DATA_VS_10"
1733  },
1734  {
1735   "chips": ["gfx103"],
1736   "map": {"at": 45404, "to": "mm"},
1737   "name": "SPI_SHADER_USER_DATA_VS_11"
1738  },
1739  {
1740   "chips": ["gfx103"],
1741   "map": {"at": 45408, "to": "mm"},
1742   "name": "SPI_SHADER_USER_DATA_VS_12"
1743  },
1744  {
1745   "chips": ["gfx103"],
1746   "map": {"at": 45412, "to": "mm"},
1747   "name": "SPI_SHADER_USER_DATA_VS_13"
1748  },
1749  {
1750   "chips": ["gfx103"],
1751   "map": {"at": 45416, "to": "mm"},
1752   "name": "SPI_SHADER_USER_DATA_VS_14"
1753  },
1754  {
1755   "chips": ["gfx103"],
1756   "map": {"at": 45420, "to": "mm"},
1757   "name": "SPI_SHADER_USER_DATA_VS_15"
1758  },
1759  {
1760   "chips": ["gfx103"],
1761   "map": {"at": 45424, "to": "mm"},
1762   "name": "SPI_SHADER_USER_DATA_VS_16"
1763  },
1764  {
1765   "chips": ["gfx103"],
1766   "map": {"at": 45428, "to": "mm"},
1767   "name": "SPI_SHADER_USER_DATA_VS_17"
1768  },
1769  {
1770   "chips": ["gfx103"],
1771   "map": {"at": 45432, "to": "mm"},
1772   "name": "SPI_SHADER_USER_DATA_VS_18"
1773  },
1774  {
1775   "chips": ["gfx103"],
1776   "map": {"at": 45436, "to": "mm"},
1777   "name": "SPI_SHADER_USER_DATA_VS_19"
1778  },
1779  {
1780   "chips": ["gfx103"],
1781   "map": {"at": 45440, "to": "mm"},
1782   "name": "SPI_SHADER_USER_DATA_VS_20"
1783  },
1784  {
1785   "chips": ["gfx103"],
1786   "map": {"at": 45444, "to": "mm"},
1787   "name": "SPI_SHADER_USER_DATA_VS_21"
1788  },
1789  {
1790   "chips": ["gfx103"],
1791   "map": {"at": 45448, "to": "mm"},
1792   "name": "SPI_SHADER_USER_DATA_VS_22"
1793  },
1794  {
1795   "chips": ["gfx103"],
1796   "map": {"at": 45452, "to": "mm"},
1797   "name": "SPI_SHADER_USER_DATA_VS_23"
1798  },
1799  {
1800   "chips": ["gfx103"],
1801   "map": {"at": 45456, "to": "mm"},
1802   "name": "SPI_SHADER_USER_DATA_VS_24"
1803  },
1804  {
1805   "chips": ["gfx103"],
1806   "map": {"at": 45460, "to": "mm"},
1807   "name": "SPI_SHADER_USER_DATA_VS_25"
1808  },
1809  {
1810   "chips": ["gfx103"],
1811   "map": {"at": 45464, "to": "mm"},
1812   "name": "SPI_SHADER_USER_DATA_VS_26"
1813  },
1814  {
1815   "chips": ["gfx103"],
1816   "map": {"at": 45468, "to": "mm"},
1817   "name": "SPI_SHADER_USER_DATA_VS_27"
1818  },
1819  {
1820   "chips": ["gfx103"],
1821   "map": {"at": 45472, "to": "mm"},
1822   "name": "SPI_SHADER_USER_DATA_VS_28"
1823  },
1824  {
1825   "chips": ["gfx103"],
1826   "map": {"at": 45476, "to": "mm"},
1827   "name": "SPI_SHADER_USER_DATA_VS_29"
1828  },
1829  {
1830   "chips": ["gfx103"],
1831   "map": {"at": 45480, "to": "mm"},
1832   "name": "SPI_SHADER_USER_DATA_VS_30"
1833  },
1834  {
1835   "chips": ["gfx103"],
1836   "map": {"at": 45484, "to": "mm"},
1837   "name": "SPI_SHADER_USER_DATA_VS_31"
1838  },
1839  {
1840   "chips": ["gfx103"],
1841   "map": {"at": 45504, "to": "mm"},
1842   "name": "SPI_SHADER_REQ_CTRL_VS",
1843   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1844  },
1845  {
1846   "chips": ["gfx103"],
1847   "map": {"at": 45512, "to": "mm"},
1848   "name": "SPI_SHADER_USER_ACCUM_VS_0",
1849   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1850  },
1851  {
1852   "chips": ["gfx103"],
1853   "map": {"at": 45516, "to": "mm"},
1854   "name": "SPI_SHADER_USER_ACCUM_VS_1",
1855   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1856  },
1857  {
1858   "chips": ["gfx103"],
1859   "map": {"at": 45520, "to": "mm"},
1860   "name": "SPI_SHADER_USER_ACCUM_VS_2",
1861   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1862  },
1863  {
1864   "chips": ["gfx103"],
1865   "map": {"at": 45524, "to": "mm"},
1866   "name": "SPI_SHADER_USER_ACCUM_VS_3",
1867   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1868  },
1869  {
1870   "chips": ["gfx103"],
1871   "map": {"at": 45548, "to": "mm"},
1872   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
1873   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
1874  },
1875  {
1876   "chips": ["gfx103"],
1877   "map": {"at": 45568, "to": "mm"},
1878   "name": "SPI_SHADER_PGM_CHKSUM_GS"
1879  },
1880  {
1881   "chips": ["gfx103"],
1882   "map": {"at": 45572, "to": "mm"},
1883   "name": "SPI_SHADER_PGM_RSRC4_GS",
1884   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
1885  },
1886  {
1887   "chips": ["gfx103"],
1888   "map": {"at": 45576, "to": "mm"},
1889   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
1890  },
1891  {
1892   "chips": ["gfx103"],
1893   "map": {"at": 45580, "to": "mm"},
1894   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
1895  },
1896  {
1897   "chips": ["gfx103"],
1898   "map": {"at": 45584, "to": "mm"},
1899   "name": "SPI_SHADER_PGM_LO_ES_GS"
1900  },
1901  {
1902   "chips": ["gfx103"],
1903   "map": {"at": 45588, "to": "mm"},
1904   "name": "SPI_SHADER_PGM_HI_ES_GS",
1905   "type_ref": "SPI_SHADER_PGM_HI_PS"
1906  },
1907  {
1908   "chips": ["gfx103"],
1909   "map": {"at": 45596, "to": "mm"},
1910   "name": "SPI_SHADER_PGM_RSRC3_GS",
1911   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
1912  },
1913  {
1914   "chips": ["gfx103"],
1915   "map": {"at": 45600, "to": "mm"},
1916   "name": "SPI_SHADER_PGM_LO_GS"
1917  },
1918  {
1919   "chips": ["gfx103"],
1920   "map": {"at": 45604, "to": "mm"},
1921   "name": "SPI_SHADER_PGM_HI_GS",
1922   "type_ref": "SPI_SHADER_PGM_HI_PS"
1923  },
1924  {
1925   "chips": ["gfx103"],
1926   "map": {"at": 45608, "to": "mm"},
1927   "name": "SPI_SHADER_PGM_RSRC1_GS",
1928   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
1929  },
1930  {
1931   "chips": ["gfx103"],
1932   "map": {"at": 45612, "to": "mm"},
1933   "name": "SPI_SHADER_PGM_RSRC2_GS",
1934   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
1935  },
1936  {
1937   "chips": ["gfx103"],
1938   "map": {"at": 45616, "to": "mm"},
1939   "name": "SPI_SHADER_USER_DATA_GS_0"
1940  },
1941  {
1942   "chips": ["gfx103"],
1943   "map": {"at": 45620, "to": "mm"},
1944   "name": "SPI_SHADER_USER_DATA_GS_1"
1945  },
1946  {
1947   "chips": ["gfx103"],
1948   "map": {"at": 45624, "to": "mm"},
1949   "name": "SPI_SHADER_USER_DATA_GS_2"
1950  },
1951  {
1952   "chips": ["gfx103"],
1953   "map": {"at": 45628, "to": "mm"},
1954   "name": "SPI_SHADER_USER_DATA_GS_3"
1955  },
1956  {
1957   "chips": ["gfx103"],
1958   "map": {"at": 45632, "to": "mm"},
1959   "name": "SPI_SHADER_USER_DATA_GS_4"
1960  },
1961  {
1962   "chips": ["gfx103"],
1963   "map": {"at": 45636, "to": "mm"},
1964   "name": "SPI_SHADER_USER_DATA_GS_5"
1965  },
1966  {
1967   "chips": ["gfx103"],
1968   "map": {"at": 45640, "to": "mm"},
1969   "name": "SPI_SHADER_USER_DATA_GS_6"
1970  },
1971  {
1972   "chips": ["gfx103"],
1973   "map": {"at": 45644, "to": "mm"},
1974   "name": "SPI_SHADER_USER_DATA_GS_7"
1975  },
1976  {
1977   "chips": ["gfx103"],
1978   "map": {"at": 45648, "to": "mm"},
1979   "name": "SPI_SHADER_USER_DATA_GS_8"
1980  },
1981  {
1982   "chips": ["gfx103"],
1983   "map": {"at": 45652, "to": "mm"},
1984   "name": "SPI_SHADER_USER_DATA_GS_9"
1985  },
1986  {
1987   "chips": ["gfx103"],
1988   "map": {"at": 45656, "to": "mm"},
1989   "name": "SPI_SHADER_USER_DATA_GS_10"
1990  },
1991  {
1992   "chips": ["gfx103"],
1993   "map": {"at": 45660, "to": "mm"},
1994   "name": "SPI_SHADER_USER_DATA_GS_11"
1995  },
1996  {
1997   "chips": ["gfx103"],
1998   "map": {"at": 45664, "to": "mm"},
1999   "name": "SPI_SHADER_USER_DATA_GS_12"
2000  },
2001  {
2002   "chips": ["gfx103"],
2003   "map": {"at": 45668, "to": "mm"},
2004   "name": "SPI_SHADER_USER_DATA_GS_13"
2005  },
2006  {
2007   "chips": ["gfx103"],
2008   "map": {"at": 45672, "to": "mm"},
2009   "name": "SPI_SHADER_USER_DATA_GS_14"
2010  },
2011  {
2012   "chips": ["gfx103"],
2013   "map": {"at": 45676, "to": "mm"},
2014   "name": "SPI_SHADER_USER_DATA_GS_15"
2015  },
2016  {
2017   "chips": ["gfx103"],
2018   "map": {"at": 45680, "to": "mm"},
2019   "name": "SPI_SHADER_USER_DATA_GS_16"
2020  },
2021  {
2022   "chips": ["gfx103"],
2023   "map": {"at": 45684, "to": "mm"},
2024   "name": "SPI_SHADER_USER_DATA_GS_17"
2025  },
2026  {
2027   "chips": ["gfx103"],
2028   "map": {"at": 45688, "to": "mm"},
2029   "name": "SPI_SHADER_USER_DATA_GS_18"
2030  },
2031  {
2032   "chips": ["gfx103"],
2033   "map": {"at": 45692, "to": "mm"},
2034   "name": "SPI_SHADER_USER_DATA_GS_19"
2035  },
2036  {
2037   "chips": ["gfx103"],
2038   "map": {"at": 45696, "to": "mm"},
2039   "name": "SPI_SHADER_USER_DATA_GS_20"
2040  },
2041  {
2042   "chips": ["gfx103"],
2043   "map": {"at": 45700, "to": "mm"},
2044   "name": "SPI_SHADER_USER_DATA_GS_21"
2045  },
2046  {
2047   "chips": ["gfx103"],
2048   "map": {"at": 45704, "to": "mm"},
2049   "name": "SPI_SHADER_USER_DATA_GS_22"
2050  },
2051  {
2052   "chips": ["gfx103"],
2053   "map": {"at": 45708, "to": "mm"},
2054   "name": "SPI_SHADER_USER_DATA_GS_23"
2055  },
2056  {
2057   "chips": ["gfx103"],
2058   "map": {"at": 45712, "to": "mm"},
2059   "name": "SPI_SHADER_USER_DATA_GS_24"
2060  },
2061  {
2062   "chips": ["gfx103"],
2063   "map": {"at": 45716, "to": "mm"},
2064   "name": "SPI_SHADER_USER_DATA_GS_25"
2065  },
2066  {
2067   "chips": ["gfx103"],
2068   "map": {"at": 45720, "to": "mm"},
2069   "name": "SPI_SHADER_USER_DATA_GS_26"
2070  },
2071  {
2072   "chips": ["gfx103"],
2073   "map": {"at": 45724, "to": "mm"},
2074   "name": "SPI_SHADER_USER_DATA_GS_27"
2075  },
2076  {
2077   "chips": ["gfx103"],
2078   "map": {"at": 45728, "to": "mm"},
2079   "name": "SPI_SHADER_USER_DATA_GS_28"
2080  },
2081  {
2082   "chips": ["gfx103"],
2083   "map": {"at": 45732, "to": "mm"},
2084   "name": "SPI_SHADER_USER_DATA_GS_29"
2085  },
2086  {
2087   "chips": ["gfx103"],
2088   "map": {"at": 45736, "to": "mm"},
2089   "name": "SPI_SHADER_USER_DATA_GS_30"
2090  },
2091  {
2092   "chips": ["gfx103"],
2093   "map": {"at": 45740, "to": "mm"},
2094   "name": "SPI_SHADER_USER_DATA_GS_31"
2095  },
2096  {
2097   "chips": ["gfx103"],
2098   "map": {"at": 45760, "to": "mm"},
2099   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2100   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2101  },
2102  {
2103   "chips": ["gfx103"],
2104   "map": {"at": 45768, "to": "mm"},
2105   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2106   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2107  },
2108  {
2109   "chips": ["gfx103"],
2110   "map": {"at": 45772, "to": "mm"},
2111   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2112   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2113  },
2114  {
2115   "chips": ["gfx103"],
2116   "map": {"at": 45776, "to": "mm"},
2117   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2118   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2119  },
2120  {
2121   "chips": ["gfx103"],
2122   "map": {"at": 45780, "to": "mm"},
2123   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2124   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2125  },
2126  {
2127   "chips": ["gfx103"],
2128   "map": {"at": 45856, "to": "mm"},
2129   "name": "SPI_SHADER_PGM_LO_ES"
2130  },
2131  {
2132   "chips": ["gfx103"],
2133   "map": {"at": 45860, "to": "mm"},
2134   "name": "SPI_SHADER_PGM_HI_ES",
2135   "type_ref": "SPI_SHADER_PGM_HI_PS"
2136  },
2137  {
2138   "chips": ["gfx103"],
2139   "map": {"at": 46080, "to": "mm"},
2140   "name": "SPI_SHADER_PGM_CHKSUM_HS"
2141  },
2142  {
2143   "chips": ["gfx103"],
2144   "map": {"at": 46084, "to": "mm"},
2145   "name": "SPI_SHADER_PGM_RSRC4_HS",
2146   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2147  },
2148  {
2149   "chips": ["gfx103"],
2150   "map": {"at": 46088, "to": "mm"},
2151   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2152  },
2153  {
2154   "chips": ["gfx103"],
2155   "map": {"at": 46092, "to": "mm"},
2156   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2157  },
2158  {
2159   "chips": ["gfx103"],
2160   "map": {"at": 46096, "to": "mm"},
2161   "name": "SPI_SHADER_PGM_LO_LS_HS"
2162  },
2163  {
2164   "chips": ["gfx103"],
2165   "map": {"at": 46100, "to": "mm"},
2166   "name": "SPI_SHADER_PGM_HI_LS_HS",
2167   "type_ref": "SPI_SHADER_PGM_HI_PS"
2168  },
2169  {
2170   "chips": ["gfx103"],
2171   "map": {"at": 46108, "to": "mm"},
2172   "name": "SPI_SHADER_PGM_RSRC3_HS",
2173   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2174  },
2175  {
2176   "chips": ["gfx103"],
2177   "map": {"at": 46112, "to": "mm"},
2178   "name": "SPI_SHADER_PGM_LO_HS"
2179  },
2180  {
2181   "chips": ["gfx103"],
2182   "map": {"at": 46116, "to": "mm"},
2183   "name": "SPI_SHADER_PGM_HI_HS",
2184   "type_ref": "SPI_SHADER_PGM_HI_PS"
2185  },
2186  {
2187   "chips": ["gfx103"],
2188   "map": {"at": 46120, "to": "mm"},
2189   "name": "SPI_SHADER_PGM_RSRC1_HS",
2190   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2191  },
2192  {
2193   "chips": ["gfx103"],
2194   "map": {"at": 46124, "to": "mm"},
2195   "name": "SPI_SHADER_PGM_RSRC2_HS",
2196   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2197  },
2198  {
2199   "chips": ["gfx103"],
2200   "map": {"at": 46128, "to": "mm"},
2201   "name": "SPI_SHADER_USER_DATA_HS_0"
2202  },
2203  {
2204   "chips": ["gfx103"],
2205   "map": {"at": 46132, "to": "mm"},
2206   "name": "SPI_SHADER_USER_DATA_HS_1"
2207  },
2208  {
2209   "chips": ["gfx103"],
2210   "map": {"at": 46136, "to": "mm"},
2211   "name": "SPI_SHADER_USER_DATA_HS_2"
2212  },
2213  {
2214   "chips": ["gfx103"],
2215   "map": {"at": 46140, "to": "mm"},
2216   "name": "SPI_SHADER_USER_DATA_HS_3"
2217  },
2218  {
2219   "chips": ["gfx103"],
2220   "map": {"at": 46144, "to": "mm"},
2221   "name": "SPI_SHADER_USER_DATA_HS_4"
2222  },
2223  {
2224   "chips": ["gfx103"],
2225   "map": {"at": 46148, "to": "mm"},
2226   "name": "SPI_SHADER_USER_DATA_HS_5"
2227  },
2228  {
2229   "chips": ["gfx103"],
2230   "map": {"at": 46152, "to": "mm"},
2231   "name": "SPI_SHADER_USER_DATA_HS_6"
2232  },
2233  {
2234   "chips": ["gfx103"],
2235   "map": {"at": 46156, "to": "mm"},
2236   "name": "SPI_SHADER_USER_DATA_HS_7"
2237  },
2238  {
2239   "chips": ["gfx103"],
2240   "map": {"at": 46160, "to": "mm"},
2241   "name": "SPI_SHADER_USER_DATA_HS_8"
2242  },
2243  {
2244   "chips": ["gfx103"],
2245   "map": {"at": 46164, "to": "mm"},
2246   "name": "SPI_SHADER_USER_DATA_HS_9"
2247  },
2248  {
2249   "chips": ["gfx103"],
2250   "map": {"at": 46168, "to": "mm"},
2251   "name": "SPI_SHADER_USER_DATA_HS_10"
2252  },
2253  {
2254   "chips": ["gfx103"],
2255   "map": {"at": 46172, "to": "mm"},
2256   "name": "SPI_SHADER_USER_DATA_HS_11"
2257  },
2258  {
2259   "chips": ["gfx103"],
2260   "map": {"at": 46176, "to": "mm"},
2261   "name": "SPI_SHADER_USER_DATA_HS_12"
2262  },
2263  {
2264   "chips": ["gfx103"],
2265   "map": {"at": 46180, "to": "mm"},
2266   "name": "SPI_SHADER_USER_DATA_HS_13"
2267  },
2268  {
2269   "chips": ["gfx103"],
2270   "map": {"at": 46184, "to": "mm"},
2271   "name": "SPI_SHADER_USER_DATA_HS_14"
2272  },
2273  {
2274   "chips": ["gfx103"],
2275   "map": {"at": 46188, "to": "mm"},
2276   "name": "SPI_SHADER_USER_DATA_HS_15"
2277  },
2278  {
2279   "chips": ["gfx103"],
2280   "map": {"at": 46192, "to": "mm"},
2281   "name": "SPI_SHADER_USER_DATA_HS_16"
2282  },
2283  {
2284   "chips": ["gfx103"],
2285   "map": {"at": 46196, "to": "mm"},
2286   "name": "SPI_SHADER_USER_DATA_HS_17"
2287  },
2288  {
2289   "chips": ["gfx103"],
2290   "map": {"at": 46200, "to": "mm"},
2291   "name": "SPI_SHADER_USER_DATA_HS_18"
2292  },
2293  {
2294   "chips": ["gfx103"],
2295   "map": {"at": 46204, "to": "mm"},
2296   "name": "SPI_SHADER_USER_DATA_HS_19"
2297  },
2298  {
2299   "chips": ["gfx103"],
2300   "map": {"at": 46208, "to": "mm"},
2301   "name": "SPI_SHADER_USER_DATA_HS_20"
2302  },
2303  {
2304   "chips": ["gfx103"],
2305   "map": {"at": 46212, "to": "mm"},
2306   "name": "SPI_SHADER_USER_DATA_HS_21"
2307  },
2308  {
2309   "chips": ["gfx103"],
2310   "map": {"at": 46216, "to": "mm"},
2311   "name": "SPI_SHADER_USER_DATA_HS_22"
2312  },
2313  {
2314   "chips": ["gfx103"],
2315   "map": {"at": 46220, "to": "mm"},
2316   "name": "SPI_SHADER_USER_DATA_HS_23"
2317  },
2318  {
2319   "chips": ["gfx103"],
2320   "map": {"at": 46224, "to": "mm"},
2321   "name": "SPI_SHADER_USER_DATA_HS_24"
2322  },
2323  {
2324   "chips": ["gfx103"],
2325   "map": {"at": 46228, "to": "mm"},
2326   "name": "SPI_SHADER_USER_DATA_HS_25"
2327  },
2328  {
2329   "chips": ["gfx103"],
2330   "map": {"at": 46232, "to": "mm"},
2331   "name": "SPI_SHADER_USER_DATA_HS_26"
2332  },
2333  {
2334   "chips": ["gfx103"],
2335   "map": {"at": 46236, "to": "mm"},
2336   "name": "SPI_SHADER_USER_DATA_HS_27"
2337  },
2338  {
2339   "chips": ["gfx103"],
2340   "map": {"at": 46240, "to": "mm"},
2341   "name": "SPI_SHADER_USER_DATA_HS_28"
2342  },
2343  {
2344   "chips": ["gfx103"],
2345   "map": {"at": 46244, "to": "mm"},
2346   "name": "SPI_SHADER_USER_DATA_HS_29"
2347  },
2348  {
2349   "chips": ["gfx103"],
2350   "map": {"at": 46248, "to": "mm"},
2351   "name": "SPI_SHADER_USER_DATA_HS_30"
2352  },
2353  {
2354   "chips": ["gfx103"],
2355   "map": {"at": 46252, "to": "mm"},
2356   "name": "SPI_SHADER_USER_DATA_HS_31"
2357  },
2358  {
2359   "chips": ["gfx103"],
2360   "map": {"at": 46272, "to": "mm"},
2361   "name": "SPI_SHADER_REQ_CTRL_LSHS",
2362   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2363  },
2364  {
2365   "chips": ["gfx103"],
2366   "map": {"at": 46280, "to": "mm"},
2367   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2368   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2369  },
2370  {
2371   "chips": ["gfx103"],
2372   "map": {"at": 46284, "to": "mm"},
2373   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2374   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2375  },
2376  {
2377   "chips": ["gfx103"],
2378   "map": {"at": 46288, "to": "mm"},
2379   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2380   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2381  },
2382  {
2383   "chips": ["gfx103"],
2384   "map": {"at": 46292, "to": "mm"},
2385   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2386   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2387  },
2388  {
2389   "chips": ["gfx103"],
2390   "map": {"at": 46368, "to": "mm"},
2391   "name": "SPI_SHADER_PGM_LO_LS"
2392  },
2393  {
2394   "chips": ["gfx103"],
2395   "map": {"at": 46372, "to": "mm"},
2396   "name": "SPI_SHADER_PGM_HI_LS",
2397   "type_ref": "SPI_SHADER_PGM_HI_PS"
2398  },
2399  {
2400   "chips": ["gfx103"],
2401   "map": {"at": 47104, "to": "mm"},
2402   "name": "COMPUTE_DISPATCH_INITIATOR",
2403   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2404  },
2405  {
2406   "chips": ["gfx103"],
2407   "map": {"at": 47108, "to": "mm"},
2408   "name": "COMPUTE_DIM_X"
2409  },
2410  {
2411   "chips": ["gfx103"],
2412   "map": {"at": 47112, "to": "mm"},
2413   "name": "COMPUTE_DIM_Y"
2414  },
2415  {
2416   "chips": ["gfx103"],
2417   "map": {"at": 47116, "to": "mm"},
2418   "name": "COMPUTE_DIM_Z"
2419  },
2420  {
2421   "chips": ["gfx103"],
2422   "map": {"at": 47120, "to": "mm"},
2423   "name": "COMPUTE_START_X"
2424  },
2425  {
2426   "chips": ["gfx103"],
2427   "map": {"at": 47124, "to": "mm"},
2428   "name": "COMPUTE_START_Y"
2429  },
2430  {
2431   "chips": ["gfx103"],
2432   "map": {"at": 47128, "to": "mm"},
2433   "name": "COMPUTE_START_Z"
2434  },
2435  {
2436   "chips": ["gfx103"],
2437   "map": {"at": 47132, "to": "mm"},
2438   "name": "COMPUTE_NUM_THREAD_X",
2439   "type_ref": "COMPUTE_NUM_THREAD_X"
2440  },
2441  {
2442   "chips": ["gfx103"],
2443   "map": {"at": 47136, "to": "mm"},
2444   "name": "COMPUTE_NUM_THREAD_Y",
2445   "type_ref": "COMPUTE_NUM_THREAD_X"
2446  },
2447  {
2448   "chips": ["gfx103"],
2449   "map": {"at": 47140, "to": "mm"},
2450   "name": "COMPUTE_NUM_THREAD_Z",
2451   "type_ref": "COMPUTE_NUM_THREAD_X"
2452  },
2453  {
2454   "chips": ["gfx103"],
2455   "map": {"at": 47144, "to": "mm"},
2456   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2457   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2458  },
2459  {
2460   "chips": ["gfx103"],
2461   "map": {"at": 47148, "to": "mm"},
2462   "name": "COMPUTE_PERFCOUNT_ENABLE",
2463   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2464  },
2465  {
2466   "chips": ["gfx103"],
2467   "map": {"at": 47152, "to": "mm"},
2468   "name": "COMPUTE_PGM_LO"
2469  },
2470  {
2471   "chips": ["gfx103"],
2472   "map": {"at": 47156, "to": "mm"},
2473   "name": "COMPUTE_PGM_HI",
2474   "type_ref": "COMPUTE_PGM_HI"
2475  },
2476  {
2477   "chips": ["gfx103"],
2478   "map": {"at": 47160, "to": "mm"},
2479   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
2480  },
2481  {
2482   "chips": ["gfx103"],
2483   "map": {"at": 47164, "to": "mm"},
2484   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
2485   "type_ref": "COMPUTE_PGM_HI"
2486  },
2487  {
2488   "chips": ["gfx103"],
2489   "map": {"at": 47168, "to": "mm"},
2490   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
2491  },
2492  {
2493   "chips": ["gfx103"],
2494   "map": {"at": 47172, "to": "mm"},
2495   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
2496   "type_ref": "COMPUTE_PGM_HI"
2497  },
2498  {
2499   "chips": ["gfx103"],
2500   "map": {"at": 47176, "to": "mm"},
2501   "name": "COMPUTE_PGM_RSRC1",
2502   "type_ref": "COMPUTE_PGM_RSRC1"
2503  },
2504  {
2505   "chips": ["gfx103"],
2506   "map": {"at": 47180, "to": "mm"},
2507   "name": "COMPUTE_PGM_RSRC2",
2508   "type_ref": "COMPUTE_PGM_RSRC2"
2509  },
2510  {
2511   "chips": ["gfx103"],
2512   "map": {"at": 47184, "to": "mm"},
2513   "name": "COMPUTE_VMID",
2514   "type_ref": "COMPUTE_VMID"
2515  },
2516  {
2517   "chips": ["gfx103"],
2518   "map": {"at": 47188, "to": "mm"},
2519   "name": "COMPUTE_RESOURCE_LIMITS",
2520   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2521  },
2522  {
2523   "chips": ["gfx103"],
2524   "map": {"at": 47192, "to": "mm"},
2525   "name": "COMPUTE_DESTINATION_EN_SE0"
2526  },
2527  {
2528   "chips": ["gfx103"],
2529   "map": {"at": 47196, "to": "mm"},
2530   "name": "COMPUTE_DESTINATION_EN_SE1"
2531  },
2532  {
2533   "chips": ["gfx103"],
2534   "map": {"at": 47200, "to": "mm"},
2535   "name": "COMPUTE_TMPRING_SIZE",
2536   "type_ref": "COMPUTE_TMPRING_SIZE"
2537  },
2538  {
2539   "chips": ["gfx103"],
2540   "map": {"at": 47204, "to": "mm"},
2541   "name": "COMPUTE_DESTINATION_EN_SE2"
2542  },
2543  {
2544   "chips": ["gfx103"],
2545   "map": {"at": 47208, "to": "mm"},
2546   "name": "COMPUTE_DESTINATION_EN_SE3"
2547  },
2548  {
2549   "chips": ["gfx103"],
2550   "map": {"at": 47212, "to": "mm"},
2551   "name": "COMPUTE_RESTART_X"
2552  },
2553  {
2554   "chips": ["gfx103"],
2555   "map": {"at": 47216, "to": "mm"},
2556   "name": "COMPUTE_RESTART_Y"
2557  },
2558  {
2559   "chips": ["gfx103"],
2560   "map": {"at": 47220, "to": "mm"},
2561   "name": "COMPUTE_RESTART_Z"
2562  },
2563  {
2564   "chips": ["gfx103"],
2565   "map": {"at": 47224, "to": "mm"},
2566   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2567   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2568  },
2569  {
2570   "chips": ["gfx103"],
2571   "map": {"at": 47228, "to": "mm"},
2572   "name": "COMPUTE_MISC_RESERVED",
2573   "type_ref": "COMPUTE_MISC_RESERVED"
2574  },
2575  {
2576   "chips": ["gfx103"],
2577   "map": {"at": 47232, "to": "mm"},
2578   "name": "COMPUTE_DISPATCH_ID"
2579  },
2580  {
2581   "chips": ["gfx103"],
2582   "map": {"at": 47236, "to": "mm"},
2583   "name": "COMPUTE_THREADGROUP_ID"
2584  },
2585  {
2586   "chips": ["gfx103"],
2587   "map": {"at": 47240, "to": "mm"},
2588   "name": "COMPUTE_REQ_CTRL",
2589   "type_ref": "COMPUTE_REQ_CTRL"
2590  },
2591  {
2592   "chips": ["gfx103"],
2593   "map": {"at": 47248, "to": "mm"},
2594   "name": "COMPUTE_USER_ACCUM_0",
2595   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2596  },
2597  {
2598   "chips": ["gfx103"],
2599   "map": {"at": 47252, "to": "mm"},
2600   "name": "COMPUTE_USER_ACCUM_1",
2601   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2602  },
2603  {
2604   "chips": ["gfx103"],
2605   "map": {"at": 47256, "to": "mm"},
2606   "name": "COMPUTE_USER_ACCUM_2",
2607   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2608  },
2609  {
2610   "chips": ["gfx103"],
2611   "map": {"at": 47260, "to": "mm"},
2612   "name": "COMPUTE_USER_ACCUM_3",
2613   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2614  },
2615  {
2616   "chips": ["gfx103"],
2617   "map": {"at": 47264, "to": "mm"},
2618   "name": "COMPUTE_PGM_RSRC3",
2619   "type_ref": "COMPUTE_PGM_RSRC3"
2620  },
2621  {
2622   "chips": ["gfx103"],
2623   "map": {"at": 47268, "to": "mm"},
2624   "name": "COMPUTE_DDID_INDEX",
2625   "type_ref": "COMPUTE_DDID_INDEX"
2626  },
2627  {
2628   "chips": ["gfx103"],
2629   "map": {"at": 47272, "to": "mm"},
2630   "name": "COMPUTE_SHADER_CHKSUM"
2631  },
2632  {
2633   "chips": ["gfx103"],
2634   "map": {"at": 47276, "to": "mm"},
2635   "name": "COMPUTE_RELAUNCH",
2636   "type_ref": "COMPUTE_RELAUNCH"
2637  },
2638  {
2639   "chips": ["gfx103"],
2640   "map": {"at": 47280, "to": "mm"},
2641   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2642  },
2643  {
2644   "chips": ["gfx103"],
2645   "map": {"at": 47284, "to": "mm"},
2646   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2647   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2648  },
2649  {
2650   "chips": ["gfx103"],
2651   "map": {"at": 47288, "to": "mm"},
2652   "name": "COMPUTE_RELAUNCH2",
2653   "type_ref": "COMPUTE_RELAUNCH"
2654  },
2655  {
2656   "chips": ["gfx103"],
2657   "map": {"at": 47360, "to": "mm"},
2658   "name": "COMPUTE_USER_DATA_0"
2659  },
2660  {
2661   "chips": ["gfx103"],
2662   "map": {"at": 47364, "to": "mm"},
2663   "name": "COMPUTE_USER_DATA_1"
2664  },
2665  {
2666   "chips": ["gfx103"],
2667   "map": {"at": 47368, "to": "mm"},
2668   "name": "COMPUTE_USER_DATA_2"
2669  },
2670  {
2671   "chips": ["gfx103"],
2672   "map": {"at": 47372, "to": "mm"},
2673   "name": "COMPUTE_USER_DATA_3"
2674  },
2675  {
2676   "chips": ["gfx103"],
2677   "map": {"at": 47376, "to": "mm"},
2678   "name": "COMPUTE_USER_DATA_4"
2679  },
2680  {
2681   "chips": ["gfx103"],
2682   "map": {"at": 47380, "to": "mm"},
2683   "name": "COMPUTE_USER_DATA_5"
2684  },
2685  {
2686   "chips": ["gfx103"],
2687   "map": {"at": 47384, "to": "mm"},
2688   "name": "COMPUTE_USER_DATA_6"
2689  },
2690  {
2691   "chips": ["gfx103"],
2692   "map": {"at": 47388, "to": "mm"},
2693   "name": "COMPUTE_USER_DATA_7"
2694  },
2695  {
2696   "chips": ["gfx103"],
2697   "map": {"at": 47392, "to": "mm"},
2698   "name": "COMPUTE_USER_DATA_8"
2699  },
2700  {
2701   "chips": ["gfx103"],
2702   "map": {"at": 47396, "to": "mm"},
2703   "name": "COMPUTE_USER_DATA_9"
2704  },
2705  {
2706   "chips": ["gfx103"],
2707   "map": {"at": 47400, "to": "mm"},
2708   "name": "COMPUTE_USER_DATA_10"
2709  },
2710  {
2711   "chips": ["gfx103"],
2712   "map": {"at": 47404, "to": "mm"},
2713   "name": "COMPUTE_USER_DATA_11"
2714  },
2715  {
2716   "chips": ["gfx103"],
2717   "map": {"at": 47408, "to": "mm"},
2718   "name": "COMPUTE_USER_DATA_12"
2719  },
2720  {
2721   "chips": ["gfx103"],
2722   "map": {"at": 47412, "to": "mm"},
2723   "name": "COMPUTE_USER_DATA_13"
2724  },
2725  {
2726   "chips": ["gfx103"],
2727   "map": {"at": 47416, "to": "mm"},
2728   "name": "COMPUTE_USER_DATA_14"
2729  },
2730  {
2731   "chips": ["gfx103"],
2732   "map": {"at": 47420, "to": "mm"},
2733   "name": "COMPUTE_USER_DATA_15"
2734  },
2735  {
2736   "chips": ["gfx103"],
2737   "map": {"at": 47604, "to": "mm"},
2738   "name": "COMPUTE_DISPATCH_TUNNEL",
2739   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
2740  },
2741  {
2742   "chips": ["gfx103"],
2743   "map": {"at": 47608, "to": "mm"},
2744   "name": "COMPUTE_DISPATCH_END"
2745  },
2746  {
2747   "chips": ["gfx103"],
2748   "map": {"at": 47612, "to": "mm"},
2749   "name": "COMPUTE_NOWHERE"
2750  },
2751  {
2752   "chips": ["gfx103"],
2753   "map": {"at": 47616, "to": "mm"},
2754   "name": "SH_RESERVED_REG0"
2755  },
2756  {
2757   "chips": ["gfx103"],
2758   "map": {"at": 47620, "to": "mm"},
2759   "name": "SH_RESERVED_REG1"
2760  },
2761  {
2762   "chips": ["gfx103"],
2763   "map": {"at": 163840, "to": "mm"},
2764   "name": "DB_RENDER_CONTROL",
2765   "type_ref": "DB_RENDER_CONTROL"
2766  },
2767  {
2768   "chips": ["gfx103"],
2769   "map": {"at": 163844, "to": "mm"},
2770   "name": "DB_COUNT_CONTROL",
2771   "type_ref": "DB_COUNT_CONTROL"
2772  },
2773  {
2774   "chips": ["gfx103"],
2775   "map": {"at": 163848, "to": "mm"},
2776   "name": "DB_DEPTH_VIEW",
2777   "type_ref": "DB_DEPTH_VIEW"
2778  },
2779  {
2780   "chips": ["gfx103"],
2781   "map": {"at": 163852, "to": "mm"},
2782   "name": "DB_RENDER_OVERRIDE",
2783   "type_ref": "DB_RENDER_OVERRIDE"
2784  },
2785  {
2786   "chips": ["gfx103"],
2787   "map": {"at": 163856, "to": "mm"},
2788   "name": "DB_RENDER_OVERRIDE2",
2789   "type_ref": "DB_RENDER_OVERRIDE2"
2790  },
2791  {
2792   "chips": ["gfx103"],
2793   "map": {"at": 163860, "to": "mm"},
2794   "name": "DB_HTILE_DATA_BASE"
2795  },
2796  {
2797   "chips": ["gfx103"],
2798   "map": {"at": 163868, "to": "mm"},
2799   "name": "DB_DEPTH_SIZE_XY",
2800   "type_ref": "DB_DEPTH_SIZE_XY"
2801  },
2802  {
2803   "chips": ["gfx103"],
2804   "map": {"at": 163872, "to": "mm"},
2805   "name": "DB_DEPTH_BOUNDS_MIN"
2806  },
2807  {
2808   "chips": ["gfx103"],
2809   "map": {"at": 163876, "to": "mm"},
2810   "name": "DB_DEPTH_BOUNDS_MAX"
2811  },
2812  {
2813   "chips": ["gfx103"],
2814   "map": {"at": 163880, "to": "mm"},
2815   "name": "DB_STENCIL_CLEAR",
2816   "type_ref": "DB_STENCIL_CLEAR"
2817  },
2818  {
2819   "chips": ["gfx103"],
2820   "map": {"at": 163884, "to": "mm"},
2821   "name": "DB_DEPTH_CLEAR"
2822  },
2823  {
2824   "chips": ["gfx103"],
2825   "map": {"at": 163888, "to": "mm"},
2826   "name": "PA_SC_SCREEN_SCISSOR_TL",
2827   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
2828  },
2829  {
2830   "chips": ["gfx103"],
2831   "map": {"at": 163892, "to": "mm"},
2832   "name": "PA_SC_SCREEN_SCISSOR_BR",
2833   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
2834  },
2835  {
2836   "chips": ["gfx103"],
2837   "map": {"at": 163896, "to": "mm"},
2838   "name": "DB_DFSM_CONTROL",
2839   "type_ref": "DB_DFSM_CONTROL"
2840  },
2841  {
2842   "chips": ["gfx103"],
2843   "map": {"at": 163900, "to": "mm"},
2844   "name": "DB_RESERVED_REG_2",
2845   "type_ref": "DB_RESERVED_REG_2"
2846  },
2847  {
2848   "chips": ["gfx103"],
2849   "map": {"at": 163904, "to": "mm"},
2850   "name": "DB_Z_INFO",
2851   "type_ref": "DB_Z_INFO"
2852  },
2853  {
2854   "chips": ["gfx103"],
2855   "map": {"at": 163908, "to": "mm"},
2856   "name": "DB_STENCIL_INFO",
2857   "type_ref": "DB_STENCIL_INFO"
2858  },
2859  {
2860   "chips": ["gfx103"],
2861   "map": {"at": 163912, "to": "mm"},
2862   "name": "DB_Z_READ_BASE"
2863  },
2864  {
2865   "chips": ["gfx103"],
2866   "map": {"at": 163916, "to": "mm"},
2867   "name": "DB_STENCIL_READ_BASE"
2868  },
2869  {
2870   "chips": ["gfx103"],
2871   "map": {"at": 163920, "to": "mm"},
2872   "name": "DB_Z_WRITE_BASE"
2873  },
2874  {
2875   "chips": ["gfx103"],
2876   "map": {"at": 163924, "to": "mm"},
2877   "name": "DB_STENCIL_WRITE_BASE"
2878  },
2879  {
2880   "chips": ["gfx103"],
2881   "map": {"at": 163928, "to": "mm"},
2882   "name": "DB_RESERVED_REG_1",
2883   "type_ref": "DB_RESERVED_REG_1"
2884  },
2885  {
2886   "chips": ["gfx103"],
2887   "map": {"at": 163932, "to": "mm"},
2888   "name": "DB_RESERVED_REG_3",
2889   "type_ref": "DB_RESERVED_REG_3"
2890  },
2891  {
2892   "chips": ["gfx103"],
2893   "map": {"at": 163940, "to": "mm"},
2894   "name": "DB_VRS_OVERRIDE_CNTL",
2895   "type_ref": "DB_VRS_OVERRIDE_CNTL"
2896  },
2897  {
2898   "chips": ["gfx103"],
2899   "map": {"at": 163944, "to": "mm"},
2900   "name": "DB_Z_READ_BASE_HI",
2901   "type_ref": "DB_Z_READ_BASE_HI"
2902  },
2903  {
2904   "chips": ["gfx103"],
2905   "map": {"at": 163948, "to": "mm"},
2906   "name": "DB_STENCIL_READ_BASE_HI",
2907   "type_ref": "DB_Z_READ_BASE_HI"
2908  },
2909  {
2910   "chips": ["gfx103"],
2911   "map": {"at": 163952, "to": "mm"},
2912   "name": "DB_Z_WRITE_BASE_HI",
2913   "type_ref": "DB_Z_READ_BASE_HI"
2914  },
2915  {
2916   "chips": ["gfx103"],
2917   "map": {"at": 163956, "to": "mm"},
2918   "name": "DB_STENCIL_WRITE_BASE_HI",
2919   "type_ref": "DB_Z_READ_BASE_HI"
2920  },
2921  {
2922   "chips": ["gfx103"],
2923   "map": {"at": 163960, "to": "mm"},
2924   "name": "DB_HTILE_DATA_BASE_HI",
2925   "type_ref": "DB_Z_READ_BASE_HI"
2926  },
2927  {
2928   "chips": ["gfx103"],
2929   "map": {"at": 163964, "to": "mm"},
2930   "name": "DB_RMI_L2_CACHE_CONTROL",
2931   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
2932  },
2933  {
2934   "chips": ["gfx103"],
2935   "map": {"at": 163968, "to": "mm"},
2936   "name": "TA_BC_BASE_ADDR"
2937  },
2938  {
2939   "chips": ["gfx103"],
2940   "map": {"at": 163972, "to": "mm"},
2941   "name": "TA_BC_BASE_ADDR_HI",
2942   "type_ref": "TA_BC_BASE_ADDR_HI"
2943  },
2944  {
2945   "chips": ["gfx103"],
2946   "map": {"at": 164328, "to": "mm"},
2947   "name": "COHER_DEST_BASE_HI_0",
2948   "type_ref": "COHER_DEST_BASE_HI_0"
2949  },
2950  {
2951   "chips": ["gfx103"],
2952   "map": {"at": 164332, "to": "mm"},
2953   "name": "COHER_DEST_BASE_HI_1",
2954   "type_ref": "COHER_DEST_BASE_HI_0"
2955  },
2956  {
2957   "chips": ["gfx103"],
2958   "map": {"at": 164336, "to": "mm"},
2959   "name": "COHER_DEST_BASE_HI_2",
2960   "type_ref": "COHER_DEST_BASE_HI_0"
2961  },
2962  {
2963   "chips": ["gfx103"],
2964   "map": {"at": 164340, "to": "mm"},
2965   "name": "COHER_DEST_BASE_HI_3",
2966   "type_ref": "COHER_DEST_BASE_HI_0"
2967  },
2968  {
2969   "chips": ["gfx103"],
2970   "map": {"at": 164344, "to": "mm"},
2971   "name": "COHER_DEST_BASE_2"
2972  },
2973  {
2974   "chips": ["gfx103"],
2975   "map": {"at": 164348, "to": "mm"},
2976   "name": "COHER_DEST_BASE_3"
2977  },
2978  {
2979   "chips": ["gfx103"],
2980   "map": {"at": 164352, "to": "mm"},
2981   "name": "PA_SC_WINDOW_OFFSET",
2982   "type_ref": "PA_SC_WINDOW_OFFSET"
2983  },
2984  {
2985   "chips": ["gfx103"],
2986   "map": {"at": 164356, "to": "mm"},
2987   "name": "PA_SC_WINDOW_SCISSOR_TL",
2988   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
2989  },
2990  {
2991   "chips": ["gfx103"],
2992   "map": {"at": 164360, "to": "mm"},
2993   "name": "PA_SC_WINDOW_SCISSOR_BR",
2994   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
2995  },
2996  {
2997   "chips": ["gfx103"],
2998   "map": {"at": 164364, "to": "mm"},
2999   "name": "PA_SC_CLIPRECT_RULE",
3000   "type_ref": "PA_SC_CLIPRECT_RULE"
3001  },
3002  {
3003   "chips": ["gfx103"],
3004   "map": {"at": 164368, "to": "mm"},
3005   "name": "PA_SC_CLIPRECT_0_TL",
3006   "type_ref": "PA_SC_CLIPRECT_0_TL"
3007  },
3008  {
3009   "chips": ["gfx103"],
3010   "map": {"at": 164372, "to": "mm"},
3011   "name": "PA_SC_CLIPRECT_0_BR",
3012   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3013  },
3014  {
3015   "chips": ["gfx103"],
3016   "map": {"at": 164376, "to": "mm"},
3017   "name": "PA_SC_CLIPRECT_1_TL",
3018   "type_ref": "PA_SC_CLIPRECT_0_TL"
3019  },
3020  {
3021   "chips": ["gfx103"],
3022   "map": {"at": 164380, "to": "mm"},
3023   "name": "PA_SC_CLIPRECT_1_BR",
3024   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3025  },
3026  {
3027   "chips": ["gfx103"],
3028   "map": {"at": 164384, "to": "mm"},
3029   "name": "PA_SC_CLIPRECT_2_TL",
3030   "type_ref": "PA_SC_CLIPRECT_0_TL"
3031  },
3032  {
3033   "chips": ["gfx103"],
3034   "map": {"at": 164388, "to": "mm"},
3035   "name": "PA_SC_CLIPRECT_2_BR",
3036   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3037  },
3038  {
3039   "chips": ["gfx103"],
3040   "map": {"at": 164392, "to": "mm"},
3041   "name": "PA_SC_CLIPRECT_3_TL",
3042   "type_ref": "PA_SC_CLIPRECT_0_TL"
3043  },
3044  {
3045   "chips": ["gfx103"],
3046   "map": {"at": 164396, "to": "mm"},
3047   "name": "PA_SC_CLIPRECT_3_BR",
3048   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3049  },
3050  {
3051   "chips": ["gfx103"],
3052   "map": {"at": 164400, "to": "mm"},
3053   "name": "PA_SC_EDGERULE",
3054   "type_ref": "PA_SC_EDGERULE"
3055  },
3056  {
3057   "chips": ["gfx103"],
3058   "map": {"at": 164404, "to": "mm"},
3059   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3060   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3061  },
3062  {
3063   "chips": ["gfx103"],
3064   "map": {"at": 164408, "to": "mm"},
3065   "name": "CB_TARGET_MASK",
3066   "type_ref": "CB_TARGET_MASK"
3067  },
3068  {
3069   "chips": ["gfx103"],
3070   "map": {"at": 164412, "to": "mm"},
3071   "name": "CB_SHADER_MASK",
3072   "type_ref": "CB_SHADER_MASK"
3073  },
3074  {
3075   "chips": ["gfx103"],
3076   "map": {"at": 164416, "to": "mm"},
3077   "name": "PA_SC_GENERIC_SCISSOR_TL",
3078   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3079  },
3080  {
3081   "chips": ["gfx103"],
3082   "map": {"at": 164420, "to": "mm"},
3083   "name": "PA_SC_GENERIC_SCISSOR_BR",
3084   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3085  },
3086  {
3087   "chips": ["gfx103"],
3088   "map": {"at": 164424, "to": "mm"},
3089   "name": "COHER_DEST_BASE_0"
3090  },
3091  {
3092   "chips": ["gfx103"],
3093   "map": {"at": 164428, "to": "mm"},
3094   "name": "COHER_DEST_BASE_1"
3095  },
3096  {
3097   "chips": ["gfx103"],
3098   "map": {"at": 164432, "to": "mm"},
3099   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3100   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3101  },
3102  {
3103   "chips": ["gfx103"],
3104   "map": {"at": 164436, "to": "mm"},
3105   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3106   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3107  },
3108  {
3109   "chips": ["gfx103"],
3110   "map": {"at": 164440, "to": "mm"},
3111   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3112   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3113  },
3114  {
3115   "chips": ["gfx103"],
3116   "map": {"at": 164444, "to": "mm"},
3117   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3118   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3119  },
3120  {
3121   "chips": ["gfx103"],
3122   "map": {"at": 164448, "to": "mm"},
3123   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3124   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3125  },
3126  {
3127   "chips": ["gfx103"],
3128   "map": {"at": 164452, "to": "mm"},
3129   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3130   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3131  },
3132  {
3133   "chips": ["gfx103"],
3134   "map": {"at": 164456, "to": "mm"},
3135   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3136   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3137  },
3138  {
3139   "chips": ["gfx103"],
3140   "map": {"at": 164460, "to": "mm"},
3141   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3142   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3143  },
3144  {
3145   "chips": ["gfx103"],
3146   "map": {"at": 164464, "to": "mm"},
3147   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3148   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3149  },
3150  {
3151   "chips": ["gfx103"],
3152   "map": {"at": 164468, "to": "mm"},
3153   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3154   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3155  },
3156  {
3157   "chips": ["gfx103"],
3158   "map": {"at": 164472, "to": "mm"},
3159   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3160   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3161  },
3162  {
3163   "chips": ["gfx103"],
3164   "map": {"at": 164476, "to": "mm"},
3165   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3166   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3167  },
3168  {
3169   "chips": ["gfx103"],
3170   "map": {"at": 164480, "to": "mm"},
3171   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3172   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3173  },
3174  {
3175   "chips": ["gfx103"],
3176   "map": {"at": 164484, "to": "mm"},
3177   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3178   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3179  },
3180  {
3181   "chips": ["gfx103"],
3182   "map": {"at": 164488, "to": "mm"},
3183   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3184   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3185  },
3186  {
3187   "chips": ["gfx103"],
3188   "map": {"at": 164492, "to": "mm"},
3189   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3190   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3191  },
3192  {
3193   "chips": ["gfx103"],
3194   "map": {"at": 164496, "to": "mm"},
3195   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3196   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3197  },
3198  {
3199   "chips": ["gfx103"],
3200   "map": {"at": 164500, "to": "mm"},
3201   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3202   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3203  },
3204  {
3205   "chips": ["gfx103"],
3206   "map": {"at": 164504, "to": "mm"},
3207   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3208   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3209  },
3210  {
3211   "chips": ["gfx103"],
3212   "map": {"at": 164508, "to": "mm"},
3213   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3214   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3215  },
3216  {
3217   "chips": ["gfx103"],
3218   "map": {"at": 164512, "to": "mm"},
3219   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3220   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3221  },
3222  {
3223   "chips": ["gfx103"],
3224   "map": {"at": 164516, "to": "mm"},
3225   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3226   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3227  },
3228  {
3229   "chips": ["gfx103"],
3230   "map": {"at": 164520, "to": "mm"},
3231   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3232   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3233  },
3234  {
3235   "chips": ["gfx103"],
3236   "map": {"at": 164524, "to": "mm"},
3237   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3238   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3239  },
3240  {
3241   "chips": ["gfx103"],
3242   "map": {"at": 164528, "to": "mm"},
3243   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3244   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3245  },
3246  {
3247   "chips": ["gfx103"],
3248   "map": {"at": 164532, "to": "mm"},
3249   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3250   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3251  },
3252  {
3253   "chips": ["gfx103"],
3254   "map": {"at": 164536, "to": "mm"},
3255   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3256   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3257  },
3258  {
3259   "chips": ["gfx103"],
3260   "map": {"at": 164540, "to": "mm"},
3261   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3262   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3263  },
3264  {
3265   "chips": ["gfx103"],
3266   "map": {"at": 164544, "to": "mm"},
3267   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3268   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3269  },
3270  {
3271   "chips": ["gfx103"],
3272   "map": {"at": 164548, "to": "mm"},
3273   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3274   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3275  },
3276  {
3277   "chips": ["gfx103"],
3278   "map": {"at": 164552, "to": "mm"},
3279   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3280   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3281  },
3282  {
3283   "chips": ["gfx103"],
3284   "map": {"at": 164556, "to": "mm"},
3285   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3286   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3287  },
3288  {
3289   "chips": ["gfx103"],
3290   "map": {"at": 164560, "to": "mm"},
3291   "name": "PA_SC_VPORT_ZMIN_0"
3292  },
3293  {
3294   "chips": ["gfx103"],
3295   "map": {"at": 164564, "to": "mm"},
3296   "name": "PA_SC_VPORT_ZMAX_0"
3297  },
3298  {
3299   "chips": ["gfx103"],
3300   "map": {"at": 164568, "to": "mm"},
3301   "name": "PA_SC_VPORT_ZMIN_1"
3302  },
3303  {
3304   "chips": ["gfx103"],
3305   "map": {"at": 164572, "to": "mm"},
3306   "name": "PA_SC_VPORT_ZMAX_1"
3307  },
3308  {
3309   "chips": ["gfx103"],
3310   "map": {"at": 164576, "to": "mm"},
3311   "name": "PA_SC_VPORT_ZMIN_2"
3312  },
3313  {
3314   "chips": ["gfx103"],
3315   "map": {"at": 164580, "to": "mm"},
3316   "name": "PA_SC_VPORT_ZMAX_2"
3317  },
3318  {
3319   "chips": ["gfx103"],
3320   "map": {"at": 164584, "to": "mm"},
3321   "name": "PA_SC_VPORT_ZMIN_3"
3322  },
3323  {
3324   "chips": ["gfx103"],
3325   "map": {"at": 164588, "to": "mm"},
3326   "name": "PA_SC_VPORT_ZMAX_3"
3327  },
3328  {
3329   "chips": ["gfx103"],
3330   "map": {"at": 164592, "to": "mm"},
3331   "name": "PA_SC_VPORT_ZMIN_4"
3332  },
3333  {
3334   "chips": ["gfx103"],
3335   "map": {"at": 164596, "to": "mm"},
3336   "name": "PA_SC_VPORT_ZMAX_4"
3337  },
3338  {
3339   "chips": ["gfx103"],
3340   "map": {"at": 164600, "to": "mm"},
3341   "name": "PA_SC_VPORT_ZMIN_5"
3342  },
3343  {
3344   "chips": ["gfx103"],
3345   "map": {"at": 164604, "to": "mm"},
3346   "name": "PA_SC_VPORT_ZMAX_5"
3347  },
3348  {
3349   "chips": ["gfx103"],
3350   "map": {"at": 164608, "to": "mm"},
3351   "name": "PA_SC_VPORT_ZMIN_6"
3352  },
3353  {
3354   "chips": ["gfx103"],
3355   "map": {"at": 164612, "to": "mm"},
3356   "name": "PA_SC_VPORT_ZMAX_6"
3357  },
3358  {
3359   "chips": ["gfx103"],
3360   "map": {"at": 164616, "to": "mm"},
3361   "name": "PA_SC_VPORT_ZMIN_7"
3362  },
3363  {
3364   "chips": ["gfx103"],
3365   "map": {"at": 164620, "to": "mm"},
3366   "name": "PA_SC_VPORT_ZMAX_7"
3367  },
3368  {
3369   "chips": ["gfx103"],
3370   "map": {"at": 164624, "to": "mm"},
3371   "name": "PA_SC_VPORT_ZMIN_8"
3372  },
3373  {
3374   "chips": ["gfx103"],
3375   "map": {"at": 164628, "to": "mm"},
3376   "name": "PA_SC_VPORT_ZMAX_8"
3377  },
3378  {
3379   "chips": ["gfx103"],
3380   "map": {"at": 164632, "to": "mm"},
3381   "name": "PA_SC_VPORT_ZMIN_9"
3382  },
3383  {
3384   "chips": ["gfx103"],
3385   "map": {"at": 164636, "to": "mm"},
3386   "name": "PA_SC_VPORT_ZMAX_9"
3387  },
3388  {
3389   "chips": ["gfx103"],
3390   "map": {"at": 164640, "to": "mm"},
3391   "name": "PA_SC_VPORT_ZMIN_10"
3392  },
3393  {
3394   "chips": ["gfx103"],
3395   "map": {"at": 164644, "to": "mm"},
3396   "name": "PA_SC_VPORT_ZMAX_10"
3397  },
3398  {
3399   "chips": ["gfx103"],
3400   "map": {"at": 164648, "to": "mm"},
3401   "name": "PA_SC_VPORT_ZMIN_11"
3402  },
3403  {
3404   "chips": ["gfx103"],
3405   "map": {"at": 164652, "to": "mm"},
3406   "name": "PA_SC_VPORT_ZMAX_11"
3407  },
3408  {
3409   "chips": ["gfx103"],
3410   "map": {"at": 164656, "to": "mm"},
3411   "name": "PA_SC_VPORT_ZMIN_12"
3412  },
3413  {
3414   "chips": ["gfx103"],
3415   "map": {"at": 164660, "to": "mm"},
3416   "name": "PA_SC_VPORT_ZMAX_12"
3417  },
3418  {
3419   "chips": ["gfx103"],
3420   "map": {"at": 164664, "to": "mm"},
3421   "name": "PA_SC_VPORT_ZMIN_13"
3422  },
3423  {
3424   "chips": ["gfx103"],
3425   "map": {"at": 164668, "to": "mm"},
3426   "name": "PA_SC_VPORT_ZMAX_13"
3427  },
3428  {
3429   "chips": ["gfx103"],
3430   "map": {"at": 164672, "to": "mm"},
3431   "name": "PA_SC_VPORT_ZMIN_14"
3432  },
3433  {
3434   "chips": ["gfx103"],
3435   "map": {"at": 164676, "to": "mm"},
3436   "name": "PA_SC_VPORT_ZMAX_14"
3437  },
3438  {
3439   "chips": ["gfx103"],
3440   "map": {"at": 164680, "to": "mm"},
3441   "name": "PA_SC_VPORT_ZMIN_15"
3442  },
3443  {
3444   "chips": ["gfx103"],
3445   "map": {"at": 164684, "to": "mm"},
3446   "name": "PA_SC_VPORT_ZMAX_15"
3447  },
3448  {
3449   "chips": ["gfx103"],
3450   "map": {"at": 164688, "to": "mm"},
3451   "name": "PA_SC_RASTER_CONFIG",
3452   "type_ref": "PA_SC_RASTER_CONFIG"
3453  },
3454  {
3455   "chips": ["gfx103"],
3456   "map": {"at": 164692, "to": "mm"},
3457   "name": "PA_SC_RASTER_CONFIG_1",
3458   "type_ref": "PA_SC_RASTER_CONFIG_1"
3459  },
3460  {
3461   "chips": ["gfx103"],
3462   "map": {"at": 164696, "to": "mm"},
3463   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3464   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3465  },
3466  {
3467   "chips": ["gfx103"],
3468   "map": {"at": 164700, "to": "mm"},
3469   "name": "PA_SC_TILE_STEERING_OVERRIDE",
3470   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
3471  },
3472  {
3473   "chips": ["gfx103"],
3474   "map": {"at": 164704, "to": "mm"},
3475   "name": "CP_PERFMON_CNTX_CNTL",
3476   "type_ref": "CP_PERFMON_CNTX_CNTL"
3477  },
3478  {
3479   "chips": ["gfx103"],
3480   "map": {"at": 164708, "to": "mm"},
3481   "name": "CP_PIPEID",
3482   "type_ref": "CP_PIPEID"
3483  },
3484  {
3485   "chips": ["gfx103"],
3486   "map": {"at": 164712, "to": "mm"},
3487   "name": "CP_VMID",
3488   "type_ref": "CP_VMID"
3489  },
3490  {
3491   "chips": ["gfx103"],
3492   "map": {"at": 164716, "to": "mm"},
3493   "name": "CONTEXT_RESERVED_REG0"
3494  },
3495  {
3496   "chips": ["gfx103"],
3497   "map": {"at": 164720, "to": "mm"},
3498   "name": "CONTEXT_RESERVED_REG1"
3499  },
3500  {
3501   "chips": ["gfx103"],
3502   "map": {"at": 164864, "to": "mm"},
3503   "name": "VGT_MAX_VTX_INDX"
3504  },
3505  {
3506   "chips": ["gfx103"],
3507   "map": {"at": 164868, "to": "mm"},
3508   "name": "VGT_MIN_VTX_INDX"
3509  },
3510  {
3511   "chips": ["gfx103"],
3512   "map": {"at": 164872, "to": "mm"},
3513   "name": "VGT_INDX_OFFSET"
3514  },
3515  {
3516   "chips": ["gfx103"],
3517   "map": {"at": 164876, "to": "mm"},
3518   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
3519  },
3520  {
3521   "chips": ["gfx103"],
3522   "map": {"at": 164880, "to": "mm"},
3523   "name": "CB_RMI_GL2_CACHE_CONTROL",
3524   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
3525  },
3526  {
3527   "chips": ["gfx103"],
3528   "map": {"at": 164884, "to": "mm"},
3529   "name": "CB_BLEND_RED"
3530  },
3531  {
3532   "chips": ["gfx103"],
3533   "map": {"at": 164888, "to": "mm"},
3534   "name": "CB_BLEND_GREEN"
3535  },
3536  {
3537   "chips": ["gfx103"],
3538   "map": {"at": 164892, "to": "mm"},
3539   "name": "CB_BLEND_BLUE"
3540  },
3541  {
3542   "chips": ["gfx103"],
3543   "map": {"at": 164896, "to": "mm"},
3544   "name": "CB_BLEND_ALPHA"
3545  },
3546  {
3547   "chips": ["gfx103"],
3548   "map": {"at": 164900, "to": "mm"},
3549   "name": "CB_DCC_CONTROL",
3550   "type_ref": "CB_DCC_CONTROL"
3551  },
3552  {
3553   "chips": ["gfx103"],
3554   "map": {"at": 164904, "to": "mm"},
3555   "name": "CB_COVERAGE_OUT_CONTROL",
3556   "type_ref": "CB_COVERAGE_OUT_CONTROL"
3557  },
3558  {
3559   "chips": ["gfx103"],
3560   "map": {"at": 164908, "to": "mm"},
3561   "name": "DB_STENCIL_CONTROL",
3562   "type_ref": "DB_STENCIL_CONTROL"
3563  },
3564  {
3565   "chips": ["gfx103"],
3566   "map": {"at": 164912, "to": "mm"},
3567   "name": "DB_STENCILREFMASK",
3568   "type_ref": "DB_STENCILREFMASK"
3569  },
3570  {
3571   "chips": ["gfx103"],
3572   "map": {"at": 164916, "to": "mm"},
3573   "name": "DB_STENCILREFMASK_BF",
3574   "type_ref": "DB_STENCILREFMASK_BF"
3575  },
3576  {
3577   "chips": ["gfx103"],
3578   "map": {"at": 164924, "to": "mm"},
3579   "name": "PA_CL_VPORT_XSCALE"
3580  },
3581  {
3582   "chips": ["gfx103"],
3583   "map": {"at": 164928, "to": "mm"},
3584   "name": "PA_CL_VPORT_XOFFSET"
3585  },
3586  {
3587   "chips": ["gfx103"],
3588   "map": {"at": 164932, "to": "mm"},
3589   "name": "PA_CL_VPORT_YSCALE"
3590  },
3591  {
3592   "chips": ["gfx103"],
3593   "map": {"at": 164936, "to": "mm"},
3594   "name": "PA_CL_VPORT_YOFFSET"
3595  },
3596  {
3597   "chips": ["gfx103"],
3598   "map": {"at": 164940, "to": "mm"},
3599   "name": "PA_CL_VPORT_ZSCALE"
3600  },
3601  {
3602   "chips": ["gfx103"],
3603   "map": {"at": 164944, "to": "mm"},
3604   "name": "PA_CL_VPORT_ZOFFSET"
3605  },
3606  {
3607   "chips": ["gfx103"],
3608   "map": {"at": 164948, "to": "mm"},
3609   "name": "PA_CL_VPORT_XSCALE_1"
3610  },
3611  {
3612   "chips": ["gfx103"],
3613   "map": {"at": 164952, "to": "mm"},
3614   "name": "PA_CL_VPORT_XOFFSET_1"
3615  },
3616  {
3617   "chips": ["gfx103"],
3618   "map": {"at": 164956, "to": "mm"},
3619   "name": "PA_CL_VPORT_YSCALE_1"
3620  },
3621  {
3622   "chips": ["gfx103"],
3623   "map": {"at": 164960, "to": "mm"},
3624   "name": "PA_CL_VPORT_YOFFSET_1"
3625  },
3626  {
3627   "chips": ["gfx103"],
3628   "map": {"at": 164964, "to": "mm"},
3629   "name": "PA_CL_VPORT_ZSCALE_1"
3630  },
3631  {
3632   "chips": ["gfx103"],
3633   "map": {"at": 164968, "to": "mm"},
3634   "name": "PA_CL_VPORT_ZOFFSET_1"
3635  },
3636  {
3637   "chips": ["gfx103"],
3638   "map": {"at": 164972, "to": "mm"},
3639   "name": "PA_CL_VPORT_XSCALE_2"
3640  },
3641  {
3642   "chips": ["gfx103"],
3643   "map": {"at": 164976, "to": "mm"},
3644   "name": "PA_CL_VPORT_XOFFSET_2"
3645  },
3646  {
3647   "chips": ["gfx103"],
3648   "map": {"at": 164980, "to": "mm"},
3649   "name": "PA_CL_VPORT_YSCALE_2"
3650  },
3651  {
3652   "chips": ["gfx103"],
3653   "map": {"at": 164984, "to": "mm"},
3654   "name": "PA_CL_VPORT_YOFFSET_2"
3655  },
3656  {
3657   "chips": ["gfx103"],
3658   "map": {"at": 164988, "to": "mm"},
3659   "name": "PA_CL_VPORT_ZSCALE_2"
3660  },
3661  {
3662   "chips": ["gfx103"],
3663   "map": {"at": 164992, "to": "mm"},
3664   "name": "PA_CL_VPORT_ZOFFSET_2"
3665  },
3666  {
3667   "chips": ["gfx103"],
3668   "map": {"at": 164996, "to": "mm"},
3669   "name": "PA_CL_VPORT_XSCALE_3"
3670  },
3671  {
3672   "chips": ["gfx103"],
3673   "map": {"at": 165000, "to": "mm"},
3674   "name": "PA_CL_VPORT_XOFFSET_3"
3675  },
3676  {
3677   "chips": ["gfx103"],
3678   "map": {"at": 165004, "to": "mm"},
3679   "name": "PA_CL_VPORT_YSCALE_3"
3680  },
3681  {
3682   "chips": ["gfx103"],
3683   "map": {"at": 165008, "to": "mm"},
3684   "name": "PA_CL_VPORT_YOFFSET_3"
3685  },
3686  {
3687   "chips": ["gfx103"],
3688   "map": {"at": 165012, "to": "mm"},
3689   "name": "PA_CL_VPORT_ZSCALE_3"
3690  },
3691  {
3692   "chips": ["gfx103"],
3693   "map": {"at": 165016, "to": "mm"},
3694   "name": "PA_CL_VPORT_ZOFFSET_3"
3695  },
3696  {
3697   "chips": ["gfx103"],
3698   "map": {"at": 165020, "to": "mm"},
3699   "name": "PA_CL_VPORT_XSCALE_4"
3700  },
3701  {
3702   "chips": ["gfx103"],
3703   "map": {"at": 165024, "to": "mm"},
3704   "name": "PA_CL_VPORT_XOFFSET_4"
3705  },
3706  {
3707   "chips": ["gfx103"],
3708   "map": {"at": 165028, "to": "mm"},
3709   "name": "PA_CL_VPORT_YSCALE_4"
3710  },
3711  {
3712   "chips": ["gfx103"],
3713   "map": {"at": 165032, "to": "mm"},
3714   "name": "PA_CL_VPORT_YOFFSET_4"
3715  },
3716  {
3717   "chips": ["gfx103"],
3718   "map": {"at": 165036, "to": "mm"},
3719   "name": "PA_CL_VPORT_ZSCALE_4"
3720  },
3721  {
3722   "chips": ["gfx103"],
3723   "map": {"at": 165040, "to": "mm"},
3724   "name": "PA_CL_VPORT_ZOFFSET_4"
3725  },
3726  {
3727   "chips": ["gfx103"],
3728   "map": {"at": 165044, "to": "mm"},
3729   "name": "PA_CL_VPORT_XSCALE_5"
3730  },
3731  {
3732   "chips": ["gfx103"],
3733   "map": {"at": 165048, "to": "mm"},
3734   "name": "PA_CL_VPORT_XOFFSET_5"
3735  },
3736  {
3737   "chips": ["gfx103"],
3738   "map": {"at": 165052, "to": "mm"},
3739   "name": "PA_CL_VPORT_YSCALE_5"
3740  },
3741  {
3742   "chips": ["gfx103"],
3743   "map": {"at": 165056, "to": "mm"},
3744   "name": "PA_CL_VPORT_YOFFSET_5"
3745  },
3746  {
3747   "chips": ["gfx103"],
3748   "map": {"at": 165060, "to": "mm"},
3749   "name": "PA_CL_VPORT_ZSCALE_5"
3750  },
3751  {
3752   "chips": ["gfx103"],
3753   "map": {"at": 165064, "to": "mm"},
3754   "name": "PA_CL_VPORT_ZOFFSET_5"
3755  },
3756  {
3757   "chips": ["gfx103"],
3758   "map": {"at": 165068, "to": "mm"},
3759   "name": "PA_CL_VPORT_XSCALE_6"
3760  },
3761  {
3762   "chips": ["gfx103"],
3763   "map": {"at": 165072, "to": "mm"},
3764   "name": "PA_CL_VPORT_XOFFSET_6"
3765  },
3766  {
3767   "chips": ["gfx103"],
3768   "map": {"at": 165076, "to": "mm"},
3769   "name": "PA_CL_VPORT_YSCALE_6"
3770  },
3771  {
3772   "chips": ["gfx103"],
3773   "map": {"at": 165080, "to": "mm"},
3774   "name": "PA_CL_VPORT_YOFFSET_6"
3775  },
3776  {
3777   "chips": ["gfx103"],
3778   "map": {"at": 165084, "to": "mm"},
3779   "name": "PA_CL_VPORT_ZSCALE_6"
3780  },
3781  {
3782   "chips": ["gfx103"],
3783   "map": {"at": 165088, "to": "mm"},
3784   "name": "PA_CL_VPORT_ZOFFSET_6"
3785  },
3786  {
3787   "chips": ["gfx103"],
3788   "map": {"at": 165092, "to": "mm"},
3789   "name": "PA_CL_VPORT_XSCALE_7"
3790  },
3791  {
3792   "chips": ["gfx103"],
3793   "map": {"at": 165096, "to": "mm"},
3794   "name": "PA_CL_VPORT_XOFFSET_7"
3795  },
3796  {
3797   "chips": ["gfx103"],
3798   "map": {"at": 165100, "to": "mm"},
3799   "name": "PA_CL_VPORT_YSCALE_7"
3800  },
3801  {
3802   "chips": ["gfx103"],
3803   "map": {"at": 165104, "to": "mm"},
3804   "name": "PA_CL_VPORT_YOFFSET_7"
3805  },
3806  {
3807   "chips": ["gfx103"],
3808   "map": {"at": 165108, "to": "mm"},
3809   "name": "PA_CL_VPORT_ZSCALE_7"
3810  },
3811  {
3812   "chips": ["gfx103"],
3813   "map": {"at": 165112, "to": "mm"},
3814   "name": "PA_CL_VPORT_ZOFFSET_7"
3815  },
3816  {
3817   "chips": ["gfx103"],
3818   "map": {"at": 165116, "to": "mm"},
3819   "name": "PA_CL_VPORT_XSCALE_8"
3820  },
3821  {
3822   "chips": ["gfx103"],
3823   "map": {"at": 165120, "to": "mm"},
3824   "name": "PA_CL_VPORT_XOFFSET_8"
3825  },
3826  {
3827   "chips": ["gfx103"],
3828   "map": {"at": 165124, "to": "mm"},
3829   "name": "PA_CL_VPORT_YSCALE_8"
3830  },
3831  {
3832   "chips": ["gfx103"],
3833   "map": {"at": 165128, "to": "mm"},
3834   "name": "PA_CL_VPORT_YOFFSET_8"
3835  },
3836  {
3837   "chips": ["gfx103"],
3838   "map": {"at": 165132, "to": "mm"},
3839   "name": "PA_CL_VPORT_ZSCALE_8"
3840  },
3841  {
3842   "chips": ["gfx103"],
3843   "map": {"at": 165136, "to": "mm"},
3844   "name": "PA_CL_VPORT_ZOFFSET_8"
3845  },
3846  {
3847   "chips": ["gfx103"],
3848   "map": {"at": 165140, "to": "mm"},
3849   "name": "PA_CL_VPORT_XSCALE_9"
3850  },
3851  {
3852   "chips": ["gfx103"],
3853   "map": {"at": 165144, "to": "mm"},
3854   "name": "PA_CL_VPORT_XOFFSET_9"
3855  },
3856  {
3857   "chips": ["gfx103"],
3858   "map": {"at": 165148, "to": "mm"},
3859   "name": "PA_CL_VPORT_YSCALE_9"
3860  },
3861  {
3862   "chips": ["gfx103"],
3863   "map": {"at": 165152, "to": "mm"},
3864   "name": "PA_CL_VPORT_YOFFSET_9"
3865  },
3866  {
3867   "chips": ["gfx103"],
3868   "map": {"at": 165156, "to": "mm"},
3869   "name": "PA_CL_VPORT_ZSCALE_9"
3870  },
3871  {
3872   "chips": ["gfx103"],
3873   "map": {"at": 165160, "to": "mm"},
3874   "name": "PA_CL_VPORT_ZOFFSET_9"
3875  },
3876  {
3877   "chips": ["gfx103"],
3878   "map": {"at": 165164, "to": "mm"},
3879   "name": "PA_CL_VPORT_XSCALE_10"
3880  },
3881  {
3882   "chips": ["gfx103"],
3883   "map": {"at": 165168, "to": "mm"},
3884   "name": "PA_CL_VPORT_XOFFSET_10"
3885  },
3886  {
3887   "chips": ["gfx103"],
3888   "map": {"at": 165172, "to": "mm"},
3889   "name": "PA_CL_VPORT_YSCALE_10"
3890  },
3891  {
3892   "chips": ["gfx103"],
3893   "map": {"at": 165176, "to": "mm"},
3894   "name": "PA_CL_VPORT_YOFFSET_10"
3895  },
3896  {
3897   "chips": ["gfx103"],
3898   "map": {"at": 165180, "to": "mm"},
3899   "name": "PA_CL_VPORT_ZSCALE_10"
3900  },
3901  {
3902   "chips": ["gfx103"],
3903   "map": {"at": 165184, "to": "mm"},
3904   "name": "PA_CL_VPORT_ZOFFSET_10"
3905  },
3906  {
3907   "chips": ["gfx103"],
3908   "map": {"at": 165188, "to": "mm"},
3909   "name": "PA_CL_VPORT_XSCALE_11"
3910  },
3911  {
3912   "chips": ["gfx103"],
3913   "map": {"at": 165192, "to": "mm"},
3914   "name": "PA_CL_VPORT_XOFFSET_11"
3915  },
3916  {
3917   "chips": ["gfx103"],
3918   "map": {"at": 165196, "to": "mm"},
3919   "name": "PA_CL_VPORT_YSCALE_11"
3920  },
3921  {
3922   "chips": ["gfx103"],
3923   "map": {"at": 165200, "to": "mm"},
3924   "name": "PA_CL_VPORT_YOFFSET_11"
3925  },
3926  {
3927   "chips": ["gfx103"],
3928   "map": {"at": 165204, "to": "mm"},
3929   "name": "PA_CL_VPORT_ZSCALE_11"
3930  },
3931  {
3932   "chips": ["gfx103"],
3933   "map": {"at": 165208, "to": "mm"},
3934   "name": "PA_CL_VPORT_ZOFFSET_11"
3935  },
3936  {
3937   "chips": ["gfx103"],
3938   "map": {"at": 165212, "to": "mm"},
3939   "name": "PA_CL_VPORT_XSCALE_12"
3940  },
3941  {
3942   "chips": ["gfx103"],
3943   "map": {"at": 165216, "to": "mm"},
3944   "name": "PA_CL_VPORT_XOFFSET_12"
3945  },
3946  {
3947   "chips": ["gfx103"],
3948   "map": {"at": 165220, "to": "mm"},
3949   "name": "PA_CL_VPORT_YSCALE_12"
3950  },
3951  {
3952   "chips": ["gfx103"],
3953   "map": {"at": 165224, "to": "mm"},
3954   "name": "PA_CL_VPORT_YOFFSET_12"
3955  },
3956  {
3957   "chips": ["gfx103"],
3958   "map": {"at": 165228, "to": "mm"},
3959   "name": "PA_CL_VPORT_ZSCALE_12"
3960  },
3961  {
3962   "chips": ["gfx103"],
3963   "map": {"at": 165232, "to": "mm"},
3964   "name": "PA_CL_VPORT_ZOFFSET_12"
3965  },
3966  {
3967   "chips": ["gfx103"],
3968   "map": {"at": 165236, "to": "mm"},
3969   "name": "PA_CL_VPORT_XSCALE_13"
3970  },
3971  {
3972   "chips": ["gfx103"],
3973   "map": {"at": 165240, "to": "mm"},
3974   "name": "PA_CL_VPORT_XOFFSET_13"
3975  },
3976  {
3977   "chips": ["gfx103"],
3978   "map": {"at": 165244, "to": "mm"},
3979   "name": "PA_CL_VPORT_YSCALE_13"
3980  },
3981  {
3982   "chips": ["gfx103"],
3983   "map": {"at": 165248, "to": "mm"},
3984   "name": "PA_CL_VPORT_YOFFSET_13"
3985  },
3986  {
3987   "chips": ["gfx103"],
3988   "map": {"at": 165252, "to": "mm"},
3989   "name": "PA_CL_VPORT_ZSCALE_13"
3990  },
3991  {
3992   "chips": ["gfx103"],
3993   "map": {"at": 165256, "to": "mm"},
3994   "name": "PA_CL_VPORT_ZOFFSET_13"
3995  },
3996  {
3997   "chips": ["gfx103"],
3998   "map": {"at": 165260, "to": "mm"},
3999   "name": "PA_CL_VPORT_XSCALE_14"
4000  },
4001  {
4002   "chips": ["gfx103"],
4003   "map": {"at": 165264, "to": "mm"},
4004   "name": "PA_CL_VPORT_XOFFSET_14"
4005  },
4006  {
4007   "chips": ["gfx103"],
4008   "map": {"at": 165268, "to": "mm"},
4009   "name": "PA_CL_VPORT_YSCALE_14"
4010  },
4011  {
4012   "chips": ["gfx103"],
4013   "map": {"at": 165272, "to": "mm"},
4014   "name": "PA_CL_VPORT_YOFFSET_14"
4015  },
4016  {
4017   "chips": ["gfx103"],
4018   "map": {"at": 165276, "to": "mm"},
4019   "name": "PA_CL_VPORT_ZSCALE_14"
4020  },
4021  {
4022   "chips": ["gfx103"],
4023   "map": {"at": 165280, "to": "mm"},
4024   "name": "PA_CL_VPORT_ZOFFSET_14"
4025  },
4026  {
4027   "chips": ["gfx103"],
4028   "map": {"at": 165284, "to": "mm"},
4029   "name": "PA_CL_VPORT_XSCALE_15"
4030  },
4031  {
4032   "chips": ["gfx103"],
4033   "map": {"at": 165288, "to": "mm"},
4034   "name": "PA_CL_VPORT_XOFFSET_15"
4035  },
4036  {
4037   "chips": ["gfx103"],
4038   "map": {"at": 165292, "to": "mm"},
4039   "name": "PA_CL_VPORT_YSCALE_15"
4040  },
4041  {
4042   "chips": ["gfx103"],
4043   "map": {"at": 165296, "to": "mm"},
4044   "name": "PA_CL_VPORT_YOFFSET_15"
4045  },
4046  {
4047   "chips": ["gfx103"],
4048   "map": {"at": 165300, "to": "mm"},
4049   "name": "PA_CL_VPORT_ZSCALE_15"
4050  },
4051  {
4052   "chips": ["gfx103"],
4053   "map": {"at": 165304, "to": "mm"},
4054   "name": "PA_CL_VPORT_ZOFFSET_15"
4055  },
4056  {
4057   "chips": ["gfx103"],
4058   "map": {"at": 165308, "to": "mm"},
4059   "name": "PA_CL_UCP_0_X"
4060  },
4061  {
4062   "chips": ["gfx103"],
4063   "map": {"at": 165312, "to": "mm"},
4064   "name": "PA_CL_UCP_0_Y"
4065  },
4066  {
4067   "chips": ["gfx103"],
4068   "map": {"at": 165316, "to": "mm"},
4069   "name": "PA_CL_UCP_0_Z"
4070  },
4071  {
4072   "chips": ["gfx103"],
4073   "map": {"at": 165320, "to": "mm"},
4074   "name": "PA_CL_UCP_0_W"
4075  },
4076  {
4077   "chips": ["gfx103"],
4078   "map": {"at": 165324, "to": "mm"},
4079   "name": "PA_CL_UCP_1_X"
4080  },
4081  {
4082   "chips": ["gfx103"],
4083   "map": {"at": 165328, "to": "mm"},
4084   "name": "PA_CL_UCP_1_Y"
4085  },
4086  {
4087   "chips": ["gfx103"],
4088   "map": {"at": 165332, "to": "mm"},
4089   "name": "PA_CL_UCP_1_Z"
4090  },
4091  {
4092   "chips": ["gfx103"],
4093   "map": {"at": 165336, "to": "mm"},
4094   "name": "PA_CL_UCP_1_W"
4095  },
4096  {
4097   "chips": ["gfx103"],
4098   "map": {"at": 165340, "to": "mm"},
4099   "name": "PA_CL_UCP_2_X"
4100  },
4101  {
4102   "chips": ["gfx103"],
4103   "map": {"at": 165344, "to": "mm"},
4104   "name": "PA_CL_UCP_2_Y"
4105  },
4106  {
4107   "chips": ["gfx103"],
4108   "map": {"at": 165348, "to": "mm"},
4109   "name": "PA_CL_UCP_2_Z"
4110  },
4111  {
4112   "chips": ["gfx103"],
4113   "map": {"at": 165352, "to": "mm"},
4114   "name": "PA_CL_UCP_2_W"
4115  },
4116  {
4117   "chips": ["gfx103"],
4118   "map": {"at": 165356, "to": "mm"},
4119   "name": "PA_CL_UCP_3_X"
4120  },
4121  {
4122   "chips": ["gfx103"],
4123   "map": {"at": 165360, "to": "mm"},
4124   "name": "PA_CL_UCP_3_Y"
4125  },
4126  {
4127   "chips": ["gfx103"],
4128   "map": {"at": 165364, "to": "mm"},
4129   "name": "PA_CL_UCP_3_Z"
4130  },
4131  {
4132   "chips": ["gfx103"],
4133   "map": {"at": 165368, "to": "mm"},
4134   "name": "PA_CL_UCP_3_W"
4135  },
4136  {
4137   "chips": ["gfx103"],
4138   "map": {"at": 165372, "to": "mm"},
4139   "name": "PA_CL_UCP_4_X"
4140  },
4141  {
4142   "chips": ["gfx103"],
4143   "map": {"at": 165376, "to": "mm"},
4144   "name": "PA_CL_UCP_4_Y"
4145  },
4146  {
4147   "chips": ["gfx103"],
4148   "map": {"at": 165380, "to": "mm"},
4149   "name": "PA_CL_UCP_4_Z"
4150  },
4151  {
4152   "chips": ["gfx103"],
4153   "map": {"at": 165384, "to": "mm"},
4154   "name": "PA_CL_UCP_4_W"
4155  },
4156  {
4157   "chips": ["gfx103"],
4158   "map": {"at": 165388, "to": "mm"},
4159   "name": "PA_CL_UCP_5_X"
4160  },
4161  {
4162   "chips": ["gfx103"],
4163   "map": {"at": 165392, "to": "mm"},
4164   "name": "PA_CL_UCP_5_Y"
4165  },
4166  {
4167   "chips": ["gfx103"],
4168   "map": {"at": 165396, "to": "mm"},
4169   "name": "PA_CL_UCP_5_Z"
4170  },
4171  {
4172   "chips": ["gfx103"],
4173   "map": {"at": 165400, "to": "mm"},
4174   "name": "PA_CL_UCP_5_W"
4175  },
4176  {
4177   "chips": ["gfx103"],
4178   "map": {"at": 165404, "to": "mm"},
4179   "name": "PA_CL_PROG_NEAR_CLIP_Z"
4180  },
4181  {
4182   "chips": ["gfx103"],
4183   "map": {"at": 165444, "to": "mm"},
4184   "name": "SPI_PS_INPUT_CNTL_0",
4185   "type_ref": "SPI_PS_INPUT_CNTL_0"
4186  },
4187  {
4188   "chips": ["gfx103"],
4189   "map": {"at": 165448, "to": "mm"},
4190   "name": "SPI_PS_INPUT_CNTL_1",
4191   "type_ref": "SPI_PS_INPUT_CNTL_0"
4192  },
4193  {
4194   "chips": ["gfx103"],
4195   "map": {"at": 165452, "to": "mm"},
4196   "name": "SPI_PS_INPUT_CNTL_2",
4197   "type_ref": "SPI_PS_INPUT_CNTL_0"
4198  },
4199  {
4200   "chips": ["gfx103"],
4201   "map": {"at": 165456, "to": "mm"},
4202   "name": "SPI_PS_INPUT_CNTL_3",
4203   "type_ref": "SPI_PS_INPUT_CNTL_0"
4204  },
4205  {
4206   "chips": ["gfx103"],
4207   "map": {"at": 165460, "to": "mm"},
4208   "name": "SPI_PS_INPUT_CNTL_4",
4209   "type_ref": "SPI_PS_INPUT_CNTL_0"
4210  },
4211  {
4212   "chips": ["gfx103"],
4213   "map": {"at": 165464, "to": "mm"},
4214   "name": "SPI_PS_INPUT_CNTL_5",
4215   "type_ref": "SPI_PS_INPUT_CNTL_0"
4216  },
4217  {
4218   "chips": ["gfx103"],
4219   "map": {"at": 165468, "to": "mm"},
4220   "name": "SPI_PS_INPUT_CNTL_6",
4221   "type_ref": "SPI_PS_INPUT_CNTL_0"
4222  },
4223  {
4224   "chips": ["gfx103"],
4225   "map": {"at": 165472, "to": "mm"},
4226   "name": "SPI_PS_INPUT_CNTL_7",
4227   "type_ref": "SPI_PS_INPUT_CNTL_0"
4228  },
4229  {
4230   "chips": ["gfx103"],
4231   "map": {"at": 165476, "to": "mm"},
4232   "name": "SPI_PS_INPUT_CNTL_8",
4233   "type_ref": "SPI_PS_INPUT_CNTL_0"
4234  },
4235  {
4236   "chips": ["gfx103"],
4237   "map": {"at": 165480, "to": "mm"},
4238   "name": "SPI_PS_INPUT_CNTL_9",
4239   "type_ref": "SPI_PS_INPUT_CNTL_0"
4240  },
4241  {
4242   "chips": ["gfx103"],
4243   "map": {"at": 165484, "to": "mm"},
4244   "name": "SPI_PS_INPUT_CNTL_10",
4245   "type_ref": "SPI_PS_INPUT_CNTL_0"
4246  },
4247  {
4248   "chips": ["gfx103"],
4249   "map": {"at": 165488, "to": "mm"},
4250   "name": "SPI_PS_INPUT_CNTL_11",
4251   "type_ref": "SPI_PS_INPUT_CNTL_0"
4252  },
4253  {
4254   "chips": ["gfx103"],
4255   "map": {"at": 165492, "to": "mm"},
4256   "name": "SPI_PS_INPUT_CNTL_12",
4257   "type_ref": "SPI_PS_INPUT_CNTL_0"
4258  },
4259  {
4260   "chips": ["gfx103"],
4261   "map": {"at": 165496, "to": "mm"},
4262   "name": "SPI_PS_INPUT_CNTL_13",
4263   "type_ref": "SPI_PS_INPUT_CNTL_0"
4264  },
4265  {
4266   "chips": ["gfx103"],
4267   "map": {"at": 165500, "to": "mm"},
4268   "name": "SPI_PS_INPUT_CNTL_14",
4269   "type_ref": "SPI_PS_INPUT_CNTL_0"
4270  },
4271  {
4272   "chips": ["gfx103"],
4273   "map": {"at": 165504, "to": "mm"},
4274   "name": "SPI_PS_INPUT_CNTL_15",
4275   "type_ref": "SPI_PS_INPUT_CNTL_0"
4276  },
4277  {
4278   "chips": ["gfx103"],
4279   "map": {"at": 165508, "to": "mm"},
4280   "name": "SPI_PS_INPUT_CNTL_16",
4281   "type_ref": "SPI_PS_INPUT_CNTL_0"
4282  },
4283  {
4284   "chips": ["gfx103"],
4285   "map": {"at": 165512, "to": "mm"},
4286   "name": "SPI_PS_INPUT_CNTL_17",
4287   "type_ref": "SPI_PS_INPUT_CNTL_0"
4288  },
4289  {
4290   "chips": ["gfx103"],
4291   "map": {"at": 165516, "to": "mm"},
4292   "name": "SPI_PS_INPUT_CNTL_18",
4293   "type_ref": "SPI_PS_INPUT_CNTL_0"
4294  },
4295  {
4296   "chips": ["gfx103"],
4297   "map": {"at": 165520, "to": "mm"},
4298   "name": "SPI_PS_INPUT_CNTL_19",
4299   "type_ref": "SPI_PS_INPUT_CNTL_0"
4300  },
4301  {
4302   "chips": ["gfx103"],
4303   "map": {"at": 165524, "to": "mm"},
4304   "name": "SPI_PS_INPUT_CNTL_20",
4305   "type_ref": "SPI_PS_INPUT_CNTL_20"
4306  },
4307  {
4308   "chips": ["gfx103"],
4309   "map": {"at": 165528, "to": "mm"},
4310   "name": "SPI_PS_INPUT_CNTL_21",
4311   "type_ref": "SPI_PS_INPUT_CNTL_20"
4312  },
4313  {
4314   "chips": ["gfx103"],
4315   "map": {"at": 165532, "to": "mm"},
4316   "name": "SPI_PS_INPUT_CNTL_22",
4317   "type_ref": "SPI_PS_INPUT_CNTL_20"
4318  },
4319  {
4320   "chips": ["gfx103"],
4321   "map": {"at": 165536, "to": "mm"},
4322   "name": "SPI_PS_INPUT_CNTL_23",
4323   "type_ref": "SPI_PS_INPUT_CNTL_20"
4324  },
4325  {
4326   "chips": ["gfx103"],
4327   "map": {"at": 165540, "to": "mm"},
4328   "name": "SPI_PS_INPUT_CNTL_24",
4329   "type_ref": "SPI_PS_INPUT_CNTL_20"
4330  },
4331  {
4332   "chips": ["gfx103"],
4333   "map": {"at": 165544, "to": "mm"},
4334   "name": "SPI_PS_INPUT_CNTL_25",
4335   "type_ref": "SPI_PS_INPUT_CNTL_20"
4336  },
4337  {
4338   "chips": ["gfx103"],
4339   "map": {"at": 165548, "to": "mm"},
4340   "name": "SPI_PS_INPUT_CNTL_26",
4341   "type_ref": "SPI_PS_INPUT_CNTL_20"
4342  },
4343  {
4344   "chips": ["gfx103"],
4345   "map": {"at": 165552, "to": "mm"},
4346   "name": "SPI_PS_INPUT_CNTL_27",
4347   "type_ref": "SPI_PS_INPUT_CNTL_20"
4348  },
4349  {
4350   "chips": ["gfx103"],
4351   "map": {"at": 165556, "to": "mm"},
4352   "name": "SPI_PS_INPUT_CNTL_28",
4353   "type_ref": "SPI_PS_INPUT_CNTL_20"
4354  },
4355  {
4356   "chips": ["gfx103"],
4357   "map": {"at": 165560, "to": "mm"},
4358   "name": "SPI_PS_INPUT_CNTL_29",
4359   "type_ref": "SPI_PS_INPUT_CNTL_20"
4360  },
4361  {
4362   "chips": ["gfx103"],
4363   "map": {"at": 165564, "to": "mm"},
4364   "name": "SPI_PS_INPUT_CNTL_30",
4365   "type_ref": "SPI_PS_INPUT_CNTL_20"
4366  },
4367  {
4368   "chips": ["gfx103"],
4369   "map": {"at": 165568, "to": "mm"},
4370   "name": "SPI_PS_INPUT_CNTL_31",
4371   "type_ref": "SPI_PS_INPUT_CNTL_20"
4372  },
4373  {
4374   "chips": ["gfx103"],
4375   "map": {"at": 165572, "to": "mm"},
4376   "name": "SPI_VS_OUT_CONFIG",
4377   "type_ref": "SPI_VS_OUT_CONFIG"
4378  },
4379  {
4380   "chips": ["gfx103"],
4381   "map": {"at": 165580, "to": "mm"},
4382   "name": "SPI_PS_INPUT_ENA",
4383   "type_ref": "SPI_PS_INPUT_ENA"
4384  },
4385  {
4386   "chips": ["gfx103"],
4387   "map": {"at": 165584, "to": "mm"},
4388   "name": "SPI_PS_INPUT_ADDR",
4389   "type_ref": "SPI_PS_INPUT_ENA"
4390  },
4391  {
4392   "chips": ["gfx103"],
4393   "map": {"at": 165588, "to": "mm"},
4394   "name": "SPI_INTERP_CONTROL_0",
4395   "type_ref": "SPI_INTERP_CONTROL_0"
4396  },
4397  {
4398   "chips": ["gfx103"],
4399   "map": {"at": 165592, "to": "mm"},
4400   "name": "SPI_PS_IN_CONTROL",
4401   "type_ref": "SPI_PS_IN_CONTROL"
4402  },
4403  {
4404   "chips": ["gfx103"],
4405   "map": {"at": 165600, "to": "mm"},
4406   "name": "SPI_BARYC_CNTL",
4407   "type_ref": "SPI_BARYC_CNTL"
4408  },
4409  {
4410   "chips": ["gfx103"],
4411   "map": {"at": 165608, "to": "mm"},
4412   "name": "SPI_TMPRING_SIZE",
4413   "type_ref": "COMPUTE_TMPRING_SIZE"
4414  },
4415  {
4416   "chips": ["gfx103"],
4417   "map": {"at": 165640, "to": "mm"},
4418   "name": "SPI_SHADER_IDX_FORMAT",
4419   "type_ref": "SPI_SHADER_IDX_FORMAT"
4420  },
4421  {
4422   "chips": ["gfx103"],
4423   "map": {"at": 165644, "to": "mm"},
4424   "name": "SPI_SHADER_POS_FORMAT",
4425   "type_ref": "SPI_SHADER_POS_FORMAT"
4426  },
4427  {
4428   "chips": ["gfx103"],
4429   "map": {"at": 165648, "to": "mm"},
4430   "name": "SPI_SHADER_Z_FORMAT",
4431   "type_ref": "SPI_SHADER_Z_FORMAT"
4432  },
4433  {
4434   "chips": ["gfx103"],
4435   "map": {"at": 165652, "to": "mm"},
4436   "name": "SPI_SHADER_COL_FORMAT",
4437   "type_ref": "SPI_SHADER_COL_FORMAT"
4438  },
4439  {
4440   "chips": ["gfx103"],
4441   "map": {"at": 165712, "to": "mm"},
4442   "name": "SX_PS_DOWNCONVERT_CONTROL",
4443   "type_ref": "SX_PS_DOWNCONVERT_CONTROL"
4444  },
4445  {
4446   "chips": ["gfx103"],
4447   "map": {"at": 165716, "to": "mm"},
4448   "name": "SX_PS_DOWNCONVERT",
4449   "type_ref": "SX_PS_DOWNCONVERT"
4450  },
4451  {
4452   "chips": ["gfx103"],
4453   "map": {"at": 165720, "to": "mm"},
4454   "name": "SX_BLEND_OPT_EPSILON",
4455   "type_ref": "SX_BLEND_OPT_EPSILON"
4456  },
4457  {
4458   "chips": ["gfx103"],
4459   "map": {"at": 165724, "to": "mm"},
4460   "name": "SX_BLEND_OPT_CONTROL",
4461   "type_ref": "SX_BLEND_OPT_CONTROL"
4462  },
4463  {
4464   "chips": ["gfx103"],
4465   "map": {"at": 165728, "to": "mm"},
4466   "name": "SX_MRT0_BLEND_OPT",
4467   "type_ref": "SX_MRT0_BLEND_OPT"
4468  },
4469  {
4470   "chips": ["gfx103"],
4471   "map": {"at": 165732, "to": "mm"},
4472   "name": "SX_MRT1_BLEND_OPT",
4473   "type_ref": "SX_MRT0_BLEND_OPT"
4474  },
4475  {
4476   "chips": ["gfx103"],
4477   "map": {"at": 165736, "to": "mm"},
4478   "name": "SX_MRT2_BLEND_OPT",
4479   "type_ref": "SX_MRT0_BLEND_OPT"
4480  },
4481  {
4482   "chips": ["gfx103"],
4483   "map": {"at": 165740, "to": "mm"},
4484   "name": "SX_MRT3_BLEND_OPT",
4485   "type_ref": "SX_MRT0_BLEND_OPT"
4486  },
4487  {
4488   "chips": ["gfx103"],
4489   "map": {"at": 165744, "to": "mm"},
4490   "name": "SX_MRT4_BLEND_OPT",
4491   "type_ref": "SX_MRT0_BLEND_OPT"
4492  },
4493  {
4494   "chips": ["gfx103"],
4495   "map": {"at": 165748, "to": "mm"},
4496   "name": "SX_MRT5_BLEND_OPT",
4497   "type_ref": "SX_MRT0_BLEND_OPT"
4498  },
4499  {
4500   "chips": ["gfx103"],
4501   "map": {"at": 165752, "to": "mm"},
4502   "name": "SX_MRT6_BLEND_OPT",
4503   "type_ref": "SX_MRT0_BLEND_OPT"
4504  },
4505  {
4506   "chips": ["gfx103"],
4507   "map": {"at": 165756, "to": "mm"},
4508   "name": "SX_MRT7_BLEND_OPT",
4509   "type_ref": "SX_MRT0_BLEND_OPT"
4510  },
4511  {
4512   "chips": ["gfx103"],
4513   "map": {"at": 165760, "to": "mm"},
4514   "name": "CB_BLEND0_CONTROL",
4515   "type_ref": "CB_BLEND0_CONTROL"
4516  },
4517  {
4518   "chips": ["gfx103"],
4519   "map": {"at": 165764, "to": "mm"},
4520   "name": "CB_BLEND1_CONTROL",
4521   "type_ref": "CB_BLEND0_CONTROL"
4522  },
4523  {
4524   "chips": ["gfx103"],
4525   "map": {"at": 165768, "to": "mm"},
4526   "name": "CB_BLEND2_CONTROL",
4527   "type_ref": "CB_BLEND0_CONTROL"
4528  },
4529  {
4530   "chips": ["gfx103"],
4531   "map": {"at": 165772, "to": "mm"},
4532   "name": "CB_BLEND3_CONTROL",
4533   "type_ref": "CB_BLEND0_CONTROL"
4534  },
4535  {
4536   "chips": ["gfx103"],
4537   "map": {"at": 165776, "to": "mm"},
4538   "name": "CB_BLEND4_CONTROL",
4539   "type_ref": "CB_BLEND0_CONTROL"
4540  },
4541  {
4542   "chips": ["gfx103"],
4543   "map": {"at": 165780, "to": "mm"},
4544   "name": "CB_BLEND5_CONTROL",
4545   "type_ref": "CB_BLEND0_CONTROL"
4546  },
4547  {
4548   "chips": ["gfx103"],
4549   "map": {"at": 165784, "to": "mm"},
4550   "name": "CB_BLEND6_CONTROL",
4551   "type_ref": "CB_BLEND0_CONTROL"
4552  },
4553  {
4554   "chips": ["gfx103"],
4555   "map": {"at": 165788, "to": "mm"},
4556   "name": "CB_BLEND7_CONTROL",
4557   "type_ref": "CB_BLEND0_CONTROL"
4558  },
4559  {
4560   "chips": ["gfx103"],
4561   "map": {"at": 165836, "to": "mm"},
4562   "name": "CS_COPY_STATE",
4563   "type_ref": "CS_COPY_STATE"
4564  },
4565  {
4566   "chips": ["gfx103"],
4567   "map": {"at": 165840, "to": "mm"},
4568   "name": "GFX_COPY_STATE",
4569   "type_ref": "CS_COPY_STATE"
4570  },
4571  {
4572   "chips": ["gfx103"],
4573   "map": {"at": 165844, "to": "mm"},
4574   "name": "PA_CL_POINT_X_RAD"
4575  },
4576  {
4577   "chips": ["gfx103"],
4578   "map": {"at": 165848, "to": "mm"},
4579   "name": "PA_CL_POINT_Y_RAD"
4580  },
4581  {
4582   "chips": ["gfx103"],
4583   "map": {"at": 165852, "to": "mm"},
4584   "name": "PA_CL_POINT_SIZE"
4585  },
4586  {
4587   "chips": ["gfx103"],
4588   "map": {"at": 165856, "to": "mm"},
4589   "name": "PA_CL_POINT_CULL_RAD"
4590  },
4591  {
4592   "chips": ["gfx103"],
4593   "map": {"at": 165860, "to": "mm"},
4594   "name": "VGT_DMA_BASE_HI",
4595   "type_ref": "VGT_DMA_BASE_HI"
4596  },
4597  {
4598   "chips": ["gfx103"],
4599   "map": {"at": 165864, "to": "mm"},
4600   "name": "VGT_DMA_BASE"
4601  },
4602  {
4603   "chips": ["gfx103"],
4604   "map": {"at": 165872, "to": "mm"},
4605   "name": "VGT_DRAW_INITIATOR",
4606   "type_ref": "VGT_DRAW_INITIATOR"
4607  },
4608  {
4609   "chips": ["gfx103"],
4610   "map": {"at": 165876, "to": "mm"},
4611   "name": "VGT_IMMED_DATA"
4612  },
4613  {
4614   "chips": ["gfx103"],
4615   "map": {"at": 165880, "to": "mm"},
4616   "name": "VGT_EVENT_ADDRESS_REG",
4617   "type_ref": "VGT_EVENT_ADDRESS_REG"
4618  },
4619  {
4620   "chips": ["gfx103"],
4621   "map": {"at": 165884, "to": "mm"},
4622   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
4623   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
4624  },
4625  {
4626   "chips": ["gfx103"],
4627   "map": {"at": 165888, "to": "mm"},
4628   "name": "DB_DEPTH_CONTROL",
4629   "type_ref": "DB_DEPTH_CONTROL"
4630  },
4631  {
4632   "chips": ["gfx103"],
4633   "map": {"at": 165892, "to": "mm"},
4634   "name": "DB_EQAA",
4635   "type_ref": "DB_EQAA"
4636  },
4637  {
4638   "chips": ["gfx103"],
4639   "map": {"at": 165896, "to": "mm"},
4640   "name": "CB_COLOR_CONTROL",
4641   "type_ref": "CB_COLOR_CONTROL"
4642  },
4643  {
4644   "chips": ["gfx103"],
4645   "map": {"at": 165900, "to": "mm"},
4646   "name": "DB_SHADER_CONTROL",
4647   "type_ref": "DB_SHADER_CONTROL"
4648  },
4649  {
4650   "chips": ["gfx103"],
4651   "map": {"at": 165904, "to": "mm"},
4652   "name": "PA_CL_CLIP_CNTL",
4653   "type_ref": "PA_CL_CLIP_CNTL"
4654  },
4655  {
4656   "chips": ["gfx103"],
4657   "map": {"at": 165908, "to": "mm"},
4658   "name": "PA_SU_SC_MODE_CNTL",
4659   "type_ref": "PA_SU_SC_MODE_CNTL"
4660  },
4661  {
4662   "chips": ["gfx103"],
4663   "map": {"at": 165912, "to": "mm"},
4664   "name": "PA_CL_VTE_CNTL",
4665   "type_ref": "PA_CL_VTE_CNTL"
4666  },
4667  {
4668   "chips": ["gfx103"],
4669   "map": {"at": 165916, "to": "mm"},
4670   "name": "PA_CL_VS_OUT_CNTL",
4671   "type_ref": "PA_CL_VS_OUT_CNTL"
4672  },
4673  {
4674   "chips": ["gfx103"],
4675   "map": {"at": 165920, "to": "mm"},
4676   "name": "PA_CL_NANINF_CNTL",
4677   "type_ref": "PA_CL_NANINF_CNTL"
4678  },
4679  {
4680   "chips": ["gfx103"],
4681   "map": {"at": 165924, "to": "mm"},
4682   "name": "PA_SU_LINE_STIPPLE_CNTL",
4683   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
4684  },
4685  {
4686   "chips": ["gfx103"],
4687   "map": {"at": 165928, "to": "mm"},
4688   "name": "PA_SU_LINE_STIPPLE_SCALE"
4689  },
4690  {
4691   "chips": ["gfx103"],
4692   "map": {"at": 165932, "to": "mm"},
4693   "name": "PA_SU_PRIM_FILTER_CNTL",
4694   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
4695  },
4696  {
4697   "chips": ["gfx103"],
4698   "map": {"at": 165936, "to": "mm"},
4699   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
4700   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
4701  },
4702  {
4703   "chips": ["gfx103"],
4704   "map": {"at": 165944, "to": "mm"},
4705   "name": "PA_CL_NGG_CNTL",
4706   "type_ref": "PA_CL_NGG_CNTL"
4707  },
4708  {
4709   "chips": ["gfx103"],
4710   "map": {"at": 165948, "to": "mm"},
4711   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
4712   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
4713  },
4714  {
4715   "chips": ["gfx103"],
4716   "map": {"at": 165952, "to": "mm"},
4717   "name": "PA_STEREO_CNTL",
4718   "type_ref": "PA_STEREO_CNTL"
4719  },
4720  {
4721   "chips": ["gfx103"],
4722   "map": {"at": 165956, "to": "mm"},
4723   "name": "PA_STATE_STEREO_X"
4724  },
4725  {
4726   "chips": ["gfx103"],
4727   "map": {"at": 165960, "to": "mm"},
4728   "name": "PA_CL_VRS_CNTL",
4729   "type_ref": "PA_CL_VRS_CNTL"
4730  },
4731  {
4732   "chips": ["gfx103"],
4733   "map": {"at": 166400, "to": "mm"},
4734   "name": "PA_SU_POINT_SIZE",
4735   "type_ref": "PA_SU_POINT_SIZE"
4736  },
4737  {
4738   "chips": ["gfx103"],
4739   "map": {"at": 166404, "to": "mm"},
4740   "name": "PA_SU_POINT_MINMAX",
4741   "type_ref": "PA_SU_POINT_MINMAX"
4742  },
4743  {
4744   "chips": ["gfx103"],
4745   "map": {"at": 166408, "to": "mm"},
4746   "name": "PA_SU_LINE_CNTL",
4747   "type_ref": "PA_SU_LINE_CNTL"
4748  },
4749  {
4750   "chips": ["gfx103"],
4751   "map": {"at": 166412, "to": "mm"},
4752   "name": "PA_SC_LINE_STIPPLE",
4753   "type_ref": "PA_SC_LINE_STIPPLE"
4754  },
4755  {
4756   "chips": ["gfx103"],
4757   "map": {"at": 166416, "to": "mm"},
4758   "name": "VGT_OUTPUT_PATH_CNTL",
4759   "type_ref": "VGT_OUTPUT_PATH_CNTL"
4760  },
4761  {
4762   "chips": ["gfx103"],
4763   "map": {"at": 166420, "to": "mm"},
4764   "name": "VGT_HOS_CNTL",
4765   "type_ref": "VGT_HOS_CNTL"
4766  },
4767  {
4768   "chips": ["gfx103"],
4769   "map": {"at": 166424, "to": "mm"},
4770   "name": "VGT_HOS_MAX_TESS_LEVEL"
4771  },
4772  {
4773   "chips": ["gfx103"],
4774   "map": {"at": 166428, "to": "mm"},
4775   "name": "VGT_HOS_MIN_TESS_LEVEL"
4776  },
4777  {
4778   "chips": ["gfx103"],
4779   "map": {"at": 166432, "to": "mm"},
4780   "name": "VGT_HOS_REUSE_DEPTH",
4781   "type_ref": "VGT_HOS_REUSE_DEPTH"
4782  },
4783  {
4784   "chips": ["gfx103"],
4785   "map": {"at": 166436, "to": "mm"},
4786   "name": "VGT_GROUP_PRIM_TYPE",
4787   "type_ref": "VGT_GROUP_PRIM_TYPE"
4788  },
4789  {
4790   "chips": ["gfx103"],
4791   "map": {"at": 166440, "to": "mm"},
4792   "name": "VGT_GROUP_FIRST_DECR",
4793   "type_ref": "VGT_GROUP_FIRST_DECR"
4794  },
4795  {
4796   "chips": ["gfx103"],
4797   "map": {"at": 166444, "to": "mm"},
4798   "name": "VGT_GROUP_DECR",
4799   "type_ref": "VGT_GROUP_DECR"
4800  },
4801  {
4802   "chips": ["gfx103"],
4803   "map": {"at": 166448, "to": "mm"},
4804   "name": "VGT_GROUP_VECT_0_CNTL",
4805   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4806  },
4807  {
4808   "chips": ["gfx103"],
4809   "map": {"at": 166452, "to": "mm"},
4810   "name": "VGT_GROUP_VECT_1_CNTL",
4811   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4812  },
4813  {
4814   "chips": ["gfx103"],
4815   "map": {"at": 166456, "to": "mm"},
4816   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
4817   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4818  },
4819  {
4820   "chips": ["gfx103"],
4821   "map": {"at": 166460, "to": "mm"},
4822   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
4823   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4824  },
4825  {
4826   "chips": ["gfx103"],
4827   "map": {"at": 166464, "to": "mm"},
4828   "name": "VGT_GS_MODE",
4829   "type_ref": "VGT_GS_MODE"
4830  },
4831  {
4832   "chips": ["gfx103"],
4833   "map": {"at": 166468, "to": "mm"},
4834   "name": "VGT_GS_ONCHIP_CNTL",
4835   "type_ref": "VGT_GS_ONCHIP_CNTL"
4836  },
4837  {
4838   "chips": ["gfx103"],
4839   "map": {"at": 166472, "to": "mm"},
4840   "name": "PA_SC_MODE_CNTL_0",
4841   "type_ref": "PA_SC_MODE_CNTL_0"
4842  },
4843  {
4844   "chips": ["gfx103"],
4845   "map": {"at": 166476, "to": "mm"},
4846   "name": "PA_SC_MODE_CNTL_1",
4847   "type_ref": "PA_SC_MODE_CNTL_1"
4848  },
4849  {
4850   "chips": ["gfx103"],
4851   "map": {"at": 166480, "to": "mm"},
4852   "name": "VGT_ENHANCE"
4853  },
4854  {
4855   "chips": ["gfx103"],
4856   "map": {"at": 166484, "to": "mm"},
4857   "name": "VGT_GS_PER_ES",
4858   "type_ref": "VGT_GS_PER_ES"
4859  },
4860  {
4861   "chips": ["gfx103"],
4862   "map": {"at": 166488, "to": "mm"},
4863   "name": "VGT_ES_PER_GS",
4864   "type_ref": "VGT_ES_PER_GS"
4865  },
4866  {
4867   "chips": ["gfx103"],
4868   "map": {"at": 166492, "to": "mm"},
4869   "name": "VGT_GS_PER_VS",
4870   "type_ref": "VGT_GS_PER_VS"
4871  },
4872  {
4873   "chips": ["gfx103"],
4874   "map": {"at": 166496, "to": "mm"},
4875   "name": "VGT_GSVS_RING_OFFSET_1",
4876   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4877  },
4878  {
4879   "chips": ["gfx103"],
4880   "map": {"at": 166500, "to": "mm"},
4881   "name": "VGT_GSVS_RING_OFFSET_2",
4882   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4883  },
4884  {
4885   "chips": ["gfx103"],
4886   "map": {"at": 166504, "to": "mm"},
4887   "name": "VGT_GSVS_RING_OFFSET_3",
4888   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4889  },
4890  {
4891   "chips": ["gfx103"],
4892   "map": {"at": 166508, "to": "mm"},
4893   "name": "VGT_GS_OUT_PRIM_TYPE",
4894   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
4895  },
4896  {
4897   "chips": ["gfx103"],
4898   "map": {"at": 166512, "to": "mm"},
4899   "name": "IA_ENHANCE"
4900  },
4901  {
4902   "chips": ["gfx103"],
4903   "map": {"at": 166516, "to": "mm"},
4904   "name": "VGT_DMA_SIZE"
4905  },
4906  {
4907   "chips": ["gfx103"],
4908   "map": {"at": 166520, "to": "mm"},
4909   "name": "VGT_DMA_MAX_SIZE"
4910  },
4911  {
4912   "chips": ["gfx103"],
4913   "map": {"at": 166524, "to": "mm"},
4914   "name": "VGT_DMA_INDEX_TYPE",
4915   "type_ref": "VGT_DMA_INDEX_TYPE"
4916  },
4917  {
4918   "chips": ["gfx103"],
4919   "map": {"at": 166528, "to": "mm"},
4920   "name": "WD_ENHANCE"
4921  },
4922  {
4923   "chips": ["gfx103"],
4924   "map": {"at": 166532, "to": "mm"},
4925   "name": "VGT_PRIMITIVEID_EN",
4926   "type_ref": "VGT_PRIMITIVEID_EN"
4927  },
4928  {
4929   "chips": ["gfx103"],
4930   "map": {"at": 166536, "to": "mm"},
4931   "name": "VGT_DMA_NUM_INSTANCES"
4932  },
4933  {
4934   "chips": ["gfx103"],
4935   "map": {"at": 166540, "to": "mm"},
4936   "name": "VGT_PRIMITIVEID_RESET"
4937  },
4938  {
4939   "chips": ["gfx103"],
4940   "map": {"at": 166544, "to": "mm"},
4941   "name": "VGT_EVENT_INITIATOR",
4942   "type_ref": "VGT_EVENT_INITIATOR"
4943  },
4944  {
4945   "chips": ["gfx103"],
4946   "map": {"at": 166548, "to": "mm"},
4947   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
4948   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
4949  },
4950  {
4951   "chips": ["gfx103"],
4952   "map": {"at": 166552, "to": "mm"},
4953   "name": "VGT_DRAW_PAYLOAD_CNTL",
4954   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
4955  },
4956  {
4957   "chips": ["gfx103"],
4958   "map": {"at": 166560, "to": "mm"},
4959   "name": "VGT_INSTANCE_STEP_RATE_0"
4960  },
4961  {
4962   "chips": ["gfx103"],
4963   "map": {"at": 166564, "to": "mm"},
4964   "name": "VGT_INSTANCE_STEP_RATE_1"
4965  },
4966  {
4967   "chips": ["gfx103"],
4968   "map": {"at": 166568, "to": "mm"},
4969   "name": "IA_MULTI_VGT_PARAM",
4970   "type_ref": "IA_MULTI_VGT_PARAM"
4971  },
4972  {
4973   "chips": ["gfx103"],
4974   "map": {"at": 166572, "to": "mm"},
4975   "name": "VGT_ESGS_RING_ITEMSIZE",
4976   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
4977  },
4978  {
4979   "chips": ["gfx103"],
4980   "map": {"at": 166576, "to": "mm"},
4981   "name": "VGT_GSVS_RING_ITEMSIZE",
4982   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
4983  },
4984  {
4985   "chips": ["gfx103"],
4986   "map": {"at": 166580, "to": "mm"},
4987   "name": "VGT_REUSE_OFF",
4988   "type_ref": "VGT_REUSE_OFF"
4989  },
4990  {
4991   "chips": ["gfx103"],
4992   "map": {"at": 166584, "to": "mm"},
4993   "name": "VGT_VTX_CNT_EN",
4994   "type_ref": "VGT_VTX_CNT_EN"
4995  },
4996  {
4997   "chips": ["gfx103"],
4998   "map": {"at": 166588, "to": "mm"},
4999   "name": "DB_HTILE_SURFACE",
5000   "type_ref": "DB_HTILE_SURFACE"
5001  },
5002  {
5003   "chips": ["gfx103"],
5004   "map": {"at": 166592, "to": "mm"},
5005   "name": "DB_SRESULTS_COMPARE_STATE0",
5006   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5007  },
5008  {
5009   "chips": ["gfx103"],
5010   "map": {"at": 166596, "to": "mm"},
5011   "name": "DB_SRESULTS_COMPARE_STATE1",
5012   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5013  },
5014  {
5015   "chips": ["gfx103"],
5016   "map": {"at": 166600, "to": "mm"},
5017   "name": "DB_PRELOAD_CONTROL",
5018   "type_ref": "DB_PRELOAD_CONTROL"
5019  },
5020  {
5021   "chips": ["gfx103"],
5022   "map": {"at": 166608, "to": "mm"},
5023   "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5024  },
5025  {
5026   "chips": ["gfx103"],
5027   "map": {"at": 166612, "to": "mm"},
5028   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5029   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5030  },
5031  {
5032   "chips": ["gfx103"],
5033   "map": {"at": 166620, "to": "mm"},
5034   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5035  },
5036  {
5037   "chips": ["gfx103"],
5038   "map": {"at": 166624, "to": "mm"},
5039   "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5040  },
5041  {
5042   "chips": ["gfx103"],
5043   "map": {"at": 166628, "to": "mm"},
5044   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5045   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5046  },
5047  {
5048   "chips": ["gfx103"],
5049   "map": {"at": 166636, "to": "mm"},
5050   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5051  },
5052  {
5053   "chips": ["gfx103"],
5054   "map": {"at": 166640, "to": "mm"},
5055   "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5056  },
5057  {
5058   "chips": ["gfx103"],
5059   "map": {"at": 166644, "to": "mm"},
5060   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5061   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5062  },
5063  {
5064   "chips": ["gfx103"],
5065   "map": {"at": 166652, "to": "mm"},
5066   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5067  },
5068  {
5069   "chips": ["gfx103"],
5070   "map": {"at": 166656, "to": "mm"},
5071   "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5072  },
5073  {
5074   "chips": ["gfx103"],
5075   "map": {"at": 166660, "to": "mm"},
5076   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5077   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5078  },
5079  {
5080   "chips": ["gfx103"],
5081   "map": {"at": 166668, "to": "mm"},
5082   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5083  },
5084  {
5085   "chips": ["gfx103"],
5086   "map": {"at": 166696, "to": "mm"},
5087   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5088  },
5089  {
5090   "chips": ["gfx103"],
5091   "map": {"at": 166700, "to": "mm"},
5092   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5093  },
5094  {
5095   "chips": ["gfx103"],
5096   "map": {"at": 166704, "to": "mm"},
5097   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5098   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5099  },
5100  {
5101   "chips": ["gfx103"],
5102   "map": {"at": 166712, "to": "mm"},
5103   "name": "VGT_GS_MAX_VERT_OUT",
5104   "type_ref": "VGT_GS_MAX_VERT_OUT"
5105  },
5106  {
5107   "chips": ["gfx103"],
5108   "map": {"at": 166732, "to": "mm"},
5109   "name": "GE_NGG_SUBGRP_CNTL",
5110   "type_ref": "GE_NGG_SUBGRP_CNTL"
5111  },
5112  {
5113   "chips": ["gfx103"],
5114   "map": {"at": 166736, "to": "mm"},
5115   "name": "VGT_TESS_DISTRIBUTION",
5116   "type_ref": "VGT_TESS_DISTRIBUTION"
5117  },
5118  {
5119   "chips": ["gfx103"],
5120   "map": {"at": 166740, "to": "mm"},
5121   "name": "VGT_SHADER_STAGES_EN",
5122   "type_ref": "VGT_SHADER_STAGES_EN"
5123  },
5124  {
5125   "chips": ["gfx103"],
5126   "map": {"at": 166744, "to": "mm"},
5127   "name": "VGT_LS_HS_CONFIG",
5128   "type_ref": "VGT_LS_HS_CONFIG"
5129  },
5130  {
5131   "chips": ["gfx103"],
5132   "map": {"at": 166748, "to": "mm"},
5133   "name": "VGT_GS_VERT_ITEMSIZE",
5134   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5135  },
5136  {
5137   "chips": ["gfx103"],
5138   "map": {"at": 166752, "to": "mm"},
5139   "name": "VGT_GS_VERT_ITEMSIZE_1",
5140   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5141  },
5142  {
5143   "chips": ["gfx103"],
5144   "map": {"at": 166756, "to": "mm"},
5145   "name": "VGT_GS_VERT_ITEMSIZE_2",
5146   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5147  },
5148  {
5149   "chips": ["gfx103"],
5150   "map": {"at": 166760, "to": "mm"},
5151   "name": "VGT_GS_VERT_ITEMSIZE_3",
5152   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5153  },
5154  {
5155   "chips": ["gfx103"],
5156   "map": {"at": 166764, "to": "mm"},
5157   "name": "VGT_TF_PARAM",
5158   "type_ref": "VGT_TF_PARAM"
5159  },
5160  {
5161   "chips": ["gfx103"],
5162   "map": {"at": 166768, "to": "mm"},
5163   "name": "DB_ALPHA_TO_MASK",
5164   "type_ref": "DB_ALPHA_TO_MASK"
5165  },
5166  {
5167   "chips": ["gfx103"],
5168   "map": {"at": 166772, "to": "mm"},
5169   "name": "VGT_DISPATCH_DRAW_INDEX"
5170  },
5171  {
5172   "chips": ["gfx103"],
5173   "map": {"at": 166776, "to": "mm"},
5174   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5175   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5176  },
5177  {
5178   "chips": ["gfx103"],
5179   "map": {"at": 166780, "to": "mm"},
5180   "name": "PA_SU_POLY_OFFSET_CLAMP"
5181  },
5182  {
5183   "chips": ["gfx103"],
5184   "map": {"at": 166784, "to": "mm"},
5185   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5186  },
5187  {
5188   "chips": ["gfx103"],
5189   "map": {"at": 166788, "to": "mm"},
5190   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5191  },
5192  {
5193   "chips": ["gfx103"],
5194   "map": {"at": 166792, "to": "mm"},
5195   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5196  },
5197  {
5198   "chips": ["gfx103"],
5199   "map": {"at": 166796, "to": "mm"},
5200   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5201  },
5202  {
5203   "chips": ["gfx103"],
5204   "map": {"at": 166800, "to": "mm"},
5205   "name": "VGT_GS_INSTANCE_CNT",
5206   "type_ref": "VGT_GS_INSTANCE_CNT"
5207  },
5208  {
5209   "chips": ["gfx103"],
5210   "map": {"at": 166804, "to": "mm"},
5211   "name": "VGT_STRMOUT_CONFIG",
5212   "type_ref": "VGT_STRMOUT_CONFIG"
5213  },
5214  {
5215   "chips": ["gfx103"],
5216   "map": {"at": 166808, "to": "mm"},
5217   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5218   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5219  },
5220  {
5221   "chips": ["gfx103"],
5222   "map": {"at": 166812, "to": "mm"},
5223   "name": "VGT_DMA_EVENT_INITIATOR",
5224   "type_ref": "VGT_EVENT_INITIATOR"
5225  },
5226  {
5227   "chips": ["gfx103"],
5228   "map": {"at": 166868, "to": "mm"},
5229   "name": "PA_SC_CENTROID_PRIORITY_0",
5230   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5231  },
5232  {
5233   "chips": ["gfx103"],
5234   "map": {"at": 166872, "to": "mm"},
5235   "name": "PA_SC_CENTROID_PRIORITY_1",
5236   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5237  },
5238  {
5239   "chips": ["gfx103"],
5240   "map": {"at": 166876, "to": "mm"},
5241   "name": "PA_SC_LINE_CNTL",
5242   "type_ref": "PA_SC_LINE_CNTL"
5243  },
5244  {
5245   "chips": ["gfx103"],
5246   "map": {"at": 166880, "to": "mm"},
5247   "name": "PA_SC_AA_CONFIG",
5248   "type_ref": "PA_SC_AA_CONFIG"
5249  },
5250  {
5251   "chips": ["gfx103"],
5252   "map": {"at": 166884, "to": "mm"},
5253   "name": "PA_SU_VTX_CNTL",
5254   "type_ref": "PA_SU_VTX_CNTL"
5255  },
5256  {
5257   "chips": ["gfx103"],
5258   "map": {"at": 166888, "to": "mm"},
5259   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5260  },
5261  {
5262   "chips": ["gfx103"],
5263   "map": {"at": 166892, "to": "mm"},
5264   "name": "PA_CL_GB_VERT_DISC_ADJ"
5265  },
5266  {
5267   "chips": ["gfx103"],
5268   "map": {"at": 166896, "to": "mm"},
5269   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5270  },
5271  {
5272   "chips": ["gfx103"],
5273   "map": {"at": 166900, "to": "mm"},
5274   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5275  },
5276  {
5277   "chips": ["gfx103"],
5278   "map": {"at": 166904, "to": "mm"},
5279   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5280   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5281  },
5282  {
5283   "chips": ["gfx103"],
5284   "map": {"at": 166908, "to": "mm"},
5285   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5286   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5287  },
5288  {
5289   "chips": ["gfx103"],
5290   "map": {"at": 166912, "to": "mm"},
5291   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5292   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5293  },
5294  {
5295   "chips": ["gfx103"],
5296   "map": {"at": 166916, "to": "mm"},
5297   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5298   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5299  },
5300  {
5301   "chips": ["gfx103"],
5302   "map": {"at": 166920, "to": "mm"},
5303   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5304   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5305  },
5306  {
5307   "chips": ["gfx103"],
5308   "map": {"at": 166924, "to": "mm"},
5309   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5310   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5311  },
5312  {
5313   "chips": ["gfx103"],
5314   "map": {"at": 166928, "to": "mm"},
5315   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5316   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5317  },
5318  {
5319   "chips": ["gfx103"],
5320   "map": {"at": 166932, "to": "mm"},
5321   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5322   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5323  },
5324  {
5325   "chips": ["gfx103"],
5326   "map": {"at": 166936, "to": "mm"},
5327   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5328   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5329  },
5330  {
5331   "chips": ["gfx103"],
5332   "map": {"at": 166940, "to": "mm"},
5333   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5334   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5335  },
5336  {
5337   "chips": ["gfx103"],
5338   "map": {"at": 166944, "to": "mm"},
5339   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5340   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5341  },
5342  {
5343   "chips": ["gfx103"],
5344   "map": {"at": 166948, "to": "mm"},
5345   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5346   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5347  },
5348  {
5349   "chips": ["gfx103"],
5350   "map": {"at": 166952, "to": "mm"},
5351   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5352   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5353  },
5354  {
5355   "chips": ["gfx103"],
5356   "map": {"at": 166956, "to": "mm"},
5357   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5358   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5359  },
5360  {
5361   "chips": ["gfx103"],
5362   "map": {"at": 166960, "to": "mm"},
5363   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5364   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5365  },
5366  {
5367   "chips": ["gfx103"],
5368   "map": {"at": 166964, "to": "mm"},
5369   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5370   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5371  },
5372  {
5373   "chips": ["gfx103"],
5374   "map": {"at": 166968, "to": "mm"},
5375   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5376   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5377  },
5378  {
5379   "chips": ["gfx103"],
5380   "map": {"at": 166972, "to": "mm"},
5381   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5382   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5383  },
5384  {
5385   "chips": ["gfx103"],
5386   "map": {"at": 166976, "to": "mm"},
5387   "name": "PA_SC_SHADER_CONTROL",
5388   "type_ref": "PA_SC_SHADER_CONTROL"
5389  },
5390  {
5391   "chips": ["gfx103"],
5392   "map": {"at": 166980, "to": "mm"},
5393   "name": "PA_SC_BINNER_CNTL_0",
5394   "type_ref": "PA_SC_BINNER_CNTL_0"
5395  },
5396  {
5397   "chips": ["gfx103"],
5398   "map": {"at": 166984, "to": "mm"},
5399   "name": "PA_SC_BINNER_CNTL_1",
5400   "type_ref": "PA_SC_BINNER_CNTL_1"
5401  },
5402  {
5403   "chips": ["gfx103"],
5404   "map": {"at": 166988, "to": "mm"},
5405   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5406   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5407  },
5408  {
5409   "chips": ["gfx103"],
5410   "map": {"at": 166992, "to": "mm"},
5411   "name": "PA_SC_NGG_MODE_CNTL",
5412   "type_ref": "PA_SC_NGG_MODE_CNTL"
5413  },
5414  {
5415   "chips": ["gfx103"],
5416   "map": {"at": 167000, "to": "mm"},
5417   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5418   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5419  },
5420  {
5421   "chips": ["gfx103"],
5422   "map": {"at": 167004, "to": "mm"},
5423   "name": "VGT_OUT_DEALLOC_CNTL",
5424   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5425  },
5426  {
5427   "chips": ["gfx103"],
5428   "map": {"at": 167008, "to": "mm"},
5429   "name": "CB_COLOR0_BASE"
5430  },
5431  {
5432   "chips": ["gfx103"],
5433   "map": {"at": 167012, "to": "mm"},
5434   "name": "CB_COLOR0_PITCH",
5435   "type_ref": "CB_COLOR0_PITCH"
5436  },
5437  {
5438   "chips": ["gfx103"],
5439   "map": {"at": 167016, "to": "mm"},
5440   "name": "CB_COLOR0_SLICE",
5441   "type_ref": "CB_COLOR0_SLICE"
5442  },
5443  {
5444   "chips": ["gfx103"],
5445   "map": {"at": 167020, "to": "mm"},
5446   "name": "CB_COLOR0_VIEW",
5447   "type_ref": "CB_COLOR0_VIEW"
5448  },
5449  {
5450   "chips": ["gfx103"],
5451   "map": {"at": 167024, "to": "mm"},
5452   "name": "CB_COLOR0_INFO",
5453   "type_ref": "CB_COLOR0_INFO"
5454  },
5455  {
5456   "chips": ["gfx103"],
5457   "map": {"at": 167028, "to": "mm"},
5458   "name": "CB_COLOR0_ATTRIB",
5459   "type_ref": "CB_COLOR0_ATTRIB"
5460  },
5461  {
5462   "chips": ["gfx103"],
5463   "map": {"at": 167032, "to": "mm"},
5464   "name": "CB_COLOR0_DCC_CONTROL",
5465   "type_ref": "CB_COLOR0_DCC_CONTROL"
5466  },
5467  {
5468   "chips": ["gfx103"],
5469   "map": {"at": 167036, "to": "mm"},
5470   "name": "CB_COLOR0_CMASK"
5471  },
5472  {
5473   "chips": ["gfx103"],
5474   "map": {"at": 167040, "to": "mm"},
5475   "name": "CB_COLOR0_CMASK_SLICE",
5476   "type_ref": "CB_COLOR0_CMASK_SLICE"
5477  },
5478  {
5479   "chips": ["gfx103"],
5480   "map": {"at": 167044, "to": "mm"},
5481   "name": "CB_COLOR0_FMASK"
5482  },
5483  {
5484   "chips": ["gfx103"],
5485   "map": {"at": 167048, "to": "mm"},
5486   "name": "CB_COLOR0_FMASK_SLICE",
5487   "type_ref": "CB_COLOR0_SLICE"
5488  },
5489  {
5490   "chips": ["gfx103"],
5491   "map": {"at": 167052, "to": "mm"},
5492   "name": "CB_COLOR0_CLEAR_WORD0"
5493  },
5494  {
5495   "chips": ["gfx103"],
5496   "map": {"at": 167056, "to": "mm"},
5497   "name": "CB_COLOR0_CLEAR_WORD1"
5498  },
5499  {
5500   "chips": ["gfx103"],
5501   "map": {"at": 167060, "to": "mm"},
5502   "name": "CB_COLOR0_DCC_BASE"
5503  },
5504  {
5505   "chips": ["gfx103"],
5506   "map": {"at": 167068, "to": "mm"},
5507   "name": "CB_COLOR1_BASE"
5508  },
5509  {
5510   "chips": ["gfx103"],
5511   "map": {"at": 167072, "to": "mm"},
5512   "name": "CB_COLOR1_PITCH",
5513   "type_ref": "CB_COLOR0_PITCH"
5514  },
5515  {
5516   "chips": ["gfx103"],
5517   "map": {"at": 167076, "to": "mm"},
5518   "name": "CB_COLOR1_SLICE",
5519   "type_ref": "CB_COLOR0_SLICE"
5520  },
5521  {
5522   "chips": ["gfx103"],
5523   "map": {"at": 167080, "to": "mm"},
5524   "name": "CB_COLOR1_VIEW",
5525   "type_ref": "CB_COLOR0_VIEW"
5526  },
5527  {
5528   "chips": ["gfx103"],
5529   "map": {"at": 167084, "to": "mm"},
5530   "name": "CB_COLOR1_INFO",
5531   "type_ref": "CB_COLOR0_INFO"
5532  },
5533  {
5534   "chips": ["gfx103"],
5535   "map": {"at": 167088, "to": "mm"},
5536   "name": "CB_COLOR1_ATTRIB",
5537   "type_ref": "CB_COLOR0_ATTRIB"
5538  },
5539  {
5540   "chips": ["gfx103"],
5541   "map": {"at": 167092, "to": "mm"},
5542   "name": "CB_COLOR1_DCC_CONTROL",
5543   "type_ref": "CB_COLOR0_DCC_CONTROL"
5544  },
5545  {
5546   "chips": ["gfx103"],
5547   "map": {"at": 167096, "to": "mm"},
5548   "name": "CB_COLOR1_CMASK"
5549  },
5550  {
5551   "chips": ["gfx103"],
5552   "map": {"at": 167100, "to": "mm"},
5553   "name": "CB_COLOR1_CMASK_SLICE",
5554   "type_ref": "CB_COLOR0_CMASK_SLICE"
5555  },
5556  {
5557   "chips": ["gfx103"],
5558   "map": {"at": 167104, "to": "mm"},
5559   "name": "CB_COLOR1_FMASK"
5560  },
5561  {
5562   "chips": ["gfx103"],
5563   "map": {"at": 167108, "to": "mm"},
5564   "name": "CB_COLOR1_FMASK_SLICE",
5565   "type_ref": "CB_COLOR0_SLICE"
5566  },
5567  {
5568   "chips": ["gfx103"],
5569   "map": {"at": 167112, "to": "mm"},
5570   "name": "CB_COLOR1_CLEAR_WORD0"
5571  },
5572  {
5573   "chips": ["gfx103"],
5574   "map": {"at": 167116, "to": "mm"},
5575   "name": "CB_COLOR1_CLEAR_WORD1"
5576  },
5577  {
5578   "chips": ["gfx103"],
5579   "map": {"at": 167120, "to": "mm"},
5580   "name": "CB_COLOR1_DCC_BASE"
5581  },
5582  {
5583   "chips": ["gfx103"],
5584   "map": {"at": 167128, "to": "mm"},
5585   "name": "CB_COLOR2_BASE"
5586  },
5587  {
5588   "chips": ["gfx103"],
5589   "map": {"at": 167132, "to": "mm"},
5590   "name": "CB_COLOR2_PITCH",
5591   "type_ref": "CB_COLOR0_PITCH"
5592  },
5593  {
5594   "chips": ["gfx103"],
5595   "map": {"at": 167136, "to": "mm"},
5596   "name": "CB_COLOR2_SLICE",
5597   "type_ref": "CB_COLOR0_SLICE"
5598  },
5599  {
5600   "chips": ["gfx103"],
5601   "map": {"at": 167140, "to": "mm"},
5602   "name": "CB_COLOR2_VIEW",
5603   "type_ref": "CB_COLOR0_VIEW"
5604  },
5605  {
5606   "chips": ["gfx103"],
5607   "map": {"at": 167144, "to": "mm"},
5608   "name": "CB_COLOR2_INFO",
5609   "type_ref": "CB_COLOR0_INFO"
5610  },
5611  {
5612   "chips": ["gfx103"],
5613   "map": {"at": 167148, "to": "mm"},
5614   "name": "CB_COLOR2_ATTRIB",
5615   "type_ref": "CB_COLOR0_ATTRIB"
5616  },
5617  {
5618   "chips": ["gfx103"],
5619   "map": {"at": 167152, "to": "mm"},
5620   "name": "CB_COLOR2_DCC_CONTROL",
5621   "type_ref": "CB_COLOR0_DCC_CONTROL"
5622  },
5623  {
5624   "chips": ["gfx103"],
5625   "map": {"at": 167156, "to": "mm"},
5626   "name": "CB_COLOR2_CMASK"
5627  },
5628  {
5629   "chips": ["gfx103"],
5630   "map": {"at": 167160, "to": "mm"},
5631   "name": "CB_COLOR2_CMASK_SLICE",
5632   "type_ref": "CB_COLOR0_CMASK_SLICE"
5633  },
5634  {
5635   "chips": ["gfx103"],
5636   "map": {"at": 167164, "to": "mm"},
5637   "name": "CB_COLOR2_FMASK"
5638  },
5639  {
5640   "chips": ["gfx103"],
5641   "map": {"at": 167168, "to": "mm"},
5642   "name": "CB_COLOR2_FMASK_SLICE",
5643   "type_ref": "CB_COLOR0_SLICE"
5644  },
5645  {
5646   "chips": ["gfx103"],
5647   "map": {"at": 167172, "to": "mm"},
5648   "name": "CB_COLOR2_CLEAR_WORD0"
5649  },
5650  {
5651   "chips": ["gfx103"],
5652   "map": {"at": 167176, "to": "mm"},
5653   "name": "CB_COLOR2_CLEAR_WORD1"
5654  },
5655  {
5656   "chips": ["gfx103"],
5657   "map": {"at": 167180, "to": "mm"},
5658   "name": "CB_COLOR2_DCC_BASE"
5659  },
5660  {
5661   "chips": ["gfx103"],
5662   "map": {"at": 167188, "to": "mm"},
5663   "name": "CB_COLOR3_BASE"
5664  },
5665  {
5666   "chips": ["gfx103"],
5667   "map": {"at": 167192, "to": "mm"},
5668   "name": "CB_COLOR3_PITCH",
5669   "type_ref": "CB_COLOR0_PITCH"
5670  },
5671  {
5672   "chips": ["gfx103"],
5673   "map": {"at": 167196, "to": "mm"},
5674   "name": "CB_COLOR3_SLICE",
5675   "type_ref": "CB_COLOR0_SLICE"
5676  },
5677  {
5678   "chips": ["gfx103"],
5679   "map": {"at": 167200, "to": "mm"},
5680   "name": "CB_COLOR3_VIEW",
5681   "type_ref": "CB_COLOR0_VIEW"
5682  },
5683  {
5684   "chips": ["gfx103"],
5685   "map": {"at": 167204, "to": "mm"},
5686   "name": "CB_COLOR3_INFO",
5687   "type_ref": "CB_COLOR0_INFO"
5688  },
5689  {
5690   "chips": ["gfx103"],
5691   "map": {"at": 167208, "to": "mm"},
5692   "name": "CB_COLOR3_ATTRIB",
5693   "type_ref": "CB_COLOR0_ATTRIB"
5694  },
5695  {
5696   "chips": ["gfx103"],
5697   "map": {"at": 167212, "to": "mm"},
5698   "name": "CB_COLOR3_DCC_CONTROL",
5699   "type_ref": "CB_COLOR0_DCC_CONTROL"
5700  },
5701  {
5702   "chips": ["gfx103"],
5703   "map": {"at": 167216, "to": "mm"},
5704   "name": "CB_COLOR3_CMASK"
5705  },
5706  {
5707   "chips": ["gfx103"],
5708   "map": {"at": 167220, "to": "mm"},
5709   "name": "CB_COLOR3_CMASK_SLICE",
5710   "type_ref": "CB_COLOR0_CMASK_SLICE"
5711  },
5712  {
5713   "chips": ["gfx103"],
5714   "map": {"at": 167224, "to": "mm"},
5715   "name": "CB_COLOR3_FMASK"
5716  },
5717  {
5718   "chips": ["gfx103"],
5719   "map": {"at": 167228, "to": "mm"},
5720   "name": "CB_COLOR3_FMASK_SLICE",
5721   "type_ref": "CB_COLOR0_SLICE"
5722  },
5723  {
5724   "chips": ["gfx103"],
5725   "map": {"at": 167232, "to": "mm"},
5726   "name": "CB_COLOR3_CLEAR_WORD0"
5727  },
5728  {
5729   "chips": ["gfx103"],
5730   "map": {"at": 167236, "to": "mm"},
5731   "name": "CB_COLOR3_CLEAR_WORD1"
5732  },
5733  {
5734   "chips": ["gfx103"],
5735   "map": {"at": 167240, "to": "mm"},
5736   "name": "CB_COLOR3_DCC_BASE"
5737  },
5738  {
5739   "chips": ["gfx103"],
5740   "map": {"at": 167248, "to": "mm"},
5741   "name": "CB_COLOR4_BASE"
5742  },
5743  {
5744   "chips": ["gfx103"],
5745   "map": {"at": 167252, "to": "mm"},
5746   "name": "CB_COLOR4_PITCH",
5747   "type_ref": "CB_COLOR0_PITCH"
5748  },
5749  {
5750   "chips": ["gfx103"],
5751   "map": {"at": 167256, "to": "mm"},
5752   "name": "CB_COLOR4_SLICE",
5753   "type_ref": "CB_COLOR0_SLICE"
5754  },
5755  {
5756   "chips": ["gfx103"],
5757   "map": {"at": 167260, "to": "mm"},
5758   "name": "CB_COLOR4_VIEW",
5759   "type_ref": "CB_COLOR0_VIEW"
5760  },
5761  {
5762   "chips": ["gfx103"],
5763   "map": {"at": 167264, "to": "mm"},
5764   "name": "CB_COLOR4_INFO",
5765   "type_ref": "CB_COLOR0_INFO"
5766  },
5767  {
5768   "chips": ["gfx103"],
5769   "map": {"at": 167268, "to": "mm"},
5770   "name": "CB_COLOR4_ATTRIB",
5771   "type_ref": "CB_COLOR0_ATTRIB"
5772  },
5773  {
5774   "chips": ["gfx103"],
5775   "map": {"at": 167272, "to": "mm"},
5776   "name": "CB_COLOR4_DCC_CONTROL",
5777   "type_ref": "CB_COLOR0_DCC_CONTROL"
5778  },
5779  {
5780   "chips": ["gfx103"],
5781   "map": {"at": 167276, "to": "mm"},
5782   "name": "CB_COLOR4_CMASK"
5783  },
5784  {
5785   "chips": ["gfx103"],
5786   "map": {"at": 167280, "to": "mm"},
5787   "name": "CB_COLOR4_CMASK_SLICE",
5788   "type_ref": "CB_COLOR0_CMASK_SLICE"
5789  },
5790  {
5791   "chips": ["gfx103"],
5792   "map": {"at": 167284, "to": "mm"},
5793   "name": "CB_COLOR4_FMASK"
5794  },
5795  {
5796   "chips": ["gfx103"],
5797   "map": {"at": 167288, "to": "mm"},
5798   "name": "CB_COLOR4_FMASK_SLICE",
5799   "type_ref": "CB_COLOR0_SLICE"
5800  },
5801  {
5802   "chips": ["gfx103"],
5803   "map": {"at": 167292, "to": "mm"},
5804   "name": "CB_COLOR4_CLEAR_WORD0"
5805  },
5806  {
5807   "chips": ["gfx103"],
5808   "map": {"at": 167296, "to": "mm"},
5809   "name": "CB_COLOR4_CLEAR_WORD1"
5810  },
5811  {
5812   "chips": ["gfx103"],
5813   "map": {"at": 167300, "to": "mm"},
5814   "name": "CB_COLOR4_DCC_BASE"
5815  },
5816  {
5817   "chips": ["gfx103"],
5818   "map": {"at": 167308, "to": "mm"},
5819   "name": "CB_COLOR5_BASE"
5820  },
5821  {
5822   "chips": ["gfx103"],
5823   "map": {"at": 167312, "to": "mm"},
5824   "name": "CB_COLOR5_PITCH",
5825   "type_ref": "CB_COLOR0_PITCH"
5826  },
5827  {
5828   "chips": ["gfx103"],
5829   "map": {"at": 167316, "to": "mm"},
5830   "name": "CB_COLOR5_SLICE",
5831   "type_ref": "CB_COLOR0_SLICE"
5832  },
5833  {
5834   "chips": ["gfx103"],
5835   "map": {"at": 167320, "to": "mm"},
5836   "name": "CB_COLOR5_VIEW",
5837   "type_ref": "CB_COLOR0_VIEW"
5838  },
5839  {
5840   "chips": ["gfx103"],
5841   "map": {"at": 167324, "to": "mm"},
5842   "name": "CB_COLOR5_INFO",
5843   "type_ref": "CB_COLOR0_INFO"
5844  },
5845  {
5846   "chips": ["gfx103"],
5847   "map": {"at": 167328, "to": "mm"},
5848   "name": "CB_COLOR5_ATTRIB",
5849   "type_ref": "CB_COLOR0_ATTRIB"
5850  },
5851  {
5852   "chips": ["gfx103"],
5853   "map": {"at": 167332, "to": "mm"},
5854   "name": "CB_COLOR5_DCC_CONTROL",
5855   "type_ref": "CB_COLOR0_DCC_CONTROL"
5856  },
5857  {
5858   "chips": ["gfx103"],
5859   "map": {"at": 167336, "to": "mm"},
5860   "name": "CB_COLOR5_CMASK"
5861  },
5862  {
5863   "chips": ["gfx103"],
5864   "map": {"at": 167340, "to": "mm"},
5865   "name": "CB_COLOR5_CMASK_SLICE",
5866   "type_ref": "CB_COLOR0_CMASK_SLICE"
5867  },
5868  {
5869   "chips": ["gfx103"],
5870   "map": {"at": 167344, "to": "mm"},
5871   "name": "CB_COLOR5_FMASK"
5872  },
5873  {
5874   "chips": ["gfx103"],
5875   "map": {"at": 167348, "to": "mm"},
5876   "name": "CB_COLOR5_FMASK_SLICE",
5877   "type_ref": "CB_COLOR0_SLICE"
5878  },
5879  {
5880   "chips": ["gfx103"],
5881   "map": {"at": 167352, "to": "mm"},
5882   "name": "CB_COLOR5_CLEAR_WORD0"
5883  },
5884  {
5885   "chips": ["gfx103"],
5886   "map": {"at": 167356, "to": "mm"},
5887   "name": "CB_COLOR5_CLEAR_WORD1"
5888  },
5889  {
5890   "chips": ["gfx103"],
5891   "map": {"at": 167360, "to": "mm"},
5892   "name": "CB_COLOR5_DCC_BASE"
5893  },
5894  {
5895   "chips": ["gfx103"],
5896   "map": {"at": 167368, "to": "mm"},
5897   "name": "CB_COLOR6_BASE"
5898  },
5899  {
5900   "chips": ["gfx103"],
5901   "map": {"at": 167372, "to": "mm"},
5902   "name": "CB_COLOR6_PITCH",
5903   "type_ref": "CB_COLOR0_PITCH"
5904  },
5905  {
5906   "chips": ["gfx103"],
5907   "map": {"at": 167376, "to": "mm"},
5908   "name": "CB_COLOR6_SLICE",
5909   "type_ref": "CB_COLOR0_SLICE"
5910  },
5911  {
5912   "chips": ["gfx103"],
5913   "map": {"at": 167380, "to": "mm"},
5914   "name": "CB_COLOR6_VIEW",
5915   "type_ref": "CB_COLOR0_VIEW"
5916  },
5917  {
5918   "chips": ["gfx103"],
5919   "map": {"at": 167384, "to": "mm"},
5920   "name": "CB_COLOR6_INFO",
5921   "type_ref": "CB_COLOR0_INFO"
5922  },
5923  {
5924   "chips": ["gfx103"],
5925   "map": {"at": 167388, "to": "mm"},
5926   "name": "CB_COLOR6_ATTRIB",
5927   "type_ref": "CB_COLOR0_ATTRIB"
5928  },
5929  {
5930   "chips": ["gfx103"],
5931   "map": {"at": 167392, "to": "mm"},
5932   "name": "CB_COLOR6_DCC_CONTROL",
5933   "type_ref": "CB_COLOR0_DCC_CONTROL"
5934  },
5935  {
5936   "chips": ["gfx103"],
5937   "map": {"at": 167396, "to": "mm"},
5938   "name": "CB_COLOR6_CMASK"
5939  },
5940  {
5941   "chips": ["gfx103"],
5942   "map": {"at": 167400, "to": "mm"},
5943   "name": "CB_COLOR6_CMASK_SLICE",
5944   "type_ref": "CB_COLOR0_CMASK_SLICE"
5945  },
5946  {
5947   "chips": ["gfx103"],
5948   "map": {"at": 167404, "to": "mm"},
5949   "name": "CB_COLOR6_FMASK"
5950  },
5951  {
5952   "chips": ["gfx103"],
5953   "map": {"at": 167408, "to": "mm"},
5954   "name": "CB_COLOR6_FMASK_SLICE",
5955   "type_ref": "CB_COLOR0_SLICE"
5956  },
5957  {
5958   "chips": ["gfx103"],
5959   "map": {"at": 167412, "to": "mm"},
5960   "name": "CB_COLOR6_CLEAR_WORD0"
5961  },
5962  {
5963   "chips": ["gfx103"],
5964   "map": {"at": 167416, "to": "mm"},
5965   "name": "CB_COLOR6_CLEAR_WORD1"
5966  },
5967  {
5968   "chips": ["gfx103"],
5969   "map": {"at": 167420, "to": "mm"},
5970   "name": "CB_COLOR6_DCC_BASE"
5971  },
5972  {
5973   "chips": ["gfx103"],
5974   "map": {"at": 167428, "to": "mm"},
5975   "name": "CB_COLOR7_BASE"
5976  },
5977  {
5978   "chips": ["gfx103"],
5979   "map": {"at": 167432, "to": "mm"},
5980   "name": "CB_COLOR7_PITCH",
5981   "type_ref": "CB_COLOR0_PITCH"
5982  },
5983  {
5984   "chips": ["gfx103"],
5985   "map": {"at": 167436, "to": "mm"},
5986   "name": "CB_COLOR7_SLICE",
5987   "type_ref": "CB_COLOR0_SLICE"
5988  },
5989  {
5990   "chips": ["gfx103"],
5991   "map": {"at": 167440, "to": "mm"},
5992   "name": "CB_COLOR7_VIEW",
5993   "type_ref": "CB_COLOR0_VIEW"
5994  },
5995  {
5996   "chips": ["gfx103"],
5997   "map": {"at": 167444, "to": "mm"},
5998   "name": "CB_COLOR7_INFO",
5999   "type_ref": "CB_COLOR0_INFO"
6000  },
6001  {
6002   "chips": ["gfx103"],
6003   "map": {"at": 167448, "to": "mm"},
6004   "name": "CB_COLOR7_ATTRIB",
6005   "type_ref": "CB_COLOR0_ATTRIB"
6006  },
6007  {
6008   "chips": ["gfx103"],
6009   "map": {"at": 167452, "to": "mm"},
6010   "name": "CB_COLOR7_DCC_CONTROL",
6011   "type_ref": "CB_COLOR0_DCC_CONTROL"
6012  },
6013  {
6014   "chips": ["gfx103"],
6015   "map": {"at": 167456, "to": "mm"},
6016   "name": "CB_COLOR7_CMASK"
6017  },
6018  {
6019   "chips": ["gfx103"],
6020   "map": {"at": 167460, "to": "mm"},
6021   "name": "CB_COLOR7_CMASK_SLICE",
6022   "type_ref": "CB_COLOR0_CMASK_SLICE"
6023  },
6024  {
6025   "chips": ["gfx103"],
6026   "map": {"at": 167464, "to": "mm"},
6027   "name": "CB_COLOR7_FMASK"
6028  },
6029  {
6030   "chips": ["gfx103"],
6031   "map": {"at": 167468, "to": "mm"},
6032   "name": "CB_COLOR7_FMASK_SLICE",
6033   "type_ref": "CB_COLOR0_SLICE"
6034  },
6035  {
6036   "chips": ["gfx103"],
6037   "map": {"at": 167472, "to": "mm"},
6038   "name": "CB_COLOR7_CLEAR_WORD0"
6039  },
6040  {
6041   "chips": ["gfx103"],
6042   "map": {"at": 167476, "to": "mm"},
6043   "name": "CB_COLOR7_CLEAR_WORD1"
6044  },
6045  {
6046   "chips": ["gfx103"],
6047   "map": {"at": 167480, "to": "mm"},
6048   "name": "CB_COLOR7_DCC_BASE"
6049  },
6050  {
6051   "chips": ["gfx103"],
6052   "map": {"at": 167488, "to": "mm"},
6053   "name": "CB_COLOR0_BASE_EXT",
6054   "type_ref": "CB_COLOR0_BASE_EXT"
6055  },
6056  {
6057   "chips": ["gfx103"],
6058   "map": {"at": 167492, "to": "mm"},
6059   "name": "CB_COLOR1_BASE_EXT",
6060   "type_ref": "CB_COLOR0_BASE_EXT"
6061  },
6062  {
6063   "chips": ["gfx103"],
6064   "map": {"at": 167496, "to": "mm"},
6065   "name": "CB_COLOR2_BASE_EXT",
6066   "type_ref": "CB_COLOR0_BASE_EXT"
6067  },
6068  {
6069   "chips": ["gfx103"],
6070   "map": {"at": 167500, "to": "mm"},
6071   "name": "CB_COLOR3_BASE_EXT",
6072   "type_ref": "CB_COLOR0_BASE_EXT"
6073  },
6074  {
6075   "chips": ["gfx103"],
6076   "map": {"at": 167504, "to": "mm"},
6077   "name": "CB_COLOR4_BASE_EXT",
6078   "type_ref": "CB_COLOR0_BASE_EXT"
6079  },
6080  {
6081   "chips": ["gfx103"],
6082   "map": {"at": 167508, "to": "mm"},
6083   "name": "CB_COLOR5_BASE_EXT",
6084   "type_ref": "CB_COLOR0_BASE_EXT"
6085  },
6086  {
6087   "chips": ["gfx103"],
6088   "map": {"at": 167512, "to": "mm"},
6089   "name": "CB_COLOR6_BASE_EXT",
6090   "type_ref": "CB_COLOR0_BASE_EXT"
6091  },
6092  {
6093   "chips": ["gfx103"],
6094   "map": {"at": 167516, "to": "mm"},
6095   "name": "CB_COLOR7_BASE_EXT",
6096   "type_ref": "CB_COLOR0_BASE_EXT"
6097  },
6098  {
6099   "chips": ["gfx103"],
6100   "map": {"at": 167520, "to": "mm"},
6101   "name": "CB_COLOR0_CMASK_BASE_EXT",
6102   "type_ref": "CB_COLOR0_BASE_EXT"
6103  },
6104  {
6105   "chips": ["gfx103"],
6106   "map": {"at": 167524, "to": "mm"},
6107   "name": "CB_COLOR1_CMASK_BASE_EXT",
6108   "type_ref": "CB_COLOR0_BASE_EXT"
6109  },
6110  {
6111   "chips": ["gfx103"],
6112   "map": {"at": 167528, "to": "mm"},
6113   "name": "CB_COLOR2_CMASK_BASE_EXT",
6114   "type_ref": "CB_COLOR0_BASE_EXT"
6115  },
6116  {
6117   "chips": ["gfx103"],
6118   "map": {"at": 167532, "to": "mm"},
6119   "name": "CB_COLOR3_CMASK_BASE_EXT",
6120   "type_ref": "CB_COLOR0_BASE_EXT"
6121  },
6122  {
6123   "chips": ["gfx103"],
6124   "map": {"at": 167536, "to": "mm"},
6125   "name": "CB_COLOR4_CMASK_BASE_EXT",
6126   "type_ref": "CB_COLOR0_BASE_EXT"
6127  },
6128  {
6129   "chips": ["gfx103"],
6130   "map": {"at": 167540, "to": "mm"},
6131   "name": "CB_COLOR5_CMASK_BASE_EXT",
6132   "type_ref": "CB_COLOR0_BASE_EXT"
6133  },
6134  {
6135   "chips": ["gfx103"],
6136   "map": {"at": 167544, "to": "mm"},
6137   "name": "CB_COLOR6_CMASK_BASE_EXT",
6138   "type_ref": "CB_COLOR0_BASE_EXT"
6139  },
6140  {
6141   "chips": ["gfx103"],
6142   "map": {"at": 167548, "to": "mm"},
6143   "name": "CB_COLOR7_CMASK_BASE_EXT",
6144   "type_ref": "CB_COLOR0_BASE_EXT"
6145  },
6146  {
6147   "chips": ["gfx103"],
6148   "map": {"at": 167552, "to": "mm"},
6149   "name": "CB_COLOR0_FMASK_BASE_EXT",
6150   "type_ref": "CB_COLOR0_BASE_EXT"
6151  },
6152  {
6153   "chips": ["gfx103"],
6154   "map": {"at": 167556, "to": "mm"},
6155   "name": "CB_COLOR1_FMASK_BASE_EXT",
6156   "type_ref": "CB_COLOR0_BASE_EXT"
6157  },
6158  {
6159   "chips": ["gfx103"],
6160   "map": {"at": 167560, "to": "mm"},
6161   "name": "CB_COLOR2_FMASK_BASE_EXT",
6162   "type_ref": "CB_COLOR0_BASE_EXT"
6163  },
6164  {
6165   "chips": ["gfx103"],
6166   "map": {"at": 167564, "to": "mm"},
6167   "name": "CB_COLOR3_FMASK_BASE_EXT",
6168   "type_ref": "CB_COLOR0_BASE_EXT"
6169  },
6170  {
6171   "chips": ["gfx103"],
6172   "map": {"at": 167568, "to": "mm"},
6173   "name": "CB_COLOR4_FMASK_BASE_EXT",
6174   "type_ref": "CB_COLOR0_BASE_EXT"
6175  },
6176  {
6177   "chips": ["gfx103"],
6178   "map": {"at": 167572, "to": "mm"},
6179   "name": "CB_COLOR5_FMASK_BASE_EXT",
6180   "type_ref": "CB_COLOR0_BASE_EXT"
6181  },
6182  {
6183   "chips": ["gfx103"],
6184   "map": {"at": 167576, "to": "mm"},
6185   "name": "CB_COLOR6_FMASK_BASE_EXT",
6186   "type_ref": "CB_COLOR0_BASE_EXT"
6187  },
6188  {
6189   "chips": ["gfx103"],
6190   "map": {"at": 167580, "to": "mm"},
6191   "name": "CB_COLOR7_FMASK_BASE_EXT",
6192   "type_ref": "CB_COLOR0_BASE_EXT"
6193  },
6194  {
6195   "chips": ["gfx103"],
6196   "map": {"at": 167584, "to": "mm"},
6197   "name": "CB_COLOR0_DCC_BASE_EXT",
6198   "type_ref": "CB_COLOR0_BASE_EXT"
6199  },
6200  {
6201   "chips": ["gfx103"],
6202   "map": {"at": 167588, "to": "mm"},
6203   "name": "CB_COLOR1_DCC_BASE_EXT",
6204   "type_ref": "CB_COLOR0_BASE_EXT"
6205  },
6206  {
6207   "chips": ["gfx103"],
6208   "map": {"at": 167592, "to": "mm"},
6209   "name": "CB_COLOR2_DCC_BASE_EXT",
6210   "type_ref": "CB_COLOR0_BASE_EXT"
6211  },
6212  {
6213   "chips": ["gfx103"],
6214   "map": {"at": 167596, "to": "mm"},
6215   "name": "CB_COLOR3_DCC_BASE_EXT",
6216   "type_ref": "CB_COLOR0_BASE_EXT"
6217  },
6218  {
6219   "chips": ["gfx103"],
6220   "map": {"at": 167600, "to": "mm"},
6221   "name": "CB_COLOR4_DCC_BASE_EXT",
6222   "type_ref": "CB_COLOR0_BASE_EXT"
6223  },
6224  {
6225   "chips": ["gfx103"],
6226   "map": {"at": 167604, "to": "mm"},
6227   "name": "CB_COLOR5_DCC_BASE_EXT",
6228   "type_ref": "CB_COLOR0_BASE_EXT"
6229  },
6230  {
6231   "chips": ["gfx103"],
6232   "map": {"at": 167608, "to": "mm"},
6233   "name": "CB_COLOR6_DCC_BASE_EXT",
6234   "type_ref": "CB_COLOR0_BASE_EXT"
6235  },
6236  {
6237   "chips": ["gfx103"],
6238   "map": {"at": 167612, "to": "mm"},
6239   "name": "CB_COLOR7_DCC_BASE_EXT",
6240   "type_ref": "CB_COLOR0_BASE_EXT"
6241  },
6242  {
6243   "chips": ["gfx103"],
6244   "map": {"at": 167616, "to": "mm"},
6245   "name": "CB_COLOR0_ATTRIB2",
6246   "type_ref": "CB_COLOR0_ATTRIB2"
6247  },
6248  {
6249   "chips": ["gfx103"],
6250   "map": {"at": 167620, "to": "mm"},
6251   "name": "CB_COLOR1_ATTRIB2",
6252   "type_ref": "CB_COLOR0_ATTRIB2"
6253  },
6254  {
6255   "chips": ["gfx103"],
6256   "map": {"at": 167624, "to": "mm"},
6257   "name": "CB_COLOR2_ATTRIB2",
6258   "type_ref": "CB_COLOR0_ATTRIB2"
6259  },
6260  {
6261   "chips": ["gfx103"],
6262   "map": {"at": 167628, "to": "mm"},
6263   "name": "CB_COLOR3_ATTRIB2",
6264   "type_ref": "CB_COLOR0_ATTRIB2"
6265  },
6266  {
6267   "chips": ["gfx103"],
6268   "map": {"at": 167632, "to": "mm"},
6269   "name": "CB_COLOR4_ATTRIB2",
6270   "type_ref": "CB_COLOR0_ATTRIB2"
6271  },
6272  {
6273   "chips": ["gfx103"],
6274   "map": {"at": 167636, "to": "mm"},
6275   "name": "CB_COLOR5_ATTRIB2",
6276   "type_ref": "CB_COLOR0_ATTRIB2"
6277  },
6278  {
6279   "chips": ["gfx103"],
6280   "map": {"at": 167640, "to": "mm"},
6281   "name": "CB_COLOR6_ATTRIB2",
6282   "type_ref": "CB_COLOR0_ATTRIB2"
6283  },
6284  {
6285   "chips": ["gfx103"],
6286   "map": {"at": 167644, "to": "mm"},
6287   "name": "CB_COLOR7_ATTRIB2",
6288   "type_ref": "CB_COLOR0_ATTRIB2"
6289  },
6290  {
6291   "chips": ["gfx103"],
6292   "map": {"at": 167648, "to": "mm"},
6293   "name": "CB_COLOR0_ATTRIB3",
6294   "type_ref": "CB_COLOR0_ATTRIB3"
6295  },
6296  {
6297   "chips": ["gfx103"],
6298   "map": {"at": 167652, "to": "mm"},
6299   "name": "CB_COLOR1_ATTRIB3",
6300   "type_ref": "CB_COLOR0_ATTRIB3"
6301  },
6302  {
6303   "chips": ["gfx103"],
6304   "map": {"at": 167656, "to": "mm"},
6305   "name": "CB_COLOR2_ATTRIB3",
6306   "type_ref": "CB_COLOR0_ATTRIB3"
6307  },
6308  {
6309   "chips": ["gfx103"],
6310   "map": {"at": 167660, "to": "mm"},
6311   "name": "CB_COLOR3_ATTRIB3",
6312   "type_ref": "CB_COLOR0_ATTRIB3"
6313  },
6314  {
6315   "chips": ["gfx103"],
6316   "map": {"at": 167664, "to": "mm"},
6317   "name": "CB_COLOR4_ATTRIB3",
6318   "type_ref": "CB_COLOR0_ATTRIB3"
6319  },
6320  {
6321   "chips": ["gfx103"],
6322   "map": {"at": 167668, "to": "mm"},
6323   "name": "CB_COLOR5_ATTRIB3",
6324   "type_ref": "CB_COLOR0_ATTRIB3"
6325  },
6326  {
6327   "chips": ["gfx103"],
6328   "map": {"at": 167672, "to": "mm"},
6329   "name": "CB_COLOR6_ATTRIB3",
6330   "type_ref": "CB_COLOR0_ATTRIB3"
6331  },
6332  {
6333   "chips": ["gfx103"],
6334   "map": {"at": 167676, "to": "mm"},
6335   "name": "CB_COLOR7_ATTRIB3",
6336   "type_ref": "CB_COLOR0_ATTRIB3"
6337  },
6338  {
6339   "chips": ["gfx103"],
6340   "map": {"at": 196608, "to": "mm"},
6341   "name": "CP_EOP_DONE_ADDR_LO",
6342   "type_ref": "CP_EOP_DONE_ADDR_LO"
6343  },
6344  {
6345   "chips": ["gfx103"],
6346   "map": {"at": 196612, "to": "mm"},
6347   "name": "CP_EOP_DONE_ADDR_HI",
6348   "type_ref": "CP_EOP_DONE_ADDR_HI"
6349  },
6350  {
6351   "chips": ["gfx103"],
6352   "map": {"at": 196616, "to": "mm"},
6353   "name": "CP_EOP_DONE_DATA_LO"
6354  },
6355  {
6356   "chips": ["gfx103"],
6357   "map": {"at": 196620, "to": "mm"},
6358   "name": "CP_EOP_DONE_DATA_HI"
6359  },
6360  {
6361   "chips": ["gfx103"],
6362   "map": {"at": 196624, "to": "mm"},
6363   "name": "CP_EOP_LAST_FENCE_LO"
6364  },
6365  {
6366   "chips": ["gfx103"],
6367   "map": {"at": 196628, "to": "mm"},
6368   "name": "CP_EOP_LAST_FENCE_HI"
6369  },
6370  {
6371   "chips": ["gfx103"],
6372   "map": {"at": 196632, "to": "mm"},
6373   "name": "CP_STREAM_OUT_ADDR_LO",
6374   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6375  },
6376  {
6377   "chips": ["gfx103"],
6378   "map": {"at": 196636, "to": "mm"},
6379   "name": "CP_STREAM_OUT_ADDR_HI",
6380   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6381  },
6382  {
6383   "chips": ["gfx103"],
6384   "map": {"at": 196640, "to": "mm"},
6385   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6386  },
6387  {
6388   "chips": ["gfx103"],
6389   "map": {"at": 196644, "to": "mm"},
6390   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6391  },
6392  {
6393   "chips": ["gfx103"],
6394   "map": {"at": 196648, "to": "mm"},
6395   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6396  },
6397  {
6398   "chips": ["gfx103"],
6399   "map": {"at": 196652, "to": "mm"},
6400   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6401  },
6402  {
6403   "chips": ["gfx103"],
6404   "map": {"at": 196656, "to": "mm"},
6405   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6406  },
6407  {
6408   "chips": ["gfx103"],
6409   "map": {"at": 196660, "to": "mm"},
6410   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6411  },
6412  {
6413   "chips": ["gfx103"],
6414   "map": {"at": 196664, "to": "mm"},
6415   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6416  },
6417  {
6418   "chips": ["gfx103"],
6419   "map": {"at": 196668, "to": "mm"},
6420   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6421  },
6422  {
6423   "chips": ["gfx103"],
6424   "map": {"at": 196672, "to": "mm"},
6425   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6426  },
6427  {
6428   "chips": ["gfx103"],
6429   "map": {"at": 196676, "to": "mm"},
6430   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6431  },
6432  {
6433   "chips": ["gfx103"],
6434   "map": {"at": 196680, "to": "mm"},
6435   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6436  },
6437  {
6438   "chips": ["gfx103"],
6439   "map": {"at": 196684, "to": "mm"},
6440   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6441  },
6442  {
6443   "chips": ["gfx103"],
6444   "map": {"at": 196688, "to": "mm"},
6445   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6446  },
6447  {
6448   "chips": ["gfx103"],
6449   "map": {"at": 196692, "to": "mm"},
6450   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6451  },
6452  {
6453   "chips": ["gfx103"],
6454   "map": {"at": 196696, "to": "mm"},
6455   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6456  },
6457  {
6458   "chips": ["gfx103"],
6459   "map": {"at": 196700, "to": "mm"},
6460   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6461  },
6462  {
6463   "chips": ["gfx103"],
6464   "map": {"at": 196704, "to": "mm"},
6465   "name": "CP_PIPE_STATS_ADDR_LO",
6466   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6467  },
6468  {
6469   "chips": ["gfx103"],
6470   "map": {"at": 196708, "to": "mm"},
6471   "name": "CP_PIPE_STATS_ADDR_HI",
6472   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6473  },
6474  {
6475   "chips": ["gfx103"],
6476   "map": {"at": 196712, "to": "mm"},
6477   "name": "CP_VGT_IAVERT_COUNT_LO"
6478  },
6479  {
6480   "chips": ["gfx103"],
6481   "map": {"at": 196716, "to": "mm"},
6482   "name": "CP_VGT_IAVERT_COUNT_HI"
6483  },
6484  {
6485   "chips": ["gfx103"],
6486   "map": {"at": 196720, "to": "mm"},
6487   "name": "CP_VGT_IAPRIM_COUNT_LO"
6488  },
6489  {
6490   "chips": ["gfx103"],
6491   "map": {"at": 196724, "to": "mm"},
6492   "name": "CP_VGT_IAPRIM_COUNT_HI"
6493  },
6494  {
6495   "chips": ["gfx103"],
6496   "map": {"at": 196728, "to": "mm"},
6497   "name": "CP_VGT_GSPRIM_COUNT_LO"
6498  },
6499  {
6500   "chips": ["gfx103"],
6501   "map": {"at": 196732, "to": "mm"},
6502   "name": "CP_VGT_GSPRIM_COUNT_HI"
6503  },
6504  {
6505   "chips": ["gfx103"],
6506   "map": {"at": 196736, "to": "mm"},
6507   "name": "CP_VGT_VSINVOC_COUNT_LO"
6508  },
6509  {
6510   "chips": ["gfx103"],
6511   "map": {"at": 196740, "to": "mm"},
6512   "name": "CP_VGT_VSINVOC_COUNT_HI"
6513  },
6514  {
6515   "chips": ["gfx103"],
6516   "map": {"at": 196744, "to": "mm"},
6517   "name": "CP_VGT_GSINVOC_COUNT_LO"
6518  },
6519  {
6520   "chips": ["gfx103"],
6521   "map": {"at": 196748, "to": "mm"},
6522   "name": "CP_VGT_GSINVOC_COUNT_HI"
6523  },
6524  {
6525   "chips": ["gfx103"],
6526   "map": {"at": 196752, "to": "mm"},
6527   "name": "CP_VGT_HSINVOC_COUNT_LO"
6528  },
6529  {
6530   "chips": ["gfx103"],
6531   "map": {"at": 196756, "to": "mm"},
6532   "name": "CP_VGT_HSINVOC_COUNT_HI"
6533  },
6534  {
6535   "chips": ["gfx103"],
6536   "map": {"at": 196760, "to": "mm"},
6537   "name": "CP_VGT_DSINVOC_COUNT_LO"
6538  },
6539  {
6540   "chips": ["gfx103"],
6541   "map": {"at": 196764, "to": "mm"},
6542   "name": "CP_VGT_DSINVOC_COUNT_HI"
6543  },
6544  {
6545   "chips": ["gfx103"],
6546   "map": {"at": 196768, "to": "mm"},
6547   "name": "CP_PA_CINVOC_COUNT_LO"
6548  },
6549  {
6550   "chips": ["gfx103"],
6551   "map": {"at": 196772, "to": "mm"},
6552   "name": "CP_PA_CINVOC_COUNT_HI"
6553  },
6554  {
6555   "chips": ["gfx103"],
6556   "map": {"at": 196776, "to": "mm"},
6557   "name": "CP_PA_CPRIM_COUNT_LO"
6558  },
6559  {
6560   "chips": ["gfx103"],
6561   "map": {"at": 196780, "to": "mm"},
6562   "name": "CP_PA_CPRIM_COUNT_HI"
6563  },
6564  {
6565   "chips": ["gfx103"],
6566   "map": {"at": 196784, "to": "mm"},
6567   "name": "CP_SC_PSINVOC_COUNT0_LO"
6568  },
6569  {
6570   "chips": ["gfx103"],
6571   "map": {"at": 196788, "to": "mm"},
6572   "name": "CP_SC_PSINVOC_COUNT0_HI"
6573  },
6574  {
6575   "chips": ["gfx103"],
6576   "map": {"at": 196792, "to": "mm"},
6577   "name": "CP_SC_PSINVOC_COUNT1_LO"
6578  },
6579  {
6580   "chips": ["gfx103"],
6581   "map": {"at": 196796, "to": "mm"},
6582   "name": "CP_SC_PSINVOC_COUNT1_HI"
6583  },
6584  {
6585   "chips": ["gfx103"],
6586   "map": {"at": 196800, "to": "mm"},
6587   "name": "CP_VGT_CSINVOC_COUNT_LO"
6588  },
6589  {
6590   "chips": ["gfx103"],
6591   "map": {"at": 196804, "to": "mm"},
6592   "name": "CP_VGT_CSINVOC_COUNT_HI"
6593  },
6594  {
6595   "chips": ["gfx103"],
6596   "map": {"at": 196852, "to": "mm"},
6597   "name": "CP_PIPE_STATS_CONTROL",
6598   "type_ref": "CP_PIPE_STATS_CONTROL"
6599  },
6600  {
6601   "chips": ["gfx103"],
6602   "map": {"at": 196856, "to": "mm"},
6603   "name": "CP_STREAM_OUT_CONTROL",
6604   "type_ref": "CP_PIPE_STATS_CONTROL"
6605  },
6606  {
6607   "chips": ["gfx103"],
6608   "map": {"at": 196860, "to": "mm"},
6609   "name": "CP_STRMOUT_CNTL",
6610   "type_ref": "CP_STRMOUT_CNTL"
6611  },
6612  {
6613   "chips": ["gfx103"],
6614   "map": {"at": 196864, "to": "mm"},
6615   "name": "SCRATCH_REG0"
6616  },
6617  {
6618   "chips": ["gfx103"],
6619   "map": {"at": 196868, "to": "mm"},
6620   "name": "SCRATCH_REG1"
6621  },
6622  {
6623   "chips": ["gfx103"],
6624   "map": {"at": 196872, "to": "mm"},
6625   "name": "SCRATCH_REG2"
6626  },
6627  {
6628   "chips": ["gfx103"],
6629   "map": {"at": 196876, "to": "mm"},
6630   "name": "SCRATCH_REG3"
6631  },
6632  {
6633   "chips": ["gfx103"],
6634   "map": {"at": 196880, "to": "mm"},
6635   "name": "SCRATCH_REG4"
6636  },
6637  {
6638   "chips": ["gfx103"],
6639   "map": {"at": 196884, "to": "mm"},
6640   "name": "SCRATCH_REG5"
6641  },
6642  {
6643   "chips": ["gfx103"],
6644   "map": {"at": 196888, "to": "mm"},
6645   "name": "SCRATCH_REG6"
6646  },
6647  {
6648   "chips": ["gfx103"],
6649   "map": {"at": 196892, "to": "mm"},
6650   "name": "SCRATCH_REG7"
6651  },
6652  {
6653   "chips": ["gfx103"],
6654   "map": {"at": 196896, "to": "mm"},
6655   "name": "SCRATCH_REG_ATOMIC",
6656   "type_ref": "SCRATCH_REG_ATOMIC"
6657  },
6658  {
6659   "chips": ["gfx103"],
6660   "map": {"at": 196908, "to": "mm"},
6661   "name": "CP_APPEND_DDID_CNT",
6662   "type_ref": "COMPUTE_PGM_HI"
6663  },
6664  {
6665   "chips": ["gfx103"],
6666   "map": {"at": 196912, "to": "mm"},
6667   "name": "CP_APPEND_DATA_HI"
6668  },
6669  {
6670   "chips": ["gfx103"],
6671   "map": {"at": 196916, "to": "mm"},
6672   "name": "CP_APPEND_LAST_CS_FENCE_HI"
6673  },
6674  {
6675   "chips": ["gfx103"],
6676   "map": {"at": 196920, "to": "mm"},
6677   "name": "CP_APPEND_LAST_PS_FENCE_HI"
6678  },
6679  {
6680   "chips": ["gfx103"],
6681   "map": {"at": 196928, "to": "mm"},
6682   "name": "SCRATCH_UMSK",
6683   "type_ref": "SCRATCH_UMSK"
6684  },
6685  {
6686   "chips": ["gfx103"],
6687   "map": {"at": 196932, "to": "mm"},
6688   "name": "SCRATCH_ADDR"
6689  },
6690  {
6691   "chips": ["gfx103"],
6692   "map": {"at": 196936, "to": "mm"},
6693   "name": "CP_PFP_ATOMIC_PREOP_LO"
6694  },
6695  {
6696   "chips": ["gfx103"],
6697   "map": {"at": 196940, "to": "mm"},
6698   "name": "CP_PFP_ATOMIC_PREOP_HI"
6699  },
6700  {
6701   "chips": ["gfx103"],
6702   "map": {"at": 196944, "to": "mm"},
6703   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6704  },
6705  {
6706   "chips": ["gfx103"],
6707   "map": {"at": 196948, "to": "mm"},
6708   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6709  },
6710  {
6711   "chips": ["gfx103"],
6712   "map": {"at": 196952, "to": "mm"},
6713   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6714  },
6715  {
6716   "chips": ["gfx103"],
6717   "map": {"at": 196956, "to": "mm"},
6718   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6719  },
6720  {
6721   "chips": ["gfx103"],
6722   "map": {"at": 196960, "to": "mm"},
6723   "name": "CP_APPEND_ADDR_LO",
6724   "type_ref": "CP_APPEND_ADDR_LO"
6725  },
6726  {
6727   "chips": ["gfx103"],
6728   "map": {"at": 196964, "to": "mm"},
6729   "name": "CP_APPEND_ADDR_HI",
6730   "type_ref": "CP_APPEND_ADDR_HI"
6731  },
6732  {
6733   "chips": ["gfx103"],
6734   "map": {"at": 196968, "to": "mm"},
6735   "name": "CP_APPEND_DATA"
6736  },
6737  {
6738   "chips": ["gfx103"],
6739   "map": {"at": 196972, "to": "mm"},
6740   "name": "CP_APPEND_LAST_CS_FENCE"
6741  },
6742  {
6743   "chips": ["gfx103"],
6744   "map": {"at": 196976, "to": "mm"},
6745   "name": "CP_APPEND_LAST_PS_FENCE"
6746  },
6747  {
6748   "chips": ["gfx103"],
6749   "map": {"at": 196980, "to": "mm"},
6750   "name": "CP_ATOMIC_PREOP_LO"
6751  },
6752  {
6753   "chips": ["gfx103"],
6754   "map": {"at": 196984, "to": "mm"},
6755   "name": "CP_ATOMIC_PREOP_HI"
6756  },
6757  {
6758   "chips": ["gfx103"],
6759   "map": {"at": 196988, "to": "mm"},
6760   "name": "CP_GDS_ATOMIC0_PREOP_LO"
6761  },
6762  {
6763   "chips": ["gfx103"],
6764   "map": {"at": 196992, "to": "mm"},
6765   "name": "CP_GDS_ATOMIC0_PREOP_HI"
6766  },
6767  {
6768   "chips": ["gfx103"],
6769   "map": {"at": 196996, "to": "mm"},
6770   "name": "CP_GDS_ATOMIC1_PREOP_LO"
6771  },
6772  {
6773   "chips": ["gfx103"],
6774   "map": {"at": 197000, "to": "mm"},
6775   "name": "CP_GDS_ATOMIC1_PREOP_HI"
6776  },
6777  {
6778   "chips": ["gfx103"],
6779   "map": {"at": 197028, "to": "mm"},
6780   "name": "CP_ME_MC_WADDR_LO",
6781   "type_ref": "CP_ME_MC_WADDR_LO"
6782  },
6783  {
6784   "chips": ["gfx103"],
6785   "map": {"at": 197032, "to": "mm"},
6786   "name": "CP_ME_MC_WADDR_HI",
6787   "type_ref": "CP_ME_MC_WADDR_HI"
6788  },
6789  {
6790   "chips": ["gfx103"],
6791   "map": {"at": 197036, "to": "mm"},
6792   "name": "CP_ME_MC_WDATA_LO"
6793  },
6794  {
6795   "chips": ["gfx103"],
6796   "map": {"at": 197040, "to": "mm"},
6797   "name": "CP_ME_MC_WDATA_HI"
6798  },
6799  {
6800   "chips": ["gfx103"],
6801   "map": {"at": 197044, "to": "mm"},
6802   "name": "CP_ME_MC_RADDR_LO",
6803   "type_ref": "CP_ME_MC_RADDR_LO"
6804  },
6805  {
6806   "chips": ["gfx103"],
6807   "map": {"at": 197048, "to": "mm"},
6808   "name": "CP_ME_MC_RADDR_HI",
6809   "type_ref": "CP_ME_MC_RADDR_HI"
6810  },
6811  {
6812   "chips": ["gfx103"],
6813   "map": {"at": 197052, "to": "mm"},
6814   "name": "CP_SEM_WAIT_TIMER"
6815  },
6816  {
6817   "chips": ["gfx103"],
6818   "map": {"at": 197056, "to": "mm"},
6819   "name": "CP_SIG_SEM_ADDR_LO",
6820   "type_ref": "CP_SIG_SEM_ADDR_LO"
6821  },
6822  {
6823   "chips": ["gfx103"],
6824   "map": {"at": 197060, "to": "mm"},
6825   "name": "CP_SIG_SEM_ADDR_HI",
6826   "type_ref": "CP_SIG_SEM_ADDR_HI"
6827  },
6828  {
6829   "chips": ["gfx103"],
6830   "map": {"at": 197072, "to": "mm"},
6831   "name": "CP_WAIT_REG_MEM_TIMEOUT"
6832  },
6833  {
6834   "chips": ["gfx103"],
6835   "map": {"at": 197076, "to": "mm"},
6836   "name": "CP_WAIT_SEM_ADDR_LO",
6837   "type_ref": "CP_SIG_SEM_ADDR_LO"
6838  },
6839  {
6840   "chips": ["gfx103"],
6841   "map": {"at": 197080, "to": "mm"},
6842   "name": "CP_WAIT_SEM_ADDR_HI",
6843   "type_ref": "CP_SIG_SEM_ADDR_HI"
6844  },
6845  {
6846   "chips": ["gfx103"],
6847   "map": {"at": 197084, "to": "mm"},
6848   "name": "CP_DMA_PFP_CONTROL",
6849   "type_ref": "CP_DMA_PFP_CONTROL"
6850  },
6851  {
6852   "chips": ["gfx103"],
6853   "map": {"at": 197088, "to": "mm"},
6854   "name": "CP_DMA_ME_CONTROL",
6855   "type_ref": "CP_DMA_PFP_CONTROL"
6856  },
6857  {
6858   "chips": ["gfx103"],
6859   "map": {"at": 197092, "to": "mm"},
6860   "name": "CP_COHER_BASE_HI",
6861   "type_ref": "CP_COHER_BASE_HI"
6862  },
6863  {
6864   "chips": ["gfx103"],
6865   "map": {"at": 197100, "to": "mm"},
6866   "name": "CP_COHER_START_DELAY",
6867   "type_ref": "CP_COHER_START_DELAY"
6868  },
6869  {
6870   "chips": ["gfx103"],
6871   "map": {"at": 197104, "to": "mm"},
6872   "name": "CP_COHER_CNTL",
6873   "type_ref": "CP_COHER_CNTL"
6874  },
6875  {
6876   "chips": ["gfx103"],
6877   "map": {"at": 197108, "to": "mm"},
6878   "name": "CP_COHER_SIZE"
6879  },
6880  {
6881   "chips": ["gfx103"],
6882   "map": {"at": 197112, "to": "mm"},
6883   "name": "CP_COHER_BASE"
6884  },
6885  {
6886   "chips": ["gfx103"],
6887   "map": {"at": 197116, "to": "mm"},
6888   "name": "CP_COHER_STATUS",
6889   "type_ref": "CP_COHER_STATUS"
6890  },
6891  {
6892   "chips": ["gfx103"],
6893   "map": {"at": 197120, "to": "mm"},
6894   "name": "CP_DMA_ME_SRC_ADDR"
6895  },
6896  {
6897   "chips": ["gfx103"],
6898   "map": {"at": 197124, "to": "mm"},
6899   "name": "CP_DMA_ME_SRC_ADDR_HI",
6900   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6901  },
6902  {
6903   "chips": ["gfx103"],
6904   "map": {"at": 197128, "to": "mm"},
6905   "name": "CP_DMA_ME_DST_ADDR"
6906  },
6907  {
6908   "chips": ["gfx103"],
6909   "map": {"at": 197132, "to": "mm"},
6910   "name": "CP_DMA_ME_DST_ADDR_HI",
6911   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6912  },
6913  {
6914   "chips": ["gfx103"],
6915   "map": {"at": 197136, "to": "mm"},
6916   "name": "CP_DMA_ME_COMMAND",
6917   "type_ref": "CP_DMA_ME_COMMAND"
6918  },
6919  {
6920   "chips": ["gfx103"],
6921   "map": {"at": 197140, "to": "mm"},
6922   "name": "CP_DMA_PFP_SRC_ADDR"
6923  },
6924  {
6925   "chips": ["gfx103"],
6926   "map": {"at": 197144, "to": "mm"},
6927   "name": "CP_DMA_PFP_SRC_ADDR_HI",
6928   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6929  },
6930  {
6931   "chips": ["gfx103"],
6932   "map": {"at": 197148, "to": "mm"},
6933   "name": "CP_DMA_PFP_DST_ADDR"
6934  },
6935  {
6936   "chips": ["gfx103"],
6937   "map": {"at": 197152, "to": "mm"},
6938   "name": "CP_DMA_PFP_DST_ADDR_HI",
6939   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6940  },
6941  {
6942   "chips": ["gfx103"],
6943   "map": {"at": 197156, "to": "mm"},
6944   "name": "CP_DMA_PFP_COMMAND",
6945   "type_ref": "CP_DMA_ME_COMMAND"
6946  },
6947  {
6948   "chips": ["gfx103"],
6949   "map": {"at": 197160, "to": "mm"},
6950   "name": "CP_DMA_CNTL",
6951   "type_ref": "CP_DMA_CNTL"
6952  },
6953  {
6954   "chips": ["gfx103"],
6955   "map": {"at": 197164, "to": "mm"},
6956   "name": "CP_DMA_READ_TAGS",
6957   "type_ref": "CP_DMA_READ_TAGS"
6958  },
6959  {
6960   "chips": ["gfx103"],
6961   "map": {"at": 197168, "to": "mm"},
6962   "name": "CP_COHER_SIZE_HI",
6963   "type_ref": "CP_COHER_SIZE_HI"
6964  },
6965  {
6966   "chips": ["gfx103"],
6967   "map": {"at": 197172, "to": "mm"},
6968   "name": "CP_PFP_IB_CONTROL",
6969   "type_ref": "CP_PFP_IB_CONTROL"
6970  },
6971  {
6972   "chips": ["gfx103"],
6973   "map": {"at": 197176, "to": "mm"},
6974   "name": "CP_PFP_LOAD_CONTROL",
6975   "type_ref": "CP_PFP_LOAD_CONTROL"
6976  },
6977  {
6978   "chips": ["gfx103"],
6979   "map": {"at": 197180, "to": "mm"},
6980   "name": "CP_SCRATCH_INDEX",
6981   "type_ref": "CP_CPC_SCRATCH_INDEX"
6982  },
6983  {
6984   "chips": ["gfx103"],
6985   "map": {"at": 197184, "to": "mm"},
6986   "name": "CP_SCRATCH_DATA"
6987  },
6988  {
6989   "chips": ["gfx103"],
6990   "map": {"at": 197188, "to": "mm"},
6991   "name": "CP_RB_OFFSET",
6992   "type_ref": "CP_RB_OFFSET"
6993  },
6994  {
6995   "chips": ["gfx103"],
6996   "map": {"at": 197196, "to": "mm"},
6997   "name": "CP_IB2_OFFSET",
6998   "type_ref": "CP_IB2_OFFSET"
6999  },
7000  {
7001   "chips": ["gfx103"],
7002   "map": {"at": 197208, "to": "mm"},
7003   "name": "CP_IB2_PREAMBLE_BEGIN",
7004   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7005  },
7006  {
7007   "chips": ["gfx103"],
7008   "map": {"at": 197212, "to": "mm"},
7009   "name": "CP_IB2_PREAMBLE_END",
7010   "type_ref": "CP_IB2_PREAMBLE_END"
7011  },
7012  {
7013   "chips": ["gfx103"],
7014   "map": {"at": 197216, "to": "mm"},
7015   "name": "CP_CE_IB1_OFFSET",
7016   "type_ref": "CP_CE_IB1_OFFSET"
7017  },
7018  {
7019   "chips": ["gfx103"],
7020   "map": {"at": 197220, "to": "mm"},
7021   "name": "CP_CE_IB2_OFFSET",
7022   "type_ref": "CP_IB2_OFFSET"
7023  },
7024  {
7025   "chips": ["gfx103"],
7026   "map": {"at": 197224, "to": "mm"},
7027   "name": "CP_CE_COUNTER"
7028  },
7029  {
7030   "chips": ["gfx103"],
7031   "map": {"at": 197232, "to": "mm"},
7032   "name": "CP_DMA_ME_CMD_ADDR_LO",
7033   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7034  },
7035  {
7036   "chips": ["gfx103"],
7037   "map": {"at": 197236, "to": "mm"},
7038   "name": "CP_DMA_ME_CMD_ADDR_HI",
7039   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7040  },
7041  {
7042   "chips": ["gfx103"],
7043   "map": {"at": 197240, "to": "mm"},
7044   "name": "CP_DMA_PFP_CMD_ADDR_LO",
7045   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7046  },
7047  {
7048   "chips": ["gfx103"],
7049   "map": {"at": 197244, "to": "mm"},
7050   "name": "CP_DMA_PFP_CMD_ADDR_HI",
7051   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7052  },
7053  {
7054   "chips": ["gfx103"],
7055   "map": {"at": 197248, "to": "mm"},
7056   "name": "CP_APPEND_CMD_ADDR_LO",
7057   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7058  },
7059  {
7060   "chips": ["gfx103"],
7061   "map": {"at": 197252, "to": "mm"},
7062   "name": "CP_APPEND_CMD_ADDR_HI",
7063   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7064  },
7065  {
7066   "chips": ["gfx103"],
7067   "map": {"at": 197256, "to": "mm"},
7068   "name": "UCONFIG_RESERVED_REG0"
7069  },
7070  {
7071   "chips": ["gfx103"],
7072   "map": {"at": 197260, "to": "mm"},
7073   "name": "UCONFIG_RESERVED_REG1"
7074  },
7075  {
7076   "chips": ["gfx103"],
7077   "map": {"at": 197280, "to": "mm"},
7078   "name": "CP_CE_ATOMIC_PREOP_LO"
7079  },
7080  {
7081   "chips": ["gfx103"],
7082   "map": {"at": 197284, "to": "mm"},
7083   "name": "CP_CE_ATOMIC_PREOP_HI"
7084  },
7085  {
7086   "chips": ["gfx103"],
7087   "map": {"at": 197288, "to": "mm"},
7088   "name": "CP_CE_GDS_ATOMIC0_PREOP_LO"
7089  },
7090  {
7091   "chips": ["gfx103"],
7092   "map": {"at": 197292, "to": "mm"},
7093   "name": "CP_CE_GDS_ATOMIC0_PREOP_HI"
7094  },
7095  {
7096   "chips": ["gfx103"],
7097   "map": {"at": 197296, "to": "mm"},
7098   "name": "CP_CE_GDS_ATOMIC1_PREOP_LO"
7099  },
7100  {
7101   "chips": ["gfx103"],
7102   "map": {"at": 197300, "to": "mm"},
7103   "name": "CP_CE_GDS_ATOMIC1_PREOP_HI"
7104  },
7105  {
7106   "chips": ["gfx103"],
7107   "map": {"at": 197364, "to": "mm"},
7108   "name": "CP_CE_INIT_CMD_BUFSZ",
7109   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
7110  },
7111  {
7112   "chips": ["gfx103"],
7113   "map": {"at": 197368, "to": "mm"},
7114   "name": "CP_CE_IB1_CMD_BUFSZ",
7115   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7116  },
7117  {
7118   "chips": ["gfx103"],
7119   "map": {"at": 197372, "to": "mm"},
7120   "name": "CP_CE_IB2_CMD_BUFSZ",
7121   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7122  },
7123  {
7124   "chips": ["gfx103"],
7125   "map": {"at": 197380, "to": "mm"},
7126   "name": "CP_IB2_CMD_BUFSZ",
7127   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7128  },
7129  {
7130   "chips": ["gfx103"],
7131   "map": {"at": 197384, "to": "mm"},
7132   "name": "CP_ST_CMD_BUFSZ",
7133   "type_ref": "CP_ST_CMD_BUFSZ"
7134  },
7135  {
7136   "chips": ["gfx103"],
7137   "map": {"at": 197388, "to": "mm"},
7138   "name": "CP_CE_INIT_BASE_LO",
7139   "type_ref": "CP_CE_INIT_BASE_LO"
7140  },
7141  {
7142   "chips": ["gfx103"],
7143   "map": {"at": 197392, "to": "mm"},
7144   "name": "CP_CE_INIT_BASE_HI",
7145   "type_ref": "CP_CE_INIT_BASE_HI"
7146  },
7147  {
7148   "chips": ["gfx103"],
7149   "map": {"at": 197396, "to": "mm"},
7150   "name": "CP_CE_INIT_BUFSZ",
7151   "type_ref": "CP_CE_INIT_BUFSZ"
7152  },
7153  {
7154   "chips": ["gfx103"],
7155   "map": {"at": 197400, "to": "mm"},
7156   "name": "CP_CE_IB1_BASE_LO",
7157   "type_ref": "CP_CE_IB1_BASE_LO"
7158  },
7159  {
7160   "chips": ["gfx103"],
7161   "map": {"at": 197404, "to": "mm"},
7162   "name": "CP_CE_IB1_BASE_HI",
7163   "type_ref": "CP_CE_IB1_BASE_HI"
7164  },
7165  {
7166   "chips": ["gfx103"],
7167   "map": {"at": 197408, "to": "mm"},
7168   "name": "CP_CE_IB1_BUFSZ",
7169   "type_ref": "CP_CE_IB1_BUFSZ"
7170  },
7171  {
7172   "chips": ["gfx103"],
7173   "map": {"at": 197412, "to": "mm"},
7174   "name": "CP_CE_IB2_BASE_LO",
7175   "type_ref": "CP_CE_IB2_BASE_LO"
7176  },
7177  {
7178   "chips": ["gfx103"],
7179   "map": {"at": 197416, "to": "mm"},
7180   "name": "CP_CE_IB2_BASE_HI",
7181   "type_ref": "CP_CE_IB2_BASE_HI"
7182  },
7183  {
7184   "chips": ["gfx103"],
7185   "map": {"at": 197420, "to": "mm"},
7186   "name": "CP_CE_IB2_BUFSZ",
7187   "type_ref": "CP_CE_IB2_BUFSZ"
7188  },
7189  {
7190   "chips": ["gfx103"],
7191   "map": {"at": 197424, "to": "mm"},
7192   "name": "CP_IB1_BASE_LO",
7193   "type_ref": "CP_CE_IB1_BASE_LO"
7194  },
7195  {
7196   "chips": ["gfx103"],
7197   "map": {"at": 197428, "to": "mm"},
7198   "name": "CP_IB1_BASE_HI",
7199   "type_ref": "CP_CE_IB1_BASE_HI"
7200  },
7201  {
7202   "chips": ["gfx103"],
7203   "map": {"at": 197432, "to": "mm"},
7204   "name": "CP_IB1_BUFSZ",
7205   "type_ref": "CP_CE_IB1_BUFSZ"
7206  },
7207  {
7208   "chips": ["gfx103"],
7209   "map": {"at": 197436, "to": "mm"},
7210   "name": "CP_IB2_BASE_LO",
7211   "type_ref": "CP_CE_IB2_BASE_LO"
7212  },
7213  {
7214   "chips": ["gfx103"],
7215   "map": {"at": 197440, "to": "mm"},
7216   "name": "CP_IB2_BASE_HI",
7217   "type_ref": "CP_CE_IB2_BASE_HI"
7218  },
7219  {
7220   "chips": ["gfx103"],
7221   "map": {"at": 197444, "to": "mm"},
7222   "name": "CP_IB2_BUFSZ",
7223   "type_ref": "CP_CE_IB2_BUFSZ"
7224  },
7225  {
7226   "chips": ["gfx103"],
7227   "map": {"at": 197448, "to": "mm"},
7228   "name": "CP_ST_BASE_LO",
7229   "type_ref": "CP_ST_BASE_LO"
7230  },
7231  {
7232   "chips": ["gfx103"],
7233   "map": {"at": 197452, "to": "mm"},
7234   "name": "CP_ST_BASE_HI",
7235   "type_ref": "CP_ST_BASE_HI"
7236  },
7237  {
7238   "chips": ["gfx103"],
7239   "map": {"at": 197456, "to": "mm"},
7240   "name": "CP_ST_BUFSZ",
7241   "type_ref": "CP_ST_BUFSZ"
7242  },
7243  {
7244   "chips": ["gfx103"],
7245   "map": {"at": 197460, "to": "mm"},
7246   "name": "CP_EOP_DONE_EVENT_CNTL",
7247   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7248  },
7249  {
7250   "chips": ["gfx103"],
7251   "map": {"at": 197464, "to": "mm"},
7252   "name": "CP_EOP_DONE_DATA_CNTL",
7253   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7254  },
7255  {
7256   "chips": ["gfx103"],
7257   "map": {"at": 197468, "to": "mm"},
7258   "name": "CP_EOP_DONE_CNTX_ID"
7259  },
7260  {
7261   "chips": ["gfx103"],
7262   "map": {"at": 197472, "to": "mm"},
7263   "name": "CP_DB_BASE_LO",
7264   "type_ref": "CP_DB_BASE_LO"
7265  },
7266  {
7267   "chips": ["gfx103"],
7268   "map": {"at": 197476, "to": "mm"},
7269   "name": "CP_DB_BASE_HI",
7270   "type_ref": "CP_DB_BASE_HI"
7271  },
7272  {
7273   "chips": ["gfx103"],
7274   "map": {"at": 197480, "to": "mm"},
7275   "name": "CP_DB_BUFSZ",
7276   "type_ref": "CP_DB_BUFSZ"
7277  },
7278  {
7279   "chips": ["gfx103"],
7280   "map": {"at": 197484, "to": "mm"},
7281   "name": "CP_DB_CMD_BUFSZ",
7282   "type_ref": "CP_DB_CMD_BUFSZ"
7283  },
7284  {
7285   "chips": ["gfx103"],
7286   "map": {"at": 197488, "to": "mm"},
7287   "name": "CP_CE_DB_BASE_LO",
7288   "type_ref": "CP_DB_BASE_LO"
7289  },
7290  {
7291   "chips": ["gfx103"],
7292   "map": {"at": 197492, "to": "mm"},
7293   "name": "CP_CE_DB_BASE_HI",
7294   "type_ref": "CP_DB_BASE_HI"
7295  },
7296  {
7297   "chips": ["gfx103"],
7298   "map": {"at": 197496, "to": "mm"},
7299   "name": "CP_CE_DB_BUFSZ",
7300   "type_ref": "CP_DB_BUFSZ"
7301  },
7302  {
7303   "chips": ["gfx103"],
7304   "map": {"at": 197500, "to": "mm"},
7305   "name": "CP_CE_DB_CMD_BUFSZ",
7306   "type_ref": "CP_DB_CMD_BUFSZ"
7307  },
7308  {
7309   "chips": ["gfx103"],
7310   "map": {"at": 197552, "to": "mm"},
7311   "name": "CP_PFP_COMPLETION_STATUS",
7312   "type_ref": "CP_PFP_COMPLETION_STATUS"
7313  },
7314  {
7315   "chips": ["gfx103"],
7316   "map": {"at": 197556, "to": "mm"},
7317   "name": "CP_CE_COMPLETION_STATUS",
7318   "type_ref": "CP_PFP_COMPLETION_STATUS"
7319  },
7320  {
7321   "chips": ["gfx103"],
7322   "map": {"at": 197560, "to": "mm"},
7323   "name": "CP_PRED_NOT_VISIBLE",
7324   "type_ref": "CP_PRED_NOT_VISIBLE"
7325  },
7326  {
7327   "chips": ["gfx103"],
7328   "map": {"at": 197568, "to": "mm"},
7329   "name": "CP_PFP_METADATA_BASE_ADDR"
7330  },
7331  {
7332   "chips": ["gfx103"],
7333   "map": {"at": 197572, "to": "mm"},
7334   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7335   "type_ref": "CP_EOP_DONE_ADDR_HI"
7336  },
7337  {
7338   "chips": ["gfx103"],
7339   "map": {"at": 197576, "to": "mm"},
7340   "name": "CP_CE_METADATA_BASE_ADDR"
7341  },
7342  {
7343   "chips": ["gfx103"],
7344   "map": {"at": 197580, "to": "mm"},
7345   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7346   "type_ref": "CP_EOP_DONE_ADDR_HI"
7347  },
7348  {
7349   "chips": ["gfx103"],
7350   "map": {"at": 197584, "to": "mm"},
7351   "name": "CP_DRAW_INDX_INDR_ADDR"
7352  },
7353  {
7354   "chips": ["gfx103"],
7355   "map": {"at": 197588, "to": "mm"},
7356   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7357   "type_ref": "CP_EOP_DONE_ADDR_HI"
7358  },
7359  {
7360   "chips": ["gfx103"],
7361   "map": {"at": 197592, "to": "mm"},
7362   "name": "CP_DISPATCH_INDR_ADDR"
7363  },
7364  {
7365   "chips": ["gfx103"],
7366   "map": {"at": 197596, "to": "mm"},
7367   "name": "CP_DISPATCH_INDR_ADDR_HI",
7368   "type_ref": "CP_EOP_DONE_ADDR_HI"
7369  },
7370  {
7371   "chips": ["gfx103"],
7372   "map": {"at": 197600, "to": "mm"},
7373   "name": "CP_INDEX_BASE_ADDR"
7374  },
7375  {
7376   "chips": ["gfx103"],
7377   "map": {"at": 197604, "to": "mm"},
7378   "name": "CP_INDEX_BASE_ADDR_HI",
7379   "type_ref": "CP_EOP_DONE_ADDR_HI"
7380  },
7381  {
7382   "chips": ["gfx103"],
7383   "map": {"at": 197608, "to": "mm"},
7384   "name": "CP_INDEX_TYPE",
7385   "type_ref": "CP_INDEX_TYPE"
7386  },
7387  {
7388   "chips": ["gfx103"],
7389   "map": {"at": 197612, "to": "mm"},
7390   "name": "CP_GDS_BKUP_ADDR"
7391  },
7392  {
7393   "chips": ["gfx103"],
7394   "map": {"at": 197616, "to": "mm"},
7395   "name": "CP_GDS_BKUP_ADDR_HI",
7396   "type_ref": "CP_EOP_DONE_ADDR_HI"
7397  },
7398  {
7399   "chips": ["gfx103"],
7400   "map": {"at": 197620, "to": "mm"},
7401   "name": "CP_SAMPLE_STATUS",
7402   "type_ref": "CP_SAMPLE_STATUS"
7403  },
7404  {
7405   "chips": ["gfx103"],
7406   "map": {"at": 197624, "to": "mm"},
7407   "name": "CP_ME_COHER_CNTL",
7408   "type_ref": "CP_ME_COHER_CNTL"
7409  },
7410  {
7411   "chips": ["gfx103"],
7412   "map": {"at": 197628, "to": "mm"},
7413   "name": "CP_ME_COHER_SIZE"
7414  },
7415  {
7416   "chips": ["gfx103"],
7417   "map": {"at": 197632, "to": "mm"},
7418   "name": "CP_ME_COHER_SIZE_HI",
7419   "type_ref": "CP_COHER_SIZE_HI"
7420  },
7421  {
7422   "chips": ["gfx103"],
7423   "map": {"at": 197636, "to": "mm"},
7424   "name": "CP_ME_COHER_BASE"
7425  },
7426  {
7427   "chips": ["gfx103"],
7428   "map": {"at": 197640, "to": "mm"},
7429   "name": "CP_ME_COHER_BASE_HI",
7430   "type_ref": "CP_COHER_BASE_HI"
7431  },
7432  {
7433   "chips": ["gfx103"],
7434   "map": {"at": 197644, "to": "mm"},
7435   "name": "CP_ME_COHER_STATUS",
7436   "type_ref": "CP_ME_COHER_STATUS"
7437  },
7438  {
7439   "chips": ["gfx103"],
7440   "map": {"at": 197888, "to": "mm"},
7441   "name": "RLC_GPM_PERF_COUNT_0",
7442   "type_ref": "RLC_GPM_PERF_COUNT_0"
7443  },
7444  {
7445   "chips": ["gfx103"],
7446   "map": {"at": 197892, "to": "mm"},
7447   "name": "RLC_GPM_PERF_COUNT_1",
7448   "type_ref": "RLC_GPM_PERF_COUNT_0"
7449  },
7450  {
7451   "chips": ["gfx103"],
7452   "map": {"at": 198656, "to": "mm"},
7453   "name": "GRBM_GFX_INDEX",
7454   "type_ref": "GRBM_GFX_INDEX"
7455  },
7456  {
7457   "chips": ["gfx103"],
7458   "map": {"at": 198912, "to": "mm"},
7459   "name": "VGT_ESGS_RING_SIZE_UMD"
7460  },
7461  {
7462   "chips": ["gfx103"],
7463   "map": {"at": 198916, "to": "mm"},
7464   "name": "VGT_GSVS_RING_SIZE_UMD"
7465  },
7466  {
7467   "chips": ["gfx103"],
7468   "map": {"at": 198920, "to": "mm"},
7469   "name": "VGT_PRIMITIVE_TYPE",
7470   "type_ref": "VGT_PRIMITIVE_TYPE"
7471  },
7472  {
7473   "chips": ["gfx103"],
7474   "map": {"at": 198924, "to": "mm"},
7475   "name": "VGT_INDEX_TYPE",
7476   "type_ref": "VGT_INDEX_TYPE"
7477  },
7478  {
7479   "chips": ["gfx103"],
7480   "map": {"at": 198928, "to": "mm"},
7481   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
7482  },
7483  {
7484   "chips": ["gfx103"],
7485   "map": {"at": 198932, "to": "mm"},
7486   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
7487  },
7488  {
7489   "chips": ["gfx103"],
7490   "map": {"at": 198936, "to": "mm"},
7491   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
7492  },
7493  {
7494   "chips": ["gfx103"],
7495   "map": {"at": 198940, "to": "mm"},
7496   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
7497  },
7498  {
7499   "chips": ["gfx103"],
7500   "map": {"at": 198948, "to": "mm"},
7501   "name": "GE_MIN_VTX_INDX"
7502  },
7503  {
7504   "chips": ["gfx103"],
7505   "map": {"at": 198952, "to": "mm"},
7506   "name": "GE_INDX_OFFSET"
7507  },
7508  {
7509   "chips": ["gfx103"],
7510   "map": {"at": 198956, "to": "mm"},
7511   "name": "GE_MULTI_PRIM_IB_RESET_EN",
7512   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
7513  },
7514  {
7515   "chips": ["gfx103"],
7516   "map": {"at": 198960, "to": "mm"},
7517   "name": "VGT_NUM_INDICES"
7518  },
7519  {
7520   "chips": ["gfx103"],
7521   "map": {"at": 198964, "to": "mm"},
7522   "name": "VGT_NUM_INSTANCES"
7523  },
7524  {
7525   "chips": ["gfx103"],
7526   "map": {"at": 198968, "to": "mm"},
7527   "name": "VGT_TF_RING_SIZE_UMD",
7528   "type_ref": "VGT_TF_RING_SIZE_UMD"
7529  },
7530  {
7531   "chips": ["gfx103"],
7532   "map": {"at": 198972, "to": "mm"},
7533   "name": "VGT_HS_OFFCHIP_PARAM_UMD",
7534   "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
7535  },
7536  {
7537   "chips": ["gfx103"],
7538   "map": {"at": 198976, "to": "mm"},
7539   "name": "VGT_TF_MEMORY_BASE_UMD"
7540  },
7541  {
7542   "chips": ["gfx103"],
7543   "map": {"at": 198980, "to": "mm"},
7544   "name": "GE_DMA_FIRST_INDEX"
7545  },
7546  {
7547   "chips": ["gfx103"],
7548   "map": {"at": 198984, "to": "mm"},
7549   "name": "WD_POS_BUF_BASE"
7550  },
7551  {
7552   "chips": ["gfx103"],
7553   "map": {"at": 198988, "to": "mm"},
7554   "name": "WD_POS_BUF_BASE_HI",
7555   "type_ref": "DB_Z_READ_BASE_HI"
7556  },
7557  {
7558   "chips": ["gfx103"],
7559   "map": {"at": 198992, "to": "mm"},
7560   "name": "WD_CNTL_SB_BUF_BASE"
7561  },
7562  {
7563   "chips": ["gfx103"],
7564   "map": {"at": 198996, "to": "mm"},
7565   "name": "WD_CNTL_SB_BUF_BASE_HI",
7566   "type_ref": "DB_Z_READ_BASE_HI"
7567  },
7568  {
7569   "chips": ["gfx103"],
7570   "map": {"at": 199000, "to": "mm"},
7571   "name": "WD_INDEX_BUF_BASE"
7572  },
7573  {
7574   "chips": ["gfx103"],
7575   "map": {"at": 199004, "to": "mm"},
7576   "name": "WD_INDEX_BUF_BASE_HI",
7577   "type_ref": "DB_Z_READ_BASE_HI"
7578  },
7579  {
7580   "chips": ["gfx103"],
7581   "map": {"at": 199008, "to": "mm"},
7582   "name": "IA_MULTI_VGT_PARAM_PIPED",
7583   "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
7584  },
7585  {
7586   "chips": ["gfx103"],
7587   "map": {"at": 199012, "to": "mm"},
7588   "name": "GE_MAX_VTX_INDX"
7589  },
7590  {
7591   "chips": ["gfx103"],
7592   "map": {"at": 199016, "to": "mm"},
7593   "name": "VGT_INSTANCE_BASE_ID"
7594  },
7595  {
7596   "chips": ["gfx103"],
7597   "map": {"at": 199020, "to": "mm"},
7598   "name": "GE_CNTL",
7599   "type_ref": "GE_CNTL"
7600  },
7601  {
7602   "chips": ["gfx103"],
7603   "map": {"at": 199024, "to": "mm"},
7604   "name": "GE_USER_VGPR1"
7605  },
7606  {
7607   "chips": ["gfx103"],
7608   "map": {"at": 199028, "to": "mm"},
7609   "name": "GE_USER_VGPR2"
7610  },
7611  {
7612   "chips": ["gfx103"],
7613   "map": {"at": 199032, "to": "mm"},
7614   "name": "GE_USER_VGPR3"
7615  },
7616  {
7617   "chips": ["gfx103"],
7618   "map": {"at": 199036, "to": "mm"},
7619   "name": "GE_STEREO_CNTL",
7620   "type_ref": "GE_STEREO_CNTL"
7621  },
7622  {
7623   "chips": ["gfx103"],
7624   "map": {"at": 199040, "to": "mm"},
7625   "name": "GE_PC_ALLOC",
7626   "type_ref": "GE_PC_ALLOC"
7627  },
7628  {
7629   "chips": ["gfx103"],
7630   "map": {"at": 199044, "to": "mm"},
7631   "name": "VGT_TF_MEMORY_BASE_HI_UMD",
7632   "type_ref": "DB_Z_READ_BASE_HI"
7633  },
7634  {
7635   "chips": ["gfx103"],
7636   "map": {"at": 199048, "to": "mm"},
7637   "name": "GE_USER_VGPR_EN",
7638   "type_ref": "GE_USER_VGPR_EN"
7639  },
7640  {
7641   "chips": ["gfx103"],
7642   "map": {"at": 199168, "to": "mm"},
7643   "name": "PA_SU_LINE_STIPPLE_VALUE",
7644   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
7645  },
7646  {
7647   "chips": ["gfx103"],
7648   "map": {"at": 199172, "to": "mm"},
7649   "name": "PA_SC_LINE_STIPPLE_STATE",
7650   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
7651  },
7652  {
7653   "chips": ["gfx103"],
7654   "map": {"at": 199184, "to": "mm"},
7655   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
7656   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7657  },
7658  {
7659   "chips": ["gfx103"],
7660   "map": {"at": 199188, "to": "mm"},
7661   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
7662   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7663  },
7664  {
7665   "chips": ["gfx103"],
7666   "map": {"at": 199192, "to": "mm"},
7667   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
7668   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7669  },
7670  {
7671   "chips": ["gfx103"],
7672   "map": {"at": 199212, "to": "mm"},
7673   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
7674   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7675  },
7676  {
7677   "chips": ["gfx103"],
7678   "map": {"at": 199296, "to": "mm"},
7679   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
7680   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7681  },
7682  {
7683   "chips": ["gfx103"],
7684   "map": {"at": 199300, "to": "mm"},
7685   "name": "PA_SC_P3D_TRAP_SCREEN_H",
7686   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7687  },
7688  {
7689   "chips": ["gfx103"],
7690   "map": {"at": 199304, "to": "mm"},
7691   "name": "PA_SC_P3D_TRAP_SCREEN_V",
7692   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7693  },
7694  {
7695   "chips": ["gfx103"],
7696   "map": {"at": 199308, "to": "mm"},
7697   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
7698   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7699  },
7700  {
7701   "chips": ["gfx103"],
7702   "map": {"at": 199312, "to": "mm"},
7703   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
7704   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7705  },
7706  {
7707   "chips": ["gfx103"],
7708   "map": {"at": 199328, "to": "mm"},
7709   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
7710   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7711  },
7712  {
7713   "chips": ["gfx103"],
7714   "map": {"at": 199332, "to": "mm"},
7715   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
7716   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7717  },
7718  {
7719   "chips": ["gfx103"],
7720   "map": {"at": 199336, "to": "mm"},
7721   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
7722   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7723  },
7724  {
7725   "chips": ["gfx103"],
7726   "map": {"at": 199340, "to": "mm"},
7727   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
7728   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7729  },
7730  {
7731   "chips": ["gfx103"],
7732   "map": {"at": 199344, "to": "mm"},
7733   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
7734   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7735  },
7736  {
7737   "chips": ["gfx103"],
7738   "map": {"at": 199360, "to": "mm"},
7739   "name": "PA_SC_TRAP_SCREEN_HV_EN",
7740   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7741  },
7742  {
7743   "chips": ["gfx103"],
7744   "map": {"at": 199364, "to": "mm"},
7745   "name": "PA_SC_TRAP_SCREEN_H",
7746   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7747  },
7748  {
7749   "chips": ["gfx103"],
7750   "map": {"at": 199368, "to": "mm"},
7751   "name": "PA_SC_TRAP_SCREEN_V",
7752   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7753  },
7754  {
7755   "chips": ["gfx103"],
7756   "map": {"at": 199372, "to": "mm"},
7757   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
7758   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7759  },
7760  {
7761   "chips": ["gfx103"],
7762   "map": {"at": 199376, "to": "mm"},
7763   "name": "PA_SC_TRAP_SCREEN_COUNT",
7764   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7765  },
7766  {
7767   "chips": ["gfx103"],
7768   "map": {"at": 199936, "to": "mm"},
7769   "name": "SQ_THREAD_TRACE_USERDATA_0"
7770  },
7771  {
7772   "chips": ["gfx103"],
7773   "map": {"at": 199940, "to": "mm"},
7774   "name": "SQ_THREAD_TRACE_USERDATA_1"
7775  },
7776  {
7777   "chips": ["gfx103"],
7778   "map": {"at": 199944, "to": "mm"},
7779   "name": "SQ_THREAD_TRACE_USERDATA_2"
7780  },
7781  {
7782   "chips": ["gfx103"],
7783   "map": {"at": 199948, "to": "mm"},
7784   "name": "SQ_THREAD_TRACE_USERDATA_3"
7785  },
7786  {
7787   "chips": ["gfx103"],
7788   "map": {"at": 199952, "to": "mm"},
7789   "name": "SQ_THREAD_TRACE_USERDATA_4"
7790  },
7791  {
7792   "chips": ["gfx103"],
7793   "map": {"at": 199956, "to": "mm"},
7794   "name": "SQ_THREAD_TRACE_USERDATA_5"
7795  },
7796  {
7797   "chips": ["gfx103"],
7798   "map": {"at": 199960, "to": "mm"},
7799   "name": "SQ_THREAD_TRACE_USERDATA_6"
7800  },
7801  {
7802   "chips": ["gfx103"],
7803   "map": {"at": 199964, "to": "mm"},
7804   "name": "SQ_THREAD_TRACE_USERDATA_7"
7805  },
7806  {
7807   "chips": ["gfx103"],
7808   "map": {"at": 199968, "to": "mm"},
7809   "name": "SQC_CACHES",
7810   "type_ref": "SQC_CACHES"
7811  },
7812  {
7813   "chips": ["gfx103"],
7814   "map": {"at": 200192, "to": "mm"},
7815   "name": "TA_CS_BC_BASE_ADDR"
7816  },
7817  {
7818   "chips": ["gfx103"],
7819   "map": {"at": 200196, "to": "mm"},
7820   "name": "TA_CS_BC_BASE_ADDR_HI",
7821   "type_ref": "TA_BC_BASE_ADDR_HI"
7822  },
7823  {
7824   "chips": ["gfx103"],
7825   "map": {"at": 200448, "to": "mm"},
7826   "name": "DB_OCCLUSION_COUNT0_LOW"
7827  },
7828  {
7829   "chips": ["gfx103"],
7830   "map": {"at": 200452, "to": "mm"},
7831   "name": "DB_OCCLUSION_COUNT0_HI",
7832   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7833  },
7834  {
7835   "chips": ["gfx103"],
7836   "map": {"at": 200456, "to": "mm"},
7837   "name": "DB_OCCLUSION_COUNT1_LOW"
7838  },
7839  {
7840   "chips": ["gfx103"],
7841   "map": {"at": 200460, "to": "mm"},
7842   "name": "DB_OCCLUSION_COUNT1_HI",
7843   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7844  },
7845  {
7846   "chips": ["gfx103"],
7847   "map": {"at": 200464, "to": "mm"},
7848   "name": "DB_OCCLUSION_COUNT2_LOW"
7849  },
7850  {
7851   "chips": ["gfx103"],
7852   "map": {"at": 200468, "to": "mm"},
7853   "name": "DB_OCCLUSION_COUNT2_HI",
7854   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7855  },
7856  {
7857   "chips": ["gfx103"],
7858   "map": {"at": 200472, "to": "mm"},
7859   "name": "DB_OCCLUSION_COUNT3_LOW"
7860  },
7861  {
7862   "chips": ["gfx103"],
7863   "map": {"at": 200476, "to": "mm"},
7864   "name": "DB_OCCLUSION_COUNT3_HI",
7865   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7866  },
7867  {
7868   "chips": ["gfx103"],
7869   "map": {"at": 200696, "to": "mm"},
7870   "name": "DB_ZPASS_COUNT_LOW"
7871  },
7872  {
7873   "chips": ["gfx103"],
7874   "map": {"at": 200700, "to": "mm"},
7875   "name": "DB_ZPASS_COUNT_HI",
7876   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7877  },
7878  {
7879   "chips": ["gfx103"],
7880   "map": {"at": 200704, "to": "mm"},
7881   "name": "GDS_RD_ADDR"
7882  },
7883  {
7884   "chips": ["gfx103"],
7885   "map": {"at": 200708, "to": "mm"},
7886   "name": "GDS_RD_DATA"
7887  },
7888  {
7889   "chips": ["gfx103"],
7890   "map": {"at": 200712, "to": "mm"},
7891   "name": "GDS_RD_BURST_ADDR"
7892  },
7893  {
7894   "chips": ["gfx103"],
7895   "map": {"at": 200716, "to": "mm"},
7896   "name": "GDS_RD_BURST_COUNT"
7897  },
7898  {
7899   "chips": ["gfx103"],
7900   "map": {"at": 200720, "to": "mm"},
7901   "name": "GDS_RD_BURST_DATA"
7902  },
7903  {
7904   "chips": ["gfx103"],
7905   "map": {"at": 200724, "to": "mm"},
7906   "name": "GDS_WR_ADDR"
7907  },
7908  {
7909   "chips": ["gfx103"],
7910   "map": {"at": 200728, "to": "mm"},
7911   "name": "GDS_WR_DATA"
7912  },
7913  {
7914   "chips": ["gfx103"],
7915   "map": {"at": 200732, "to": "mm"},
7916   "name": "GDS_WR_BURST_ADDR"
7917  },
7918  {
7919   "chips": ["gfx103"],
7920   "map": {"at": 200736, "to": "mm"},
7921   "name": "GDS_WR_BURST_DATA"
7922  },
7923  {
7924   "chips": ["gfx103"],
7925   "map": {"at": 200740, "to": "mm"},
7926   "name": "GDS_WRITE_COMPLETE"
7927  },
7928  {
7929   "chips": ["gfx103"],
7930   "map": {"at": 200744, "to": "mm"},
7931   "name": "GDS_ATOM_CNTL",
7932   "type_ref": "GDS_ATOM_CNTL"
7933  },
7934  {
7935   "chips": ["gfx103"],
7936   "map": {"at": 200748, "to": "mm"},
7937   "name": "GDS_ATOM_COMPLETE",
7938   "type_ref": "GDS_ATOM_COMPLETE"
7939  },
7940  {
7941   "chips": ["gfx103"],
7942   "map": {"at": 200752, "to": "mm"},
7943   "name": "GDS_ATOM_BASE",
7944   "type_ref": "GDS_ATOM_BASE"
7945  },
7946  {
7947   "chips": ["gfx103"],
7948   "map": {"at": 200756, "to": "mm"},
7949   "name": "GDS_ATOM_SIZE",
7950   "type_ref": "GDS_ATOM_SIZE"
7951  },
7952  {
7953   "chips": ["gfx103"],
7954   "map": {"at": 200760, "to": "mm"},
7955   "name": "GDS_ATOM_OFFSET0",
7956   "type_ref": "GDS_ATOM_OFFSET0"
7957  },
7958  {
7959   "chips": ["gfx103"],
7960   "map": {"at": 200764, "to": "mm"},
7961   "name": "GDS_ATOM_OFFSET1",
7962   "type_ref": "GDS_ATOM_OFFSET1"
7963  },
7964  {
7965   "chips": ["gfx103"],
7966   "map": {"at": 200768, "to": "mm"},
7967   "name": "GDS_ATOM_DST"
7968  },
7969  {
7970   "chips": ["gfx103"],
7971   "map": {"at": 200772, "to": "mm"},
7972   "name": "GDS_ATOM_OP",
7973   "type_ref": "GDS_ATOM_OP"
7974  },
7975  {
7976   "chips": ["gfx103"],
7977   "map": {"at": 200776, "to": "mm"},
7978   "name": "GDS_ATOM_SRC0"
7979  },
7980  {
7981   "chips": ["gfx103"],
7982   "map": {"at": 200780, "to": "mm"},
7983   "name": "GDS_ATOM_SRC0_U"
7984  },
7985  {
7986   "chips": ["gfx103"],
7987   "map": {"at": 200784, "to": "mm"},
7988   "name": "GDS_ATOM_SRC1"
7989  },
7990  {
7991   "chips": ["gfx103"],
7992   "map": {"at": 200788, "to": "mm"},
7993   "name": "GDS_ATOM_SRC1_U"
7994  },
7995  {
7996   "chips": ["gfx103"],
7997   "map": {"at": 200792, "to": "mm"},
7998   "name": "GDS_ATOM_READ0"
7999  },
8000  {
8001   "chips": ["gfx103"],
8002   "map": {"at": 200796, "to": "mm"},
8003   "name": "GDS_ATOM_READ0_U"
8004  },
8005  {
8006   "chips": ["gfx103"],
8007   "map": {"at": 200800, "to": "mm"},
8008   "name": "GDS_ATOM_READ1"
8009  },
8010  {
8011   "chips": ["gfx103"],
8012   "map": {"at": 200804, "to": "mm"},
8013   "name": "GDS_ATOM_READ1_U"
8014  },
8015  {
8016   "chips": ["gfx103"],
8017   "map": {"at": 200808, "to": "mm"},
8018   "name": "GDS_GWS_RESOURCE_CNTL",
8019   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8020  },
8021  {
8022   "chips": ["gfx103"],
8023   "map": {"at": 200812, "to": "mm"},
8024   "name": "GDS_GWS_RESOURCE",
8025   "type_ref": "GDS_GWS_RESOURCE"
8026  },
8027  {
8028   "chips": ["gfx103"],
8029   "map": {"at": 200816, "to": "mm"},
8030   "name": "GDS_GWS_RESOURCE_CNT",
8031   "type_ref": "GDS_GWS_RESOURCE_CNT"
8032  },
8033  {
8034   "chips": ["gfx103"],
8035   "map": {"at": 200820, "to": "mm"},
8036   "name": "GDS_OA_CNTL",
8037   "type_ref": "GDS_OA_CNTL"
8038  },
8039  {
8040   "chips": ["gfx103"],
8041   "map": {"at": 200824, "to": "mm"},
8042   "name": "GDS_OA_COUNTER"
8043  },
8044  {
8045   "chips": ["gfx103"],
8046   "map": {"at": 200828, "to": "mm"},
8047   "name": "GDS_OA_ADDRESS",
8048   "type_ref": "GDS_OA_ADDRESS"
8049  },
8050  {
8051   "chips": ["gfx103"],
8052   "map": {"at": 200832, "to": "mm"},
8053   "name": "GDS_OA_INCDEC",
8054   "type_ref": "GDS_OA_INCDEC"
8055  },
8056  {
8057   "chips": ["gfx103"],
8058   "map": {"at": 200836, "to": "mm"},
8059   "name": "GDS_OA_RING_SIZE"
8060  },
8061  {
8062   "chips": ["gfx103"],
8063   "map": {"at": 200960, "to": "mm"},
8064   "name": "SPI_CONFIG_CNTL_REMAP"
8065  },
8066  {
8067   "chips": ["gfx103"],
8068   "map": {"at": 200964, "to": "mm"},
8069   "name": "SPI_CONFIG_CNTL_1_REMAP"
8070  },
8071  {
8072   "chips": ["gfx103"],
8073   "map": {"at": 200968, "to": "mm"},
8074   "name": "SPI_CONFIG_CNTL_2_REMAP"
8075  },
8076  {
8077   "chips": ["gfx103"],
8078   "map": {"at": 200972, "to": "mm"},
8079   "name": "SPI_WAVE_LIMIT_CNTL_REMAP"
8080  },
8081  {
8082   "chips": ["gfx103"],
8083   "map": {"at": 212992, "to": "mm"},
8084   "name": "CPG_PERFCOUNTER1_LO"
8085  },
8086  {
8087   "chips": ["gfx103"],
8088   "map": {"at": 212996, "to": "mm"},
8089   "name": "CPG_PERFCOUNTER1_HI"
8090  },
8091  {
8092   "chips": ["gfx103"],
8093   "map": {"at": 213000, "to": "mm"},
8094   "name": "CPG_PERFCOUNTER0_LO"
8095  },
8096  {
8097   "chips": ["gfx103"],
8098   "map": {"at": 213004, "to": "mm"},
8099   "name": "CPG_PERFCOUNTER0_HI"
8100  },
8101  {
8102   "chips": ["gfx103"],
8103   "map": {"at": 213008, "to": "mm"},
8104   "name": "CPC_PERFCOUNTER1_LO"
8105  },
8106  {
8107   "chips": ["gfx103"],
8108   "map": {"at": 213012, "to": "mm"},
8109   "name": "CPC_PERFCOUNTER1_HI"
8110  },
8111  {
8112   "chips": ["gfx103"],
8113   "map": {"at": 213016, "to": "mm"},
8114   "name": "CPC_PERFCOUNTER0_LO"
8115  },
8116  {
8117   "chips": ["gfx103"],
8118   "map": {"at": 213020, "to": "mm"},
8119   "name": "CPC_PERFCOUNTER0_HI"
8120  },
8121  {
8122   "chips": ["gfx103"],
8123   "map": {"at": 213024, "to": "mm"},
8124   "name": "CPF_PERFCOUNTER1_LO"
8125  },
8126  {
8127   "chips": ["gfx103"],
8128   "map": {"at": 213028, "to": "mm"},
8129   "name": "CPF_PERFCOUNTER1_HI"
8130  },
8131  {
8132   "chips": ["gfx103"],
8133   "map": {"at": 213032, "to": "mm"},
8134   "name": "CPF_PERFCOUNTER0_LO"
8135  },
8136  {
8137   "chips": ["gfx103"],
8138   "map": {"at": 213036, "to": "mm"},
8139   "name": "CPF_PERFCOUNTER0_HI"
8140  },
8141  {
8142   "chips": ["gfx103"],
8143   "map": {"at": 213040, "to": "mm"},
8144   "name": "CPF_LATENCY_STATS_DATA"
8145  },
8146  {
8147   "chips": ["gfx103"],
8148   "map": {"at": 213044, "to": "mm"},
8149   "name": "CPG_LATENCY_STATS_DATA"
8150  },
8151  {
8152   "chips": ["gfx103"],
8153   "map": {"at": 213048, "to": "mm"},
8154   "name": "CPC_LATENCY_STATS_DATA"
8155  },
8156  {
8157   "chips": ["gfx103"],
8158   "map": {"at": 213248, "to": "mm"},
8159   "name": "GRBM_PERFCOUNTER0_LO"
8160  },
8161  {
8162   "chips": ["gfx103"],
8163   "map": {"at": 213252, "to": "mm"},
8164   "name": "GRBM_PERFCOUNTER0_HI"
8165  },
8166  {
8167   "chips": ["gfx103"],
8168   "map": {"at": 213260, "to": "mm"},
8169   "name": "GRBM_PERFCOUNTER1_LO"
8170  },
8171  {
8172   "chips": ["gfx103"],
8173   "map": {"at": 213264, "to": "mm"},
8174   "name": "GRBM_PERFCOUNTER1_HI"
8175  },
8176  {
8177   "chips": ["gfx103"],
8178   "map": {"at": 213268, "to": "mm"},
8179   "name": "GRBM_SE0_PERFCOUNTER_LO"
8180  },
8181  {
8182   "chips": ["gfx103"],
8183   "map": {"at": 213272, "to": "mm"},
8184   "name": "GRBM_SE0_PERFCOUNTER_HI"
8185  },
8186  {
8187   "chips": ["gfx103"],
8188   "map": {"at": 213276, "to": "mm"},
8189   "name": "GRBM_SE1_PERFCOUNTER_LO"
8190  },
8191  {
8192   "chips": ["gfx103"],
8193   "map": {"at": 213280, "to": "mm"},
8194   "name": "GRBM_SE1_PERFCOUNTER_HI"
8195  },
8196  {
8197   "chips": ["gfx103"],
8198   "map": {"at": 213284, "to": "mm"},
8199   "name": "GRBM_SE2_PERFCOUNTER_LO"
8200  },
8201  {
8202   "chips": ["gfx103"],
8203   "map": {"at": 213288, "to": "mm"},
8204   "name": "GRBM_SE2_PERFCOUNTER_HI"
8205  },
8206  {
8207   "chips": ["gfx103"],
8208   "map": {"at": 213292, "to": "mm"},
8209   "name": "GRBM_SE3_PERFCOUNTER_LO"
8210  },
8211  {
8212   "chips": ["gfx103"],
8213   "map": {"at": 213296, "to": "mm"},
8214   "name": "GRBM_SE3_PERFCOUNTER_HI"
8215  },
8216  {
8217   "chips": ["gfx103"],
8218   "map": {"at": 213648, "to": "mm"},
8219   "name": "GE1_PERFCOUNTER0_LO"
8220  },
8221  {
8222   "chips": ["gfx103"],
8223   "map": {"at": 213652, "to": "mm"},
8224   "name": "GE1_PERFCOUNTER0_HI"
8225  },
8226  {
8227   "chips": ["gfx103"],
8228   "map": {"at": 213656, "to": "mm"},
8229   "name": "GE1_PERFCOUNTER1_LO"
8230  },
8231  {
8232   "chips": ["gfx103"],
8233   "map": {"at": 213660, "to": "mm"},
8234   "name": "GE1_PERFCOUNTER1_HI"
8235  },
8236  {
8237   "chips": ["gfx103"],
8238   "map": {"at": 213664, "to": "mm"},
8239   "name": "GE1_PERFCOUNTER2_LO"
8240  },
8241  {
8242   "chips": ["gfx103"],
8243   "map": {"at": 213668, "to": "mm"},
8244   "name": "GE1_PERFCOUNTER2_HI"
8245  },
8246  {
8247   "chips": ["gfx103"],
8248   "map": {"at": 213672, "to": "mm"},
8249   "name": "GE1_PERFCOUNTER3_LO"
8250  },
8251  {
8252   "chips": ["gfx103"],
8253   "map": {"at": 213676, "to": "mm"},
8254   "name": "GE1_PERFCOUNTER3_HI"
8255  },
8256  {
8257   "chips": ["gfx103"],
8258   "map": {"at": 213680, "to": "mm"},
8259   "name": "GE2_DIST_PERFCOUNTER0_LO"
8260  },
8261  {
8262   "chips": ["gfx103"],
8263   "map": {"at": 213684, "to": "mm"},
8264   "name": "GE2_DIST_PERFCOUNTER0_HI"
8265  },
8266  {
8267   "chips": ["gfx103"],
8268   "map": {"at": 213688, "to": "mm"},
8269   "name": "GE2_DIST_PERFCOUNTER1_LO"
8270  },
8271  {
8272   "chips": ["gfx103"],
8273   "map": {"at": 213692, "to": "mm"},
8274   "name": "GE2_DIST_PERFCOUNTER1_HI"
8275  },
8276  {
8277   "chips": ["gfx103"],
8278   "map": {"at": 213696, "to": "mm"},
8279   "name": "GE2_DIST_PERFCOUNTER2_LO"
8280  },
8281  {
8282   "chips": ["gfx103"],
8283   "map": {"at": 213700, "to": "mm"},
8284   "name": "GE2_DIST_PERFCOUNTER2_HI"
8285  },
8286  {
8287   "chips": ["gfx103"],
8288   "map": {"at": 213704, "to": "mm"},
8289   "name": "GE2_DIST_PERFCOUNTER3_LO"
8290  },
8291  {
8292   "chips": ["gfx103"],
8293   "map": {"at": 213708, "to": "mm"},
8294   "name": "GE2_DIST_PERFCOUNTER3_HI"
8295  },
8296  {
8297   "chips": ["gfx103"],
8298   "map": {"at": 213712, "to": "mm"},
8299   "name": "GE2_SE_PERFCOUNTER0_LO"
8300  },
8301  {
8302   "chips": ["gfx103"],
8303   "map": {"at": 213716, "to": "mm"},
8304   "name": "GE2_SE_PERFCOUNTER0_HI"
8305  },
8306  {
8307   "chips": ["gfx103"],
8308   "map": {"at": 213720, "to": "mm"},
8309   "name": "GE2_SE_PERFCOUNTER1_LO"
8310  },
8311  {
8312   "chips": ["gfx103"],
8313   "map": {"at": 213724, "to": "mm"},
8314   "name": "GE2_SE_PERFCOUNTER1_HI"
8315  },
8316  {
8317   "chips": ["gfx103"],
8318   "map": {"at": 213728, "to": "mm"},
8319   "name": "GE2_SE_PERFCOUNTER2_LO"
8320  },
8321  {
8322   "chips": ["gfx103"],
8323   "map": {"at": 213732, "to": "mm"},
8324   "name": "GE2_SE_PERFCOUNTER2_HI"
8325  },
8326  {
8327   "chips": ["gfx103"],
8328   "map": {"at": 213736, "to": "mm"},
8329   "name": "GE2_SE_PERFCOUNTER3_LO"
8330  },
8331  {
8332   "chips": ["gfx103"],
8333   "map": {"at": 213740, "to": "mm"},
8334   "name": "GE2_SE_PERFCOUNTER3_HI"
8335  },
8336  {
8337   "chips": ["gfx103"],
8338   "map": {"at": 214016, "to": "mm"},
8339   "name": "PA_SU_PERFCOUNTER0_LO"
8340  },
8341  {
8342   "chips": ["gfx103"],
8343   "map": {"at": 214020, "to": "mm"},
8344   "name": "PA_SU_PERFCOUNTER0_HI"
8345  },
8346  {
8347   "chips": ["gfx103"],
8348   "map": {"at": 214024, "to": "mm"},
8349   "name": "PA_SU_PERFCOUNTER1_LO"
8350  },
8351  {
8352   "chips": ["gfx103"],
8353   "map": {"at": 214028, "to": "mm"},
8354   "name": "PA_SU_PERFCOUNTER1_HI"
8355  },
8356  {
8357   "chips": ["gfx103"],
8358   "map": {"at": 214032, "to": "mm"},
8359   "name": "PA_SU_PERFCOUNTER2_LO"
8360  },
8361  {
8362   "chips": ["gfx103"],
8363   "map": {"at": 214036, "to": "mm"},
8364   "name": "PA_SU_PERFCOUNTER2_HI"
8365  },
8366  {
8367   "chips": ["gfx103"],
8368   "map": {"at": 214040, "to": "mm"},
8369   "name": "PA_SU_PERFCOUNTER3_LO"
8370  },
8371  {
8372   "chips": ["gfx103"],
8373   "map": {"at": 214044, "to": "mm"},
8374   "name": "PA_SU_PERFCOUNTER3_HI"
8375  },
8376  {
8377   "chips": ["gfx103"],
8378   "map": {"at": 214272, "to": "mm"},
8379   "name": "PA_SC_PERFCOUNTER0_LO"
8380  },
8381  {
8382   "chips": ["gfx103"],
8383   "map": {"at": 214276, "to": "mm"},
8384   "name": "PA_SC_PERFCOUNTER0_HI"
8385  },
8386  {
8387   "chips": ["gfx103"],
8388   "map": {"at": 214280, "to": "mm"},
8389   "name": "PA_SC_PERFCOUNTER1_LO"
8390  },
8391  {
8392   "chips": ["gfx103"],
8393   "map": {"at": 214284, "to": "mm"},
8394   "name": "PA_SC_PERFCOUNTER1_HI"
8395  },
8396  {
8397   "chips": ["gfx103"],
8398   "map": {"at": 214288, "to": "mm"},
8399   "name": "PA_SC_PERFCOUNTER2_LO"
8400  },
8401  {
8402   "chips": ["gfx103"],
8403   "map": {"at": 214292, "to": "mm"},
8404   "name": "PA_SC_PERFCOUNTER2_HI"
8405  },
8406  {
8407   "chips": ["gfx103"],
8408   "map": {"at": 214296, "to": "mm"},
8409   "name": "PA_SC_PERFCOUNTER3_LO"
8410  },
8411  {
8412   "chips": ["gfx103"],
8413   "map": {"at": 214300, "to": "mm"},
8414   "name": "PA_SC_PERFCOUNTER3_HI"
8415  },
8416  {
8417   "chips": ["gfx103"],
8418   "map": {"at": 214304, "to": "mm"},
8419   "name": "PA_SC_PERFCOUNTER4_LO"
8420  },
8421  {
8422   "chips": ["gfx103"],
8423   "map": {"at": 214308, "to": "mm"},
8424   "name": "PA_SC_PERFCOUNTER4_HI"
8425  },
8426  {
8427   "chips": ["gfx103"],
8428   "map": {"at": 214312, "to": "mm"},
8429   "name": "PA_SC_PERFCOUNTER5_LO"
8430  },
8431  {
8432   "chips": ["gfx103"],
8433   "map": {"at": 214316, "to": "mm"},
8434   "name": "PA_SC_PERFCOUNTER5_HI"
8435  },
8436  {
8437   "chips": ["gfx103"],
8438   "map": {"at": 214320, "to": "mm"},
8439   "name": "PA_SC_PERFCOUNTER6_LO"
8440  },
8441  {
8442   "chips": ["gfx103"],
8443   "map": {"at": 214324, "to": "mm"},
8444   "name": "PA_SC_PERFCOUNTER6_HI"
8445  },
8446  {
8447   "chips": ["gfx103"],
8448   "map": {"at": 214328, "to": "mm"},
8449   "name": "PA_SC_PERFCOUNTER7_LO"
8450  },
8451  {
8452   "chips": ["gfx103"],
8453   "map": {"at": 214332, "to": "mm"},
8454   "name": "PA_SC_PERFCOUNTER7_HI"
8455  },
8456  {
8457   "chips": ["gfx103"],
8458   "map": {"at": 214528, "to": "mm"},
8459   "name": "SPI_PERFCOUNTER0_HI"
8460  },
8461  {
8462   "chips": ["gfx103"],
8463   "map": {"at": 214532, "to": "mm"},
8464   "name": "SPI_PERFCOUNTER0_LO"
8465  },
8466  {
8467   "chips": ["gfx103"],
8468   "map": {"at": 214536, "to": "mm"},
8469   "name": "SPI_PERFCOUNTER1_HI"
8470  },
8471  {
8472   "chips": ["gfx103"],
8473   "map": {"at": 214540, "to": "mm"},
8474   "name": "SPI_PERFCOUNTER1_LO"
8475  },
8476  {
8477   "chips": ["gfx103"],
8478   "map": {"at": 214544, "to": "mm"},
8479   "name": "SPI_PERFCOUNTER2_HI"
8480  },
8481  {
8482   "chips": ["gfx103"],
8483   "map": {"at": 214548, "to": "mm"},
8484   "name": "SPI_PERFCOUNTER2_LO"
8485  },
8486  {
8487   "chips": ["gfx103"],
8488   "map": {"at": 214552, "to": "mm"},
8489   "name": "SPI_PERFCOUNTER3_HI"
8490  },
8491  {
8492   "chips": ["gfx103"],
8493   "map": {"at": 214556, "to": "mm"},
8494   "name": "SPI_PERFCOUNTER3_LO"
8495  },
8496  {
8497   "chips": ["gfx103"],
8498   "map": {"at": 214560, "to": "mm"},
8499   "name": "SPI_PERFCOUNTER4_HI"
8500  },
8501  {
8502   "chips": ["gfx103"],
8503   "map": {"at": 214564, "to": "mm"},
8504   "name": "SPI_PERFCOUNTER4_LO"
8505  },
8506  {
8507   "chips": ["gfx103"],
8508   "map": {"at": 214568, "to": "mm"},
8509   "name": "SPI_PERFCOUNTER5_HI"
8510  },
8511  {
8512   "chips": ["gfx103"],
8513   "map": {"at": 214572, "to": "mm"},
8514   "name": "SPI_PERFCOUNTER5_LO"
8515  },
8516  {
8517   "chips": ["gfx103"],
8518   "map": {"at": 214784, "to": "mm"},
8519   "name": "SQ_PERFCOUNTER0_LO"
8520  },
8521  {
8522   "chips": ["gfx103"],
8523   "map": {"at": 214788, "to": "mm"},
8524   "name": "SQ_PERFCOUNTER0_HI"
8525  },
8526  {
8527   "chips": ["gfx103"],
8528   "map": {"at": 214792, "to": "mm"},
8529   "name": "SQ_PERFCOUNTER1_LO"
8530  },
8531  {
8532   "chips": ["gfx103"],
8533   "map": {"at": 214796, "to": "mm"},
8534   "name": "SQ_PERFCOUNTER1_HI"
8535  },
8536  {
8537   "chips": ["gfx103"],
8538   "map": {"at": 214800, "to": "mm"},
8539   "name": "SQ_PERFCOUNTER2_LO"
8540  },
8541  {
8542   "chips": ["gfx103"],
8543   "map": {"at": 214804, "to": "mm"},
8544   "name": "SQ_PERFCOUNTER2_HI"
8545  },
8546  {
8547   "chips": ["gfx103"],
8548   "map": {"at": 214808, "to": "mm"},
8549   "name": "SQ_PERFCOUNTER3_LO"
8550  },
8551  {
8552   "chips": ["gfx103"],
8553   "map": {"at": 214812, "to": "mm"},
8554   "name": "SQ_PERFCOUNTER3_HI"
8555  },
8556  {
8557   "chips": ["gfx103"],
8558   "map": {"at": 214816, "to": "mm"},
8559   "name": "SQ_PERFCOUNTER4_LO"
8560  },
8561  {
8562   "chips": ["gfx103"],
8563   "map": {"at": 214820, "to": "mm"},
8564   "name": "SQ_PERFCOUNTER4_HI"
8565  },
8566  {
8567   "chips": ["gfx103"],
8568   "map": {"at": 214824, "to": "mm"},
8569   "name": "SQ_PERFCOUNTER5_LO"
8570  },
8571  {
8572   "chips": ["gfx103"],
8573   "map": {"at": 214828, "to": "mm"},
8574   "name": "SQ_PERFCOUNTER5_HI"
8575  },
8576  {
8577   "chips": ["gfx103"],
8578   "map": {"at": 214832, "to": "mm"},
8579   "name": "SQ_PERFCOUNTER6_LO"
8580  },
8581  {
8582   "chips": ["gfx103"],
8583   "map": {"at": 214836, "to": "mm"},
8584   "name": "SQ_PERFCOUNTER6_HI"
8585  },
8586  {
8587   "chips": ["gfx103"],
8588   "map": {"at": 214840, "to": "mm"},
8589   "name": "SQ_PERFCOUNTER7_LO"
8590  },
8591  {
8592   "chips": ["gfx103"],
8593   "map": {"at": 214844, "to": "mm"},
8594   "name": "SQ_PERFCOUNTER7_HI"
8595  },
8596  {
8597   "chips": ["gfx103"],
8598   "map": {"at": 214848, "to": "mm"},
8599   "name": "SQ_PERFCOUNTER8_LO"
8600  },
8601  {
8602   "chips": ["gfx103"],
8603   "map": {"at": 214852, "to": "mm"},
8604   "name": "SQ_PERFCOUNTER8_HI"
8605  },
8606  {
8607   "chips": ["gfx103"],
8608   "map": {"at": 214856, "to": "mm"},
8609   "name": "SQ_PERFCOUNTER9_LO"
8610  },
8611  {
8612   "chips": ["gfx103"],
8613   "map": {"at": 214860, "to": "mm"},
8614   "name": "SQ_PERFCOUNTER9_HI"
8615  },
8616  {
8617   "chips": ["gfx103"],
8618   "map": {"at": 214864, "to": "mm"},
8619   "name": "SQ_PERFCOUNTER10_LO"
8620  },
8621  {
8622   "chips": ["gfx103"],
8623   "map": {"at": 214868, "to": "mm"},
8624   "name": "SQ_PERFCOUNTER10_HI"
8625  },
8626  {
8627   "chips": ["gfx103"],
8628   "map": {"at": 214872, "to": "mm"},
8629   "name": "SQ_PERFCOUNTER11_LO"
8630  },
8631  {
8632   "chips": ["gfx103"],
8633   "map": {"at": 214876, "to": "mm"},
8634   "name": "SQ_PERFCOUNTER11_HI"
8635  },
8636  {
8637   "chips": ["gfx103"],
8638   "map": {"at": 214880, "to": "mm"},
8639   "name": "SQ_PERFCOUNTER12_LO"
8640  },
8641  {
8642   "chips": ["gfx103"],
8643   "map": {"at": 214884, "to": "mm"},
8644   "name": "SQ_PERFCOUNTER12_HI"
8645  },
8646  {
8647   "chips": ["gfx103"],
8648   "map": {"at": 214888, "to": "mm"},
8649   "name": "SQ_PERFCOUNTER13_LO"
8650  },
8651  {
8652   "chips": ["gfx103"],
8653   "map": {"at": 214892, "to": "mm"},
8654   "name": "SQ_PERFCOUNTER13_HI"
8655  },
8656  {
8657   "chips": ["gfx103"],
8658   "map": {"at": 214896, "to": "mm"},
8659   "name": "SQ_PERFCOUNTER14_LO"
8660  },
8661  {
8662   "chips": ["gfx103"],
8663   "map": {"at": 214900, "to": "mm"},
8664   "name": "SQ_PERFCOUNTER14_HI"
8665  },
8666  {
8667   "chips": ["gfx103"],
8668   "map": {"at": 214904, "to": "mm"},
8669   "name": "SQ_PERFCOUNTER15_LO"
8670  },
8671  {
8672   "chips": ["gfx103"],
8673   "map": {"at": 214908, "to": "mm"},
8674   "name": "SQ_PERFCOUNTER15_HI"
8675  },
8676  {
8677   "chips": ["gfx103"],
8678   "map": {"at": 215296, "to": "mm"},
8679   "name": "SX_PERFCOUNTER0_LO"
8680  },
8681  {
8682   "chips": ["gfx103"],
8683   "map": {"at": 215300, "to": "mm"},
8684   "name": "SX_PERFCOUNTER0_HI"
8685  },
8686  {
8687   "chips": ["gfx103"],
8688   "map": {"at": 215304, "to": "mm"},
8689   "name": "SX_PERFCOUNTER1_LO"
8690  },
8691  {
8692   "chips": ["gfx103"],
8693   "map": {"at": 215308, "to": "mm"},
8694   "name": "SX_PERFCOUNTER1_HI"
8695  },
8696  {
8697   "chips": ["gfx103"],
8698   "map": {"at": 215312, "to": "mm"},
8699   "name": "SX_PERFCOUNTER2_LO"
8700  },
8701  {
8702   "chips": ["gfx103"],
8703   "map": {"at": 215316, "to": "mm"},
8704   "name": "SX_PERFCOUNTER2_HI"
8705  },
8706  {
8707   "chips": ["gfx103"],
8708   "map": {"at": 215320, "to": "mm"},
8709   "name": "SX_PERFCOUNTER3_LO"
8710  },
8711  {
8712   "chips": ["gfx103"],
8713   "map": {"at": 215324, "to": "mm"},
8714   "name": "SX_PERFCOUNTER3_HI"
8715  },
8716  {
8717   "chips": ["gfx103"],
8718   "map": {"at": 215424, "to": "mm"},
8719   "name": "GCEA_PERFCOUNTER2_LO"
8720  },
8721  {
8722   "chips": ["gfx103"],
8723   "map": {"at": 215428, "to": "mm"},
8724   "name": "GCEA_PERFCOUNTER2_HI"
8725  },
8726  {
8727   "chips": ["gfx103"],
8728   "map": {"at": 215432, "to": "mm"},
8729   "name": "GCEA_PERFCOUNTER_LO"
8730  },
8731  {
8732   "chips": ["gfx103"],
8733   "map": {"at": 215436, "to": "mm"},
8734   "name": "GCEA_PERFCOUNTER_HI",
8735   "type_ref": "GCEA_PERFCOUNTER_HI"
8736  },
8737  {
8738   "chips": ["gfx103"],
8739   "map": {"at": 215552, "to": "mm"},
8740   "name": "GDS_PERFCOUNTER0_LO"
8741  },
8742  {
8743   "chips": ["gfx103"],
8744   "map": {"at": 215556, "to": "mm"},
8745   "name": "GDS_PERFCOUNTER0_HI"
8746  },
8747  {
8748   "chips": ["gfx103"],
8749   "map": {"at": 215560, "to": "mm"},
8750   "name": "GDS_PERFCOUNTER1_LO"
8751  },
8752  {
8753   "chips": ["gfx103"],
8754   "map": {"at": 215564, "to": "mm"},
8755   "name": "GDS_PERFCOUNTER1_HI"
8756  },
8757  {
8758   "chips": ["gfx103"],
8759   "map": {"at": 215568, "to": "mm"},
8760   "name": "GDS_PERFCOUNTER2_LO"
8761  },
8762  {
8763   "chips": ["gfx103"],
8764   "map": {"at": 215572, "to": "mm"},
8765   "name": "GDS_PERFCOUNTER2_HI"
8766  },
8767  {
8768   "chips": ["gfx103"],
8769   "map": {"at": 215576, "to": "mm"},
8770   "name": "GDS_PERFCOUNTER3_LO"
8771  },
8772  {
8773   "chips": ["gfx103"],
8774   "map": {"at": 215580, "to": "mm"},
8775   "name": "GDS_PERFCOUNTER3_HI"
8776  },
8777  {
8778   "chips": ["gfx103"],
8779   "map": {"at": 215808, "to": "mm"},
8780   "name": "TA_PERFCOUNTER0_LO"
8781  },
8782  {
8783   "chips": ["gfx103"],
8784   "map": {"at": 215812, "to": "mm"},
8785   "name": "TA_PERFCOUNTER0_HI"
8786  },
8787  {
8788   "chips": ["gfx103"],
8789   "map": {"at": 215816, "to": "mm"},
8790   "name": "TA_PERFCOUNTER1_LO"
8791  },
8792  {
8793   "chips": ["gfx103"],
8794   "map": {"at": 215820, "to": "mm"},
8795   "name": "TA_PERFCOUNTER1_HI"
8796  },
8797  {
8798   "chips": ["gfx103"],
8799   "map": {"at": 216064, "to": "mm"},
8800   "name": "TD_PERFCOUNTER0_LO"
8801  },
8802  {
8803   "chips": ["gfx103"],
8804   "map": {"at": 216068, "to": "mm"},
8805   "name": "TD_PERFCOUNTER0_HI"
8806  },
8807  {
8808   "chips": ["gfx103"],
8809   "map": {"at": 216072, "to": "mm"},
8810   "name": "TD_PERFCOUNTER1_LO"
8811  },
8812  {
8813   "chips": ["gfx103"],
8814   "map": {"at": 216076, "to": "mm"},
8815   "name": "TD_PERFCOUNTER1_HI"
8816  },
8817  {
8818   "chips": ["gfx103"],
8819   "map": {"at": 216320, "to": "mm"},
8820   "name": "TCP_PERFCOUNTER0_LO"
8821  },
8822  {
8823   "chips": ["gfx103"],
8824   "map": {"at": 216324, "to": "mm"},
8825   "name": "TCP_PERFCOUNTER0_HI"
8826  },
8827  {
8828   "chips": ["gfx103"],
8829   "map": {"at": 216328, "to": "mm"},
8830   "name": "TCP_PERFCOUNTER1_LO"
8831  },
8832  {
8833   "chips": ["gfx103"],
8834   "map": {"at": 216332, "to": "mm"},
8835   "name": "TCP_PERFCOUNTER1_HI"
8836  },
8837  {
8838   "chips": ["gfx103"],
8839   "map": {"at": 216336, "to": "mm"},
8840   "name": "TCP_PERFCOUNTER2_LO"
8841  },
8842  {
8843   "chips": ["gfx103"],
8844   "map": {"at": 216340, "to": "mm"},
8845   "name": "TCP_PERFCOUNTER2_HI"
8846  },
8847  {
8848   "chips": ["gfx103"],
8849   "map": {"at": 216344, "to": "mm"},
8850   "name": "TCP_PERFCOUNTER3_LO"
8851  },
8852  {
8853   "chips": ["gfx103"],
8854   "map": {"at": 216348, "to": "mm"},
8855   "name": "TCP_PERFCOUNTER3_HI"
8856  },
8857  {
8858   "chips": ["gfx103"],
8859   "map": {"at": 216576, "to": "mm"},
8860   "name": "GL2C_PERFCOUNTER0_LO"
8861  },
8862  {
8863   "chips": ["gfx103"],
8864   "map": {"at": 216580, "to": "mm"},
8865   "name": "GL2C_PERFCOUNTER0_HI"
8866  },
8867  {
8868   "chips": ["gfx103"],
8869   "map": {"at": 216584, "to": "mm"},
8870   "name": "GL2C_PERFCOUNTER1_LO"
8871  },
8872  {
8873   "chips": ["gfx103"],
8874   "map": {"at": 216588, "to": "mm"},
8875   "name": "GL2C_PERFCOUNTER1_HI"
8876  },
8877  {
8878   "chips": ["gfx103"],
8879   "map": {"at": 216592, "to": "mm"},
8880   "name": "GL2C_PERFCOUNTER2_LO"
8881  },
8882  {
8883   "chips": ["gfx103"],
8884   "map": {"at": 216596, "to": "mm"},
8885   "name": "GL2C_PERFCOUNTER2_HI"
8886  },
8887  {
8888   "chips": ["gfx103"],
8889   "map": {"at": 216600, "to": "mm"},
8890   "name": "GL2C_PERFCOUNTER3_LO"
8891  },
8892  {
8893   "chips": ["gfx103"],
8894   "map": {"at": 216604, "to": "mm"},
8895   "name": "GL2C_PERFCOUNTER3_HI"
8896  },
8897  {
8898   "chips": ["gfx103"],
8899   "map": {"at": 216640, "to": "mm"},
8900   "name": "GL2A_PERFCOUNTER0_LO"
8901  },
8902  {
8903   "chips": ["gfx103"],
8904   "map": {"at": 216644, "to": "mm"},
8905   "name": "GL2A_PERFCOUNTER0_HI"
8906  },
8907  {
8908   "chips": ["gfx103"],
8909   "map": {"at": 216648, "to": "mm"},
8910   "name": "GL2A_PERFCOUNTER1_LO"
8911  },
8912  {
8913   "chips": ["gfx103"],
8914   "map": {"at": 216652, "to": "mm"},
8915   "name": "GL2A_PERFCOUNTER1_HI"
8916  },
8917  {
8918   "chips": ["gfx103"],
8919   "map": {"at": 216656, "to": "mm"},
8920   "name": "GL2A_PERFCOUNTER2_LO"
8921  },
8922  {
8923   "chips": ["gfx103"],
8924   "map": {"at": 216660, "to": "mm"},
8925   "name": "GL2A_PERFCOUNTER2_HI"
8926  },
8927  {
8928   "chips": ["gfx103"],
8929   "map": {"at": 216664, "to": "mm"},
8930   "name": "GL2A_PERFCOUNTER3_LO"
8931  },
8932  {
8933   "chips": ["gfx103"],
8934   "map": {"at": 216668, "to": "mm"},
8935   "name": "GL2A_PERFCOUNTER3_HI"
8936  },
8937  {
8938   "chips": ["gfx103"],
8939   "map": {"at": 216704, "to": "mm"},
8940   "name": "GL1C_PERFCOUNTER0_LO"
8941  },
8942  {
8943   "chips": ["gfx103"],
8944   "map": {"at": 216708, "to": "mm"},
8945   "name": "GL1C_PERFCOUNTER0_HI"
8946  },
8947  {
8948   "chips": ["gfx103"],
8949   "map": {"at": 216712, "to": "mm"},
8950   "name": "GL1C_PERFCOUNTER1_LO"
8951  },
8952  {
8953   "chips": ["gfx103"],
8954   "map": {"at": 216716, "to": "mm"},
8955   "name": "GL1C_PERFCOUNTER1_HI"
8956  },
8957  {
8958   "chips": ["gfx103"],
8959   "map": {"at": 216720, "to": "mm"},
8960   "name": "GL1C_PERFCOUNTER2_LO"
8961  },
8962  {
8963   "chips": ["gfx103"],
8964   "map": {"at": 216724, "to": "mm"},
8965   "name": "GL1C_PERFCOUNTER2_HI"
8966  },
8967  {
8968   "chips": ["gfx103"],
8969   "map": {"at": 216728, "to": "mm"},
8970   "name": "GL1C_PERFCOUNTER3_LO"
8971  },
8972  {
8973   "chips": ["gfx103"],
8974   "map": {"at": 216732, "to": "mm"},
8975   "name": "GL1C_PERFCOUNTER3_HI"
8976  },
8977  {
8978   "chips": ["gfx103"],
8979   "map": {"at": 216832, "to": "mm"},
8980   "name": "CHC_PERFCOUNTER0_LO"
8981  },
8982  {
8983   "chips": ["gfx103"],
8984   "map": {"at": 216836, "to": "mm"},
8985   "name": "CHC_PERFCOUNTER0_HI"
8986  },
8987  {
8988   "chips": ["gfx103"],
8989   "map": {"at": 216840, "to": "mm"},
8990   "name": "CHC_PERFCOUNTER1_LO"
8991  },
8992  {
8993   "chips": ["gfx103"],
8994   "map": {"at": 216844, "to": "mm"},
8995   "name": "CHC_PERFCOUNTER1_HI"
8996  },
8997  {
8998   "chips": ["gfx103"],
8999   "map": {"at": 216848, "to": "mm"},
9000   "name": "CHC_PERFCOUNTER2_LO"
9001  },
9002  {
9003   "chips": ["gfx103"],
9004   "map": {"at": 216852, "to": "mm"},
9005   "name": "CHC_PERFCOUNTER2_HI"
9006  },
9007  {
9008   "chips": ["gfx103"],
9009   "map": {"at": 216856, "to": "mm"},
9010   "name": "CHC_PERFCOUNTER3_LO"
9011  },
9012  {
9013   "chips": ["gfx103"],
9014   "map": {"at": 216860, "to": "mm"},
9015   "name": "CHC_PERFCOUNTER3_HI"
9016  },
9017  {
9018   "chips": ["gfx103"],
9019   "map": {"at": 216864, "to": "mm"},
9020   "name": "CHCG_PERFCOUNTER0_LO"
9021  },
9022  {
9023   "chips": ["gfx103"],
9024   "map": {"at": 216868, "to": "mm"},
9025   "name": "CHCG_PERFCOUNTER0_HI"
9026  },
9027  {
9028   "chips": ["gfx103"],
9029   "map": {"at": 216872, "to": "mm"},
9030   "name": "CHCG_PERFCOUNTER1_LO"
9031  },
9032  {
9033   "chips": ["gfx103"],
9034   "map": {"at": 216876, "to": "mm"},
9035   "name": "CHCG_PERFCOUNTER1_HI"
9036  },
9037  {
9038   "chips": ["gfx103"],
9039   "map": {"at": 216880, "to": "mm"},
9040   "name": "CHCG_PERFCOUNTER2_LO"
9041  },
9042  {
9043   "chips": ["gfx103"],
9044   "map": {"at": 216884, "to": "mm"},
9045   "name": "CHCG_PERFCOUNTER2_HI"
9046  },
9047  {
9048   "chips": ["gfx103"],
9049   "map": {"at": 216888, "to": "mm"},
9050   "name": "CHCG_PERFCOUNTER3_LO"
9051  },
9052  {
9053   "chips": ["gfx103"],
9054   "map": {"at": 216892, "to": "mm"},
9055   "name": "CHCG_PERFCOUNTER3_HI"
9056  },
9057  {
9058   "chips": ["gfx103"],
9059   "map": {"at": 217112, "to": "mm"},
9060   "name": "CB_PERFCOUNTER0_LO"
9061  },
9062  {
9063   "chips": ["gfx103"],
9064   "map": {"at": 217116, "to": "mm"},
9065   "name": "CB_PERFCOUNTER0_HI"
9066  },
9067  {
9068   "chips": ["gfx103"],
9069   "map": {"at": 217120, "to": "mm"},
9070   "name": "CB_PERFCOUNTER1_LO"
9071  },
9072  {
9073   "chips": ["gfx103"],
9074   "map": {"at": 217124, "to": "mm"},
9075   "name": "CB_PERFCOUNTER1_HI"
9076  },
9077  {
9078   "chips": ["gfx103"],
9079   "map": {"at": 217128, "to": "mm"},
9080   "name": "CB_PERFCOUNTER2_LO"
9081  },
9082  {
9083   "chips": ["gfx103"],
9084   "map": {"at": 217132, "to": "mm"},
9085   "name": "CB_PERFCOUNTER2_HI"
9086  },
9087  {
9088   "chips": ["gfx103"],
9089   "map": {"at": 217136, "to": "mm"},
9090   "name": "CB_PERFCOUNTER3_LO"
9091  },
9092  {
9093   "chips": ["gfx103"],
9094   "map": {"at": 217140, "to": "mm"},
9095   "name": "CB_PERFCOUNTER3_HI"
9096  },
9097  {
9098   "chips": ["gfx103"],
9099   "map": {"at": 217344, "to": "mm"},
9100   "name": "DB_PERFCOUNTER0_LO"
9101  },
9102  {
9103   "chips": ["gfx103"],
9104   "map": {"at": 217348, "to": "mm"},
9105   "name": "DB_PERFCOUNTER0_HI"
9106  },
9107  {
9108   "chips": ["gfx103"],
9109   "map": {"at": 217352, "to": "mm"},
9110   "name": "DB_PERFCOUNTER1_LO"
9111  },
9112  {
9113   "chips": ["gfx103"],
9114   "map": {"at": 217356, "to": "mm"},
9115   "name": "DB_PERFCOUNTER1_HI"
9116  },
9117  {
9118   "chips": ["gfx103"],
9119   "map": {"at": 217360, "to": "mm"},
9120   "name": "DB_PERFCOUNTER2_LO"
9121  },
9122  {
9123   "chips": ["gfx103"],
9124   "map": {"at": 217364, "to": "mm"},
9125   "name": "DB_PERFCOUNTER2_HI"
9126  },
9127  {
9128   "chips": ["gfx103"],
9129   "map": {"at": 217368, "to": "mm"},
9130   "name": "DB_PERFCOUNTER3_LO"
9131  },
9132  {
9133   "chips": ["gfx103"],
9134   "map": {"at": 217372, "to": "mm"},
9135   "name": "DB_PERFCOUNTER3_HI"
9136  },
9137  {
9138   "chips": ["gfx103"],
9139   "map": {"at": 217600, "to": "mm"},
9140   "name": "RLC_PERFCOUNTER0_LO"
9141  },
9142  {
9143   "chips": ["gfx103"],
9144   "map": {"at": 217604, "to": "mm"},
9145   "name": "RLC_PERFCOUNTER0_HI"
9146  },
9147  {
9148   "chips": ["gfx103"],
9149   "map": {"at": 217608, "to": "mm"},
9150   "name": "RLC_PERFCOUNTER1_LO"
9151  },
9152  {
9153   "chips": ["gfx103"],
9154   "map": {"at": 217612, "to": "mm"},
9155   "name": "RLC_PERFCOUNTER1_HI"
9156  },
9157  {
9158   "chips": ["gfx103"],
9159   "map": {"at": 217856, "to": "mm"},
9160   "name": "RMI_PERFCOUNTER0_LO"
9161  },
9162  {
9163   "chips": ["gfx103"],
9164   "map": {"at": 217860, "to": "mm"},
9165   "name": "RMI_PERFCOUNTER0_HI"
9166  },
9167  {
9168   "chips": ["gfx103"],
9169   "map": {"at": 217864, "to": "mm"},
9170   "name": "RMI_PERFCOUNTER1_LO"
9171  },
9172  {
9173   "chips": ["gfx103"],
9174   "map": {"at": 217868, "to": "mm"},
9175   "name": "RMI_PERFCOUNTER1_HI"
9176  },
9177  {
9178   "chips": ["gfx103"],
9179   "map": {"at": 217872, "to": "mm"},
9180   "name": "RMI_PERFCOUNTER2_LO"
9181  },
9182  {
9183   "chips": ["gfx103"],
9184   "map": {"at": 217876, "to": "mm"},
9185   "name": "RMI_PERFCOUNTER2_HI"
9186  },
9187  {
9188   "chips": ["gfx103"],
9189   "map": {"at": 217880, "to": "mm"},
9190   "name": "RMI_PERFCOUNTER3_LO"
9191  },
9192  {
9193   "chips": ["gfx103"],
9194   "map": {"at": 217884, "to": "mm"},
9195   "name": "RMI_PERFCOUNTER3_HI"
9196  },
9197  {
9198   "chips": ["gfx103"],
9199   "map": {"at": 218016, "to": "mm"},
9200   "name": "GCMC_VM_L2_PERFCOUNTER_LO"
9201  },
9202  {
9203   "chips": ["gfx103"],
9204   "map": {"at": 218020, "to": "mm"},
9205   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
9206   "type_ref": "GCEA_PERFCOUNTER_HI"
9207  },
9208  {
9209   "chips": ["gfx103"],
9210   "map": {"at": 218024, "to": "mm"},
9211   "name": "GCUTCL2_PERFCOUNTER_LO"
9212  },
9213  {
9214   "chips": ["gfx103"],
9215   "map": {"at": 218028, "to": "mm"},
9216   "name": "GCUTCL2_PERFCOUNTER_HI",
9217   "type_ref": "GCEA_PERFCOUNTER_HI"
9218  },
9219  {
9220   "chips": ["gfx103"],
9221   "map": {"at": 218080, "to": "mm"},
9222   "name": "GCVML2_PERFCOUNTER2_0_LO"
9223  },
9224  {
9225   "chips": ["gfx103"],
9226   "map": {"at": 218084, "to": "mm"},
9227   "name": "GCVML2_PERFCOUNTER2_1_LO"
9228  },
9229  {
9230   "chips": ["gfx103"],
9231   "map": {"at": 218088, "to": "mm"},
9232   "name": "GCVML2_PERFCOUNTER2_0_HI"
9233  },
9234  {
9235   "chips": ["gfx103"],
9236   "map": {"at": 218092, "to": "mm"},
9237   "name": "GCVML2_PERFCOUNTER2_1_HI"
9238  },
9239  {
9240   "chips": ["gfx103"],
9241   "map": {"at": 218224, "to": "mm"},
9242   "name": "UTCL1_PERFCOUNTER0_LO"
9243  },
9244  {
9245   "chips": ["gfx103"],
9246   "map": {"at": 218228, "to": "mm"},
9247   "name": "UTCL1_PERFCOUNTER0_HI"
9248  },
9249  {
9250   "chips": ["gfx103"],
9251   "map": {"at": 218232, "to": "mm"},
9252   "name": "UTCL1_PERFCOUNTER1_LO"
9253  },
9254  {
9255   "chips": ["gfx103"],
9256   "map": {"at": 218236, "to": "mm"},
9257   "name": "UTCL1_PERFCOUNTER1_HI"
9258  },
9259  {
9260   "chips": ["gfx103"],
9261   "map": {"at": 218240, "to": "mm"},
9262   "name": "GCR_PERFCOUNTER0_LO"
9263  },
9264  {
9265   "chips": ["gfx103"],
9266   "map": {"at": 218244, "to": "mm"},
9267   "name": "GCR_PERFCOUNTER0_HI"
9268  },
9269  {
9270   "chips": ["gfx103"],
9271   "map": {"at": 218248, "to": "mm"},
9272   "name": "GCR_PERFCOUNTER1_LO"
9273  },
9274  {
9275   "chips": ["gfx103"],
9276   "map": {"at": 218252, "to": "mm"},
9277   "name": "GCR_PERFCOUNTER1_HI"
9278  },
9279  {
9280   "chips": ["gfx103"],
9281   "map": {"at": 218624, "to": "mm"},
9282   "name": "PA_PH_PERFCOUNTER0_LO"
9283  },
9284  {
9285   "chips": ["gfx103"],
9286   "map": {"at": 218628, "to": "mm"},
9287   "name": "PA_PH_PERFCOUNTER0_HI"
9288  },
9289  {
9290   "chips": ["gfx103"],
9291   "map": {"at": 218632, "to": "mm"},
9292   "name": "PA_PH_PERFCOUNTER1_LO"
9293  },
9294  {
9295   "chips": ["gfx103"],
9296   "map": {"at": 218636, "to": "mm"},
9297   "name": "PA_PH_PERFCOUNTER1_HI"
9298  },
9299  {
9300   "chips": ["gfx103"],
9301   "map": {"at": 218640, "to": "mm"},
9302   "name": "PA_PH_PERFCOUNTER2_LO"
9303  },
9304  {
9305   "chips": ["gfx103"],
9306   "map": {"at": 218644, "to": "mm"},
9307   "name": "PA_PH_PERFCOUNTER2_HI"
9308  },
9309  {
9310   "chips": ["gfx103"],
9311   "map": {"at": 218648, "to": "mm"},
9312   "name": "PA_PH_PERFCOUNTER3_LO"
9313  },
9314  {
9315   "chips": ["gfx103"],
9316   "map": {"at": 218652, "to": "mm"},
9317   "name": "PA_PH_PERFCOUNTER3_HI"
9318  },
9319  {
9320   "chips": ["gfx103"],
9321   "map": {"at": 218656, "to": "mm"},
9322   "name": "PA_PH_PERFCOUNTER4_LO"
9323  },
9324  {
9325   "chips": ["gfx103"],
9326   "map": {"at": 218660, "to": "mm"},
9327   "name": "PA_PH_PERFCOUNTER4_HI"
9328  },
9329  {
9330   "chips": ["gfx103"],
9331   "map": {"at": 218664, "to": "mm"},
9332   "name": "PA_PH_PERFCOUNTER5_LO"
9333  },
9334  {
9335   "chips": ["gfx103"],
9336   "map": {"at": 218668, "to": "mm"},
9337   "name": "PA_PH_PERFCOUNTER5_HI"
9338  },
9339  {
9340   "chips": ["gfx103"],
9341   "map": {"at": 218672, "to": "mm"},
9342   "name": "PA_PH_PERFCOUNTER6_LO"
9343  },
9344  {
9345   "chips": ["gfx103"],
9346   "map": {"at": 218676, "to": "mm"},
9347   "name": "PA_PH_PERFCOUNTER6_HI"
9348  },
9349  {
9350   "chips": ["gfx103"],
9351   "map": {"at": 218680, "to": "mm"},
9352   "name": "PA_PH_PERFCOUNTER7_LO"
9353  },
9354  {
9355   "chips": ["gfx103"],
9356   "map": {"at": 218684, "to": "mm"},
9357   "name": "PA_PH_PERFCOUNTER7_HI"
9358  },
9359  {
9360   "chips": ["gfx103"],
9361   "map": {"at": 218880, "to": "mm"},
9362   "name": "GL1A_PERFCOUNTER0_LO"
9363  },
9364  {
9365   "chips": ["gfx103"],
9366   "map": {"at": 218884, "to": "mm"},
9367   "name": "GL1A_PERFCOUNTER0_HI"
9368  },
9369  {
9370   "chips": ["gfx103"],
9371   "map": {"at": 218888, "to": "mm"},
9372   "name": "GL1A_PERFCOUNTER1_LO"
9373  },
9374  {
9375   "chips": ["gfx103"],
9376   "map": {"at": 218892, "to": "mm"},
9377   "name": "GL1A_PERFCOUNTER1_HI"
9378  },
9379  {
9380   "chips": ["gfx103"],
9381   "map": {"at": 218896, "to": "mm"},
9382   "name": "GL1A_PERFCOUNTER2_LO"
9383  },
9384  {
9385   "chips": ["gfx103"],
9386   "map": {"at": 218900, "to": "mm"},
9387   "name": "GL1A_PERFCOUNTER2_HI"
9388  },
9389  {
9390   "chips": ["gfx103"],
9391   "map": {"at": 218904, "to": "mm"},
9392   "name": "GL1A_PERFCOUNTER3_LO"
9393  },
9394  {
9395   "chips": ["gfx103"],
9396   "map": {"at": 218908, "to": "mm"},
9397   "name": "GL1A_PERFCOUNTER3_HI"
9398  },
9399  {
9400   "chips": ["gfx103"],
9401   "map": {"at": 219136, "to": "mm"},
9402   "name": "CHA_PERFCOUNTER0_LO"
9403  },
9404  {
9405   "chips": ["gfx103"],
9406   "map": {"at": 219140, "to": "mm"},
9407   "name": "CHA_PERFCOUNTER0_HI"
9408  },
9409  {
9410   "chips": ["gfx103"],
9411   "map": {"at": 219144, "to": "mm"},
9412   "name": "CHA_PERFCOUNTER1_LO"
9413  },
9414  {
9415   "chips": ["gfx103"],
9416   "map": {"at": 219148, "to": "mm"},
9417   "name": "CHA_PERFCOUNTER1_HI"
9418  },
9419  {
9420   "chips": ["gfx103"],
9421   "map": {"at": 219152, "to": "mm"},
9422   "name": "CHA_PERFCOUNTER2_LO"
9423  },
9424  {
9425   "chips": ["gfx103"],
9426   "map": {"at": 219156, "to": "mm"},
9427   "name": "CHA_PERFCOUNTER2_HI"
9428  },
9429  {
9430   "chips": ["gfx103"],
9431   "map": {"at": 219160, "to": "mm"},
9432   "name": "CHA_PERFCOUNTER3_LO"
9433  },
9434  {
9435   "chips": ["gfx103"],
9436   "map": {"at": 219164, "to": "mm"},
9437   "name": "CHA_PERFCOUNTER3_HI"
9438  },
9439  {
9440   "chips": ["gfx103"],
9441   "map": {"at": 219392, "to": "mm"},
9442   "name": "GUS_PERFCOUNTER2_LO"
9443  },
9444  {
9445   "chips": ["gfx103"],
9446   "map": {"at": 219396, "to": "mm"},
9447   "name": "GUS_PERFCOUNTER2_HI"
9448  },
9449  {
9450   "chips": ["gfx103"],
9451   "map": {"at": 219400, "to": "mm"},
9452   "name": "GUS_PERFCOUNTER_LO"
9453  },
9454  {
9455   "chips": ["gfx103"],
9456   "map": {"at": 219404, "to": "mm"},
9457   "name": "GUS_PERFCOUNTER_HI",
9458   "type_ref": "GCEA_PERFCOUNTER_HI"
9459  },
9460  {
9461   "chips": ["gfx103"],
9462   "map": {"at": 219520, "to": "mm"},
9463   "name": "SDMA0_PERFCNT_PERFCOUNTER_LO"
9464  },
9465  {
9466   "chips": ["gfx103"],
9467   "map": {"at": 219524, "to": "mm"},
9468   "name": "SDMA0_PERFCNT_PERFCOUNTER_HI",
9469   "type_ref": "GCEA_PERFCOUNTER_HI"
9470  },
9471  {
9472   "chips": ["gfx103"],
9473   "map": {"at": 219528, "to": "mm"},
9474   "name": "SDMA0_PERFCOUNTER0_LO"
9475  },
9476  {
9477   "chips": ["gfx103"],
9478   "map": {"at": 219532, "to": "mm"},
9479   "name": "SDMA0_PERFCOUNTER0_HI"
9480  },
9481  {
9482   "chips": ["gfx103"],
9483   "map": {"at": 219536, "to": "mm"},
9484   "name": "SDMA0_PERFCOUNTER1_LO"
9485  },
9486  {
9487   "chips": ["gfx103"],
9488   "map": {"at": 219540, "to": "mm"},
9489   "name": "SDMA0_PERFCOUNTER1_HI"
9490  },
9491  {
9492   "chips": ["gfx103"],
9493   "map": {"at": 219568, "to": "mm"},
9494   "name": "SDMA1_PERFCNT_PERFCOUNTER_LO"
9495  },
9496  {
9497   "chips": ["gfx103"],
9498   "map": {"at": 219572, "to": "mm"},
9499   "name": "SDMA1_PERFCNT_PERFCOUNTER_HI",
9500   "type_ref": "GCEA_PERFCOUNTER_HI"
9501  },
9502  {
9503   "chips": ["gfx103"],
9504   "map": {"at": 219576, "to": "mm"},
9505   "name": "SDMA1_PERFCOUNTER0_LO"
9506  },
9507  {
9508   "chips": ["gfx103"],
9509   "map": {"at": 219580, "to": "mm"},
9510   "name": "SDMA1_PERFCOUNTER0_HI"
9511  },
9512  {
9513   "chips": ["gfx103"],
9514   "map": {"at": 219584, "to": "mm"},
9515   "name": "SDMA1_PERFCOUNTER1_LO"
9516  },
9517  {
9518   "chips": ["gfx103"],
9519   "map": {"at": 219588, "to": "mm"},
9520   "name": "SDMA1_PERFCOUNTER1_HI"
9521  },
9522  {
9523   "chips": ["gfx103"],
9524   "map": {"at": 219616, "to": "mm"},
9525   "name": "SDMA2_PERFCNT_PERFCOUNTER_LO"
9526  },
9527  {
9528   "chips": ["gfx103"],
9529   "map": {"at": 219620, "to": "mm"},
9530   "name": "SDMA2_PERFCNT_PERFCOUNTER_HI",
9531   "type_ref": "GCEA_PERFCOUNTER_HI"
9532  },
9533  {
9534   "chips": ["gfx103"],
9535   "map": {"at": 219624, "to": "mm"},
9536   "name": "SDMA2_PERFCOUNTER0_LO"
9537  },
9538  {
9539   "chips": ["gfx103"],
9540   "map": {"at": 219628, "to": "mm"},
9541   "name": "SDMA2_PERFCOUNTER0_HI"
9542  },
9543  {
9544   "chips": ["gfx103"],
9545   "map": {"at": 219632, "to": "mm"},
9546   "name": "SDMA2_PERFCOUNTER1_LO"
9547  },
9548  {
9549   "chips": ["gfx103"],
9550   "map": {"at": 219636, "to": "mm"},
9551   "name": "SDMA2_PERFCOUNTER1_HI"
9552  },
9553  {
9554   "chips": ["gfx103"],
9555   "map": {"at": 219664, "to": "mm"},
9556   "name": "SDMA3_PERFCNT_PERFCOUNTER_LO"
9557  },
9558  {
9559   "chips": ["gfx103"],
9560   "map": {"at": 219668, "to": "mm"},
9561   "name": "SDMA3_PERFCNT_PERFCOUNTER_HI",
9562   "type_ref": "GCEA_PERFCOUNTER_HI"
9563  },
9564  {
9565   "chips": ["gfx103"],
9566   "map": {"at": 219672, "to": "mm"},
9567   "name": "SDMA3_PERFCOUNTER0_LO"
9568  },
9569  {
9570   "chips": ["gfx103"],
9571   "map": {"at": 219676, "to": "mm"},
9572   "name": "SDMA3_PERFCOUNTER0_HI"
9573  },
9574  {
9575   "chips": ["gfx103"],
9576   "map": {"at": 219680, "to": "mm"},
9577   "name": "SDMA3_PERFCOUNTER1_LO"
9578  },
9579  {
9580   "chips": ["gfx103"],
9581   "map": {"at": 219684, "to": "mm"},
9582   "name": "SDMA3_PERFCOUNTER1_HI"
9583  },
9584  {
9585   "chips": ["gfx103"],
9586   "map": {"at": 221184, "to": "mm"},
9587   "name": "CPG_PERFCOUNTER1_SELECT",
9588   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9589  },
9590  {
9591   "chips": ["gfx103"],
9592   "map": {"at": 221188, "to": "mm"},
9593   "name": "CPG_PERFCOUNTER0_SELECT1",
9594   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9595  },
9596  {
9597   "chips": ["gfx103"],
9598   "map": {"at": 221192, "to": "mm"},
9599   "name": "CPG_PERFCOUNTER0_SELECT",
9600   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9601  },
9602  {
9603   "chips": ["gfx103"],
9604   "map": {"at": 221196, "to": "mm"},
9605   "name": "CPC_PERFCOUNTER1_SELECT",
9606   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9607  },
9608  {
9609   "chips": ["gfx103"],
9610   "map": {"at": 221200, "to": "mm"},
9611   "name": "CPC_PERFCOUNTER0_SELECT1",
9612   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9613  },
9614  {
9615   "chips": ["gfx103"],
9616   "map": {"at": 221204, "to": "mm"},
9617   "name": "CPF_PERFCOUNTER1_SELECT",
9618   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9619  },
9620  {
9621   "chips": ["gfx103"],
9622   "map": {"at": 221208, "to": "mm"},
9623   "name": "CPF_PERFCOUNTER0_SELECT1",
9624   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9625  },
9626  {
9627   "chips": ["gfx103"],
9628   "map": {"at": 221212, "to": "mm"},
9629   "name": "CPF_PERFCOUNTER0_SELECT",
9630   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9631  },
9632  {
9633   "chips": ["gfx103"],
9634   "map": {"at": 221216, "to": "mm"},
9635   "name": "CP_PERFMON_CNTL",
9636   "type_ref": "CP_PERFMON_CNTL"
9637  },
9638  {
9639   "chips": ["gfx103"],
9640   "map": {"at": 221220, "to": "mm"},
9641   "name": "CPC_PERFCOUNTER0_SELECT",
9642   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9643  },
9644  {
9645   "chips": ["gfx103"],
9646   "map": {"at": 221224, "to": "mm"},
9647   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
9648   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
9649  },
9650  {
9651   "chips": ["gfx103"],
9652   "map": {"at": 221228, "to": "mm"},
9653   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
9654   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
9655  },
9656  {
9657   "chips": ["gfx103"],
9658   "map": {"at": 221232, "to": "mm"},
9659   "name": "CPF_LATENCY_STATS_SELECT",
9660   "type_ref": "CPF_LATENCY_STATS_SELECT"
9661  },
9662  {
9663   "chips": ["gfx103"],
9664   "map": {"at": 221236, "to": "mm"},
9665   "name": "CPG_LATENCY_STATS_SELECT",
9666   "type_ref": "CPG_LATENCY_STATS_SELECT"
9667  },
9668  {
9669   "chips": ["gfx103"],
9670   "map": {"at": 221240, "to": "mm"},
9671   "name": "CPC_LATENCY_STATS_SELECT",
9672   "type_ref": "CPF_LATENCY_STATS_SELECT"
9673  },
9674  {
9675   "chips": ["gfx103"],
9676   "map": {"at": 221248, "to": "mm"},
9677   "name": "CP_DRAW_OBJECT"
9678  },
9679  {
9680   "chips": ["gfx103"],
9681   "map": {"at": 221252, "to": "mm"},
9682   "name": "CP_DRAW_OBJECT_COUNTER",
9683   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
9684  },
9685  {
9686   "chips": ["gfx103"],
9687   "map": {"at": 221256, "to": "mm"},
9688   "name": "CP_DRAW_WINDOW_MASK_HI"
9689  },
9690  {
9691   "chips": ["gfx103"],
9692   "map": {"at": 221260, "to": "mm"},
9693   "name": "CP_DRAW_WINDOW_HI"
9694  },
9695  {
9696   "chips": ["gfx103"],
9697   "map": {"at": 221264, "to": "mm"},
9698   "name": "CP_DRAW_WINDOW_LO",
9699   "type_ref": "CP_DRAW_WINDOW_LO"
9700  },
9701  {
9702   "chips": ["gfx103"],
9703   "map": {"at": 221268, "to": "mm"},
9704   "name": "CP_DRAW_WINDOW_CNTL",
9705   "type_ref": "CP_DRAW_WINDOW_CNTL"
9706  },
9707  {
9708   "chips": ["gfx103"],
9709   "map": {"at": 221440, "to": "mm"},
9710   "name": "GRBM_PERFCOUNTER0_SELECT",
9711   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9712  },
9713  {
9714   "chips": ["gfx103"],
9715   "map": {"at": 221444, "to": "mm"},
9716   "name": "GRBM_PERFCOUNTER1_SELECT",
9717   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9718  },
9719  {
9720   "chips": ["gfx103"],
9721   "map": {"at": 221448, "to": "mm"},
9722   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
9723   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9724  },
9725  {
9726   "chips": ["gfx103"],
9727   "map": {"at": 221452, "to": "mm"},
9728   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
9729   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9730  },
9731  {
9732   "chips": ["gfx103"],
9733   "map": {"at": 221456, "to": "mm"},
9734   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
9735   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9736  },
9737  {
9738   "chips": ["gfx103"],
9739   "map": {"at": 221460, "to": "mm"},
9740   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
9741   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9742  },
9743  {
9744   "chips": ["gfx103"],
9745   "map": {"at": 221492, "to": "mm"},
9746   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
9747   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9748  },
9749  {
9750   "chips": ["gfx103"],
9751   "map": {"at": 221496, "to": "mm"},
9752   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
9753   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9754  },
9755  {
9756   "chips": ["gfx103"],
9757   "map": {"at": 221840, "to": "mm"},
9758   "name": "GE1_PERFCOUNTER0_SELECT",
9759   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9760  },
9761  {
9762   "chips": ["gfx103"],
9763   "map": {"at": 221844, "to": "mm"},
9764   "name": "GE1_PERFCOUNTER0_SELECT1",
9765   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9766  },
9767  {
9768   "chips": ["gfx103"],
9769   "map": {"at": 221848, "to": "mm"},
9770   "name": "GE1_PERFCOUNTER1_SELECT",
9771   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9772  },
9773  {
9774   "chips": ["gfx103"],
9775   "map": {"at": 221852, "to": "mm"},
9776   "name": "GE1_PERFCOUNTER1_SELECT1",
9777   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9778  },
9779  {
9780   "chips": ["gfx103"],
9781   "map": {"at": 221856, "to": "mm"},
9782   "name": "GE1_PERFCOUNTER2_SELECT",
9783   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9784  },
9785  {
9786   "chips": ["gfx103"],
9787   "map": {"at": 221860, "to": "mm"},
9788   "name": "GE1_PERFCOUNTER2_SELECT1",
9789   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9790  },
9791  {
9792   "chips": ["gfx103"],
9793   "map": {"at": 221864, "to": "mm"},
9794   "name": "GE1_PERFCOUNTER3_SELECT",
9795   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9796  },
9797  {
9798   "chips": ["gfx103"],
9799   "map": {"at": 221868, "to": "mm"},
9800   "name": "GE1_PERFCOUNTER3_SELECT1",
9801   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9802  },
9803  {
9804   "chips": ["gfx103"],
9805   "map": {"at": 221872, "to": "mm"},
9806   "name": "GE2_DIST_PERFCOUNTER0_SELECT",
9807   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9808  },
9809  {
9810   "chips": ["gfx103"],
9811   "map": {"at": 221876, "to": "mm"},
9812   "name": "GE2_DIST_PERFCOUNTER0_SELECT1",
9813   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9814  },
9815  {
9816   "chips": ["gfx103"],
9817   "map": {"at": 221880, "to": "mm"},
9818   "name": "GE2_DIST_PERFCOUNTER1_SELECT",
9819   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9820  },
9821  {
9822   "chips": ["gfx103"],
9823   "map": {"at": 221884, "to": "mm"},
9824   "name": "GE2_DIST_PERFCOUNTER1_SELECT1",
9825   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9826  },
9827  {
9828   "chips": ["gfx103"],
9829   "map": {"at": 221888, "to": "mm"},
9830   "name": "GE2_DIST_PERFCOUNTER2_SELECT",
9831   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9832  },
9833  {
9834   "chips": ["gfx103"],
9835   "map": {"at": 221892, "to": "mm"},
9836   "name": "GE2_DIST_PERFCOUNTER2_SELECT1",
9837   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9838  },
9839  {
9840   "chips": ["gfx103"],
9841   "map": {"at": 221896, "to": "mm"},
9842   "name": "GE2_DIST_PERFCOUNTER3_SELECT",
9843   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9844  },
9845  {
9846   "chips": ["gfx103"],
9847   "map": {"at": 221900, "to": "mm"},
9848   "name": "GE2_DIST_PERFCOUNTER3_SELECT1",
9849   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9850  },
9851  {
9852   "chips": ["gfx103"],
9853   "map": {"at": 221904, "to": "mm"},
9854   "name": "GE2_SE_PERFCOUNTER0_SELECT",
9855   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9856  },
9857  {
9858   "chips": ["gfx103"],
9859   "map": {"at": 221908, "to": "mm"},
9860   "name": "GE2_SE_PERFCOUNTER0_SELECT1",
9861   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9862  },
9863  {
9864   "chips": ["gfx103"],
9865   "map": {"at": 221912, "to": "mm"},
9866   "name": "GE2_SE_PERFCOUNTER1_SELECT",
9867   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9868  },
9869  {
9870   "chips": ["gfx103"],
9871   "map": {"at": 221916, "to": "mm"},
9872   "name": "GE2_SE_PERFCOUNTER1_SELECT1",
9873   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9874  },
9875  {
9876   "chips": ["gfx103"],
9877   "map": {"at": 221920, "to": "mm"},
9878   "name": "GE2_SE_PERFCOUNTER2_SELECT",
9879   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9880  },
9881  {
9882   "chips": ["gfx103"],
9883   "map": {"at": 221924, "to": "mm"},
9884   "name": "GE2_SE_PERFCOUNTER2_SELECT1",
9885   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9886  },
9887  {
9888   "chips": ["gfx103"],
9889   "map": {"at": 221928, "to": "mm"},
9890   "name": "GE2_SE_PERFCOUNTER3_SELECT",
9891   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9892  },
9893  {
9894   "chips": ["gfx103"],
9895   "map": {"at": 221932, "to": "mm"},
9896   "name": "GE2_SE_PERFCOUNTER3_SELECT1",
9897   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9898  },
9899  {
9900   "chips": ["gfx103"],
9901   "map": {"at": 222208, "to": "mm"},
9902   "name": "PA_SU_PERFCOUNTER0_SELECT",
9903   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9904  },
9905  {
9906   "chips": ["gfx103"],
9907   "map": {"at": 222212, "to": "mm"},
9908   "name": "PA_SU_PERFCOUNTER0_SELECT1",
9909   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9910  },
9911  {
9912   "chips": ["gfx103"],
9913   "map": {"at": 222216, "to": "mm"},
9914   "name": "PA_SU_PERFCOUNTER1_SELECT",
9915   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9916  },
9917  {
9918   "chips": ["gfx103"],
9919   "map": {"at": 222220, "to": "mm"},
9920   "name": "PA_SU_PERFCOUNTER1_SELECT1",
9921   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9922  },
9923  {
9924   "chips": ["gfx103"],
9925   "map": {"at": 222224, "to": "mm"},
9926   "name": "PA_SU_PERFCOUNTER2_SELECT",
9927   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9928  },
9929  {
9930   "chips": ["gfx103"],
9931   "map": {"at": 222228, "to": "mm"},
9932   "name": "PA_SU_PERFCOUNTER2_SELECT1",
9933   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9934  },
9935  {
9936   "chips": ["gfx103"],
9937   "map": {"at": 222232, "to": "mm"},
9938   "name": "PA_SU_PERFCOUNTER3_SELECT",
9939   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9940  },
9941  {
9942   "chips": ["gfx103"],
9943   "map": {"at": 222236, "to": "mm"},
9944   "name": "PA_SU_PERFCOUNTER3_SELECT1",
9945   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9946  },
9947  {
9948   "chips": ["gfx103"],
9949   "map": {"at": 222464, "to": "mm"},
9950   "name": "PA_SC_PERFCOUNTER0_SELECT",
9951   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9952  },
9953  {
9954   "chips": ["gfx103"],
9955   "map": {"at": 222468, "to": "mm"},
9956   "name": "PA_SC_PERFCOUNTER0_SELECT1",
9957   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9958  },
9959  {
9960   "chips": ["gfx103"],
9961   "map": {"at": 222472, "to": "mm"},
9962   "name": "PA_SC_PERFCOUNTER1_SELECT",
9963   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9964  },
9965  {
9966   "chips": ["gfx103"],
9967   "map": {"at": 222476, "to": "mm"},
9968   "name": "PA_SC_PERFCOUNTER2_SELECT",
9969   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9970  },
9971  {
9972   "chips": ["gfx103"],
9973   "map": {"at": 222480, "to": "mm"},
9974   "name": "PA_SC_PERFCOUNTER3_SELECT",
9975   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9976  },
9977  {
9978   "chips": ["gfx103"],
9979   "map": {"at": 222484, "to": "mm"},
9980   "name": "PA_SC_PERFCOUNTER4_SELECT",
9981   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9982  },
9983  {
9984   "chips": ["gfx103"],
9985   "map": {"at": 222488, "to": "mm"},
9986   "name": "PA_SC_PERFCOUNTER5_SELECT",
9987   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9988  },
9989  {
9990   "chips": ["gfx103"],
9991   "map": {"at": 222492, "to": "mm"},
9992   "name": "PA_SC_PERFCOUNTER6_SELECT",
9993   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9994  },
9995  {
9996   "chips": ["gfx103"],
9997   "map": {"at": 222496, "to": "mm"},
9998   "name": "PA_SC_PERFCOUNTER7_SELECT",
9999   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10000  },
10001  {
10002   "chips": ["gfx103"],
10003   "map": {"at": 222720, "to": "mm"},
10004   "name": "SPI_PERFCOUNTER0_SELECT",
10005   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10006  },
10007  {
10008   "chips": ["gfx103"],
10009   "map": {"at": 222724, "to": "mm"},
10010   "name": "SPI_PERFCOUNTER1_SELECT",
10011   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10012  },
10013  {
10014   "chips": ["gfx103"],
10015   "map": {"at": 222728, "to": "mm"},
10016   "name": "SPI_PERFCOUNTER2_SELECT",
10017   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10018  },
10019  {
10020   "chips": ["gfx103"],
10021   "map": {"at": 222732, "to": "mm"},
10022   "name": "SPI_PERFCOUNTER3_SELECT",
10023   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10024  },
10025  {
10026   "chips": ["gfx103"],
10027   "map": {"at": 222736, "to": "mm"},
10028   "name": "SPI_PERFCOUNTER0_SELECT1",
10029   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10030  },
10031  {
10032   "chips": ["gfx103"],
10033   "map": {"at": 222740, "to": "mm"},
10034   "name": "SPI_PERFCOUNTER1_SELECT1",
10035   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10036  },
10037  {
10038   "chips": ["gfx103"],
10039   "map": {"at": 222744, "to": "mm"},
10040   "name": "SPI_PERFCOUNTER2_SELECT1",
10041   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10042  },
10043  {
10044   "chips": ["gfx103"],
10045   "map": {"at": 222748, "to": "mm"},
10046   "name": "SPI_PERFCOUNTER3_SELECT1",
10047   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10048  },
10049  {
10050   "chips": ["gfx103"],
10051   "map": {"at": 222752, "to": "mm"},
10052   "name": "SPI_PERFCOUNTER4_SELECT",
10053   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10054  },
10055  {
10056   "chips": ["gfx103"],
10057   "map": {"at": 222756, "to": "mm"},
10058   "name": "SPI_PERFCOUNTER5_SELECT",
10059   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10060  },
10061  {
10062   "chips": ["gfx103"],
10063   "map": {"at": 222760, "to": "mm"},
10064   "name": "SPI_PERFCOUNTER_BINS",
10065   "type_ref": "SPI_PERFCOUNTER_BINS"
10066  },
10067  {
10068   "chips": ["gfx103"],
10069   "map": {"at": 222976, "to": "mm"},
10070   "name": "SQ_PERFCOUNTER0_SELECT",
10071   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10072  },
10073  {
10074   "chips": ["gfx103"],
10075   "map": {"at": 222980, "to": "mm"},
10076   "name": "SQ_PERFCOUNTER1_SELECT",
10077   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10078  },
10079  {
10080   "chips": ["gfx103"],
10081   "map": {"at": 222984, "to": "mm"},
10082   "name": "SQ_PERFCOUNTER2_SELECT",
10083   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10084  },
10085  {
10086   "chips": ["gfx103"],
10087   "map": {"at": 222988, "to": "mm"},
10088   "name": "SQ_PERFCOUNTER3_SELECT",
10089   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10090  },
10091  {
10092   "chips": ["gfx103"],
10093   "map": {"at": 222992, "to": "mm"},
10094   "name": "SQ_PERFCOUNTER4_SELECT",
10095   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10096  },
10097  {
10098   "chips": ["gfx103"],
10099   "map": {"at": 222996, "to": "mm"},
10100   "name": "SQ_PERFCOUNTER5_SELECT",
10101   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10102  },
10103  {
10104   "chips": ["gfx103"],
10105   "map": {"at": 223000, "to": "mm"},
10106   "name": "SQ_PERFCOUNTER6_SELECT",
10107   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10108  },
10109  {
10110   "chips": ["gfx103"],
10111   "map": {"at": 223004, "to": "mm"},
10112   "name": "SQ_PERFCOUNTER7_SELECT",
10113   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10114  },
10115  {
10116   "chips": ["gfx103"],
10117   "map": {"at": 223008, "to": "mm"},
10118   "name": "SQ_PERFCOUNTER8_SELECT",
10119   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10120  },
10121  {
10122   "chips": ["gfx103"],
10123   "map": {"at": 223012, "to": "mm"},
10124   "name": "SQ_PERFCOUNTER9_SELECT",
10125   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10126  },
10127  {
10128   "chips": ["gfx103"],
10129   "map": {"at": 223016, "to": "mm"},
10130   "name": "SQ_PERFCOUNTER10_SELECT",
10131   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10132  },
10133  {
10134   "chips": ["gfx103"],
10135   "map": {"at": 223020, "to": "mm"},
10136   "name": "SQ_PERFCOUNTER11_SELECT",
10137   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10138  },
10139  {
10140   "chips": ["gfx103"],
10141   "map": {"at": 223024, "to": "mm"},
10142   "name": "SQ_PERFCOUNTER12_SELECT",
10143   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10144  },
10145  {
10146   "chips": ["gfx103"],
10147   "map": {"at": 223028, "to": "mm"},
10148   "name": "SQ_PERFCOUNTER13_SELECT",
10149   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10150  },
10151  {
10152   "chips": ["gfx103"],
10153   "map": {"at": 223032, "to": "mm"},
10154   "name": "SQ_PERFCOUNTER14_SELECT",
10155   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10156  },
10157  {
10158   "chips": ["gfx103"],
10159   "map": {"at": 223036, "to": "mm"},
10160   "name": "SQ_PERFCOUNTER15_SELECT",
10161   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10162  },
10163  {
10164   "chips": ["gfx103"],
10165   "map": {"at": 223104, "to": "mm"},
10166   "name": "SQ_PERFCOUNTER_CTRL",
10167   "type_ref": "SQ_PERFCOUNTER_CTRL"
10168  },
10169  {
10170   "chips": ["gfx103"],
10171   "map": {"at": 223112, "to": "mm"},
10172   "name": "SQ_PERFCOUNTER_CTRL2",
10173   "type_ref": "SQ_PERFCOUNTER_CTRL2"
10174  },
10175  {
10176   "chips": ["gfx103"],
10177   "map": {"at": 223232, "to": "mm"},
10178   "name": "GCEA_PERFCOUNTER2_SELECT",
10179   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10180  },
10181  {
10182   "chips": ["gfx103"],
10183   "map": {"at": 223236, "to": "mm"},
10184   "name": "GCEA_PERFCOUNTER2_SELECT1",
10185   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10186  },
10187  {
10188   "chips": ["gfx103"],
10189   "map": {"at": 223240, "to": "mm"},
10190   "name": "GCEA_PERFCOUNTER2_MODE",
10191   "type_ref": "GCEA_PERFCOUNTER2_MODE"
10192  },
10193  {
10194   "chips": ["gfx103"],
10195   "map": {"at": 223244, "to": "mm"},
10196   "name": "GCEA_PERFCOUNTER0_CFG",
10197   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10198  },
10199  {
10200   "chips": ["gfx103"],
10201   "map": {"at": 223248, "to": "mm"},
10202   "name": "GCEA_PERFCOUNTER1_CFG",
10203   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10204  },
10205  {
10206   "chips": ["gfx103"],
10207   "map": {"at": 223252, "to": "mm"},
10208   "name": "GCEA_PERFCOUNTER_RSLT_CNTL",
10209   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
10210  },
10211  {
10212   "chips": ["gfx103"],
10213   "map": {"at": 223488, "to": "mm"},
10214   "name": "SX_PERFCOUNTER0_SELECT",
10215   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10216  },
10217  {
10218   "chips": ["gfx103"],
10219   "map": {"at": 223492, "to": "mm"},
10220   "name": "SX_PERFCOUNTER1_SELECT",
10221   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10222  },
10223  {
10224   "chips": ["gfx103"],
10225   "map": {"at": 223496, "to": "mm"},
10226   "name": "SX_PERFCOUNTER2_SELECT",
10227   "type_ref": "SX_PERFCOUNTER2_SELECT"
10228  },
10229  {
10230   "chips": ["gfx103"],
10231   "map": {"at": 223500, "to": "mm"},
10232   "name": "SX_PERFCOUNTER3_SELECT",
10233   "type_ref": "SX_PERFCOUNTER2_SELECT"
10234  },
10235  {
10236   "chips": ["gfx103"],
10237   "map": {"at": 223504, "to": "mm"},
10238   "name": "SX_PERFCOUNTER0_SELECT1",
10239   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10240  },
10241  {
10242   "chips": ["gfx103"],
10243   "map": {"at": 223508, "to": "mm"},
10244   "name": "SX_PERFCOUNTER1_SELECT1",
10245   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10246  },
10247  {
10248   "chips": ["gfx103"],
10249   "map": {"at": 223744, "to": "mm"},
10250   "name": "GDS_PERFCOUNTER0_SELECT",
10251   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10252  },
10253  {
10254   "chips": ["gfx103"],
10255   "map": {"at": 223748, "to": "mm"},
10256   "name": "GDS_PERFCOUNTER1_SELECT",
10257   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10258  },
10259  {
10260   "chips": ["gfx103"],
10261   "map": {"at": 223752, "to": "mm"},
10262   "name": "GDS_PERFCOUNTER2_SELECT",
10263   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10264  },
10265  {
10266   "chips": ["gfx103"],
10267   "map": {"at": 223756, "to": "mm"},
10268   "name": "GDS_PERFCOUNTER3_SELECT",
10269   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10270  },
10271  {
10272   "chips": ["gfx103"],
10273   "map": {"at": 223760, "to": "mm"},
10274   "name": "GDS_PERFCOUNTER0_SELECT1",
10275   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10276  },
10277  {
10278   "chips": ["gfx103"],
10279   "map": {"at": 223764, "to": "mm"},
10280   "name": "GDS_PERFCOUNTER1_SELECT1",
10281   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10282  },
10283  {
10284   "chips": ["gfx103"],
10285   "map": {"at": 223768, "to": "mm"},
10286   "name": "GDS_PERFCOUNTER2_SELECT1",
10287   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10288  },
10289  {
10290   "chips": ["gfx103"],
10291   "map": {"at": 223772, "to": "mm"},
10292   "name": "GDS_PERFCOUNTER3_SELECT1",
10293   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10294  },
10295  {
10296   "chips": ["gfx103"],
10297   "map": {"at": 224000, "to": "mm"},
10298   "name": "TA_PERFCOUNTER0_SELECT",
10299   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10300  },
10301  {
10302   "chips": ["gfx103"],
10303   "map": {"at": 224004, "to": "mm"},
10304   "name": "TA_PERFCOUNTER0_SELECT1",
10305   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10306  },
10307  {
10308   "chips": ["gfx103"],
10309   "map": {"at": 224008, "to": "mm"},
10310   "name": "TA_PERFCOUNTER1_SELECT",
10311   "type_ref": "SX_PERFCOUNTER2_SELECT"
10312  },
10313  {
10314   "chips": ["gfx103"],
10315   "map": {"at": 224256, "to": "mm"},
10316   "name": "TD_PERFCOUNTER0_SELECT",
10317   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10318  },
10319  {
10320   "chips": ["gfx103"],
10321   "map": {"at": 224260, "to": "mm"},
10322   "name": "TD_PERFCOUNTER0_SELECT1",
10323   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10324  },
10325  {
10326   "chips": ["gfx103"],
10327   "map": {"at": 224264, "to": "mm"},
10328   "name": "TD_PERFCOUNTER1_SELECT",
10329   "type_ref": "SX_PERFCOUNTER2_SELECT"
10330  },
10331  {
10332   "chips": ["gfx103"],
10333   "map": {"at": 224512, "to": "mm"},
10334   "name": "TCP_PERFCOUNTER0_SELECT",
10335   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10336  },
10337  {
10338   "chips": ["gfx103"],
10339   "map": {"at": 224516, "to": "mm"},
10340   "name": "TCP_PERFCOUNTER0_SELECT1",
10341   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10342  },
10343  {
10344   "chips": ["gfx103"],
10345   "map": {"at": 224520, "to": "mm"},
10346   "name": "TCP_PERFCOUNTER1_SELECT",
10347   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10348  },
10349  {
10350   "chips": ["gfx103"],
10351   "map": {"at": 224524, "to": "mm"},
10352   "name": "TCP_PERFCOUNTER1_SELECT1",
10353   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10354  },
10355  {
10356   "chips": ["gfx103"],
10357   "map": {"at": 224528, "to": "mm"},
10358   "name": "TCP_PERFCOUNTER2_SELECT",
10359   "type_ref": "SX_PERFCOUNTER2_SELECT"
10360  },
10361  {
10362   "chips": ["gfx103"],
10363   "map": {"at": 224532, "to": "mm"},
10364   "name": "TCP_PERFCOUNTER3_SELECT",
10365   "type_ref": "SX_PERFCOUNTER2_SELECT"
10366  },
10367  {
10368   "chips": ["gfx103"],
10369   "map": {"at": 224768, "to": "mm"},
10370   "name": "GL2C_PERFCOUNTER0_SELECT",
10371   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10372  },
10373  {
10374   "chips": ["gfx103"],
10375   "map": {"at": 224772, "to": "mm"},
10376   "name": "GL2C_PERFCOUNTER0_SELECT1",
10377   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10378  },
10379  {
10380   "chips": ["gfx103"],
10381   "map": {"at": 224776, "to": "mm"},
10382   "name": "GL2C_PERFCOUNTER1_SELECT",
10383   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10384  },
10385  {
10386   "chips": ["gfx103"],
10387   "map": {"at": 224780, "to": "mm"},
10388   "name": "GL2C_PERFCOUNTER1_SELECT1",
10389   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10390  },
10391  {
10392   "chips": ["gfx103"],
10393   "map": {"at": 224784, "to": "mm"},
10394   "name": "GL2C_PERFCOUNTER2_SELECT",
10395   "type_ref": "SX_PERFCOUNTER2_SELECT"
10396  },
10397  {
10398   "chips": ["gfx103"],
10399   "map": {"at": 224788, "to": "mm"},
10400   "name": "GL2C_PERFCOUNTER3_SELECT",
10401   "type_ref": "SX_PERFCOUNTER2_SELECT"
10402  },
10403  {
10404   "chips": ["gfx103"],
10405   "map": {"at": 224832, "to": "mm"},
10406   "name": "GL2A_PERFCOUNTER0_SELECT",
10407   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10408  },
10409  {
10410   "chips": ["gfx103"],
10411   "map": {"at": 224836, "to": "mm"},
10412   "name": "GL2A_PERFCOUNTER0_SELECT1",
10413   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10414  },
10415  {
10416   "chips": ["gfx103"],
10417   "map": {"at": 224840, "to": "mm"},
10418   "name": "GL2A_PERFCOUNTER1_SELECT",
10419   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10420  },
10421  {
10422   "chips": ["gfx103"],
10423   "map": {"at": 224844, "to": "mm"},
10424   "name": "GL2A_PERFCOUNTER1_SELECT1",
10425   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10426  },
10427  {
10428   "chips": ["gfx103"],
10429   "map": {"at": 224848, "to": "mm"},
10430   "name": "GL2A_PERFCOUNTER2_SELECT",
10431   "type_ref": "SX_PERFCOUNTER2_SELECT"
10432  },
10433  {
10434   "chips": ["gfx103"],
10435   "map": {"at": 224852, "to": "mm"},
10436   "name": "GL2A_PERFCOUNTER3_SELECT",
10437   "type_ref": "SX_PERFCOUNTER2_SELECT"
10438  },
10439  {
10440   "chips": ["gfx103"],
10441   "map": {"at": 224896, "to": "mm"},
10442   "name": "GL1C_PERFCOUNTER0_SELECT",
10443   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10444  },
10445  {
10446   "chips": ["gfx103"],
10447   "map": {"at": 224900, "to": "mm"},
10448   "name": "GL1C_PERFCOUNTER0_SELECT1",
10449   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10450  },
10451  {
10452   "chips": ["gfx103"],
10453   "map": {"at": 224904, "to": "mm"},
10454   "name": "GL1C_PERFCOUNTER1_SELECT",
10455   "type_ref": "SX_PERFCOUNTER2_SELECT"
10456  },
10457  {
10458   "chips": ["gfx103"],
10459   "map": {"at": 224908, "to": "mm"},
10460   "name": "GL1C_PERFCOUNTER2_SELECT",
10461   "type_ref": "SX_PERFCOUNTER2_SELECT"
10462  },
10463  {
10464   "chips": ["gfx103"],
10465   "map": {"at": 224912, "to": "mm"},
10466   "name": "GL1C_PERFCOUNTER3_SELECT",
10467   "type_ref": "SX_PERFCOUNTER2_SELECT"
10468  },
10469  {
10470   "chips": ["gfx103"],
10471   "map": {"at": 225024, "to": "mm"},
10472   "name": "CHC_PERFCOUNTER0_SELECT",
10473   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10474  },
10475  {
10476   "chips": ["gfx103"],
10477   "map": {"at": 225028, "to": "mm"},
10478   "name": "CHC_PERFCOUNTER0_SELECT1",
10479   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10480  },
10481  {
10482   "chips": ["gfx103"],
10483   "map": {"at": 225032, "to": "mm"},
10484   "name": "CHC_PERFCOUNTER1_SELECT",
10485   "type_ref": "SX_PERFCOUNTER2_SELECT"
10486  },
10487  {
10488   "chips": ["gfx103"],
10489   "map": {"at": 225036, "to": "mm"},
10490   "name": "CHC_PERFCOUNTER2_SELECT",
10491   "type_ref": "SX_PERFCOUNTER2_SELECT"
10492  },
10493  {
10494   "chips": ["gfx103"],
10495   "map": {"at": 225040, "to": "mm"},
10496   "name": "CHC_PERFCOUNTER3_SELECT",
10497   "type_ref": "SX_PERFCOUNTER2_SELECT"
10498  },
10499  {
10500   "chips": ["gfx103"],
10501   "map": {"at": 225048, "to": "mm"},
10502   "name": "CHCG_PERFCOUNTER0_SELECT",
10503   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10504  },
10505  {
10506   "chips": ["gfx103"],
10507   "map": {"at": 225052, "to": "mm"},
10508   "name": "CHCG_PERFCOUNTER0_SELECT1",
10509   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10510  },
10511  {
10512   "chips": ["gfx103"],
10513   "map": {"at": 225056, "to": "mm"},
10514   "name": "CHCG_PERFCOUNTER1_SELECT",
10515   "type_ref": "SX_PERFCOUNTER2_SELECT"
10516  },
10517  {
10518   "chips": ["gfx103"],
10519   "map": {"at": 225060, "to": "mm"},
10520   "name": "CHCG_PERFCOUNTER2_SELECT",
10521   "type_ref": "SX_PERFCOUNTER2_SELECT"
10522  },
10523  {
10524   "chips": ["gfx103"],
10525   "map": {"at": 225064, "to": "mm"},
10526   "name": "CHCG_PERFCOUNTER3_SELECT",
10527   "type_ref": "SX_PERFCOUNTER2_SELECT"
10528  },
10529  {
10530   "chips": ["gfx103"],
10531   "map": {"at": 225280, "to": "mm"},
10532   "name": "CB_PERFCOUNTER_FILTER",
10533   "type_ref": "CB_PERFCOUNTER_FILTER"
10534  },
10535  {
10536   "chips": ["gfx103"],
10537   "map": {"at": 225284, "to": "mm"},
10538   "name": "CB_PERFCOUNTER0_SELECT",
10539   "type_ref": "CB_PERFCOUNTER0_SELECT"
10540  },
10541  {
10542   "chips": ["gfx103"],
10543   "map": {"at": 225288, "to": "mm"},
10544   "name": "CB_PERFCOUNTER0_SELECT1",
10545   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10546  },
10547  {
10548   "chips": ["gfx103"],
10549   "map": {"at": 225292, "to": "mm"},
10550   "name": "CB_PERFCOUNTER1_SELECT",
10551   "type_ref": "CB_PERFCOUNTER1_SELECT"
10552  },
10553  {
10554   "chips": ["gfx103"],
10555   "map": {"at": 225296, "to": "mm"},
10556   "name": "CB_PERFCOUNTER2_SELECT",
10557   "type_ref": "CB_PERFCOUNTER1_SELECT"
10558  },
10559  {
10560   "chips": ["gfx103"],
10561   "map": {"at": 225300, "to": "mm"},
10562   "name": "CB_PERFCOUNTER3_SELECT",
10563   "type_ref": "CB_PERFCOUNTER1_SELECT"
10564  },
10565  {
10566   "chips": ["gfx103"],
10567   "map": {"at": 225536, "to": "mm"},
10568   "name": "DB_PERFCOUNTER0_SELECT",
10569   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10570  },
10571  {
10572   "chips": ["gfx103"],
10573   "map": {"at": 225540, "to": "mm"},
10574   "name": "DB_PERFCOUNTER0_SELECT1",
10575   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10576  },
10577  {
10578   "chips": ["gfx103"],
10579   "map": {"at": 225544, "to": "mm"},
10580   "name": "DB_PERFCOUNTER1_SELECT",
10581   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10582  },
10583  {
10584   "chips": ["gfx103"],
10585   "map": {"at": 225548, "to": "mm"},
10586   "name": "DB_PERFCOUNTER1_SELECT1",
10587   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10588  },
10589  {
10590   "chips": ["gfx103"],
10591   "map": {"at": 225552, "to": "mm"},
10592   "name": "DB_PERFCOUNTER2_SELECT",
10593   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10594  },
10595  {
10596   "chips": ["gfx103"],
10597   "map": {"at": 225560, "to": "mm"},
10598   "name": "DB_PERFCOUNTER3_SELECT",
10599   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10600  },
10601  {
10602   "chips": ["gfx103"],
10603   "map": {"at": 225792, "to": "mm"},
10604   "name": "RLC_SPM_PERFMON_CNTL",
10605   "type_ref": "RLC_SPM_PERFMON_CNTL"
10606  },
10607  {
10608   "chips": ["gfx103"],
10609   "map": {"at": 225796, "to": "mm"},
10610   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
10611  },
10612  {
10613   "chips": ["gfx103"],
10614   "map": {"at": 225800, "to": "mm"},
10615   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
10616   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
10617  },
10618  {
10619   "chips": ["gfx103"],
10620   "map": {"at": 225804, "to": "mm"},
10621   "name": "RLC_SPM_PERFMON_RING_SIZE"
10622  },
10623  {
10624   "chips": ["gfx103"],
10625   "map": {"at": 225808, "to": "mm"},
10626   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
10627   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
10628  },
10629  {
10630   "chips": ["gfx103"],
10631   "map": {"at": 225812, "to": "mm"},
10632   "name": "RLC_SPM_RING_RDPTR"
10633  },
10634  {
10635   "chips": ["gfx103"],
10636   "map": {"at": 225816, "to": "mm"},
10637   "name": "RLC_SPM_SEGMENT_THRESHOLD",
10638   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
10639  },
10640  {
10641   "chips": ["gfx103"],
10642   "map": {"at": 225820, "to": "mm"},
10643   "name": "RLC_SPM_SE_MUXSEL_ADDR",
10644   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
10645  },
10646  {
10647   "chips": ["gfx103"],
10648   "map": {"at": 225824, "to": "mm"},
10649   "name": "RLC_SPM_SE_MUXSEL_DATA"
10650  },
10651  {
10652   "chips": ["gfx103"],
10653   "map": {"at": 225828, "to": "mm"},
10654   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
10655   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
10656  },
10657  {
10658   "chips": ["gfx103"],
10659   "map": {"at": 225832, "to": "mm"},
10660   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
10661  },
10662  {
10663   "chips": ["gfx103"],
10664   "map": {"at": 225836, "to": "mm"},
10665   "name": "RLC_SPM_DESER_START_SKEW",
10666   "type_ref": "RLC_SPM_DESER_START_SKEW"
10667  },
10668  {
10669   "chips": ["gfx103"],
10670   "map": {"at": 225840, "to": "mm"},
10671   "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
10672   "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
10673  },
10674  {
10675   "chips": ["gfx103"],
10676   "map": {"at": 225844, "to": "mm"},
10677   "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
10678   "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
10679  },
10680  {
10681   "chips": ["gfx103"],
10682   "map": {"at": 225848, "to": "mm"},
10683   "name": "RLC_SPM_SE_SAMPLE_SKEW",
10684   "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
10685  },
10686  {
10687   "chips": ["gfx103"],
10688   "map": {"at": 225852, "to": "mm"},
10689   "name": "RLC_SPM_SE_MUXSEL_SKEW",
10690   "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
10691  },
10692  {
10693   "chips": ["gfx103"],
10694   "map": {"at": 225856, "to": "mm"},
10695   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
10696  },
10697  {
10698   "chips": ["gfx103"],
10699   "map": {"at": 225860, "to": "mm"},
10700   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
10701   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
10702  },
10703  {
10704   "chips": ["gfx103"],
10705   "map": {"at": 225864, "to": "mm"},
10706   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
10707  },
10708  {
10709   "chips": ["gfx103"],
10710   "map": {"at": 225868, "to": "mm"},
10711   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
10712   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
10713  },
10714  {
10715   "chips": ["gfx103"],
10716   "map": {"at": 225872, "to": "mm"},
10717   "name": "RLC_SPM_RING_WRPTR",
10718   "type_ref": "RLC_SPM_RING_WRPTR"
10719  },
10720  {
10721   "chips": ["gfx103"],
10722   "map": {"at": 225876, "to": "mm"},
10723   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
10724   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10725  },
10726  {
10727   "chips": ["gfx103"],
10728   "map": {"at": 225880, "to": "mm"},
10729   "name": "RLC_SPM_ACCUM_DATARAM_DATA"
10730  },
10731  {
10732   "chips": ["gfx103"],
10733   "map": {"at": 225884, "to": "mm"},
10734   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
10735   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
10736  },
10737  {
10738   "chips": ["gfx103"],
10739   "map": {"at": 225888, "to": "mm"},
10740   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
10741   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
10742  },
10743  {
10744   "chips": ["gfx103"],
10745   "map": {"at": 225892, "to": "mm"},
10746   "name": "RLC_SPM_ACCUM_STATUS",
10747   "type_ref": "RLC_SPM_ACCUM_STATUS"
10748  },
10749  {
10750   "chips": ["gfx103"],
10751   "map": {"at": 225896, "to": "mm"},
10752   "name": "RLC_SPM_ACCUM_CTRL",
10753   "type_ref": "RLC_SPM_ACCUM_CTRL"
10754  },
10755  {
10756   "chips": ["gfx103"],
10757   "map": {"at": 225900, "to": "mm"},
10758   "name": "RLC_SPM_ACCUM_MODE",
10759   "type_ref": "RLC_SPM_ACCUM_MODE"
10760  },
10761  {
10762   "chips": ["gfx103"],
10763   "map": {"at": 225904, "to": "mm"},
10764   "name": "RLC_SPM_ACCUM_THRESHOLD",
10765   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
10766  },
10767  {
10768   "chips": ["gfx103"],
10769   "map": {"at": 225908, "to": "mm"},
10770   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
10771   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
10772  },
10773  {
10774   "chips": ["gfx103"],
10775   "map": {"at": 225912, "to": "mm"},
10776   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
10777   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
10778  },
10779  {
10780   "chips": ["gfx103"],
10781   "map": {"at": 225916, "to": "mm"},
10782   "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
10783   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
10784  },
10785  {
10786   "chips": ["gfx103"],
10787   "map": {"at": 225920, "to": "mm"},
10788   "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
10789   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
10790  },
10791  {
10792   "chips": ["gfx103"],
10793   "map": {"at": 225924, "to": "mm"},
10794   "name": "RLC_SPM_VIRT_CTRL",
10795   "type_ref": "RLC_SPM_VIRT_CTRL"
10796  },
10797  {
10798   "chips": ["gfx103"],
10799   "map": {"at": 225928, "to": "mm"},
10800   "name": "RLC_SPM_PERFMON_SWA_SEGMENT_SIZE",
10801   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
10802  },
10803  {
10804   "chips": ["gfx103"],
10805   "map": {"at": 225932, "to": "mm"},
10806   "name": "RLC_SPM_VIRT_STATUS",
10807   "type_ref": "RLC_SPM_VIRT_STATUS"
10808  },
10809  {
10810   "chips": ["gfx103"],
10811   "map": {"at": 225936, "to": "mm"},
10812   "name": "RLC_SPM_GFXCLOCK_HIGHCOUNT"
10813  },
10814  {
10815   "chips": ["gfx103"],
10816   "map": {"at": 225940, "to": "mm"},
10817   "name": "RLC_SPM_GFXCLOCK_LOWCOUNT"
10818  },
10819  {
10820   "chips": ["gfx103"],
10821   "map": {"at": 225944, "to": "mm"},
10822   "name": "RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE",
10823   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
10824  },
10825  {
10826   "chips": ["gfx103"],
10827   "map": {"at": 225948, "to": "mm"},
10828   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET",
10829   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
10830  },
10831  {
10832   "chips": ["gfx103"],
10833   "map": {"at": 225952, "to": "mm"},
10834   "name": "RLC_SPM_SE_MUXSEL_ADDR_OFFSET",
10835   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
10836  },
10837  {
10838   "chips": ["gfx103"],
10839   "map": {"at": 225956, "to": "mm"},
10840   "name": "RLC_SPM_ACCUM_SWA_DATARAM_ADDR",
10841   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10842  },
10843  {
10844   "chips": ["gfx103"],
10845   "map": {"at": 225960, "to": "mm"},
10846   "name": "RLC_SPM_ACCUM_SWA_DATARAM_DATA"
10847  },
10848  {
10849   "chips": ["gfx103"],
10850   "map": {"at": 225964, "to": "mm"},
10851   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET",
10852   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET"
10853  },
10854  {
10855   "chips": ["gfx103"],
10856   "map": {"at": 225968, "to": "mm"},
10857   "name": "RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE",
10858   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
10859  },
10860  {
10861   "chips": ["gfx103"],
10862   "map": {"at": 225972, "to": "mm"},
10863   "name": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS",
10864   "type_ref": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS"
10865  },
10866  {
10867   "chips": ["gfx103"],
10868   "map": {"at": 226048, "to": "mm"},
10869   "name": "RLC_PERFMON_CNTL",
10870   "type_ref": "RLC_PERFMON_CNTL"
10871  },
10872  {
10873   "chips": ["gfx103"],
10874   "map": {"at": 226052, "to": "mm"},
10875   "name": "RLC_PERFCOUNTER0_SELECT",
10876   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10877  },
10878  {
10879   "chips": ["gfx103"],
10880   "map": {"at": 226056, "to": "mm"},
10881   "name": "RLC_PERFCOUNTER1_SELECT",
10882   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10883  },
10884  {
10885   "chips": ["gfx103"],
10886   "map": {"at": 226060, "to": "mm"},
10887   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
10888   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
10889  },
10890  {
10891   "chips": ["gfx103"],
10892   "map": {"at": 226064, "to": "mm"},
10893   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
10894   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10895  },
10896  {
10897   "chips": ["gfx103"],
10898   "map": {"at": 226068, "to": "mm"},
10899   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA"
10900  },
10901  {
10902   "chips": ["gfx103"],
10903   "map": {"at": 226072, "to": "mm"},
10904   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
10905   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10906  },
10907  {
10908   "chips": ["gfx103"],
10909   "map": {"at": 226076, "to": "mm"},
10910   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA"
10911  },
10912  {
10913   "chips": ["gfx103"],
10914   "map": {"at": 226192, "to": "mm"},
10915   "name": "RLC_PERFMON_CLK_CNTL",
10916   "type_ref": "RLC_PERFMON_CLK_CNTL"
10917  },
10918  {
10919   "chips": ["gfx103"],
10920   "map": {"at": 226304, "to": "mm"},
10921   "name": "RMI_PERFCOUNTER0_SELECT",
10922   "type_ref": "CB_PERFCOUNTER0_SELECT"
10923  },
10924  {
10925   "chips": ["gfx103"],
10926   "map": {"at": 226308, "to": "mm"},
10927   "name": "RMI_PERFCOUNTER0_SELECT1",
10928   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10929  },
10930  {
10931   "chips": ["gfx103"],
10932   "map": {"at": 226312, "to": "mm"},
10933   "name": "RMI_PERFCOUNTER1_SELECT",
10934   "type_ref": "CB_PERFCOUNTER1_SELECT"
10935  },
10936  {
10937   "chips": ["gfx103"],
10938   "map": {"at": 226316, "to": "mm"},
10939   "name": "RMI_PERFCOUNTER2_SELECT",
10940   "type_ref": "CB_PERFCOUNTER0_SELECT"
10941  },
10942  {
10943   "chips": ["gfx103"],
10944   "map": {"at": 226320, "to": "mm"},
10945   "name": "RMI_PERFCOUNTER2_SELECT1",
10946   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10947  },
10948  {
10949   "chips": ["gfx103"],
10950   "map": {"at": 226324, "to": "mm"},
10951   "name": "RMI_PERFCOUNTER3_SELECT",
10952   "type_ref": "CB_PERFCOUNTER1_SELECT"
10953  },
10954  {
10955   "chips": ["gfx103"],
10956   "map": {"at": 226328, "to": "mm"},
10957   "name": "RMI_PERF_COUNTER_CNTL",
10958   "type_ref": "RMI_PERF_COUNTER_CNTL"
10959  },
10960  {
10961   "chips": ["gfx103"],
10962   "map": {"at": 226480, "to": "mm"},
10963   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
10964   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10965  },
10966  {
10967   "chips": ["gfx103"],
10968   "map": {"at": 226484, "to": "mm"},
10969   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
10970   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10971  },
10972  {
10973   "chips": ["gfx103"],
10974   "map": {"at": 226488, "to": "mm"},
10975   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
10976   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10977  },
10978  {
10979   "chips": ["gfx103"],
10980   "map": {"at": 226492, "to": "mm"},
10981   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
10982   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10983  },
10984  {
10985   "chips": ["gfx103"],
10986   "map": {"at": 226496, "to": "mm"},
10987   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
10988   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10989  },
10990  {
10991   "chips": ["gfx103"],
10992   "map": {"at": 226500, "to": "mm"},
10993   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
10994   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10995  },
10996  {
10997   "chips": ["gfx103"],
10998   "map": {"at": 226504, "to": "mm"},
10999   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
11000   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11001  },
11002  {
11003   "chips": ["gfx103"],
11004   "map": {"at": 226508, "to": "mm"},
11005   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
11006   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11007  },
11008  {
11009   "chips": ["gfx103"],
11010   "map": {"at": 226512, "to": "mm"},
11011   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
11012   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11013  },
11014  {
11015   "chips": ["gfx103"],
11016   "map": {"at": 226516, "to": "mm"},
11017   "name": "GCUTCL2_PERFCOUNTER0_CFG",
11018   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11019  },
11020  {
11021   "chips": ["gfx103"],
11022   "map": {"at": 226520, "to": "mm"},
11023   "name": "GCUTCL2_PERFCOUNTER1_CFG",
11024   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11025  },
11026  {
11027   "chips": ["gfx103"],
11028   "map": {"at": 226524, "to": "mm"},
11029   "name": "GCUTCL2_PERFCOUNTER2_CFG",
11030   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11031  },
11032  {
11033   "chips": ["gfx103"],
11034   "map": {"at": 226528, "to": "mm"},
11035   "name": "GCUTCL2_PERFCOUNTER3_CFG",
11036   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11037  },
11038  {
11039   "chips": ["gfx103"],
11040   "map": {"at": 226532, "to": "mm"},
11041   "name": "GCUTCL2_PERFCOUNTER_RSLT_CNTL",
11042   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11043  },
11044  {
11045   "chips": ["gfx103"],
11046   "map": {"at": 226544, "to": "mm"},
11047   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
11048   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11049  },
11050  {
11051   "chips": ["gfx103"],
11052   "map": {"at": 226548, "to": "mm"},
11053   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
11054   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11055  },
11056  {
11057   "chips": ["gfx103"],
11058   "map": {"at": 226552, "to": "mm"},
11059   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
11060   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11061  },
11062  {
11063   "chips": ["gfx103"],
11064   "map": {"at": 226556, "to": "mm"},
11065   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
11066   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11067  },
11068  {
11069   "chips": ["gfx103"],
11070   "map": {"at": 226560, "to": "mm"},
11071   "name": "GCVML2_PERFCOUNTER2_0_MODE",
11072   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11073  },
11074  {
11075   "chips": ["gfx103"],
11076   "map": {"at": 226564, "to": "mm"},
11077   "name": "GCVML2_PERFCOUNTER2_1_MODE",
11078   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11079  },
11080  {
11081   "chips": ["gfx103"],
11082   "map": {"at": 226688, "to": "mm"},
11083   "name": "GCR_PERFCOUNTER0_SELECT",
11084   "type_ref": "CB_PERFCOUNTER0_SELECT"
11085  },
11086  {
11087   "chips": ["gfx103"],
11088   "map": {"at": 226692, "to": "mm"},
11089   "name": "GCR_PERFCOUNTER0_SELECT1",
11090   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11091  },
11092  {
11093   "chips": ["gfx103"],
11094   "map": {"at": 226696, "to": "mm"},
11095   "name": "GCR_PERFCOUNTER1_SELECT",
11096   "type_ref": "GCR_PERFCOUNTER1_SELECT"
11097  },
11098  {
11099   "chips": ["gfx103"],
11100   "map": {"at": 226700, "to": "mm"},
11101   "name": "UTCL1_PERFCOUNTER0_SELECT",
11102   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11103  },
11104  {
11105   "chips": ["gfx103"],
11106   "map": {"at": 226704, "to": "mm"},
11107   "name": "UTCL1_PERFCOUNTER1_SELECT",
11108   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11109  },
11110  {
11111   "chips": ["gfx103"],
11112   "map": {"at": 226816, "to": "mm"},
11113   "name": "PA_PH_PERFCOUNTER0_SELECT",
11114   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11115  },
11116  {
11117   "chips": ["gfx103"],
11118   "map": {"at": 226820, "to": "mm"},
11119   "name": "PA_PH_PERFCOUNTER0_SELECT1",
11120   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11121  },
11122  {
11123   "chips": ["gfx103"],
11124   "map": {"at": 226824, "to": "mm"},
11125   "name": "PA_PH_PERFCOUNTER1_SELECT",
11126   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11127  },
11128  {
11129   "chips": ["gfx103"],
11130   "map": {"at": 226828, "to": "mm"},
11131   "name": "PA_PH_PERFCOUNTER2_SELECT",
11132   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11133  },
11134  {
11135   "chips": ["gfx103"],
11136   "map": {"at": 226832, "to": "mm"},
11137   "name": "PA_PH_PERFCOUNTER3_SELECT",
11138   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11139  },
11140  {
11141   "chips": ["gfx103"],
11142   "map": {"at": 226836, "to": "mm"},
11143   "name": "PA_PH_PERFCOUNTER4_SELECT",
11144   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11145  },
11146  {
11147   "chips": ["gfx103"],
11148   "map": {"at": 226840, "to": "mm"},
11149   "name": "PA_PH_PERFCOUNTER5_SELECT",
11150   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11151  },
11152  {
11153   "chips": ["gfx103"],
11154   "map": {"at": 226844, "to": "mm"},
11155   "name": "PA_PH_PERFCOUNTER6_SELECT",
11156   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11157  },
11158  {
11159   "chips": ["gfx103"],
11160   "map": {"at": 226848, "to": "mm"},
11161   "name": "PA_PH_PERFCOUNTER7_SELECT",
11162   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11163  },
11164  {
11165   "chips": ["gfx103"],
11166   "map": {"at": 226880, "to": "mm"},
11167   "name": "PA_PH_PERFCOUNTER1_SELECT1",
11168   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11169  },
11170  {
11171   "chips": ["gfx103"],
11172   "map": {"at": 226884, "to": "mm"},
11173   "name": "PA_PH_PERFCOUNTER2_SELECT1",
11174   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11175  },
11176  {
11177   "chips": ["gfx103"],
11178   "map": {"at": 226888, "to": "mm"},
11179   "name": "PA_PH_PERFCOUNTER3_SELECT1",
11180   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11181  },
11182  {
11183   "chips": ["gfx103"],
11184   "map": {"at": 227072, "to": "mm"},
11185   "name": "GL1A_PERFCOUNTER0_SELECT",
11186   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11187  },
11188  {
11189   "chips": ["gfx103"],
11190   "map": {"at": 227076, "to": "mm"},
11191   "name": "GL1A_PERFCOUNTER0_SELECT1",
11192   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11193  },
11194  {
11195   "chips": ["gfx103"],
11196   "map": {"at": 227080, "to": "mm"},
11197   "name": "GL1A_PERFCOUNTER1_SELECT",
11198   "type_ref": "SX_PERFCOUNTER2_SELECT"
11199  },
11200  {
11201   "chips": ["gfx103"],
11202   "map": {"at": 227084, "to": "mm"},
11203   "name": "GL1A_PERFCOUNTER2_SELECT",
11204   "type_ref": "SX_PERFCOUNTER2_SELECT"
11205  },
11206  {
11207   "chips": ["gfx103"],
11208   "map": {"at": 227088, "to": "mm"},
11209   "name": "GL1A_PERFCOUNTER3_SELECT",
11210   "type_ref": "SX_PERFCOUNTER2_SELECT"
11211  },
11212  {
11213   "chips": ["gfx103"],
11214   "map": {"at": 227200, "to": "mm"},
11215   "name": "CHA_PERFCOUNTER0_SELECT",
11216   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11217  },
11218  {
11219   "chips": ["gfx103"],
11220   "map": {"at": 227204, "to": "mm"},
11221   "name": "CHA_PERFCOUNTER0_SELECT1",
11222   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11223  },
11224  {
11225   "chips": ["gfx103"],
11226   "map": {"at": 227208, "to": "mm"},
11227   "name": "CHA_PERFCOUNTER1_SELECT",
11228   "type_ref": "SX_PERFCOUNTER2_SELECT"
11229  },
11230  {
11231   "chips": ["gfx103"],
11232   "map": {"at": 227212, "to": "mm"},
11233   "name": "CHA_PERFCOUNTER2_SELECT",
11234   "type_ref": "SX_PERFCOUNTER2_SELECT"
11235  },
11236  {
11237   "chips": ["gfx103"],
11238   "map": {"at": 227216, "to": "mm"},
11239   "name": "CHA_PERFCOUNTER3_SELECT",
11240   "type_ref": "SX_PERFCOUNTER2_SELECT"
11241  },
11242  {
11243   "chips": ["gfx103"],
11244   "map": {"at": 227328, "to": "mm"},
11245   "name": "GUS_PERFCOUNTER2_SELECT",
11246   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11247  },
11248  {
11249   "chips": ["gfx103"],
11250   "map": {"at": 227332, "to": "mm"},
11251   "name": "GUS_PERFCOUNTER2_SELECT1",
11252   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11253  },
11254  {
11255   "chips": ["gfx103"],
11256   "map": {"at": 227336, "to": "mm"},
11257   "name": "GUS_PERFCOUNTER2_MODE",
11258   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11259  },
11260  {
11261   "chips": ["gfx103"],
11262   "map": {"at": 227340, "to": "mm"},
11263   "name": "GUS_PERFCOUNTER0_CFG",
11264   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11265  },
11266  {
11267   "chips": ["gfx103"],
11268   "map": {"at": 227344, "to": "mm"},
11269   "name": "GUS_PERFCOUNTER1_CFG",
11270   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11271  },
11272  {
11273   "chips": ["gfx103"],
11274   "map": {"at": 227348, "to": "mm"},
11275   "name": "GUS_PERFCOUNTER_RSLT_CNTL",
11276   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11277  },
11278  {
11279   "chips": ["gfx103"],
11280   "map": {"at": 227456, "to": "mm"},
11281   "name": "SDMA0_PERFCNT_PERFCOUNTER0_CFG",
11282   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11283  },
11284  {
11285   "chips": ["gfx103"],
11286   "map": {"at": 227460, "to": "mm"},
11287   "name": "SDMA0_PERFCNT_PERFCOUNTER1_CFG",
11288   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11289  },
11290  {
11291   "chips": ["gfx103"],
11292   "map": {"at": 227464, "to": "mm"},
11293   "name": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11294   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11295  },
11296  {
11297   "chips": ["gfx103"],
11298   "map": {"at": 227468, "to": "mm"},
11299   "name": "SDMA0_PERFCNT_MISC_CNTL",
11300   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11301  },
11302  {
11303   "chips": ["gfx103"],
11304   "map": {"at": 227472, "to": "mm"},
11305   "name": "SDMA0_PERFCOUNTER0_SELECT",
11306   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11307  },
11308  {
11309   "chips": ["gfx103"],
11310   "map": {"at": 227476, "to": "mm"},
11311   "name": "SDMA0_PERFCOUNTER0_SELECT1",
11312   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11313  },
11314  {
11315   "chips": ["gfx103"],
11316   "map": {"at": 227480, "to": "mm"},
11317   "name": "SDMA0_PERFCOUNTER1_SELECT",
11318   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11319  },
11320  {
11321   "chips": ["gfx103"],
11322   "map": {"at": 227484, "to": "mm"},
11323   "name": "SDMA0_PERFCOUNTER1_SELECT1",
11324   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11325  },
11326  {
11327   "chips": ["gfx103"],
11328   "map": {"at": 227504, "to": "mm"},
11329   "name": "SDMA1_PERFCNT_PERFCOUNTER0_CFG",
11330   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11331  },
11332  {
11333   "chips": ["gfx103"],
11334   "map": {"at": 227508, "to": "mm"},
11335   "name": "SDMA1_PERFCNT_PERFCOUNTER1_CFG",
11336   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11337  },
11338  {
11339   "chips": ["gfx103"],
11340   "map": {"at": 227512, "to": "mm"},
11341   "name": "SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11342   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11343  },
11344  {
11345   "chips": ["gfx103"],
11346   "map": {"at": 227516, "to": "mm"},
11347   "name": "SDMA1_PERFCNT_MISC_CNTL",
11348   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11349  },
11350  {
11351   "chips": ["gfx103"],
11352   "map": {"at": 227520, "to": "mm"},
11353   "name": "SDMA1_PERFCOUNTER0_SELECT",
11354   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11355  },
11356  {
11357   "chips": ["gfx103"],
11358   "map": {"at": 227524, "to": "mm"},
11359   "name": "SDMA1_PERFCOUNTER0_SELECT1",
11360   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11361  },
11362  {
11363   "chips": ["gfx103"],
11364   "map": {"at": 227528, "to": "mm"},
11365   "name": "SDMA1_PERFCOUNTER1_SELECT",
11366   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11367  },
11368  {
11369   "chips": ["gfx103"],
11370   "map": {"at": 227532, "to": "mm"},
11371   "name": "SDMA1_PERFCOUNTER1_SELECT1",
11372   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11373  },
11374  {
11375   "chips": ["gfx103"],
11376   "map": {"at": 227552, "to": "mm"},
11377   "name": "SDMA2_PERFCNT_PERFCOUNTER0_CFG",
11378   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11379  },
11380  {
11381   "chips": ["gfx103"],
11382   "map": {"at": 227556, "to": "mm"},
11383   "name": "SDMA2_PERFCNT_PERFCOUNTER1_CFG",
11384   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11385  },
11386  {
11387   "chips": ["gfx103"],
11388   "map": {"at": 227560, "to": "mm"},
11389   "name": "SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11390   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11391  },
11392  {
11393   "chips": ["gfx103"],
11394   "map": {"at": 227564, "to": "mm"},
11395   "name": "SDMA2_PERFCNT_MISC_CNTL",
11396   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11397  },
11398  {
11399   "chips": ["gfx103"],
11400   "map": {"at": 227568, "to": "mm"},
11401   "name": "SDMA2_PERFCOUNTER0_SELECT",
11402   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11403  },
11404  {
11405   "chips": ["gfx103"],
11406   "map": {"at": 227572, "to": "mm"},
11407   "name": "SDMA2_PERFCOUNTER0_SELECT1",
11408   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11409  },
11410  {
11411   "chips": ["gfx103"],
11412   "map": {"at": 227576, "to": "mm"},
11413   "name": "SDMA2_PERFCOUNTER1_SELECT",
11414   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11415  },
11416  {
11417   "chips": ["gfx103"],
11418   "map": {"at": 227580, "to": "mm"},
11419   "name": "SDMA2_PERFCOUNTER1_SELECT1",
11420   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11421  },
11422  {
11423   "chips": ["gfx103"],
11424   "map": {"at": 227600, "to": "mm"},
11425   "name": "SDMA3_PERFCNT_PERFCOUNTER0_CFG",
11426   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11427  },
11428  {
11429   "chips": ["gfx103"],
11430   "map": {"at": 227604, "to": "mm"},
11431   "name": "SDMA3_PERFCNT_PERFCOUNTER1_CFG",
11432   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11433  },
11434  {
11435   "chips": ["gfx103"],
11436   "map": {"at": 227608, "to": "mm"},
11437   "name": "SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11438   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11439  },
11440  {
11441   "chips": ["gfx103"],
11442   "map": {"at": 227612, "to": "mm"},
11443   "name": "SDMA3_PERFCNT_MISC_CNTL",
11444   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11445  },
11446  {
11447   "chips": ["gfx103"],
11448   "map": {"at": 227616, "to": "mm"},
11449   "name": "SDMA3_PERFCOUNTER0_SELECT",
11450   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11451  },
11452  {
11453   "chips": ["gfx103"],
11454   "map": {"at": 227620, "to": "mm"},
11455   "name": "SDMA3_PERFCOUNTER0_SELECT1",
11456   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11457  },
11458  {
11459   "chips": ["gfx103"],
11460   "map": {"at": 227624, "to": "mm"},
11461   "name": "SDMA3_PERFCOUNTER1_SELECT",
11462   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11463  },
11464  {
11465   "chips": ["gfx103"],
11466   "map": {"at": 227628, "to": "mm"},
11467   "name": "SDMA3_PERFCOUNTER1_SELECT1",
11468   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11469  }
11470 ],
11471 "register_types": {
11472  "CB_BLEND0_CONTROL": {
11473   "fields": [
11474    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11475    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11476    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11477    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11478    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11479    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11480    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
11481    {"bits": [30, 30], "name": "ENABLE"},
11482    {"bits": [31, 31], "name": "DISABLE_ROP3"}
11483   ]
11484  },
11485  "CB_COLOR0_ATTRIB": {
11486   "fields": [
11487    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
11488    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
11489    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
11490    {"bits": [12, 14], "name": "NUM_SAMPLES"},
11491    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
11492    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
11493    {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
11494    {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
11495   ]
11496  },
11497  "CB_COLOR0_ATTRIB2": {
11498   "fields": [
11499    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
11500    {"bits": [14, 27], "name": "MIP0_WIDTH"},
11501    {"bits": [28, 31], "name": "MAX_MIP"}
11502   ]
11503  },
11504  "CB_COLOR0_ATTRIB3": {
11505   "fields": [
11506    {"bits": [0, 12], "name": "MIP0_DEPTH"},
11507    {"bits": [13, 13], "name": "META_LINEAR"},
11508    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
11509    {"bits": [19, 23], "name": "FMASK_SW_MODE"},
11510    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
11511    {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
11512    {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
11513    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"},
11514    {"bits": [31, 31], "name": "VRS_RATE_HINT_ENABLE"}
11515   ]
11516  },
11517  "CB_COLOR0_BASE_EXT": {
11518   "fields": [
11519    {"bits": [0, 7], "name": "BASE_256B"}
11520   ]
11521  },
11522  "CB_COLOR0_CMASK_SLICE": {
11523   "fields": [
11524    {"bits": [0, 13], "name": "TILE_MAX"}
11525   ]
11526  },
11527  "CB_COLOR0_DCC_CONTROL": {
11528   "fields": [
11529    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11530    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
11531    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11532    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11533    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
11534    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
11535    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
11536    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
11537    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
11538    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11539    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
11540    {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"},
11541    {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"},
11542    {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE"}
11543   ]
11544  },
11545  "CB_COLOR0_INFO": {
11546   "fields": [
11547    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11548    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11549    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
11550    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11551    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11552    {"bits": [13, 13], "name": "FAST_CLEAR"},
11553    {"bits": [14, 14], "name": "COMPRESSION"},
11554    {"bits": [15, 15], "name": "BLEND_CLAMP"},
11555    {"bits": [16, 16], "name": "BLEND_BYPASS"},
11556    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
11557    {"bits": [18, 18], "name": "ROUND_MODE"},
11558    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
11559    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11560    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11561    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
11562    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
11563    {"bits": [28, 28], "name": "DCC_ENABLE"},
11564    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11565    {"bits": [31, 31], "name": "NBC_TILING"}
11566   ]
11567  },
11568  "CB_COLOR0_PITCH": {
11569   "fields": [
11570    {"bits": [0, 10], "name": "TILE_MAX"},
11571    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
11572   ]
11573  },
11574  "CB_COLOR0_SLICE": {
11575   "fields": [
11576    {"bits": [0, 21], "name": "TILE_MAX"}
11577   ]
11578  },
11579  "CB_COLOR0_VIEW": {
11580   "fields": [
11581    {"bits": [0, 12], "name": "SLICE_START"},
11582    {"bits": [13, 25], "name": "SLICE_MAX"},
11583    {"bits": [26, 29], "name": "MIP_LEVEL"}
11584   ]
11585  },
11586  "CB_COLOR_CONTROL": {
11587   "fields": [
11588    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
11589    {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"},
11590    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
11591    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11592    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11593   ]
11594  },
11595  "CB_COVERAGE_OUT_CONTROL": {
11596   "fields": [
11597    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
11598    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
11599    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
11600    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
11601   ]
11602  },
11603  "CB_DCC_CONTROL": {
11604   "fields": [
11605    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11606    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
11607    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
11608    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
11609    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11610    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
11611    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
11612    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
11613   ]
11614  },
11615  "CB_PERFCOUNTER0_SELECT": {
11616   "fields": [
11617    {"bits": [0, 8], "name": "PERF_SEL"},
11618    {"bits": [10, 18], "name": "PERF_SEL1"},
11619    {"bits": [20, 23], "name": "CNTR_MODE"},
11620    {"bits": [24, 27], "name": "PERF_MODE1"},
11621    {"bits": [28, 31], "name": "PERF_MODE"}
11622   ]
11623  },
11624  "CB_PERFCOUNTER0_SELECT1": {
11625   "fields": [
11626    {"bits": [0, 8], "name": "PERF_SEL2"},
11627    {"bits": [10, 18], "name": "PERF_SEL3"},
11628    {"bits": [24, 27], "name": "PERF_MODE3"},
11629    {"bits": [28, 31], "name": "PERF_MODE2"}
11630   ]
11631  },
11632  "CB_PERFCOUNTER1_SELECT": {
11633   "fields": [
11634    {"bits": [0, 8], "name": "PERF_SEL"},
11635    {"bits": [28, 31], "name": "PERF_MODE"}
11636   ]
11637  },
11638  "CB_PERFCOUNTER_FILTER": {
11639   "fields": [
11640    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
11641    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11642    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
11643    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
11644    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
11645    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11646    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
11647    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
11648    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
11649    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
11650    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
11651    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
11652   ]
11653  },
11654  "CB_RMI_GL2_CACHE_CONTROL": {
11655   "fields": [
11656    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11657    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11658    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11659    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11660    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11661    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11662    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11663    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11664    {"bits": [24, 24], "name": "CMASK_L3_BYPASS"},
11665    {"bits": [25, 25], "name": "FMASK_L3_BYPASS"},
11666    {"bits": [26, 26], "name": "DCC_L3_BYPASS"},
11667    {"bits": [27, 27], "name": "COLOR_L3_BYPASS"},
11668    {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
11669    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
11670   ]
11671  },
11672  "CB_SHADER_MASK": {
11673   "fields": [
11674    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11675    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11676    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11677    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11678    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11679    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11680    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11681    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11682   ]
11683  },
11684  "CB_TARGET_MASK": {
11685   "fields": [
11686    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11687    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11688    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11689    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11690    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11691    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11692    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11693    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11694   ]
11695  },
11696  "COHER_DEST_BASE_HI_0": {
11697   "fields": [
11698    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11699   ]
11700  },
11701  "COMPUTE_DDID_INDEX": {
11702   "fields": [
11703    {"bits": [0, 10], "name": "INDEX"}
11704   ]
11705  },
11706  "COMPUTE_DISPATCH_INITIATOR": {
11707   "fields": [
11708    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11709    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11710    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11711    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11712    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11713    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11714    {"bits": [6, 6], "name": "ORDER_MODE"},
11715    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11716    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11717    {"bits": [12, 12], "name": "RESERVED"},
11718    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11719    {"bits": [14, 14], "name": "RESTORE"},
11720    {"bits": [15, 15], "name": "CS_W32_EN"}
11721   ]
11722  },
11723  "COMPUTE_DISPATCH_TUNNEL": {
11724   "fields": [
11725    {"bits": [0, 9], "name": "OFF_DELAY"},
11726    {"bits": [10, 10], "name": "IMMEDIATE"}
11727   ]
11728  },
11729  "COMPUTE_MISC_RESERVED": {
11730   "fields": [
11731    {"bits": [0, 1], "name": "SEND_SEID"},
11732    {"bits": [2, 2], "name": "RESERVED2"},
11733    {"bits": [3, 3], "name": "RESERVED3"},
11734    {"bits": [4, 4], "name": "RESERVED4"},
11735    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11736   ]
11737  },
11738  "COMPUTE_NUM_THREAD_X": {
11739   "fields": [
11740    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11741    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11742   ]
11743  },
11744  "COMPUTE_PERFCOUNT_ENABLE": {
11745   "fields": [
11746    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11747   ]
11748  },
11749  "COMPUTE_PGM_HI": {
11750   "fields": [
11751    {"bits": [0, 7], "name": "DATA"}
11752   ]
11753  },
11754  "COMPUTE_PGM_RSRC1": {
11755   "fields": [
11756    {"bits": [0, 5], "name": "VGPRS"},
11757    {"bits": [6, 9], "name": "SGPRS"},
11758    {"bits": [10, 11], "name": "PRIORITY"},
11759    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11760    {"bits": [20, 20], "name": "PRIV"},
11761    {"bits": [21, 21], "name": "DX10_CLAMP"},
11762    {"bits": [23, 23], "name": "IEEE_MODE"},
11763    {"bits": [24, 24], "name": "BULKY"},
11764    {"bits": [26, 26], "name": "FP16_OVFL"},
11765    {"bits": [29, 29], "name": "WGP_MODE"},
11766    {"bits": [30, 30], "name": "MEM_ORDERED"},
11767    {"bits": [31, 31], "name": "FWD_PROGRESS"}
11768   ]
11769  },
11770  "COMPUTE_PGM_RSRC2": {
11771   "fields": [
11772    {"bits": [0, 0], "name": "SCRATCH_EN"},
11773    {"bits": [1, 5], "name": "USER_SGPR"},
11774    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11775    {"bits": [7, 7], "name": "TGID_X_EN"},
11776    {"bits": [8, 8], "name": "TGID_Y_EN"},
11777    {"bits": [9, 9], "name": "TGID_Z_EN"},
11778    {"bits": [10, 10], "name": "TG_SIZE_EN"},
11779    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11780    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11781    {"bits": [15, 23], "name": "LDS_SIZE"},
11782    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11783   ]
11784  },
11785  "COMPUTE_PGM_RSRC3": {
11786   "fields": [
11787    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
11788   ]
11789  },
11790  "COMPUTE_PIPELINESTAT_ENABLE": {
11791   "fields": [
11792    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11793   ]
11794  },
11795  "COMPUTE_RELAUNCH": {
11796   "fields": [
11797    {"bits": [0, 29], "name": "PAYLOAD"},
11798    {"bits": [30, 30], "name": "IS_EVENT"},
11799    {"bits": [31, 31], "name": "IS_STATE"}
11800   ]
11801  },
11802  "COMPUTE_REQ_CTRL": {
11803   "fields": [
11804    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11805    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11806    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11807    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11808    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11809    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11810    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11811    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11812    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11813   ]
11814  },
11815  "COMPUTE_RESOURCE_LIMITS": {
11816   "fields": [
11817    {"bits": [0, 9], "name": "WAVES_PER_SH"},
11818    {"bits": [12, 15], "name": "TG_PER_CU"},
11819    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11820    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11821    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11822    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11823   ]
11824  },
11825  "COMPUTE_THREAD_TRACE_ENABLE": {
11826   "fields": [
11827    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11828   ]
11829  },
11830  "COMPUTE_TMPRING_SIZE": {
11831   "fields": [
11832    {"bits": [0, 11], "name": "WAVES"},
11833    {"bits": [12, 24], "name": "WAVESIZE"}
11834   ]
11835  },
11836  "COMPUTE_VMID": {
11837   "fields": [
11838    {"bits": [0, 3], "name": "DATA"}
11839   ]
11840  },
11841  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
11842   "fields": [
11843    {"bits": [0, 15], "name": "ADDR"}
11844   ]
11845  },
11846  "CPF_LATENCY_STATS_SELECT": {
11847   "fields": [
11848    {"bits": [0, 3], "name": "INDEX"},
11849    {"bits": [30, 30], "name": "CLEAR"},
11850    {"bits": [31, 31], "name": "ENABLE"}
11851   ]
11852  },
11853  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
11854   "fields": [
11855    {"bits": [0, 2], "name": "INDEX"},
11856    {"bits": [30, 30], "name": "ALWAYS"},
11857    {"bits": [31, 31], "name": "ENABLE"}
11858   ]
11859  },
11860  "CPG_LATENCY_STATS_SELECT": {
11861   "fields": [
11862    {"bits": [0, 4], "name": "INDEX"},
11863    {"bits": [30, 30], "name": "CLEAR"},
11864    {"bits": [31, 31], "name": "ENABLE"}
11865   ]
11866  },
11867  "CPG_PERFCOUNTER0_SELECT1": {
11868   "fields": [
11869    {"bits": [0, 9], "name": "PERF_SEL2"},
11870    {"bits": [10, 19], "name": "PERF_SEL3"},
11871    {"bits": [24, 27], "name": "CNTR_MODE3"},
11872    {"bits": [28, 31], "name": "CNTR_MODE2"}
11873   ]
11874  },
11875  "CPG_PERFCOUNTER1_SELECT": {
11876   "fields": [
11877    {"bits": [0, 9], "name": "PERF_SEL"},
11878    {"bits": [10, 19], "name": "PERF_SEL1"},
11879    {"bits": [20, 23], "name": "SPM_MODE"},
11880    {"bits": [24, 27], "name": "CNTR_MODE1"},
11881    {"bits": [28, 31], "name": "CNTR_MODE0"}
11882   ]
11883  },
11884  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
11885   "fields": [
11886    {"bits": [0, 4], "name": "INDEX"},
11887    {"bits": [30, 30], "name": "ALWAYS"},
11888    {"bits": [31, 31], "name": "ENABLE"}
11889   ]
11890  },
11891  "CP_APPEND_ADDR_HI": {
11892   "fields": [
11893    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
11894    {"bits": [16, 16], "name": "CS_PS_SEL"},
11895    {"bits": [25, 26], "name": "CACHE_POLICY"},
11896    {"bits": [29, 31], "name": "COMMAND"}
11897   ]
11898  },
11899  "CP_APPEND_ADDR_LO": {
11900   "fields": [
11901    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
11902   ]
11903  },
11904  "CP_CE_IB1_BASE_HI": {
11905   "fields": [
11906    {"bits": [0, 15], "name": "IB1_BASE_HI"}
11907   ]
11908  },
11909  "CP_CE_IB1_BASE_LO": {
11910   "fields": [
11911    {"bits": [2, 31], "name": "IB1_BASE_LO"}
11912   ]
11913  },
11914  "CP_CE_IB1_BUFSZ": {
11915   "fields": [
11916    {"bits": [0, 19], "name": "IB1_BUFSZ"}
11917   ]
11918  },
11919  "CP_CE_IB1_CMD_BUFSZ": {
11920   "fields": [
11921    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
11922   ]
11923  },
11924  "CP_CE_IB1_OFFSET": {
11925   "fields": [
11926    {"bits": [0, 19], "name": "IB1_OFFSET"}
11927   ]
11928  },
11929  "CP_CE_IB2_BASE_HI": {
11930   "fields": [
11931    {"bits": [0, 15], "name": "IB2_BASE_HI"}
11932   ]
11933  },
11934  "CP_CE_IB2_BASE_LO": {
11935   "fields": [
11936    {"bits": [2, 31], "name": "IB2_BASE_LO"}
11937   ]
11938  },
11939  "CP_CE_IB2_BUFSZ": {
11940   "fields": [
11941    {"bits": [0, 19], "name": "IB2_BUFSZ"}
11942   ]
11943  },
11944  "CP_CE_IB2_CMD_BUFSZ": {
11945   "fields": [
11946    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
11947   ]
11948  },
11949  "CP_CE_INIT_BASE_HI": {
11950   "fields": [
11951    {"bits": [0, 15], "name": "INIT_BASE_HI"}
11952   ]
11953  },
11954  "CP_CE_INIT_BASE_LO": {
11955   "fields": [
11956    {"bits": [5, 31], "name": "INIT_BASE_LO"}
11957   ]
11958  },
11959  "CP_CE_INIT_BUFSZ": {
11960   "fields": [
11961    {"bits": [0, 11], "name": "INIT_BUFSZ"}
11962   ]
11963  },
11964  "CP_CE_INIT_CMD_BUFSZ": {
11965   "fields": [
11966    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
11967   ]
11968  },
11969  "CP_COHER_BASE_HI": {
11970   "fields": [
11971    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
11972   ]
11973  },
11974  "CP_COHER_CNTL": {
11975   "fields": [
11976    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
11977    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
11978    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
11979    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
11980    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
11981    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
11982    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
11983    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
11984    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
11985    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
11986    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
11987    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
11988    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
11989   ]
11990  },
11991  "CP_COHER_SIZE_HI": {
11992   "fields": [
11993    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
11994   ]
11995  },
11996  "CP_COHER_START_DELAY": {
11997   "fields": [
11998    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
11999   ]
12000  },
12001  "CP_COHER_STATUS": {
12002   "fields": [
12003    {"bits": [24, 25], "name": "MEID"},
12004    {"bits": [31, 31], "name": "STATUS"}
12005   ]
12006  },
12007  "CP_CPC_BUSY_STAT": {
12008   "fields": [
12009    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
12010    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
12011    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
12012    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
12013    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
12014    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
12015    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
12016    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
12017    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
12018    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
12019    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
12020    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
12021    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
12022    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
12023    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
12024    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
12025    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
12026    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
12027    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
12028    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
12029    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
12030    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
12031    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
12032    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
12033    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
12034    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
12035    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
12036    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
12037   ]
12038  },
12039  "CP_CPC_BUSY_STAT2": {
12040   "fields": [
12041    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
12042    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
12043    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
12044    {"bits": [7, 7], "name": "MES_TC_BUSY"},
12045    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
12046    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
12047    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
12048    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
12049    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
12050   ]
12051  },
12052  "CP_CPC_GRBM_FREE_COUNT": {
12053   "fields": [
12054    {"bits": [0, 5], "name": "FREE_COUNT"}
12055   ]
12056  },
12057  "CP_CPC_HALT_HYST_COUNT": {
12058   "fields": [
12059    {"bits": [0, 3], "name": "COUNT"}
12060   ]
12061  },
12062  "CP_CPC_PRIV_VIOLATION_ADDR": {
12063   "fields": [
12064    {"bits": [0, 15], "name": "PRIV_VIOLATION_ADDR"}
12065   ]
12066  },
12067  "CP_CPC_SCRATCH_INDEX": {
12068   "fields": [
12069    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
12070    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12071   ]
12072  },
12073  "CP_CPC_STALLED_STAT1": {
12074   "fields": [
12075    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
12076    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
12077    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
12078    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
12079    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
12080    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
12081    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
12082    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
12083    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
12084    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
12085    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
12086    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
12087    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
12088    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
12089    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
12090   ]
12091  },
12092  "CP_CPC_STATUS": {
12093   "fields": [
12094    {"bits": [0, 0], "name": "MEC1_BUSY"},
12095    {"bits": [1, 1], "name": "MEC2_BUSY"},
12096    {"bits": [2, 2], "name": "DC0_BUSY"},
12097    {"bits": [3, 3], "name": "DC1_BUSY"},
12098    {"bits": [4, 4], "name": "RCIU1_BUSY"},
12099    {"bits": [5, 5], "name": "RCIU2_BUSY"},
12100    {"bits": [6, 6], "name": "ROQ1_BUSY"},
12101    {"bits": [7, 7], "name": "ROQ2_BUSY"},
12102    {"bits": [10, 10], "name": "TCIU_BUSY"},
12103    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
12104    {"bits": [12, 12], "name": "QU_BUSY"},
12105    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
12106    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
12107    {"bits": [15, 15], "name": "GCRIU_BUSY"},
12108    {"bits": [16, 16], "name": "MES_BUSY"},
12109    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
12110    {"bits": [18, 18], "name": "RCIU3_BUSY"},
12111    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
12112    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
12113    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
12114    {"bits": [31, 31], "name": "CPC_BUSY"}
12115   ]
12116  },
12117  "CP_CPF_BUSY_STAT": {
12118   "fields": [
12119    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
12120    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
12121    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
12122    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
12123    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
12124    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
12125    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
12126    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
12127    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
12128    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
12129    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
12130    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
12131    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
12132    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
12133    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
12134    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
12135    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
12136    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
12137    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
12138    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
12139    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
12140    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
12141    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
12142    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
12143    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
12144    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
12145    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
12146    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
12147    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
12148    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
12149    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
12150    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
12151   ]
12152  },
12153  "CP_CPF_BUSY_STAT2": {
12154   "fields": [
12155    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
12156    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
12157    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
12158    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
12159    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
12160    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
12161    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
12162    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
12163    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
12164   ]
12165  },
12166  "CP_CPF_GRBM_FREE_COUNT": {
12167   "fields": [
12168    {"bits": [0, 2], "name": "FREE_COUNT"}
12169   ]
12170  },
12171  "CP_CPF_STALLED_STAT1": {
12172   "fields": [
12173    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
12174    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
12175    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
12176    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
12177    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
12178    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
12179    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
12180    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
12181    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
12182    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
12183    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
12184    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
12185    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
12186   ]
12187  },
12188  "CP_CPF_STATUS": {
12189   "fields": [
12190    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
12191    {"bits": [1, 1], "name": "CSF_BUSY"},
12192    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
12193    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
12194    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
12195    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
12196    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
12197    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
12198    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
12199    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
12200    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
12201    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
12202    {"bits": [14, 14], "name": "TCIU_BUSY"},
12203    {"bits": [15, 15], "name": "HQD_BUSY"},
12204    {"bits": [16, 16], "name": "PRT_BUSY"},
12205    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
12206    {"bits": [18, 18], "name": "RCIU_BUSY"},
12207    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
12208    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
12209    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
12210    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
12211    {"bits": [23, 23], "name": "GCRIU_BUSY"},
12212    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
12213    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
12214    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
12215    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
12216    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
12217    {"bits": [31, 31], "name": "CPF_BUSY"}
12218   ]
12219  },
12220  "CP_DB_BASE_HI": {
12221   "fields": [
12222    {"bits": [0, 15], "name": "DB_BASE_HI"}
12223   ]
12224  },
12225  "CP_DB_BASE_LO": {
12226   "fields": [
12227    {"bits": [2, 31], "name": "DB_BASE_LO"}
12228   ]
12229  },
12230  "CP_DB_BUFSZ": {
12231   "fields": [
12232    {"bits": [0, 19], "name": "DB_BUFSZ"}
12233   ]
12234  },
12235  "CP_DB_CMD_BUFSZ": {
12236   "fields": [
12237    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
12238   ]
12239  },
12240  "CP_DMA_CNTL": {
12241   "fields": [
12242    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
12243    {"bits": [1, 1], "name": "WATCH_CONTROL"},
12244    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
12245    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
12246    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
12247    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
12248    {"bits": [30, 31], "name": "PIO_COUNT"}
12249   ]
12250  },
12251  "CP_DMA_ME_CMD_ADDR_HI": {
12252   "fields": [
12253    {"bits": [0, 15], "name": "ADDR_HI"},
12254    {"bits": [16, 31], "name": "RSVD"}
12255   ]
12256  },
12257  "CP_DMA_ME_CMD_ADDR_LO": {
12258   "fields": [
12259    {"bits": [0, 1], "name": "RSVD"},
12260    {"bits": [2, 31], "name": "ADDR_LO"}
12261   ]
12262  },
12263  "CP_DMA_ME_COMMAND": {
12264   "fields": [
12265    {"bits": [0, 25], "name": "BYTE_COUNT"},
12266    {"bits": [26, 26], "name": "SAS"},
12267    {"bits": [27, 27], "name": "DAS"},
12268    {"bits": [28, 28], "name": "SAIC"},
12269    {"bits": [29, 29], "name": "DAIC"},
12270    {"bits": [30, 30], "name": "RAW_WAIT"},
12271    {"bits": [31, 31], "name": "DIS_WC"}
12272   ]
12273  },
12274  "CP_DMA_ME_DST_ADDR_HI": {
12275   "fields": [
12276    {"bits": [0, 15], "name": "DST_ADDR_HI"}
12277   ]
12278  },
12279  "CP_DMA_ME_SRC_ADDR_HI": {
12280   "fields": [
12281    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
12282   ]
12283  },
12284  "CP_DMA_PFP_CONTROL": {
12285   "fields": [
12286    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
12287    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
12288    {"bits": [15, 15], "name": "SRC_VOLATLE"},
12289    {"bits": [20, 21], "name": "DST_SELECT"},
12290    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
12291    {"bits": [27, 27], "name": "DST_VOLATLE"},
12292    {"bits": [29, 30], "name": "SRC_SELECT"}
12293   ]
12294  },
12295  "CP_DMA_READ_TAGS": {
12296   "fields": [
12297    {"bits": [0, 25], "name": "DMA_READ_TAG"},
12298    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
12299   ]
12300  },
12301  "CP_DRAW_WINDOW_CNTL": {
12302   "fields": [
12303    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
12304    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
12305    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
12306    {"bits": [8, 8], "name": "MODE"}
12307   ]
12308  },
12309  "CP_DRAW_WINDOW_LO": {
12310   "fields": [
12311    {"bits": [0, 15], "name": "MIN"},
12312    {"bits": [16, 31], "name": "MAX"}
12313   ]
12314  },
12315  "CP_EOP_DONE_ADDR_HI": {
12316   "fields": [
12317    {"bits": [0, 15], "name": "ADDR_HI"}
12318   ]
12319  },
12320  "CP_EOP_DONE_ADDR_LO": {
12321   "fields": [
12322    {"bits": [2, 31], "name": "ADDR_LO"}
12323   ]
12324  },
12325  "CP_EOP_DONE_DATA_CNTL": {
12326   "fields": [
12327    {"bits": [16, 17], "name": "DST_SEL"},
12328    {"bits": [20, 21], "name": "ACTION_PIPE_ID"},
12329    {"bits": [22, 23], "name": "ACTION_ID"},
12330    {"bits": [24, 26], "name": "INT_SEL"},
12331    {"bits": [29, 31], "name": "DATA_SEL"}
12332   ]
12333  },
12334  "CP_EOP_DONE_EVENT_CNTL": {
12335   "fields": [
12336    {"bits": [12, 23], "name": "GCR_CNTL"},
12337    {"bits": [25, 26], "name": "CACHE_POLICY"},
12338    {"bits": [27, 27], "name": "EOP_VOLATILE"},
12339    {"bits": [28, 28], "name": "EXECUTE"}
12340   ]
12341  },
12342  "CP_IB2_OFFSET": {
12343   "fields": [
12344    {"bits": [0, 19], "name": "IB2_OFFSET"}
12345   ]
12346  },
12347  "CP_IB2_PREAMBLE_BEGIN": {
12348   "fields": [
12349    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
12350   ]
12351  },
12352  "CP_IB2_PREAMBLE_END": {
12353   "fields": [
12354    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
12355   ]
12356  },
12357  "CP_INDEX_TYPE": {
12358   "fields": [
12359    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12360   ]
12361  },
12362  "CP_ME_COHER_CNTL": {
12363   "fields": [
12364    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
12365    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
12366    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
12367    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
12368    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
12369    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
12370    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
12371    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
12372    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
12373    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
12374    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
12375    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
12376    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
12377   ]
12378  },
12379  "CP_ME_COHER_STATUS": {
12380   "fields": [
12381    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
12382    {"bits": [31, 31], "name": "STATUS"}
12383   ]
12384  },
12385  "CP_ME_MC_RADDR_HI": {
12386   "fields": [
12387    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
12388    {"bits": [22, 23], "name": "CACHE_POLICY"}
12389   ]
12390  },
12391  "CP_ME_MC_RADDR_LO": {
12392   "fields": [
12393    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
12394   ]
12395  },
12396  "CP_ME_MC_WADDR_HI": {
12397   "fields": [
12398    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
12399    {"bits": [22, 23], "name": "CACHE_POLICY"}
12400   ]
12401  },
12402  "CP_ME_MC_WADDR_LO": {
12403   "fields": [
12404    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
12405   ]
12406  },
12407  "CP_PERFMON_CNTL": {
12408   "fields": [
12409    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12410    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12411    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12412    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12413   ]
12414  },
12415  "CP_PERFMON_CNTX_CNTL": {
12416   "fields": [
12417    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
12418   ]
12419  },
12420  "CP_PFP_COMPLETION_STATUS": {
12421   "fields": [
12422    {"bits": [0, 1], "name": "STATUS"}
12423   ]
12424  },
12425  "CP_PFP_IB_CONTROL": {
12426   "fields": [
12427    {"bits": [0, 7], "name": "IB_EN"}
12428   ]
12429  },
12430  "CP_PFP_LOAD_CONTROL": {
12431   "fields": [
12432    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
12433    {"bits": [1, 1], "name": "CNTX_REG_EN"},
12434    {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
12435    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
12436    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
12437   ]
12438  },
12439  "CP_PIPEID": {
12440   "fields": [
12441    {"bits": [0, 1], "name": "PIPE_ID"}
12442   ]
12443  },
12444  "CP_PIPE_STATS_ADDR_HI": {
12445   "fields": [
12446    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
12447   ]
12448  },
12449  "CP_PIPE_STATS_ADDR_LO": {
12450   "fields": [
12451    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
12452   ]
12453  },
12454  "CP_PIPE_STATS_CONTROL": {
12455   "fields": [
12456    {"bits": [25, 26], "name": "CACHE_POLICY"}
12457   ]
12458  },
12459  "CP_PRED_NOT_VISIBLE": {
12460   "fields": [
12461    {"bits": [0, 0], "name": "NOT_VISIBLE"}
12462   ]
12463  },
12464  "CP_RB_OFFSET": {
12465   "fields": [
12466    {"bits": [0, 19], "name": "RB_OFFSET"}
12467   ]
12468  },
12469  "CP_SAMPLE_STATUS": {
12470   "fields": [
12471    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
12472    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
12473    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
12474    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
12475    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
12476    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
12477    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
12478    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
12479   ]
12480  },
12481  "CP_SIG_SEM_ADDR_HI": {
12482   "fields": [
12483    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
12484    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
12485    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
12486    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
12487    {"bits": [29, 31], "name": "SEM_SELECT"}
12488   ]
12489  },
12490  "CP_SIG_SEM_ADDR_LO": {
12491   "fields": [
12492    {"bits": [0, 0], "name": "SEM_PRIV"},
12493    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
12494   ]
12495  },
12496  "CP_STREAM_OUT_ADDR_HI": {
12497   "fields": [
12498    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
12499   ]
12500  },
12501  "CP_STREAM_OUT_ADDR_LO": {
12502   "fields": [
12503    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
12504   ]
12505  },
12506  "CP_STRMOUT_CNTL": {
12507   "fields": [
12508    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
12509   ]
12510  },
12511  "CP_ST_BASE_HI": {
12512   "fields": [
12513    {"bits": [0, 15], "name": "ST_BASE_HI"}
12514   ]
12515  },
12516  "CP_ST_BASE_LO": {
12517   "fields": [
12518    {"bits": [2, 31], "name": "ST_BASE_LO"}
12519   ]
12520  },
12521  "CP_ST_BUFSZ": {
12522   "fields": [
12523    {"bits": [0, 19], "name": "ST_BUFSZ"}
12524   ]
12525  },
12526  "CP_ST_CMD_BUFSZ": {
12527   "fields": [
12528    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
12529   ]
12530  },
12531  "CP_VMID": {
12532   "fields": [
12533    {"bits": [0, 3], "name": "VMID"}
12534   ]
12535  },
12536  "CS_COPY_STATE": {
12537   "fields": [
12538    {"bits": [0, 2], "name": "SRC_STATE_ID"}
12539   ]
12540  },
12541  "DB_ALPHA_TO_MASK": {
12542   "fields": [
12543    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
12544    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
12545    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
12546    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
12547    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
12548    {"bits": [16, 16], "name": "OFFSET_ROUND"}
12549   ]
12550  },
12551  "DB_COUNT_CONTROL": {
12552   "fields": [
12553    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
12554    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
12555    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
12556    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
12557    {"bits": [4, 6], "name": "SAMPLE_RATE"},
12558    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
12559    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
12560    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
12561    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
12562    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
12563    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
12564   ]
12565  },
12566  "DB_DEPTH_CONTROL": {
12567   "fields": [
12568    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
12569    {"bits": [1, 1], "name": "Z_ENABLE"},
12570    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
12571    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
12572    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12573    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
12574    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12575    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12576    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
12577    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
12578   ]
12579  },
12580  "DB_DEPTH_SIZE_XY": {
12581   "fields": [
12582    {"bits": [0, 13], "name": "X_MAX"},
12583    {"bits": [16, 29], "name": "Y_MAX"}
12584   ]
12585  },
12586  "DB_DEPTH_VIEW": {
12587   "fields": [
12588    {"bits": [0, 10], "name": "SLICE_START"},
12589    {"bits": [11, 12], "name": "SLICE_START_HI"},
12590    {"bits": [13, 23], "name": "SLICE_MAX"},
12591    {"bits": [24, 24], "name": "Z_READ_ONLY"},
12592    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
12593    {"bits": [26, 29], "name": "MIPID"},
12594    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
12595   ]
12596  },
12597  "DB_DFSM_CONTROL": {
12598   "fields": [
12599    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12600    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
12601    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
12602   ]
12603  },
12604  "DB_EQAA": {
12605   "fields": [
12606    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12607    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12608    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12609    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12610    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12611    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12612    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12613    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12614    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12615    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12616    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12617    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12618   ]
12619  },
12620  "DB_HTILE_SURFACE": {
12621   "fields": [
12622    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12623    {"bits": [1, 1], "name": "FULL_CACHE"},
12624    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12625    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12626    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12627    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12628    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12629    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12630    {"bits": [18, 18], "name": "PIPE_ALIGNED"},
12631    {"bits": [19, 20], "enum_ref": "VRSHtileEncoding", "name": "VRS_HTILE_ENCODING"}
12632   ]
12633  },
12634  "DB_OCCLUSION_COUNT0_HI": {
12635   "fields": [
12636    {"bits": [0, 30], "name": "COUNT_HI"}
12637   ]
12638  },
12639  "DB_PRELOAD_CONTROL": {
12640   "fields": [
12641    {"bits": [0, 7], "name": "START_X"},
12642    {"bits": [8, 15], "name": "START_Y"},
12643    {"bits": [16, 23], "name": "MAX_X"},
12644    {"bits": [24, 31], "name": "MAX_Y"}
12645   ]
12646  },
12647  "DB_RENDER_CONTROL": {
12648   "fields": [
12649    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12650    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12651    {"bits": [2, 2], "name": "DEPTH_COPY"},
12652    {"bits": [3, 3], "name": "STENCIL_COPY"},
12653    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12654    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12655    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12656    {"bits": [7, 7], "name": "COPY_CENTROID"},
12657    {"bits": [8, 11], "name": "COPY_SAMPLE"},
12658    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"},
12659    {"bits": [13, 13], "name": "PS_INVOKE_DISABLE"}
12660   ]
12661  },
12662  "DB_RENDER_OVERRIDE": {
12663   "fields": [
12664    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12665    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12666    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12667    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12668    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12669    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12670    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12671    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12672    {"bits": [11, 11], "name": "FORCE_Z_READ"},
12673    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12674    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12675    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
12676    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12677    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12678    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12679    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12680    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12681    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12682    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12683    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12684    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12685    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12686    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12687   ]
12688  },
12689  "DB_RENDER_OVERRIDE2": {
12690   "fields": [
12691    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12692    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12693    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12694    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12695    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12696    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12697    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12698    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12699    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12700    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12701    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12702    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12703    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12704    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12705    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12706    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
12707    {"bits": [26, 26], "name": "FORCE_VRS_RATE_FINE"},
12708    {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"}
12709   ]
12710  },
12711  "DB_RESERVED_REG_1": {
12712   "fields": [
12713    {"bits": [0, 10], "name": "FIELD_1"},
12714    {"bits": [11, 21], "name": "FIELD_2"}
12715   ]
12716  },
12717  "DB_RESERVED_REG_2": {
12718   "fields": [
12719    {"bits": [0, 3], "name": "FIELD_1"},
12720    {"bits": [4, 7], "name": "FIELD_2"},
12721    {"bits": [8, 12], "name": "FIELD_3"},
12722    {"bits": [13, 14], "name": "FIELD_4"},
12723    {"bits": [15, 16], "name": "FIELD_5"},
12724    {"bits": [17, 18], "name": "FIELD_6"},
12725    {"bits": [19, 20], "name": "FIELD_7"},
12726    {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
12727   ]
12728  },
12729  "DB_RESERVED_REG_3": {
12730   "fields": [
12731    {"bits": [0, 21], "name": "FIELD_1"}
12732   ]
12733  },
12734  "DB_RMI_L2_CACHE_CONTROL": {
12735   "fields": [
12736    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12737    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12738    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12739    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12740    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12741    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12742    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12743    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12744    {"bits": [25, 25], "name": "S_BIG_PAGE"},
12745    {"bits": [26, 26], "name": "Z_NOALLOC"},
12746    {"bits": [27, 27], "name": "S_NOALLOC"},
12747    {"bits": [28, 28], "name": "HTILE_NOALLOC"},
12748    {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"}
12749   ]
12750  },
12751  "DB_SHADER_CONTROL": {
12752   "fields": [
12753    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12754    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12755    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12756    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12757    {"bits": [6, 6], "name": "KILL_ENABLE"},
12758    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12759    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12760    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12761    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12762    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12763    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12764    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12765    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12766    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12767    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
12768    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
12769    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
12770   ]
12771  },
12772  "DB_SRESULTS_COMPARE_STATE0": {
12773   "fields": [
12774    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12775    {"bits": [4, 11], "name": "COMPAREVALUE0"},
12776    {"bits": [12, 19], "name": "COMPAREMASK0"},
12777    {"bits": [24, 24], "name": "ENABLE0"}
12778   ]
12779  },
12780  "DB_SRESULTS_COMPARE_STATE1": {
12781   "fields": [
12782    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12783    {"bits": [4, 11], "name": "COMPAREVALUE1"},
12784    {"bits": [12, 19], "name": "COMPAREMASK1"},
12785    {"bits": [24, 24], "name": "ENABLE1"}
12786   ]
12787  },
12788  "DB_STENCILREFMASK": {
12789   "fields": [
12790    {"bits": [0, 7], "name": "STENCILTESTVAL"},
12791    {"bits": [8, 15], "name": "STENCILMASK"},
12792    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12793    {"bits": [24, 31], "name": "STENCILOPVAL"}
12794   ]
12795  },
12796  "DB_STENCILREFMASK_BF": {
12797   "fields": [
12798    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12799    {"bits": [8, 15], "name": "STENCILMASK_BF"},
12800    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12801    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12802   ]
12803  },
12804  "DB_STENCIL_CLEAR": {
12805   "fields": [
12806    {"bits": [0, 7], "name": "CLEAR"}
12807   ]
12808  },
12809  "DB_STENCIL_CONTROL": {
12810   "fields": [
12811    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12812    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12813    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12814    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12815    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12816    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12817   ]
12818  },
12819  "DB_STENCIL_INFO": {
12820   "fields": [
12821    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12822    {"bits": [4, 8], "name": "SW_MODE"},
12823    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12824    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12825    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12826    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12827    {"bits": [20, 20], "name": "ITERATE_256"},
12828    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12829    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12830   ]
12831  },
12832  "DB_VRS_OVERRIDE_CNTL": {
12833   "fields": [
12834    {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"},
12835    {"bits": [4, 5], "name": "VRS_OVERRIDE_RATE_X"},
12836    {"bits": [6, 7], "name": "VRS_OVERRIDE_RATE_Y"}
12837   ]
12838  },
12839  "DB_Z_INFO": {
12840   "fields": [
12841    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12842    {"bits": [2, 3], "name": "NUM_SAMPLES"},
12843    {"bits": [4, 8], "name": "SW_MODE"},
12844    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12845    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12846    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12847    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12848    {"bits": [16, 19], "name": "MAXMIP"},
12849    {"bits": [20, 20], "name": "ITERATE_256"},
12850    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12851    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12852    {"bits": [28, 28], "name": "READ_SIZE"},
12853    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12854    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12855   ]
12856  },
12857  "DB_Z_READ_BASE_HI": {
12858   "fields": [
12859    {"bits": [0, 7], "name": "BASE_HI"}
12860   ]
12861  },
12862  "GB_ADDR_CONFIG": {
12863   "fields": [
12864    {"bits": [0, 2], "name": "NUM_PIPES"},
12865    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12866    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12867    {"bits": [8, 10], "name": "NUM_PKRS"},
12868    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12869    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12870   ]
12871  },
12872  "GCEA_PERFCOUNTER0_CFG": {
12873   "fields": [
12874    {"bits": [0, 7], "name": "PERF_SEL"},
12875    {"bits": [8, 15], "name": "PERF_SEL_END"},
12876    {"bits": [24, 27], "name": "PERF_MODE"},
12877    {"bits": [28, 28], "name": "ENABLE"},
12878    {"bits": [29, 29], "name": "CLEAR"}
12879   ]
12880  },
12881  "GCEA_PERFCOUNTER2_MODE": {
12882   "fields": [
12883    {"bits": [0, 1], "name": "COMPARE_MODE0"},
12884    {"bits": [2, 3], "name": "COMPARE_MODE1"},
12885    {"bits": [4, 5], "name": "COMPARE_MODE2"},
12886    {"bits": [6, 7], "name": "COMPARE_MODE3"},
12887    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
12888    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
12889    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
12890    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
12891   ]
12892  },
12893  "GCEA_PERFCOUNTER_HI": {
12894   "fields": [
12895    {"bits": [0, 15], "name": "COUNTER_HI"},
12896    {"bits": [16, 31], "name": "COMPARE_VALUE"}
12897   ]
12898  },
12899  "GCEA_PERFCOUNTER_RSLT_CNTL": {
12900   "fields": [
12901    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
12902    {"bits": [8, 15], "name": "START_TRIGGER"},
12903    {"bits": [16, 23], "name": "STOP_TRIGGER"},
12904    {"bits": [24, 24], "name": "ENABLE_ANY"},
12905    {"bits": [25, 25], "name": "CLEAR_ALL"},
12906    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
12907   ]
12908  },
12909  "GCR_PERFCOUNTER1_SELECT": {
12910   "fields": [
12911    {"bits": [0, 8], "name": "PERF_SEL"},
12912    {"bits": [24, 27], "name": "PERF_MODE"},
12913    {"bits": [28, 31], "name": "CNTL_MODE"}
12914   ]
12915  },
12916  "GDS_ATOM_BASE": {
12917   "fields": [
12918    {"bits": [0, 15], "name": "BASE"},
12919    {"bits": [16, 31], "name": "UNUSED"}
12920   ]
12921  },
12922  "GDS_ATOM_CNTL": {
12923   "fields": [
12924    {"bits": [0, 5], "name": "AINC"},
12925    {"bits": [6, 7], "name": "UNUSED1"},
12926    {"bits": [8, 9], "name": "DMODE"},
12927    {"bits": [10, 31], "name": "UNUSED2"}
12928   ]
12929  },
12930  "GDS_ATOM_COMPLETE": {
12931   "fields": [
12932    {"bits": [0, 0], "name": "COMPLETE"},
12933    {"bits": [1, 31], "name": "UNUSED"}
12934   ]
12935  },
12936  "GDS_ATOM_OFFSET0": {
12937   "fields": [
12938    {"bits": [0, 7], "name": "OFFSET0"},
12939    {"bits": [8, 31], "name": "UNUSED"}
12940   ]
12941  },
12942  "GDS_ATOM_OFFSET1": {
12943   "fields": [
12944    {"bits": [0, 7], "name": "OFFSET1"},
12945    {"bits": [8, 31], "name": "UNUSED"}
12946   ]
12947  },
12948  "GDS_ATOM_OP": {
12949   "fields": [
12950    {"bits": [0, 7], "name": "OP"},
12951    {"bits": [8, 31], "name": "UNUSED"}
12952   ]
12953  },
12954  "GDS_ATOM_SIZE": {
12955   "fields": [
12956    {"bits": [0, 15], "name": "SIZE"},
12957    {"bits": [16, 31], "name": "UNUSED"}
12958   ]
12959  },
12960  "GDS_GWS_RESOURCE": {
12961   "fields": [
12962    {"bits": [0, 0], "name": "FLAG"},
12963    {"bits": [1, 12], "name": "COUNTER"},
12964    {"bits": [13, 13], "name": "TYPE"},
12965    {"bits": [14, 14], "name": "DED"},
12966    {"bits": [15, 15], "name": "RELEASE_ALL"},
12967    {"bits": [16, 26], "name": "HEAD_QUEUE"},
12968    {"bits": [27, 27], "name": "HEAD_VALID"},
12969    {"bits": [28, 28], "name": "HEAD_FLAG"},
12970    {"bits": [29, 29], "name": "HALTED"},
12971    {"bits": [30, 30], "name": "HEAD_QUEUE1"},
12972    {"bits": [31, 31], "name": "UNUSED1"}
12973   ]
12974  },
12975  "GDS_GWS_RESOURCE_CNT": {
12976   "fields": [
12977    {"bits": [0, 15], "name": "RESOURCE_CNT"},
12978    {"bits": [16, 31], "name": "UNUSED"}
12979   ]
12980  },
12981  "GDS_GWS_RESOURCE_CNTL": {
12982   "fields": [
12983    {"bits": [0, 5], "name": "INDEX"},
12984    {"bits": [6, 31], "name": "UNUSED"}
12985   ]
12986  },
12987  "GDS_OA_ADDRESS": {
12988   "fields": [
12989    {"bits": [0, 15], "name": "DS_ADDRESS"},
12990    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
12991    {"bits": [20, 23], "name": "CRAWLER"},
12992    {"bits": [24, 29], "name": "UNUSED"},
12993    {"bits": [30, 30], "name": "NO_ALLOC"},
12994    {"bits": [31, 31], "name": "ENABLE"}
12995   ]
12996  },
12997  "GDS_OA_CNTL": {
12998   "fields": [
12999    {"bits": [0, 3], "name": "INDEX"},
13000    {"bits": [4, 31], "name": "UNUSED"}
13001   ]
13002  },
13003  "GDS_OA_INCDEC": {
13004   "fields": [
13005    {"bits": [0, 30], "name": "VALUE"},
13006    {"bits": [31, 31], "name": "INCDEC"}
13007   ]
13008  },
13009  "GE1_PERFCOUNTER0_SELECT": {
13010   "fields": [
13011    {"bits": [0, 9], "name": "PERF_SEL0"},
13012    {"bits": [10, 19], "name": "PERF_SEL1"},
13013    {"bits": [20, 23], "name": "CNTR_MODE"},
13014    {"bits": [24, 27], "name": "PERF_MODE0"},
13015    {"bits": [28, 31], "name": "PERF_MODE1"}
13016   ]
13017  },
13018  "GE1_PERFCOUNTER0_SELECT1": {
13019   "fields": [
13020    {"bits": [0, 9], "name": "PERF_SEL2"},
13021    {"bits": [10, 19], "name": "PERF_SEL3"},
13022    {"bits": [24, 27], "name": "PERF_MODE2"},
13023    {"bits": [28, 31], "name": "PERF_MODE3"}
13024   ]
13025  },
13026  "GE_CNTL": {
13027   "fields": [
13028    {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
13029    {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
13030    {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
13031    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
13032   ]
13033  },
13034  "GE_MAX_OUTPUT_PER_SUBGROUP": {
13035   "fields": [
13036    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
13037   ]
13038  },
13039  "GE_NGG_SUBGRP_CNTL": {
13040   "fields": [
13041    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
13042    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
13043   ]
13044  },
13045  "GE_PC_ALLOC": {
13046   "fields": [
13047    {"bits": [0, 0], "name": "OVERSUB_EN"},
13048    {"bits": [1, 10], "name": "NUM_PC_LINES"}
13049   ]
13050  },
13051  "GE_STEREO_CNTL": {
13052   "fields": [
13053    {"bits": [0, 2], "name": "RT_SLICE"},
13054    {"bits": [3, 6], "name": "VIEWPORT"},
13055    {"bits": [8, 8], "name": "EN_STEREO"}
13056   ]
13057  },
13058  "GE_USER_VGPR_EN": {
13059   "fields": [
13060    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
13061    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
13062    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
13063   ]
13064  },
13065  "GRBM_GFX_INDEX": {
13066   "fields": [
13067    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
13068    {"bits": [8, 15], "name": "SA_INDEX"},
13069    {"bits": [16, 23], "name": "SE_INDEX"},
13070    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
13071    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
13072    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
13073   ]
13074  },
13075  "GRBM_PERFCOUNTER0_SELECT": {
13076   "fields": [
13077    {"bits": [0, 5], "name": "PERF_SEL"},
13078    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13079    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13080    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
13081    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
13082    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13083    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
13084    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
13085    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
13086    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
13087    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
13088    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
13089    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
13090    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13091    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
13092    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13093    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
13094    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
13095    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
13096    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
13097   ]
13098  },
13099  "GRBM_PERFCOUNTER0_SELECT_HI": {
13100   "fields": [
13101    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13102    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
13103    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
13104    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
13105    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
13106    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
13107    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
13108    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13109   ]
13110  },
13111  "GRBM_SE0_PERFCOUNTER_SELECT": {
13112   "fields": [
13113    {"bits": [0, 5], "name": "PERF_SEL"},
13114    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13115    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13116    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
13117    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
13118    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13119    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
13120    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
13121    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
13122    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
13123    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13124    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
13125    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13126    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13127    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13128   ]
13129  },
13130  "GRBM_STATUS": {
13131   "fields": [
13132    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
13133    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
13134    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
13135    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
13136    {"bits": [12, 12], "name": "DB_CLEAN"},
13137    {"bits": [13, 13], "name": "CB_CLEAN"},
13138    {"bits": [14, 14], "name": "TA_BUSY"},
13139    {"bits": [15, 15], "name": "GDS_BUSY"},
13140    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
13141    {"bits": [20, 20], "name": "SX_BUSY"},
13142    {"bits": [21, 21], "name": "GE_BUSY"},
13143    {"bits": [22, 22], "name": "SPI_BUSY"},
13144    {"bits": [23, 23], "name": "BCI_BUSY"},
13145    {"bits": [24, 24], "name": "SC_BUSY"},
13146    {"bits": [25, 25], "name": "PA_BUSY"},
13147    {"bits": [26, 26], "name": "DB_BUSY"},
13148    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
13149    {"bits": [29, 29], "name": "CP_BUSY"},
13150    {"bits": [30, 30], "name": "CB_BUSY"},
13151    {"bits": [31, 31], "name": "GUI_ACTIVE"}
13152   ]
13153  },
13154  "GRBM_STATUS2": {
13155   "fields": [
13156    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
13157    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
13158    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
13159    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
13160    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
13161    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
13162    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
13163    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
13164    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
13165    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
13166    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
13167    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
13168    {"bits": [15, 15], "name": "UTCL2_BUSY"},
13169    {"bits": [16, 16], "name": "EA_BUSY"},
13170    {"bits": [17, 17], "name": "RMI_BUSY"},
13171    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
13172    {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"},
13173    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
13174    {"bits": [21, 21], "name": "SDMA_BUSY"},
13175    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
13176    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
13177    {"bits": [24, 24], "name": "SDMA2_RQ_PENDING"},
13178    {"bits": [25, 25], "name": "SDMA3_RQ_PENDING"},
13179    {"bits": [26, 26], "name": "RLC_BUSY"},
13180    {"bits": [27, 27], "name": "TCP_BUSY"},
13181    {"bits": [28, 28], "name": "CPF_BUSY"},
13182    {"bits": [29, 29], "name": "CPC_BUSY"},
13183    {"bits": [30, 30], "name": "CPG_BUSY"},
13184    {"bits": [31, 31], "name": "CPAXI_BUSY"}
13185   ]
13186  },
13187  "GRBM_STATUS3": {
13188   "fields": [
13189    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
13190    {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
13191    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
13192    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
13193    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
13194    {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
13195    {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
13196    {"bits": [13, 13], "name": "PH_BUSY"},
13197    {"bits": [14, 14], "name": "CH_BUSY"},
13198    {"bits": [15, 15], "name": "GL2CC_BUSY"},
13199    {"bits": [16, 16], "name": "GL1CC_BUSY"},
13200    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
13201    {"bits": [29, 29], "name": "GUS_BUSY"},
13202    {"bits": [30, 30], "name": "UTCL1_BUSY"},
13203    {"bits": [31, 31], "name": "PMM_BUSY"}
13204   ]
13205  },
13206  "GRBM_STATUS_SE0": {
13207   "fields": [
13208    {"bits": [1, 1], "name": "DB_CLEAN"},
13209    {"bits": [2, 2], "name": "CB_CLEAN"},
13210    {"bits": [3, 3], "name": "UTCL1_BUSY"},
13211    {"bits": [4, 4], "name": "TCP_BUSY"},
13212    {"bits": [5, 5], "name": "GL1CC_BUSY"},
13213    {"bits": [21, 21], "name": "RMI_BUSY"},
13214    {"bits": [22, 22], "name": "BCI_BUSY"},
13215    {"bits": [24, 24], "name": "PA_BUSY"},
13216    {"bits": [25, 25], "name": "TA_BUSY"},
13217    {"bits": [26, 26], "name": "SX_BUSY"},
13218    {"bits": [27, 27], "name": "SPI_BUSY"},
13219    {"bits": [29, 29], "name": "SC_BUSY"},
13220    {"bits": [30, 30], "name": "DB_BUSY"},
13221    {"bits": [31, 31], "name": "CB_BUSY"}
13222   ]
13223  },
13224  "IA_MULTI_VGT_PARAM": {
13225   "fields": [
13226    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13227    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13228    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13229    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13230    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13231    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
13232   ]
13233  },
13234  "IA_MULTI_VGT_PARAM_PIPED": {
13235   "fields": [
13236    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13237    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13238    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13239    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13240    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13241    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
13242    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
13243    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
13244    {"bits": [23, 23], "name": "HW_USE_ONLY"}
13245   ]
13246  },
13247  "PA_CL_CLIP_CNTL": {
13248   "fields": [
13249    {"bits": [0, 0], "name": "UCP_ENA_0"},
13250    {"bits": [1, 1], "name": "UCP_ENA_1"},
13251    {"bits": [2, 2], "name": "UCP_ENA_2"},
13252    {"bits": [3, 3], "name": "UCP_ENA_3"},
13253    {"bits": [4, 4], "name": "UCP_ENA_4"},
13254    {"bits": [5, 5], "name": "UCP_ENA_5"},
13255    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
13256    {"bits": [14, 15], "name": "PS_UCP_MODE"},
13257    {"bits": [16, 16], "name": "CLIP_DISABLE"},
13258    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
13259    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
13260    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
13261    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
13262    {"bits": [21, 21], "name": "VTX_KILL_OR"},
13263    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
13264    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
13265    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
13266    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
13267    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
13268    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
13269   ]
13270  },
13271  "PA_CL_NANINF_CNTL": {
13272   "fields": [
13273    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
13274    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
13275    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
13276    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
13277    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
13278    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
13279    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
13280    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
13281    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
13282    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
13283    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
13284    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
13285    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
13286    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
13287    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
13288    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
13289   ]
13290  },
13291  "PA_CL_NGG_CNTL": {
13292   "fields": [
13293    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
13294    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
13295    {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"}
13296   ]
13297  },
13298  "PA_CL_VRS_CNTL": {
13299   "fields": [
13300    {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VERTEX_RATE_COMBINER_MODE"},
13301    {"bits": [3, 5], "enum_ref": "VRSCombinerMode", "name": "PRIMITIVE_RATE_COMBINER_MODE"},
13302    {"bits": [6, 8], "enum_ref": "VRSCombinerMode", "name": "HTILE_RATE_COMBINER_MODE"},
13303    {"bits": [9, 11], "enum_ref": "VRSCombinerMode", "name": "SAMPLE_ITER_COMBINER_MODE"},
13304    {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"},
13305    {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"}
13306   ]
13307  },
13308  "PA_CL_VS_OUT_CNTL": {
13309   "fields": [
13310    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
13311    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
13312    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
13313    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
13314    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
13315    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
13316    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
13317    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
13318    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
13319    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
13320    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
13321    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
13322    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
13323    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
13324    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
13325    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
13326    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
13327    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
13328    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
13329    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
13330    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
13331    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
13332    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
13333    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
13334    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
13335    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
13336    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
13337    {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"},
13338    {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"},
13339    {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"}
13340   ]
13341  },
13342  "PA_CL_VTE_CNTL": {
13343   "fields": [
13344    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
13345    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
13346    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
13347    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
13348    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
13349    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
13350    {"bits": [8, 8], "name": "VTX_XY_FMT"},
13351    {"bits": [9, 9], "name": "VTX_Z_FMT"},
13352    {"bits": [10, 10], "name": "VTX_W0_FMT"},
13353    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
13354   ]
13355  },
13356  "PA_SC_AA_CONFIG": {
13357   "fields": [
13358    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
13359    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
13360    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
13361    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
13362    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
13363    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
13364    {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"},
13365    {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"}
13366   ]
13367  },
13368  "PA_SC_AA_MASK_X0Y0_X1Y0": {
13369   "fields": [
13370    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
13371    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
13372   ]
13373  },
13374  "PA_SC_AA_MASK_X0Y1_X1Y1": {
13375   "fields": [
13376    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
13377    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
13378   ]
13379  },
13380  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
13381   "fields": [
13382    {"bits": [0, 3], "name": "S0_X"},
13383    {"bits": [4, 7], "name": "S0_Y"},
13384    {"bits": [8, 11], "name": "S1_X"},
13385    {"bits": [12, 15], "name": "S1_Y"},
13386    {"bits": [16, 19], "name": "S2_X"},
13387    {"bits": [20, 23], "name": "S2_Y"},
13388    {"bits": [24, 27], "name": "S3_X"},
13389    {"bits": [28, 31], "name": "S3_Y"}
13390   ]
13391  },
13392  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
13393   "fields": [
13394    {"bits": [0, 3], "name": "S4_X"},
13395    {"bits": [4, 7], "name": "S4_Y"},
13396    {"bits": [8, 11], "name": "S5_X"},
13397    {"bits": [12, 15], "name": "S5_Y"},
13398    {"bits": [16, 19], "name": "S6_X"},
13399    {"bits": [20, 23], "name": "S6_Y"},
13400    {"bits": [24, 27], "name": "S7_X"},
13401    {"bits": [28, 31], "name": "S7_Y"}
13402   ]
13403  },
13404  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
13405   "fields": [
13406    {"bits": [0, 3], "name": "S8_X"},
13407    {"bits": [4, 7], "name": "S8_Y"},
13408    {"bits": [8, 11], "name": "S9_X"},
13409    {"bits": [12, 15], "name": "S9_Y"},
13410    {"bits": [16, 19], "name": "S10_X"},
13411    {"bits": [20, 23], "name": "S10_Y"},
13412    {"bits": [24, 27], "name": "S11_X"},
13413    {"bits": [28, 31], "name": "S11_Y"}
13414   ]
13415  },
13416  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
13417   "fields": [
13418    {"bits": [0, 3], "name": "S12_X"},
13419    {"bits": [4, 7], "name": "S12_Y"},
13420    {"bits": [8, 11], "name": "S13_X"},
13421    {"bits": [12, 15], "name": "S13_Y"},
13422    {"bits": [16, 19], "name": "S14_X"},
13423    {"bits": [20, 23], "name": "S14_Y"},
13424    {"bits": [24, 27], "name": "S15_X"},
13425    {"bits": [28, 31], "name": "S15_Y"}
13426   ]
13427  },
13428  "PA_SC_BINNER_CNTL_0": {
13429   "fields": [
13430    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13431    {"bits": [2, 2], "name": "BIN_SIZE_X"},
13432    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13433    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13434    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13435    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13436    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13437    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13438    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13439    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13440    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13441    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13442   ]
13443  },
13444  "PA_SC_BINNER_CNTL_1": {
13445   "fields": [
13446    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13447    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13448   ]
13449  },
13450  "PA_SC_CENTROID_PRIORITY_0": {
13451   "fields": [
13452    {"bits": [0, 3], "name": "DISTANCE_0"},
13453    {"bits": [4, 7], "name": "DISTANCE_1"},
13454    {"bits": [8, 11], "name": "DISTANCE_2"},
13455    {"bits": [12, 15], "name": "DISTANCE_3"},
13456    {"bits": [16, 19], "name": "DISTANCE_4"},
13457    {"bits": [20, 23], "name": "DISTANCE_5"},
13458    {"bits": [24, 27], "name": "DISTANCE_6"},
13459    {"bits": [28, 31], "name": "DISTANCE_7"}
13460   ]
13461  },
13462  "PA_SC_CENTROID_PRIORITY_1": {
13463   "fields": [
13464    {"bits": [0, 3], "name": "DISTANCE_8"},
13465    {"bits": [4, 7], "name": "DISTANCE_9"},
13466    {"bits": [8, 11], "name": "DISTANCE_10"},
13467    {"bits": [12, 15], "name": "DISTANCE_11"},
13468    {"bits": [16, 19], "name": "DISTANCE_12"},
13469    {"bits": [20, 23], "name": "DISTANCE_13"},
13470    {"bits": [24, 27], "name": "DISTANCE_14"},
13471    {"bits": [28, 31], "name": "DISTANCE_15"}
13472   ]
13473  },
13474  "PA_SC_CLIPRECT_0_TL": {
13475   "fields": [
13476    {"bits": [0, 14], "name": "TL_X"},
13477    {"bits": [16, 30], "name": "TL_Y"}
13478   ]
13479  },
13480  "PA_SC_CLIPRECT_RULE": {
13481   "fields": [
13482    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13483   ]
13484  },
13485  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
13486   "fields": [
13487    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13488    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13489    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13490    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13491    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13492    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13493    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13494    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13495    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13496    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13497    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13498    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13499    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13500    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13501    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13502    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13503    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13504    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13505    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13506    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13507   ]
13508  },
13509  "PA_SC_EDGERULE": {
13510   "fields": [
13511    {"bits": [0, 3], "name": "ER_TRI"},
13512    {"bits": [4, 7], "name": "ER_POINT"},
13513    {"bits": [8, 11], "name": "ER_RECT"},
13514    {"bits": [12, 17], "name": "ER_LINE_LR"},
13515    {"bits": [18, 23], "name": "ER_LINE_RL"},
13516    {"bits": [24, 27], "name": "ER_LINE_TB"},
13517    {"bits": [28, 31], "name": "ER_LINE_BT"}
13518   ]
13519  },
13520  "PA_SC_LINE_CNTL": {
13521   "fields": [
13522    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13523    {"bits": [10, 10], "name": "LAST_PIXEL"},
13524    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13525    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13526    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13527   ]
13528  },
13529  "PA_SC_LINE_STIPPLE": {
13530   "fields": [
13531    {"bits": [0, 15], "name": "LINE_PATTERN"},
13532    {"bits": [16, 23], "name": "REPEAT_COUNT"},
13533    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13534    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13535   ]
13536  },
13537  "PA_SC_LINE_STIPPLE_STATE": {
13538   "fields": [
13539    {"bits": [0, 3], "name": "CURRENT_PTR"},
13540    {"bits": [8, 15], "name": "CURRENT_COUNT"}
13541   ]
13542  },
13543  "PA_SC_MODE_CNTL_0": {
13544   "fields": [
13545    {"bits": [0, 0], "name": "MSAA_ENABLE"},
13546    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13547    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13548    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13549    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13550    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13551   ]
13552  },
13553  "PA_SC_MODE_CNTL_1": {
13554   "fields": [
13555    {"bits": [0, 0], "name": "WALK_SIZE"},
13556    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13557    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13558    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13559    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13560    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13561    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13562    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13563    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13564    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13565    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13566    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13567    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13568    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13569    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13570    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13571    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13572    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13573    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13574    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13575    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13576    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13577    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13578    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13579   ]
13580  },
13581  "PA_SC_NGG_MODE_CNTL": {
13582   "fields": [
13583    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13584    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
13585   ]
13586  },
13587  "PA_SC_P3D_TRAP_SCREEN_H": {
13588   "fields": [
13589    {"bits": [0, 13], "name": "X_COORD"}
13590   ]
13591  },
13592  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
13593   "fields": [
13594    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13595    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13596   ]
13597  },
13598  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
13599   "fields": [
13600    {"bits": [0, 15], "name": "COUNT"}
13601   ]
13602  },
13603  "PA_SC_P3D_TRAP_SCREEN_V": {
13604   "fields": [
13605    {"bits": [0, 13], "name": "Y_COORD"}
13606   ]
13607  },
13608  "PA_SC_PERFCOUNTER1_SELECT": {
13609   "fields": [
13610    {"bits": [0, 9], "name": "PERF_SEL"}
13611   ]
13612  },
13613  "PA_SC_RASTER_CONFIG": {
13614   "fields": [
13615    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13616    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13617    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13618    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13619    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13620    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13621    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13622    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13623    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13624    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13625    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13626    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13627    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13628    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13629    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13630   ]
13631  },
13632  "PA_SC_RASTER_CONFIG_1": {
13633   "fields": [
13634    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13635    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13636    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13637   ]
13638  },
13639  "PA_SC_SCREEN_EXTENT_CONTROL": {
13640   "fields": [
13641    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13642    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13643   ]
13644  },
13645  "PA_SC_SCREEN_EXTENT_MIN_0": {
13646   "fields": [
13647    {"bits": [0, 15], "name": "X"},
13648    {"bits": [16, 31], "name": "Y"}
13649   ]
13650  },
13651  "PA_SC_SCREEN_SCISSOR_BR": {
13652   "fields": [
13653    {"bits": [0, 15], "name": "BR_X"},
13654    {"bits": [16, 31], "name": "BR_Y"}
13655   ]
13656  },
13657  "PA_SC_SCREEN_SCISSOR_TL": {
13658   "fields": [
13659    {"bits": [0, 15], "name": "TL_X"},
13660    {"bits": [16, 31], "name": "TL_Y"}
13661   ]
13662  },
13663  "PA_SC_SHADER_CONTROL": {
13664   "fields": [
13665    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13666    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13667    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13668    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
13669   ]
13670  },
13671  "PA_SC_TILE_STEERING_OVERRIDE": {
13672   "fields": [
13673    {"bits": [0, 0], "name": "ENABLE"},
13674    {"bits": [1, 2], "name": "NUM_SE"},
13675    {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
13676    {"bits": [12, 13], "name": "NUM_SC"},
13677    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13678    {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"}
13679   ]
13680  },
13681  "PA_SC_WINDOW_OFFSET": {
13682   "fields": [
13683    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13684    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13685   ]
13686  },
13687  "PA_SC_WINDOW_SCISSOR_BR": {
13688   "fields": [
13689    {"bits": [0, 14], "name": "BR_X"},
13690    {"bits": [16, 30], "name": "BR_Y"}
13691   ]
13692  },
13693  "PA_SC_WINDOW_SCISSOR_TL": {
13694   "fields": [
13695    {"bits": [0, 14], "name": "TL_X"},
13696    {"bits": [16, 30], "name": "TL_Y"},
13697    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13698   ]
13699  },
13700  "PA_STEREO_CNTL": {
13701   "fields": [
13702    {"bits": [1, 4], "name": "STEREO_MODE"},
13703    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13704    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13705    {"bits": [16, 18], "name": "VP_ID_MODE"},
13706    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13707   ]
13708  },
13709  "PA_SU_HARDWARE_SCREEN_OFFSET": {
13710   "fields": [
13711    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13712    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13713   ]
13714  },
13715  "PA_SU_LINE_CNTL": {
13716   "fields": [
13717    {"bits": [0, 15], "name": "WIDTH"}
13718   ]
13719  },
13720  "PA_SU_LINE_STIPPLE_CNTL": {
13721   "fields": [
13722    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13723    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13724    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
13725    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
13726   ]
13727  },
13728  "PA_SU_LINE_STIPPLE_VALUE": {
13729   "fields": [
13730    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13731   ]
13732  },
13733  "PA_SU_OVER_RASTERIZATION_CNTL": {
13734   "fields": [
13735    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13736    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13737    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13738    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13739    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13740   ]
13741  },
13742  "PA_SU_PERFCOUNTER0_SELECT": {
13743   "fields": [
13744    {"bits": [0, 9], "name": "PERF_SEL"},
13745    {"bits": [10, 19], "name": "PERF_SEL1"},
13746    {"bits": [20, 23], "name": "CNTR_MODE"},
13747    {"bits": [24, 27], "name": "PERF_MODE1"},
13748    {"bits": [28, 31], "name": "PERF_MODE"}
13749   ]
13750  },
13751  "PA_SU_PERFCOUNTER0_SELECT1": {
13752   "fields": [
13753    {"bits": [0, 9], "name": "PERF_SEL2"},
13754    {"bits": [10, 19], "name": "PERF_SEL3"},
13755    {"bits": [24, 27], "name": "PERF_MODE3"},
13756    {"bits": [28, 31], "name": "PERF_MODE2"}
13757   ]
13758  },
13759  "PA_SU_POINT_MINMAX": {
13760   "fields": [
13761    {"bits": [0, 15], "name": "MIN_SIZE"},
13762    {"bits": [16, 31], "name": "MAX_SIZE"}
13763   ]
13764  },
13765  "PA_SU_POINT_SIZE": {
13766   "fields": [
13767    {"bits": [0, 15], "name": "HEIGHT"},
13768    {"bits": [16, 31], "name": "WIDTH"}
13769   ]
13770  },
13771  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
13772   "fields": [
13773    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13774    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13775   ]
13776  },
13777  "PA_SU_PRIM_FILTER_CNTL": {
13778   "fields": [
13779    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13780    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13781    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13782    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13783    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13784    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13785    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13786    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13787    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13788    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13789    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13790   ]
13791  },
13792  "PA_SU_SC_MODE_CNTL": {
13793   "fields": [
13794    {"bits": [0, 0], "name": "CULL_FRONT"},
13795    {"bits": [1, 1], "name": "CULL_BACK"},
13796    {"bits": [2, 2], "name": "FACE"},
13797    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13798    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13799    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13800    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13801    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13802    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13803    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13804    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13805    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13806    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13807    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13808    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13809    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13810   ]
13811  },
13812  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
13813   "fields": [
13814    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13815    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13816    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13817    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13818    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}
13819   ]
13820  },
13821  "PA_SU_VTX_CNTL": {
13822   "fields": [
13823    {"bits": [0, 0], "name": "PIX_CENTER"},
13824    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13825    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13826   ]
13827  },
13828  "RLC_GPM_PERF_COUNT_0": {
13829   "fields": [
13830    {"bits": [0, 3], "name": "FEATURE_SEL"},
13831    {"bits": [4, 7], "name": "SE_INDEX"},
13832    {"bits": [8, 11], "name": "SA_INDEX"},
13833    {"bits": [12, 15], "name": "WGP_INDEX"},
13834    {"bits": [16, 17], "name": "EVENT_SEL"},
13835    {"bits": [18, 19], "name": "UNUSED"},
13836    {"bits": [20, 20], "name": "ENABLE"},
13837    {"bits": [21, 31], "name": "RESERVED"}
13838   ]
13839  },
13840  "RLC_GPU_IOV_PERF_CNT_CNTL": {
13841   "fields": [
13842    {"bits": [0, 0], "name": "ENABLE"},
13843    {"bits": [1, 1], "name": "MODE_SELECT"},
13844    {"bits": [2, 2], "name": "RESET"},
13845    {"bits": [3, 31], "name": "RESERVED"}
13846   ]
13847  },
13848  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
13849   "fields": [
13850    {"bits": [0, 3], "name": "VFID"},
13851    {"bits": [4, 5], "name": "CNT_ID"},
13852    {"bits": [6, 31], "name": "RESERVED"}
13853   ]
13854  },
13855  "RLC_PERFCOUNTER0_SELECT": {
13856   "fields": [
13857    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
13858   ]
13859  },
13860  "RLC_PERFMON_CLK_CNTL": {
13861   "fields": [
13862    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
13863   ]
13864  },
13865  "RLC_PERFMON_CNTL": {
13866   "fields": [
13867    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13868    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13869   ]
13870  },
13871  "RLC_SPM_ACCUM_CTRL": {
13872   "fields": [
13873    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
13874    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
13875    {"bits": [2, 2], "name": "StrobeRearmAccum"},
13876    {"bits": [3, 3], "name": "StrobeResetSpmBlock"},
13877    {"bits": [4, 7], "name": "StrobeStartSpm"},
13878    {"bits": [8, 8], "name": "StrobeRearmSwaAccum"},
13879    {"bits": [9, 9], "name": "StrobeStartSwa"},
13880    {"bits": [10, 10], "name": "StrobePerfmonSampleWires"},
13881    {"bits": [11, 31], "name": "RESERVED"}
13882   ]
13883  },
13884  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
13885   "fields": [
13886    {"bits": [0, 10], "name": "addr"},
13887    {"bits": [11, 31], "name": "RESERVED"}
13888   ]
13889  },
13890  "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET": {
13891   "fields": [
13892    {"bits": [0, 7], "name": "global_offset"},
13893    {"bits": [8, 15], "name": "spmwithaccum_se_offset"},
13894    {"bits": [16, 23], "name": "spmwithaccum_global_offset"},
13895    {"bits": [24, 31], "name": "RESERVED"}
13896   ]
13897  },
13898  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
13899   "fields": [
13900    {"bits": [0, 7], "name": "data"},
13901    {"bits": [8, 31], "name": "RESERVED"}
13902   ]
13903  },
13904  "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS": {
13905   "fields": [
13906    {"bits": [0, 7], "name": "spp_addr_region"},
13907    {"bits": [8, 15], "name": "swa_addr_region"},
13908    {"bits": [16, 31], "name": "RESERVED"}
13909   ]
13910  },
13911  "RLC_SPM_ACCUM_DATARAM_ADDR": {
13912   "fields": [
13913    {"bits": [0, 6], "name": "addr"},
13914    {"bits": [7, 31], "name": "RESERVED"}
13915   ]
13916  },
13917  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
13918   "fields": [
13919    {"bits": [0, 18], "name": "DataRamWrCount"},
13920    {"bits": [19, 31], "name": "RESERVED"}
13921   ]
13922  },
13923  "RLC_SPM_ACCUM_MODE": {
13924   "fields": [
13925    {"bits": [0, 0], "name": "EnableAccum"},
13926    {"bits": [1, 1], "name": "EnableSpmWithAccumMode"},
13927    {"bits": [2, 2], "name": "EnableSPPMode"},
13928    {"bits": [3, 3], "name": "AutoResetPerfmonDisable"},
13929    {"bits": [4, 4], "name": "SwaAutoResetPerfmonDisable"},
13930    {"bits": [5, 5], "name": "AutoAccumEn"},
13931    {"bits": [6, 6], "name": "SwaAutoAccumEn"},
13932    {"bits": [7, 7], "name": "AutoSpmEn"},
13933    {"bits": [8, 8], "name": "SwaAutoSpmEn"},
13934    {"bits": [9, 9], "name": "Globals_LoadOverride"},
13935    {"bits": [10, 10], "name": "Globals_SwaLoadOverride"},
13936    {"bits": [11, 11], "name": "SE0_LoadOverride"},
13937    {"bits": [12, 12], "name": "SE0_SwaLoadOverride"},
13938    {"bits": [13, 13], "name": "SE1_LoadOverride"},
13939    {"bits": [14, 14], "name": "SE1_SwaLoadOverride"},
13940    {"bits": [15, 15], "name": "SE2_LoadOverride"},
13941    {"bits": [16, 16], "name": "SE2_SwaLoadOverride"},
13942    {"bits": [17, 17], "name": "SE3_LoadOverride"},
13943    {"bits": [18, 18], "name": "SE3_SwaLoadOverride"}
13944   ]
13945  },
13946  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
13947   "fields": [
13948    {"bits": [0, 7], "name": "SamplesRequested"}
13949   ]
13950  },
13951  "RLC_SPM_ACCUM_STATUS": {
13952   "fields": [
13953    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
13954    {"bits": [8, 8], "name": "AccumDone"},
13955    {"bits": [9, 9], "name": "SpmDone"},
13956    {"bits": [10, 10], "name": "AccumOverflow"},
13957    {"bits": [11, 11], "name": "AccumArmed"},
13958    {"bits": [12, 12], "name": "SequenceInProgress"},
13959    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
13960    {"bits": [14, 14], "name": "AllFifosEmpty"},
13961    {"bits": [15, 15], "name": "FSMIsIdle"},
13962    {"bits": [16, 16], "name": "SwaAccumDone"},
13963    {"bits": [17, 17], "name": "SwaSpmDone"},
13964    {"bits": [18, 18], "name": "SwaAccumOverflow"},
13965    {"bits": [19, 19], "name": "SwaAccumArmed"},
13966    {"bits": [20, 20], "name": "AllSegsDone"},
13967    {"bits": [21, 21], "name": "RearmSwaPending"},
13968    {"bits": [22, 22], "name": "RearmSppPending"},
13969    {"bits": [23, 31], "name": "RESERVED"}
13970   ]
13971  },
13972  "RLC_SPM_ACCUM_THRESHOLD": {
13973   "fields": [
13974    {"bits": [0, 15], "name": "Threshold"}
13975   ]
13976  },
13977  "RLC_SPM_DESER_START_SKEW": {
13978   "fields": [
13979    {"bits": [0, 6], "name": "DESER_START_SKEW"},
13980    {"bits": [7, 31], "name": "RESERVED"}
13981   ]
13982  },
13983  "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
13984   "fields": [
13985    {"bits": [0, 6], "name": "data"},
13986    {"bits": [7, 31], "name": "RESERVED"}
13987   ]
13988  },
13989  "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
13990   "fields": [
13991    {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
13992    {"bits": [7, 31], "name": "RESERVED"}
13993   ]
13994  },
13995  "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
13996   "fields": [
13997    {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
13998    {"bits": [7, 31], "name": "RESERVED"}
13999   ]
14000  },
14001  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
14002   "fields": [
14003    {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
14004    {"bits": [8, 31], "name": "RESERVED"}
14005   ]
14006  },
14007  "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET": {
14008   "fields": [
14009    {"bits": [0, 15], "name": "OFFSET"},
14010    {"bits": [16, 31], "name": "RESERVED"}
14011   ]
14012  },
14013  "RLC_SPM_PERFMON_CNTL": {
14014   "fields": [
14015    {"bits": [0, 11], "name": "RESERVED1"},
14016    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
14017    {"bits": [14, 15], "name": "RESERVED"},
14018    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
14019   ]
14020  },
14021  "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
14022   "fields": [
14023    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14024    {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
14025    {"bits": [16, 31], "name": "RESERVED"}
14026   ]
14027  },
14028  "RLC_SPM_PERFMON_RING_BASE_HI": {
14029   "fields": [
14030    {"bits": [0, 15], "name": "RING_BASE_HI"},
14031    {"bits": [16, 31], "name": "RESERVED"}
14032   ]
14033  },
14034  "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
14035   "fields": [
14036    {"bits": [0, 7], "name": "SE0_NUM_LINE"},
14037    {"bits": [8, 15], "name": "SE1_NUM_LINE"},
14038    {"bits": [16, 23], "name": "SE2_NUM_LINE"},
14039    {"bits": [24, 31], "name": "SE3_NUM_LINE"}
14040   ]
14041  },
14042  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
14043   "fields": [
14044    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14045    {"bits": [8, 10], "name": "RESERVED1"},
14046    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
14047    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
14048    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
14049    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
14050    {"bits": [31, 31], "name": "RESERVED"}
14051   ]
14052  },
14053  "RLC_SPM_RING_WRPTR": {
14054   "fields": [
14055    {"bits": [0, 4], "name": "RESERVED"},
14056    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
14057   ]
14058  },
14059  "RLC_SPM_SEGMENT_THRESHOLD": {
14060   "fields": [
14061    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
14062    {"bits": [8, 31], "name": "RESERVED"}
14063   ]
14064  },
14065  "RLC_SPM_SE_MUXSEL_ADDR": {
14066   "fields": [
14067    {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
14068    {"bits": [9, 31], "name": "RESERVED"}
14069   ]
14070  },
14071  "RLC_SPM_SE_MUXSEL_SKEW": {
14072   "fields": [
14073    {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
14074    {"bits": [7, 31], "name": "RESERVED"}
14075   ]
14076  },
14077  "RLC_SPM_SE_SAMPLE_SKEW": {
14078   "fields": [
14079    {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
14080    {"bits": [7, 31], "name": "RESERVED"}
14081   ]
14082  },
14083  "RLC_SPM_VIRT_CTRL": {
14084   "fields": [
14085    {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
14086   ]
14087  },
14088  "RLC_SPM_VIRT_STATUS": {
14089   "fields": [
14090    {"bits": [0, 0], "name": "SpmSamplingPaused"}
14091   ]
14092  },
14093  "RMI_PERF_COUNTER_CNTL": {
14094   "fields": [
14095    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
14096    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
14097    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
14098    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
14099    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
14100    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
14101    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
14102    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
14103    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
14104    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
14105   ]
14106  },
14107  "SCRATCH_REG_ATOMIC": {
14108   "fields": [
14109    {"bits": [0, 23], "name": "IMMED"},
14110    {"bits": [24, 26], "name": "ID"},
14111    {"bits": [27, 27], "name": "reserved27"},
14112    {"bits": [28, 30], "name": "OP"},
14113    {"bits": [31, 31], "name": "reserved31"}
14114   ]
14115  },
14116  "SCRATCH_UMSK": {
14117   "fields": [
14118    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
14119    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
14120   ]
14121  },
14122  "SDMA0_PERFCNT_MISC_CNTL": {
14123   "fields": [
14124    {"bits": [0, 15], "name": "CMD_OP"}
14125   ]
14126  },
14127  "SPI_BARYC_CNTL": {
14128   "fields": [
14129    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
14130    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
14131    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
14132    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
14133    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
14134    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
14135    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
14136   ]
14137  },
14138  "SPI_CONFIG_CNTL": {
14139   "fields": [
14140    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
14141    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
14142    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
14143    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
14144    {"bits": [26, 26], "name": "FORCE_HALF_RATE_PC_EXP"},
14145    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
14146    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
14147    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
14148    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
14149   ]
14150  },
14151  "SPI_INTERP_CONTROL_0": {
14152   "fields": [
14153    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
14154    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
14155    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14156    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14157    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14158    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14159    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
14160   ]
14161  },
14162  "SPI_PERFCOUNTER_BINS": {
14163   "fields": [
14164    {"bits": [0, 3], "name": "BIN0_MIN"},
14165    {"bits": [4, 7], "name": "BIN0_MAX"},
14166    {"bits": [8, 11], "name": "BIN1_MIN"},
14167    {"bits": [12, 15], "name": "BIN1_MAX"},
14168    {"bits": [16, 19], "name": "BIN2_MIN"},
14169    {"bits": [20, 23], "name": "BIN2_MAX"},
14170    {"bits": [24, 27], "name": "BIN3_MIN"},
14171    {"bits": [28, 31], "name": "BIN3_MAX"}
14172   ]
14173  },
14174  "SPI_PS_INPUT_CNTL_0": {
14175   "fields": [
14176    {"bits": [0, 5], "name": "OFFSET"},
14177    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14178    {"bits": [10, 10], "name": "FLAT_SHADE"},
14179    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14180    {"bits": [13, 16], "name": "CYL_WRAP"},
14181    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
14182    {"bits": [18, 18], "name": "DUP"},
14183    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14184    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14185    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14186    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
14187    {"bits": [24, 24], "name": "ATTR0_VALID"},
14188    {"bits": [25, 25], "name": "ATTR1_VALID"}
14189   ]
14190  },
14191  "SPI_PS_INPUT_CNTL_20": {
14192   "fields": [
14193    {"bits": [0, 5], "name": "OFFSET"},
14194    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14195    {"bits": [10, 10], "name": "FLAT_SHADE"},
14196    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14197    {"bits": [18, 18], "name": "DUP"},
14198    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14199    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14200    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14201    {"bits": [24, 24], "name": "ATTR0_VALID"},
14202    {"bits": [25, 25], "name": "ATTR1_VALID"}
14203   ]
14204  },
14205  "SPI_PS_INPUT_ENA": {
14206   "fields": [
14207    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
14208    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
14209    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
14210    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
14211    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
14212    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
14213    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
14214    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
14215    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
14216    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
14217    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
14218    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
14219    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
14220    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
14221    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
14222    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
14223   ]
14224  },
14225  "SPI_PS_IN_CONTROL": {
14226   "fields": [
14227    {"bits": [0, 5], "name": "NUM_INTERP"},
14228    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
14229    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
14230    {"bits": [9, 13], "name": "NUM_PRIM_INTERP"},
14231    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
14232    {"bits": [15, 15], "name": "PS_W32_EN"}
14233   ]
14234  },
14235  "SPI_SHADER_COL_FORMAT": {
14236   "fields": [
14237    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14238    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14239    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14240    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14241    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14242    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14243    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14244    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14245   ]
14246  },
14247  "SPI_SHADER_IDX_FORMAT": {
14248   "fields": [
14249    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14250   ]
14251  },
14252  "SPI_SHADER_LATE_ALLOC_VS": {
14253   "fields": [
14254    {"bits": [0, 5], "name": "LIMIT"}
14255   ]
14256  },
14257  "SPI_SHADER_PGM_HI_PS": {
14258   "fields": [
14259    {"bits": [0, 7], "name": "MEM_BASE"}
14260   ]
14261  },
14262  "SPI_SHADER_PGM_RSRC1_GS": {
14263   "fields": [
14264    {"bits": [0, 5], "name": "VGPRS"},
14265    {"bits": [6, 9], "name": "SGPRS"},
14266    {"bits": [10, 11], "name": "PRIORITY"},
14267    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14268    {"bits": [20, 20], "name": "PRIV"},
14269    {"bits": [21, 21], "name": "DX10_CLAMP"},
14270    {"bits": [23, 23], "name": "IEEE_MODE"},
14271    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
14272    {"bits": [25, 25], "name": "MEM_ORDERED"},
14273    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14274    {"bits": [27, 27], "name": "WGP_MODE"},
14275    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
14276    {"bits": [31, 31], "name": "FP16_OVFL"}
14277   ]
14278  },
14279  "SPI_SHADER_PGM_RSRC1_HS": {
14280   "fields": [
14281    {"bits": [0, 5], "name": "VGPRS"},
14282    {"bits": [6, 9], "name": "SGPRS"},
14283    {"bits": [10, 11], "name": "PRIORITY"},
14284    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14285    {"bits": [20, 20], "name": "PRIV"},
14286    {"bits": [21, 21], "name": "DX10_CLAMP"},
14287    {"bits": [23, 23], "name": "IEEE_MODE"},
14288    {"bits": [24, 24], "name": "MEM_ORDERED"},
14289    {"bits": [25, 25], "name": "FWD_PROGRESS"},
14290    {"bits": [26, 26], "name": "WGP_MODE"},
14291    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14292    {"bits": [30, 30], "name": "FP16_OVFL"}
14293   ]
14294  },
14295  "SPI_SHADER_PGM_RSRC1_PS": {
14296   "fields": [
14297    {"bits": [0, 5], "name": "VGPRS"},
14298    {"bits": [6, 9], "name": "SGPRS"},
14299    {"bits": [10, 11], "name": "PRIORITY"},
14300    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14301    {"bits": [20, 20], "name": "PRIV"},
14302    {"bits": [21, 21], "name": "DX10_CLAMP"},
14303    {"bits": [23, 23], "name": "IEEE_MODE"},
14304    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14305    {"bits": [25, 25], "name": "MEM_ORDERED"},
14306    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14307    {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"},
14308    {"bits": [29, 29], "name": "FP16_OVFL"}
14309   ]
14310  },
14311  "SPI_SHADER_PGM_RSRC1_VS": {
14312   "fields": [
14313    {"bits": [0, 5], "name": "VGPRS"},
14314    {"bits": [6, 9], "name": "SGPRS"},
14315    {"bits": [10, 11], "name": "PRIORITY"},
14316    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14317    {"bits": [20, 20], "name": "PRIV"},
14318    {"bits": [21, 21], "name": "DX10_CLAMP"},
14319    {"bits": [23, 23], "name": "IEEE_MODE"},
14320    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14321    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14322    {"bits": [27, 27], "name": "MEM_ORDERED"},
14323    {"bits": [28, 28], "name": "FWD_PROGRESS"},
14324    {"bits": [31, 31], "name": "FP16_OVFL"}
14325   ]
14326  },
14327  "SPI_SHADER_PGM_RSRC2_GS": {
14328   "fields": [
14329    {"bits": [0, 0], "name": "SCRATCH_EN"},
14330    {"bits": [1, 5], "name": "USER_SGPR"},
14331    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14332    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14333    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14334    {"bits": [18, 18], "name": "OC_LDS_EN"},
14335    {"bits": [19, 26], "name": "LDS_SIZE"},
14336    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14337    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14338   ]
14339  },
14340  "SPI_SHADER_PGM_RSRC2_GS_VS": {
14341   "fields": [
14342    {"bits": [0, 0], "name": "SCRATCH_EN"},
14343    {"bits": [1, 5], "name": "USER_SGPR"},
14344    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14345    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14346    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
14347    {"bits": [18, 18], "name": "OC_LDS_EN"},
14348    {"bits": [19, 26], "name": "LDS_SIZE"},
14349    {"bits": [27, 27], "name": "SKIP_USGPR0"},
14350    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
14351   ]
14352  },
14353  "SPI_SHADER_PGM_RSRC2_HS": {
14354   "fields": [
14355    {"bits": [0, 0], "name": "SCRATCH_EN"},
14356    {"bits": [1, 5], "name": "USER_SGPR"},
14357    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14358    {"bits": [7, 7], "name": "OC_LDS_EN"},
14359    {"bits": [8, 8], "name": "TG_SIZE_EN"},
14360    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14361    {"bits": [18, 26], "name": "LDS_SIZE"},
14362    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14363    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14364   ]
14365  },
14366  "SPI_SHADER_PGM_RSRC2_PS": {
14367   "fields": [
14368    {"bits": [0, 0], "name": "SCRATCH_EN"},
14369    {"bits": [1, 5], "name": "USER_SGPR"},
14370    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14371    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14372    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14373    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14374    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14375    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14376    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14377    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14378   ]
14379  },
14380  "SPI_SHADER_PGM_RSRC2_VS": {
14381   "fields": [
14382    {"bits": [0, 0], "name": "SCRATCH_EN"},
14383    {"bits": [1, 5], "name": "USER_SGPR"},
14384    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14385    {"bits": [7, 7], "name": "OC_LDS_EN"},
14386    {"bits": [8, 8], "name": "SO_BASE0_EN"},
14387    {"bits": [9, 9], "name": "SO_BASE1_EN"},
14388    {"bits": [10, 10], "name": "SO_BASE2_EN"},
14389    {"bits": [11, 11], "name": "SO_BASE3_EN"},
14390    {"bits": [12, 12], "name": "SO_EN"},
14391    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14392    {"bits": [22, 22], "name": "PC_BASE_EN"},
14393    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
14394    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14395    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14396   ]
14397  },
14398  "SPI_SHADER_PGM_RSRC3_GS": {
14399   "fields": [
14400    {"bits": [0, 15], "name": "CU_EN"},
14401    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14402    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14403    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14404   ]
14405  },
14406  "SPI_SHADER_PGM_RSRC3_HS": {
14407   "fields": [
14408    {"bits": [0, 5], "name": "WAVE_LIMIT"},
14409    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14410    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14411    {"bits": [16, 31], "name": "CU_EN"}
14412   ]
14413  },
14414  "SPI_SHADER_PGM_RSRC3_PS": {
14415   "fields": [
14416    {"bits": [0, 15], "name": "CU_EN"},
14417    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14418    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
14419   ]
14420  },
14421  "SPI_SHADER_PGM_RSRC4_GS": {
14422   "fields": [
14423    {"bits": [0, 15], "name": "CU_EN"},
14424    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
14425   ]
14426  },
14427  "SPI_SHADER_PGM_RSRC4_PS": {
14428   "fields": [
14429    {"bits": [0, 15], "name": "CU_EN"}
14430   ]
14431  },
14432  "SPI_SHADER_POS_FORMAT": {
14433   "fields": [
14434    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14435    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14436    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14437    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14438    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14439   ]
14440  },
14441  "SPI_SHADER_REQ_CTRL_PS": {
14442   "fields": [
14443    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14444    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14445    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14446    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14447    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14448    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14449    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14450    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14451   ]
14452  },
14453  "SPI_SHADER_USER_ACCUM_PS_0": {
14454   "fields": [
14455    {"bits": [0, 6], "name": "CONTRIBUTION"}
14456   ]
14457  },
14458  "SPI_SHADER_Z_FORMAT": {
14459   "fields": [
14460    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14461   ]
14462  },
14463  "SPI_VS_OUT_CONFIG": {
14464   "fields": [
14465    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14466    {"bits": [6, 6], "name": "VS_HALF_PACK"},
14467    {"bits": [7, 7], "name": "NO_PC_EXPORT"},
14468    {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"}
14469   ]
14470  },
14471  "SQC_CACHES": {
14472   "fields": [
14473    {"bits": [0, 0], "name": "TARGET_INST"},
14474    {"bits": [1, 1], "name": "TARGET_DATA"},
14475    {"bits": [2, 2], "name": "INVALIDATE"},
14476    {"bits": [16, 16], "name": "COMPLETE"},
14477    {"bits": [17, 18], "name": "L2_WB_POLICY"}
14478   ]
14479  },
14480  "SQ_PERFCOUNTER0_SELECT": {
14481   "fields": [
14482    {"bits": [0, 8], "name": "PERF_SEL"},
14483    {"bits": [20, 23], "name": "SPM_MODE"},
14484    {"bits": [28, 31], "name": "PERF_MODE"}
14485   ]
14486  },
14487  "SQ_PERFCOUNTER_CTRL": {
14488   "fields": [
14489    {"bits": [0, 0], "name": "PS_EN"},
14490    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14491    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14492    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14493    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14494    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14495    {"bits": [6, 6], "name": "CS_EN"},
14496    {"bits": [8, 9], "name": "CNTR_RATE"},
14497    {"bits": [13, 13], "name": "DISABLE_FLUSH"},
14498    {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"},
14499    {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"},
14500    {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"},
14501    {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"},
14502    {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"},
14503    {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"}
14504   ]
14505  },
14506  "SQ_PERFCOUNTER_CTRL2": {
14507   "fields": [
14508    {"bits": [0, 0], "name": "FORCE_EN"}
14509   ]
14510  },
14511  "SQ_THREAD_TRACE_BUF0_SIZE": {
14512   "fields": [
14513    {"bits": [0, 3], "name": "BASE_HI"},
14514    {"bits": [8, 29], "name": "SIZE"}
14515   ]
14516  },
14517  "SQ_THREAD_TRACE_CTRL": {
14518   "fields": [
14519    {"bits": [0, 1], "name": "MODE"},
14520    {"bits": [2, 2], "name": "ALL_VMID"},
14521    {"bits": [3, 3], "name": "CH_PERF_EN"},
14522    {"bits": [4, 4], "name": "INTERRUPT_EN"},
14523    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14524    {"bits": [6, 8], "name": "HIWATER"},
14525    {"bits": [9, 9], "name": "REG_STALL_EN"},
14526    {"bits": [10, 10], "name": "SPI_STALL_EN"},
14527    {"bits": [11, 11], "name": "SQ_STALL_EN"},
14528    {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
14529    {"bits": [13, 13], "name": "UTIL_TIMER"},
14530    {"bits": [14, 15], "name": "WAVESTART_MODE"},
14531    {"bits": [16, 17], "name": "RT_FREQ"},
14532    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14533    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14534    {"bits": [20, 22], "name": "LOWATER_OFFSET"},
14535    {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"},
14536    {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"},
14537    {"bits": [30, 30], "name": "CAPTURE_ALL"},
14538    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14539   ]
14540  },
14541  "SQ_THREAD_TRACE_MASK": {
14542   "fields": [
14543    {"bits": [0, 1], "name": "SIMD_SEL"},
14544    {"bits": [4, 7], "name": "WGP_SEL"},
14545    {"bits": [9, 9], "name": "SA_SEL"},
14546    {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
14547   ]
14548  },
14549  "SQ_THREAD_TRACE_STATUS": {
14550   "fields": [
14551    {"bits": [0, 11], "name": "FINISH_PENDING"},
14552    {"bits": [12, 23], "name": "FINISH_DONE"},
14553    {"bits": [24, 24], "name": "UTC_ERR"},
14554    {"bits": [25, 25], "name": "BUSY"},
14555    {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
14556    {"bits": [27, 27], "name": "EVENT_CNTR_STALL"},
14557    {"bits": [28, 31], "name": "OWNER_VMID"}
14558   ]
14559  },
14560  "SQ_THREAD_TRACE_STATUS2": {
14561   "fields": [
14562    {"bits": [0, 0], "name": "BUF0_FULL"},
14563    {"bits": [1, 1], "name": "BUF1_FULL"},
14564    {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"}
14565   ]
14566  },
14567  "SQ_THREAD_TRACE_TOKEN_MASK": {
14568   "fields": [
14569    {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14570    {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"},
14571    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14572    {"bits": [24, 25], "name": "INST_EXCLUDE"},
14573    {"bits": [26, 28], "name": "REG_EXCLUDE"},
14574    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14575   ]
14576  },
14577  "SQ_THREAD_TRACE_WPTR": {
14578   "fields": [
14579    {"bits": [0, 28], "name": "OFFSET"},
14580    {"bits": [31, 31], "name": "BUFFER_ID"}
14581   ]
14582  },
14583  "SQ_WAVE_ACTIVE": {
14584   "fields": [
14585    {"bits": [0, 19], "name": "WAVE_SLOT"}
14586   ]
14587  },
14588  "SQ_WAVE_GPR_ALLOC": {
14589   "fields": [
14590    {"bits": [0, 7], "name": "VGPR_BASE"},
14591    {"bits": [8, 15], "name": "VGPR_SIZE"},
14592    {"bits": [16, 23], "name": "SGPR_BASE"},
14593    {"bits": [24, 27], "name": "SGPR_SIZE"}
14594   ]
14595  },
14596  "SQ_WAVE_HW_ID1": {
14597   "fields": [
14598    {"bits": [0, 4], "name": "WAVE_ID"},
14599    {"bits": [8, 9], "name": "SIMD_ID"},
14600    {"bits": [10, 13], "name": "WGP_ID"},
14601    {"bits": [16, 16], "name": "SA_ID"},
14602    {"bits": [18, 19], "name": "SE_ID"}
14603   ]
14604  },
14605  "SQ_WAVE_HW_ID2": {
14606   "fields": [
14607    {"bits": [0, 3], "name": "QUEUE_ID"},
14608    {"bits": [4, 5], "name": "PIPE_ID"},
14609    {"bits": [8, 9], "name": "ME_ID"},
14610    {"bits": [12, 14], "name": "STATE_ID"},
14611    {"bits": [16, 20], "name": "WG_ID"},
14612    {"bits": [24, 27], "name": "VM_ID"}
14613   ]
14614  },
14615  "SQ_WAVE_HW_ID_LEGACY": {
14616   "fields": [
14617    {"bits": [0, 3], "name": "WAVE_ID"},
14618    {"bits": [4, 5], "name": "SIMD_ID"},
14619    {"bits": [6, 7], "name": "PIPE_ID"},
14620    {"bits": [8, 11], "name": "CU_ID"},
14621    {"bits": [12, 12], "name": "SH_ID"},
14622    {"bits": [13, 14], "name": "SE_ID"},
14623    {"bits": [15, 15], "name": "WAVE_ID_MSB"},
14624    {"bits": [16, 19], "name": "TG_ID"},
14625    {"bits": [20, 23], "name": "VM_ID"},
14626    {"bits": [24, 26], "name": "QUEUE_ID"},
14627    {"bits": [27, 29], "name": "STATE_ID"},
14628    {"bits": [30, 31], "name": "ME_ID"}
14629   ]
14630  },
14631  "SQ_WAVE_IB_DBG1": {
14632   "fields": [
14633    {"bits": [24, 24], "name": "WAVE_IDLE"},
14634    {"bits": [25, 31], "name": "MISC_CNT"}
14635   ]
14636  },
14637  "SQ_WAVE_IB_STS": {
14638   "fields": [
14639    {"bits": [0, 3], "name": "VM_CNT"},
14640    {"bits": [4, 6], "name": "EXP_CNT"},
14641    {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
14642    {"bits": [8, 11], "name": "LGKM_CNT"},
14643    {"bits": [12, 14], "name": "VALU_CNT"},
14644    {"bits": [22, 23], "name": "VM_CNT_HI"},
14645    {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
14646    {"bits": [26, 31], "name": "VS_CNT"}
14647   ]
14648  },
14649  "SQ_WAVE_IB_STS2": {
14650   "fields": [
14651    {"bits": [0, 1], "name": "INST_PREFETCH"},
14652    {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
14653    {"bits": [8, 9], "name": "MEM_ORDER"},
14654    {"bits": [10, 10], "name": "FWD_PROGRESS"},
14655    {"bits": [11, 11], "name": "WAVE64"}
14656   ]
14657  },
14658  "SQ_WAVE_LDS_ALLOC": {
14659   "fields": [
14660    {"bits": [0, 8], "name": "LDS_BASE"},
14661    {"bits": [12, 20], "name": "LDS_SIZE"},
14662    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14663   ]
14664  },
14665  "SQ_WAVE_MODE": {
14666   "fields": [
14667    {"bits": [0, 3], "name": "FP_ROUND"},
14668    {"bits": [4, 7], "name": "FP_DENORM"},
14669    {"bits": [8, 8], "name": "DX10_CLAMP"},
14670    {"bits": [9, 9], "name": "IEEE"},
14671    {"bits": [10, 10], "name": "LOD_CLAMPED"},
14672    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14673    {"bits": [23, 23], "name": "FP16_OVFL"},
14674    {"bits": [27, 27], "name": "DISABLE_PERF"}
14675   ]
14676  },
14677  "SQ_WAVE_PC_HI": {
14678   "fields": [
14679    {"bits": [0, 15], "name": "PC_HI"}
14680   ]
14681  },
14682  "SQ_WAVE_POPS_PACKER": {
14683   "fields": [
14684    {"bits": [0, 0], "name": "POPS_EN"},
14685    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14686   ]
14687  },
14688  "SQ_WAVE_SCHED_MODE": {
14689   "fields": [
14690    {"bits": [0, 1], "name": "DEP_MODE"}
14691   ]
14692  },
14693  "SQ_WAVE_SHADER_CYCLES": {
14694   "fields": [
14695    {"bits": [0, 19], "name": "CYCLES"}
14696   ]
14697  },
14698  "SQ_WAVE_STATUS": {
14699   "fields": [
14700    {"bits": [0, 0], "name": "SCC"},
14701    {"bits": [1, 2], "name": "SPI_PRIO"},
14702    {"bits": [3, 4], "name": "USER_PRIO"},
14703    {"bits": [5, 5], "name": "PRIV"},
14704    {"bits": [6, 6], "name": "TRAP_EN"},
14705    {"bits": [7, 7], "name": "TTRACE_EN"},
14706    {"bits": [8, 8], "name": "EXPORT_RDY"},
14707    {"bits": [9, 9], "name": "EXECZ"},
14708    {"bits": [10, 10], "name": "VCCZ"},
14709    {"bits": [11, 11], "name": "IN_TG"},
14710    {"bits": [12, 12], "name": "IN_BARRIER"},
14711    {"bits": [13, 13], "name": "HALT"},
14712    {"bits": [14, 14], "name": "TRAP"},
14713    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14714    {"bits": [16, 16], "name": "VALID"},
14715    {"bits": [17, 17], "name": "ECC_ERR"},
14716    {"bits": [18, 18], "name": "SKIP_EXPORT"},
14717    {"bits": [19, 19], "name": "PERF_EN"},
14718    {"bits": [23, 23], "name": "FATAL_HALT"},
14719    {"bits": [27, 27], "name": "MUST_EXPORT"}
14720   ]
14721  },
14722  "SQ_WAVE_TRAPSTS": {
14723   "fields": [
14724    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14725    {"bits": [10, 10], "name": "SAVECTX"},
14726    {"bits": [11, 11], "name": "ILLEGAL_INST"},
14727    {"bits": [12, 14], "name": "EXCP_HI"},
14728    {"bits": [15, 15], "name": "BUFFER_OOB"},
14729    {"bits": [16, 19], "name": "EXCP_CYCLE"},
14730    {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
14731    {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
14732    {"bits": [28, 28], "name": "UTC_ERROR"},
14733    {"bits": [29, 31], "name": "DP_RATE"}
14734   ]
14735  },
14736  "SQ_WAVE_VGPR_OFFSET": {
14737   "fields": [
14738    {"bits": [0, 5], "name": "SRC0"},
14739    {"bits": [6, 11], "name": "SRC1"},
14740    {"bits": [12, 17], "name": "SRC2"},
14741    {"bits": [18, 23], "name": "DST"}
14742   ]
14743  },
14744  "SX_BLEND_OPT_CONTROL": {
14745   "fields": [
14746    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14747    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14748    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14749    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14750    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14751    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14752    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14753    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14754    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14755    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14756    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14757    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14758    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14759    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14760    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14761    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14762    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14763   ]
14764  },
14765  "SX_BLEND_OPT_EPSILON": {
14766   "fields": [
14767    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14768    {"bits": [4, 7], "name": "MRT1_EPSILON"},
14769    {"bits": [8, 11], "name": "MRT2_EPSILON"},
14770    {"bits": [12, 15], "name": "MRT3_EPSILON"},
14771    {"bits": [16, 19], "name": "MRT4_EPSILON"},
14772    {"bits": [20, 23], "name": "MRT5_EPSILON"},
14773    {"bits": [24, 27], "name": "MRT6_EPSILON"},
14774    {"bits": [28, 31], "name": "MRT7_EPSILON"}
14775   ]
14776  },
14777  "SX_MRT0_BLEND_OPT": {
14778   "fields": [
14779    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14780    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14781    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14782    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14783    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14784    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14785   ]
14786  },
14787  "SX_PERFCOUNTER2_SELECT": {
14788   "fields": [
14789    {"bits": [0, 9], "name": "PERF_SEL"},
14790    {"bits": [20, 23], "name": "CNTR_MODE"},
14791    {"bits": [28, 31], "name": "PERF_MODE"}
14792   ]
14793  },
14794  "SX_PS_DOWNCONVERT": {
14795   "fields": [
14796    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14797    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14798    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14799    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14800    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14801    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14802    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14803    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14804   ]
14805  },
14806  "SX_PS_DOWNCONVERT_CONTROL": {
14807   "fields": [
14808    {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
14809    {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
14810    {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
14811    {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
14812    {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
14813    {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
14814    {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
14815    {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
14816   ]
14817  },
14818  "TA_BC_BASE_ADDR_HI": {
14819   "fields": [
14820    {"bits": [0, 7], "name": "ADDRESS"}
14821   ]
14822  },
14823  "UTCL1_PERFCOUNTER0_SELECT": {
14824   "fields": [
14825    {"bits": [0, 9], "name": "PERF_SEL"},
14826    {"bits": [28, 31], "name": "COUNTER_MODE"}
14827   ]
14828  },
14829  "VGT_DMA_BASE_HI": {
14830   "fields": [
14831    {"bits": [0, 15], "name": "BASE_ADDR"}
14832   ]
14833  },
14834  "VGT_DMA_INDEX_TYPE": {
14835   "fields": [
14836    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
14837    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
14838    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
14839    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
14840    {"bits": [8, 8], "name": "ATC"},
14841    {"bits": [9, 9], "name": "NOT_EOP"},
14842    {"bits": [10, 10], "name": "REQ_PATH"},
14843    {"bits": [11, 13], "name": "MTYPE"},
14844    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
14845   ]
14846  },
14847  "VGT_DRAW_INITIATOR": {
14848   "fields": [
14849    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
14850    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
14851    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
14852    {"bits": [5, 5], "name": "NOT_EOP"},
14853    {"bits": [6, 6], "name": "USE_OPAQUE"},
14854    {"bits": [29, 31], "name": "REG_RT_INDEX"}
14855   ]
14856  },
14857  "VGT_DRAW_PAYLOAD_CNTL": {
14858   "fields": [
14859    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
14860    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
14861    {"bits": [4, 4], "name": "EN_DRAW_VP"},
14862    {"bits": [6, 6], "name": "EN_VRS_RATE"}
14863   ]
14864  },
14865  "VGT_ESGS_RING_ITEMSIZE": {
14866   "fields": [
14867    {"bits": [0, 14], "name": "ITEMSIZE"}
14868   ]
14869  },
14870  "VGT_ES_PER_GS": {
14871   "fields": [
14872    {"bits": [0, 10], "name": "ES_PER_GS"}
14873   ]
14874  },
14875  "VGT_EVENT_ADDRESS_REG": {
14876   "fields": [
14877    {"bits": [0, 27], "name": "ADDRESS_LOW"}
14878   ]
14879  },
14880  "VGT_EVENT_INITIATOR": {
14881   "fields": [
14882    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
14883    {"bits": [10, 26], "name": "ADDRESS_HI"},
14884    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
14885   ]
14886  },
14887  "VGT_GROUP_DECR": {
14888   "fields": [
14889    {"bits": [0, 3], "name": "DECR"}
14890   ]
14891  },
14892  "VGT_GROUP_FIRST_DECR": {
14893   "fields": [
14894    {"bits": [0, 3], "name": "FIRST_DECR"}
14895   ]
14896  },
14897  "VGT_GROUP_PRIM_TYPE": {
14898   "fields": [
14899    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
14900    {"bits": [14, 14], "name": "RETAIN_ORDER"},
14901    {"bits": [15, 15], "name": "RETAIN_QUADS"},
14902    {"bits": [16, 18], "name": "PRIM_ORDER"}
14903   ]
14904  },
14905  "VGT_GROUP_VECT_0_CNTL": {
14906   "fields": [
14907    {"bits": [0, 0], "name": "COMP_X_EN"},
14908    {"bits": [1, 1], "name": "COMP_Y_EN"},
14909    {"bits": [2, 2], "name": "COMP_Z_EN"},
14910    {"bits": [3, 3], "name": "COMP_W_EN"},
14911    {"bits": [8, 15], "name": "STRIDE"},
14912    {"bits": [16, 23], "name": "SHIFT"}
14913   ]
14914  },
14915  "VGT_GROUP_VECT_0_FMT_CNTL": {
14916   "fields": [
14917    {"bits": [0, 3], "name": "X_CONV"},
14918    {"bits": [4, 7], "name": "X_OFFSET"},
14919    {"bits": [8, 11], "name": "Y_CONV"},
14920    {"bits": [12, 15], "name": "Y_OFFSET"},
14921    {"bits": [16, 19], "name": "Z_CONV"},
14922    {"bits": [20, 23], "name": "Z_OFFSET"},
14923    {"bits": [24, 27], "name": "W_CONV"},
14924    {"bits": [28, 31], "name": "W_OFFSET"}
14925   ]
14926  },
14927  "VGT_GSVS_RING_OFFSET_1": {
14928   "fields": [
14929    {"bits": [0, 14], "name": "OFFSET"}
14930   ]
14931  },
14932  "VGT_GS_INSTANCE_CNT": {
14933   "fields": [
14934    {"bits": [0, 0], "name": "ENABLE"},
14935    {"bits": [2, 8], "name": "CNT"},
14936    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
14937   ]
14938  },
14939  "VGT_GS_MAX_VERT_OUT": {
14940   "fields": [
14941    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
14942   ]
14943  },
14944  "VGT_GS_MODE": {
14945   "fields": [
14946    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
14947    {"bits": [3, 3], "name": "RESERVED_0"},
14948    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
14949    {"bits": [6, 10], "name": "RESERVED_1"},
14950    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
14951    {"bits": [12, 12], "name": "RESERVED_2"},
14952    {"bits": [13, 13], "name": "ES_PASSTHRU"},
14953    {"bits": [14, 14], "name": "COMPUTE_MODE"},
14954    {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
14955    {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
14956    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
14957    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
14958    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
14959    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
14960    {"bits": [21, 22], "name": "ONCHIP"}
14961   ]
14962  },
14963  "VGT_GS_ONCHIP_CNTL": {
14964   "fields": [
14965    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
14966    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
14967    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
14968   ]
14969  },
14970  "VGT_GS_OUT_PRIM_TYPE": {
14971   "fields": [
14972    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
14973    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
14974    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
14975    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
14976    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
14977   ]
14978  },
14979  "VGT_GS_PER_ES": {
14980   "fields": [
14981    {"bits": [0, 10], "name": "GS_PER_ES"}
14982   ]
14983  },
14984  "VGT_GS_PER_VS": {
14985   "fields": [
14986    {"bits": [0, 3], "name": "GS_PER_VS"}
14987   ]
14988  },
14989  "VGT_HOS_CNTL": {
14990   "fields": [
14991    {"bits": [0, 1], "name": "TESS_MODE"}
14992   ]
14993  },
14994  "VGT_HOS_REUSE_DEPTH": {
14995   "fields": [
14996    {"bits": [0, 7], "name": "REUSE_DEPTH"}
14997   ]
14998  },
14999  "VGT_HS_OFFCHIP_PARAM_UMD": {
15000   "fields": [
15001    {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
15002    {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15003   ]
15004  },
15005  "VGT_INDEX_TYPE": {
15006   "fields": [
15007    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15008    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
15009   ]
15010  },
15011  "VGT_LS_HS_CONFIG": {
15012   "fields": [
15013    {"bits": [0, 7], "name": "NUM_PATCHES"},
15014    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
15015    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
15016   ]
15017  },
15018  "VGT_MULTI_PRIM_IB_RESET_EN": {
15019   "fields": [
15020    {"bits": [0, 0], "name": "RESET_EN"},
15021    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
15022   ]
15023  },
15024  "VGT_OUTPUT_PATH_CNTL": {
15025   "fields": [
15026    {"bits": [0, 2], "name": "PATH_SELECT"}
15027   ]
15028  },
15029  "VGT_OUT_DEALLOC_CNTL": {
15030   "fields": [
15031    {"bits": [0, 6], "name": "DEALLOC_DIST"}
15032   ]
15033  },
15034  "VGT_PRIMITIVEID_EN": {
15035   "fields": [
15036    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
15037    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
15038    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
15039   ]
15040  },
15041  "VGT_PRIMITIVE_TYPE": {
15042   "fields": [
15043    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15044   ]
15045  },
15046  "VGT_REUSE_OFF": {
15047   "fields": [
15048    {"bits": [0, 0], "name": "REUSE_OFF"}
15049   ]
15050  },
15051  "VGT_SHADER_STAGES_EN": {
15052   "fields": [
15053    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15054    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15055    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15056    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15057    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15058    {"bits": [8, 8], "name": "DYNAMIC_HS"},
15059    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
15060    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
15061    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
15062    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
15063    {"bits": [13, 13], "name": "PRIMGEN_EN"},
15064    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
15065    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
15066    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
15067    {"bits": [21, 21], "name": "HS_W32_EN"},
15068    {"bits": [22, 22], "name": "GS_W32_EN"},
15069    {"bits": [23, 23], "name": "VS_W32_EN"},
15070    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
15071    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"},
15072    {"bits": [26, 26], "name": "PRIMGEN_PASSTHRU_NO_MSG"}
15073   ]
15074  },
15075  "VGT_STRMOUT_BUFFER_CONFIG": {
15076   "fields": [
15077    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
15078    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
15079    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
15080    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
15081   ]
15082  },
15083  "VGT_STRMOUT_CONFIG": {
15084   "fields": [
15085    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
15086    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
15087    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
15088    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
15089    {"bits": [4, 6], "name": "RAST_STREAM"},
15090    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
15091    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
15092    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
15093   ]
15094  },
15095  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
15096   "fields": [
15097    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
15098   ]
15099  },
15100  "VGT_STRMOUT_VTX_STRIDE_0": {
15101   "fields": [
15102    {"bits": [0, 9], "name": "STRIDE"}
15103   ]
15104  },
15105  "VGT_TESS_DISTRIBUTION": {
15106   "fields": [
15107    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
15108    {"bits": [8, 15], "name": "ACCUM_TRI"},
15109    {"bits": [16, 23], "name": "ACCUM_QUAD"},
15110    {"bits": [24, 28], "name": "DONUT_SPLIT"},
15111    {"bits": [29, 31], "name": "TRAP_SPLIT"}
15112   ]
15113  },
15114  "VGT_TF_PARAM": {
15115   "fields": [
15116    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15117    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15118    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15119    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
15120    {"bits": [9, 9], "name": "DEPRECATED"},
15121    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
15122    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
15123    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15124    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15125    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15126    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
15127    {"bits": [23, 25], "name": "MTYPE"}
15128   ]
15129  },
15130  "VGT_TF_RING_SIZE_UMD": {
15131   "fields": [
15132    {"bits": [0, 15], "name": "SIZE"}
15133   ]
15134  },
15135  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
15136   "fields": [
15137    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
15138   ]
15139  },
15140  "VGT_VTX_CNT_EN": {
15141   "fields": [
15142    {"bits": [0, 0], "name": "VTX_CNT_EN"}
15143   ]
15144  }
15145 }
15146}
15147