radv_debug.c revision 01e04c3f
1/* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 25 * IN THE SOFTWARE. 26 */ 27 28#include <stdlib.h> 29#include <stdio.h> 30#include <sys/utsname.h> 31 32#include "util/mesa-sha1.h" 33#include "sid.h" 34#include "gfx9d.h" 35#include "ac_debug.h" 36#include "radv_debug.h" 37#include "radv_shader.h" 38 39#define TRACE_BO_SIZE 4096 40 41#define COLOR_RESET "\033[0m" 42#define COLOR_RED "\033[31m" 43#define COLOR_GREEN "\033[1;32m" 44#define COLOR_YELLOW "\033[1;33m" 45#define COLOR_CYAN "\033[1;36m" 46 47/* Trace BO layout (offsets are 4 bytes): 48 * 49 * [0]: primary trace ID 50 * [1]: secondary trace ID 51 * [2-3]: 64-bit GFX pipeline pointer 52 * [4-5]: 64-bit COMPUTE pipeline pointer 53 * [6-7]: 64-bit descriptor set #0 pointer 54 * ... 55 * [68-69]: 64-bit descriptor set #31 pointer 56 */ 57 58bool 59radv_init_trace(struct radv_device *device) 60{ 61 struct radeon_winsys *ws = device->ws; 62 63 device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8, 64 RADEON_DOMAIN_VRAM, 65 RADEON_FLAG_CPU_ACCESS| 66 RADEON_FLAG_NO_INTERPROCESS_SHARING); 67 if (!device->trace_bo) 68 return false; 69 70 device->trace_id_ptr = ws->buffer_map(device->trace_bo); 71 if (!device->trace_id_ptr) 72 return false; 73 74 memset(device->trace_id_ptr, 0, TRACE_BO_SIZE); 75 76 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, 77 &device->dmesg_timestamp, NULL); 78 79 return true; 80} 81 82static void 83radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs) 84{ 85 const char *filename = getenv("RADV_TRACE_FILE"); 86 FILE *f = fopen(filename, "w"); 87 88 if (!f) { 89 fprintf(stderr, "Failed to write trace dump to %s\n", filename); 90 return; 91 } 92 93 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr); 94 device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2); 95 fclose(f); 96} 97 98static void 99radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset) 100{ 101 struct radeon_winsys *ws = device->ws; 102 uint32_t value; 103 104 if (ws->read_registers(ws, offset, 1, &value)) 105 ac_dump_reg(f, device->physical_device->rad_info.chip_class, 106 offset, value, ~0); 107} 108 109static void 110radv_dump_debug_registers(struct radv_device *device, FILE *f) 111{ 112 struct radeon_info *info = &device->physical_device->rad_info; 113 114 if (info->drm_major == 2 && info->drm_minor < 42) 115 return; /* no radeon support */ 116 117 fprintf(f, "Memory-mapped registers:\n"); 118 radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS); 119 120 /* No other registers can be read on DRM < 3.1.0. */ 121 if (info->drm_major < 3 || info->drm_minor < 1) { 122 fprintf(f, "\n"); 123 return; 124 } 125 126 radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2); 127 radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0); 128 radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1); 129 radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2); 130 radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3); 131 radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG); 132 radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG); 133 if (info->chip_class <= VI) { 134 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS); 135 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2); 136 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3); 137 } 138 radv_dump_mmapped_reg(device, f, R_008680_CP_STAT); 139 radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1); 140 radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2); 141 radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3); 142 radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS); 143 radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT); 144 radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1); 145 radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS); 146 radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT); 147 radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1); 148 fprintf(f, "\n"); 149} 150 151static const char * 152radv_get_descriptor_name(enum VkDescriptorType type) 153{ 154 switch (type) { 155 case VK_DESCRIPTOR_TYPE_SAMPLER: 156 return "SAMPLER"; 157 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: 158 return "COMBINED_IMAGE_SAMPLER"; 159 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: 160 return "SAMPLED_IMAGE"; 161 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: 162 return "STORAGE_IMAGE"; 163 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: 164 return "UNIFORM_TEXEL_BUFFER"; 165 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: 166 return "STORAGE_TEXEL_BUFFER"; 167 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: 168 return "UNIFORM_BUFFER"; 169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: 170 return "STORAGE_BUFFER"; 171 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: 172 return "UNIFORM_BUFFER_DYNAMIC"; 173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: 174 return "STORAGE_BUFFER_DYNAMIC"; 175 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: 176 return "INPUT_ATTACHMENT"; 177 default: 178 return "UNKNOWN"; 179 } 180} 181 182static void 183radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, 184 FILE *f) 185{ 186 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); 187 for (unsigned j = 0; j < 4; j++) 188 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, 189 desc[j], 0xffffffff); 190} 191 192static void 193radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, 194 FILE *f) 195{ 196 fprintf(f, COLOR_CYAN " Image:" COLOR_RESET "\n"); 197 for (unsigned j = 0; j < 8; j++) 198 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, 199 desc[j], 0xffffffff); 200 201 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n"); 202 for (unsigned j = 0; j < 8; j++) 203 ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4, 204 desc[8 + j], 0xffffffff); 205} 206 207static void 208radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, 209 FILE *f) 210{ 211 fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n"); 212 for (unsigned j = 0; j < 4; j++) { 213 ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, 214 desc[j], 0xffffffff); 215 } 216} 217 218static void 219radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class, 220 const uint32_t *desc, FILE *f) 221{ 222 radv_dump_image_descriptor(chip_class, desc, f); 223 radv_dump_sampler_descriptor(chip_class, desc + 16, f); 224} 225 226static void 227radv_dump_descriptor_set(enum chip_class chip_class, 228 struct radv_descriptor_set *set, unsigned id, FILE *f) 229{ 230 const struct radv_descriptor_set_layout *layout; 231 int i; 232 233 if (!set) 234 return; 235 layout = set->layout; 236 237 fprintf(f, "** descriptor set (%d) **\n", id); 238 fprintf(f, "va: 0x%"PRIx64"\n", set->va); 239 fprintf(f, "size: %d\n", set->size); 240 fprintf(f, "mapped_ptr:\n"); 241 242 for (i = 0; i < set->size / 4; i++) { 243 fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]); 244 } 245 fprintf(f, "\n"); 246 247 fprintf(f, "\t*** layout ***\n"); 248 fprintf(f, "\tbinding_count: %d\n", layout->binding_count); 249 fprintf(f, "\tsize: %d\n", layout->size); 250 fprintf(f, "\tshader_stages: %x\n", layout->shader_stages); 251 fprintf(f, "\tdynamic_shader_stages: %x\n", 252 layout->dynamic_shader_stages); 253 fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count); 254 fprintf(f, "\tdynamic_offset_count: %d\n", 255 layout->dynamic_offset_count); 256 fprintf(f, "\n"); 257 258 for (i = 0; i < set->layout->binding_count; i++) { 259 uint32_t *desc = 260 set->mapped_ptr + layout->binding[i].offset / 4; 261 262 fprintf(f, "\t\t**** binding layout (%d) ****\n", i); 263 fprintf(f, "\t\ttype: %s\n", 264 radv_get_descriptor_name(layout->binding[i].type)); 265 fprintf(f, "\t\tarray_size: %d\n", 266 layout->binding[i].array_size); 267 fprintf(f, "\t\toffset: %d\n", 268 layout->binding[i].offset); 269 fprintf(f, "\t\tbuffer_offset: %d\n", 270 layout->binding[i].buffer_offset); 271 fprintf(f, "\t\tdynamic_offset_offset: %d\n", 272 layout->binding[i].dynamic_offset_offset); 273 fprintf(f, "\t\tdynamic_offset_count: %d\n", 274 layout->binding[i].dynamic_offset_count); 275 fprintf(f, "\t\tsize: %d\n", 276 layout->binding[i].size); 277 fprintf(f, "\t\timmutable_samplers_offset: %d\n", 278 layout->binding[i].immutable_samplers_offset); 279 fprintf(f, "\t\timmutable_samplers_equal: %d\n", 280 layout->binding[i].immutable_samplers_equal); 281 fprintf(f, "\n"); 282 283 switch (layout->binding[i].type) { 284 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: 285 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER: 286 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: 287 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER: 288 radv_dump_buffer_descriptor(chip_class, desc, f); 289 break; 290 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: 291 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: 292 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT: 293 radv_dump_image_descriptor(chip_class, desc, f); 294 break; 295 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: 296 radv_dump_combined_image_sampler_descriptor(chip_class, desc, f); 297 break; 298 case VK_DESCRIPTOR_TYPE_SAMPLER: 299 radv_dump_sampler_descriptor(chip_class, desc, f); 300 break; 301 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: 302 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: 303 /* todo */ 304 break; 305 default: 306 assert(!"unknown descriptor type"); 307 break; 308 } 309 fprintf(f, "\n"); 310 } 311 fprintf(f, "\n\n"); 312} 313 314static void 315radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f) 316{ 317 struct radv_device *device = pipeline->device; 318 enum chip_class chip_class = device->physical_device->rad_info.chip_class; 319 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 320 int i; 321 322 fprintf(f, "List of descriptors:\n"); 323 for (i = 0; i < MAX_SETS; i++) { 324 struct radv_descriptor_set *set = 325 (struct radv_descriptor_set *)ptr[i + 3]; 326 327 radv_dump_descriptor_set(chip_class, set, i, f); 328 } 329} 330 331struct radv_shader_inst { 332 char text[160]; /* one disasm line */ 333 unsigned offset; /* instruction offset */ 334 unsigned size; /* instruction size = 4 or 8 */ 335}; 336 337/* Split a disassembly string into lines and add them to the array pointed 338 * to by "instructions". */ 339static void si_add_split_disasm(const char *disasm, 340 uint64_t start_addr, 341 unsigned *num, 342 struct radv_shader_inst *instructions) 343{ 344 struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL; 345 char *next; 346 347 while ((next = strchr(disasm, '\n'))) { 348 struct radv_shader_inst *inst = &instructions[*num]; 349 unsigned len = next - disasm; 350 351 assert(len < ARRAY_SIZE(inst->text)); 352 memcpy(inst->text, disasm, len); 353 inst->text[len] = 0; 354 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0; 355 356 const char *semicolon = strchr(disasm, ';'); 357 assert(semicolon); 358 /* More than 16 chars after ";" means the instruction is 8 bytes long. */ 359 inst->size = next - semicolon > 16 ? 8 : 4; 360 361 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len, 362 " [PC=0x%"PRIx64", off=%u, size=%u]", 363 start_addr + inst->offset, inst->offset, inst->size); 364 365 last_inst = inst; 366 (*num)++; 367 disasm = next + 1; 368 } 369} 370 371static void 372radv_dump_annotated_shader(struct radv_shader_variant *shader, 373 gl_shader_stage stage, struct ac_wave_info *waves, 374 unsigned num_waves, FILE *f) 375{ 376 uint64_t start_addr, end_addr; 377 unsigned i; 378 379 if (!shader) 380 return; 381 382 start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset; 383 end_addr = start_addr + shader->code_size; 384 385 /* See if any wave executes the shader. */ 386 for (i = 0; i < num_waves; i++) { 387 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr) 388 break; 389 } 390 391 if (i == num_waves) 392 return; /* the shader is not being executed */ 393 394 /* Remember the first found wave. The waves are sorted according to PC. */ 395 waves = &waves[i]; 396 num_waves -= i; 397 398 /* Get the list of instructions. 399 * Buffer size / 4 is the upper bound of the instruction count. 400 */ 401 unsigned num_inst = 0; 402 struct radv_shader_inst *instructions = 403 calloc(shader->code_size / 4, sizeof(struct radv_shader_inst)); 404 405 si_add_split_disasm(shader->disasm_string, 406 start_addr, &num_inst, instructions); 407 408 fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n", 409 radv_get_shader_name(shader, stage)); 410 411 /* Print instructions with annotations. */ 412 for (i = 0; i < num_inst; i++) { 413 struct radv_shader_inst *inst = &instructions[i]; 414 415 fprintf(f, "%s\n", inst->text); 416 417 /* Print which waves execute the instruction right now. */ 418 while (num_waves && start_addr + inst->offset == waves->pc) { 419 fprintf(f, 420 " " COLOR_GREEN "^ SE%u SH%u CU%u " 421 "SIMD%u WAVE%u EXEC=%016"PRIx64 " ", 422 waves->se, waves->sh, waves->cu, waves->simd, 423 waves->wave, waves->exec); 424 425 if (inst->size == 4) { 426 fprintf(f, "INST32=%08X" COLOR_RESET "\n", 427 waves->inst_dw0); 428 } else { 429 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n", 430 waves->inst_dw0, waves->inst_dw1); 431 } 432 433 waves->matched = true; 434 waves = &waves[1]; 435 num_waves--; 436 } 437 } 438 439 fprintf(f, "\n\n"); 440 free(instructions); 441} 442 443static void 444radv_dump_annotated_shaders(struct radv_pipeline *pipeline, 445 VkShaderStageFlagBits active_stages, FILE *f) 446{ 447 struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]; 448 unsigned num_waves = ac_get_wave_info(waves); 449 450 fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET 451 "\n\n", num_waves); 452 453 /* Dump annotated active graphics shaders. */ 454 while (active_stages) { 455 int stage = u_bit_scan(&active_stages); 456 457 radv_dump_annotated_shader(pipeline->shaders[stage], 458 stage, waves, num_waves, f); 459 } 460 461 /* Print waves executing shaders that are not currently bound. */ 462 unsigned i; 463 bool found = false; 464 for (i = 0; i < num_waves; i++) { 465 if (waves[i].matched) 466 continue; 467 468 if (!found) { 469 fprintf(f, COLOR_CYAN 470 "Waves not executing currently-bound shaders:" 471 COLOR_RESET "\n"); 472 found = true; 473 } 474 fprintf(f, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64 475 " INST=%08X %08X PC=%"PRIx64"\n", 476 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, 477 waves[i].wave, waves[i].exec, waves[i].inst_dw0, 478 waves[i].inst_dw1, waves[i].pc); 479 } 480 if (found) 481 fprintf(f, "\n\n"); 482} 483 484static void 485radv_dump_shader(struct radv_pipeline *pipeline, 486 struct radv_shader_variant *shader, gl_shader_stage stage, 487 FILE *f) 488{ 489 if (!shader) 490 return; 491 492 fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage)); 493 494 if (shader->spirv) { 495 unsigned char sha1[21]; 496 char sha1buf[41]; 497 498 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1); 499 _mesa_sha1_format(sha1buf, sha1); 500 501 fprintf(f, "SPIRV (sha1: %s):\n", sha1buf); 502 radv_print_spirv(shader->spirv, shader->spirv_size, f); 503 } 504 505 if (shader->nir) { 506 fprintf(f, "NIR:\n"); 507 nir_print_shader(shader->nir, f); 508 } 509 510 fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string); 511 fprintf(f, "DISASM:\n%s\n", shader->disasm_string); 512 513 radv_shader_dump_stats(pipeline->device, shader, stage, f); 514} 515 516static void 517radv_dump_shaders(struct radv_pipeline *pipeline, 518 VkShaderStageFlagBits active_stages, FILE *f) 519{ 520 /* Dump active graphics shaders. */ 521 while (active_stages) { 522 int stage = u_bit_scan(&active_stages); 523 524 radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f); 525 } 526} 527 528static void 529radv_dump_pipeline_state(struct radv_pipeline *pipeline, 530 VkShaderStageFlagBits active_stages, FILE *f) 531{ 532 radv_dump_shaders(pipeline, active_stages, f); 533 radv_dump_annotated_shaders(pipeline, active_stages, f); 534 radv_dump_descriptors(pipeline, f); 535} 536 537static void 538radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline, 539 struct radv_pipeline *compute_pipeline, FILE *f) 540{ 541 VkShaderStageFlagBits active_stages; 542 543 if (graphics_pipeline) { 544 active_stages = graphics_pipeline->active_stages; 545 radv_dump_pipeline_state(graphics_pipeline, active_stages, f); 546 } 547 548 if (compute_pipeline) { 549 active_stages = VK_SHADER_STAGE_COMPUTE_BIT; 550 radv_dump_pipeline_state(compute_pipeline, active_stages, f); 551 } 552} 553 554static void 555radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f) 556{ 557 VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT; 558 559 if (!compute_pipeline) 560 return; 561 562 radv_dump_pipeline_state(compute_pipeline, active_stages, f); 563} 564 565static struct radv_pipeline * 566radv_get_saved_graphics_pipeline(struct radv_device *device) 567{ 568 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 569 570 return (struct radv_pipeline *)ptr[1]; 571} 572 573static struct radv_pipeline * 574radv_get_saved_compute_pipeline(struct radv_device *device) 575{ 576 uint64_t *ptr = (uint64_t *)device->trace_id_ptr; 577 578 return (struct radv_pipeline *)ptr[2]; 579} 580 581static void 582radv_dump_dmesg(FILE *f) 583{ 584 char line[2000]; 585 FILE *p; 586 587 p = popen("dmesg | tail -n60", "r"); 588 if (!p) 589 return; 590 591 fprintf(f, "\nLast 60 lines of dmesg:\n\n"); 592 while (fgets(line, sizeof(line), p)) 593 fputs(line, f); 594 fprintf(f, "\n"); 595 596 pclose(p); 597} 598 599void 600radv_dump_enabled_options(struct radv_device *device, FILE *f) 601{ 602 uint64_t mask; 603 604 if (device->instance->debug_flags) { 605 fprintf(f, "Enabled debug options: "); 606 607 mask = device->instance->debug_flags; 608 while (mask) { 609 int i = u_bit_scan64(&mask); 610 fprintf(f, "%s, ", radv_get_debug_option_name(i)); 611 } 612 fprintf(f, "\n"); 613 } 614 615 if (device->instance->perftest_flags) { 616 fprintf(f, "Enabled perftest options: "); 617 618 mask = device->instance->perftest_flags; 619 while (mask) { 620 int i = u_bit_scan64(&mask); 621 fprintf(f, "%s, ", radv_get_perftest_option_name(i)); 622 } 623 fprintf(f, "\n"); 624 } 625} 626 627static void 628radv_dump_device_name(struct radv_device *device, FILE *f) 629{ 630 struct radeon_info *info = &device->physical_device->rad_info; 631 char llvm_string[32] = {}, kernel_version[128] = {}; 632 struct utsname uname_data; 633 const char *chip_name; 634 635 chip_name = device->ws->get_chip_name(device->ws); 636 637 if (uname(&uname_data) == 0) 638 snprintf(kernel_version, sizeof(kernel_version), 639 " / %s", uname_data.release); 640 641 snprintf(llvm_string, sizeof(llvm_string), 642 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff, 643 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH); 644 645 fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n", 646 chip_name, device->physical_device->name, 647 info->drm_major, info->drm_minor, info->drm_patchlevel, 648 kernel_version, llvm_string); 649} 650 651static bool 652radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring) 653{ 654 struct radeon_winsys *ws = queue->device->ws; 655 656 if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx)) 657 return true; 658 659 return false; 660} 661 662void 663radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs) 664{ 665 struct radv_pipeline *graphics_pipeline, *compute_pipeline; 666 struct radv_device *device = queue->device; 667 enum ring_type ring; 668 uint64_t addr; 669 670 ring = radv_queue_family_to_ring(queue->queue_family_index); 671 672 bool hang_occurred = radv_gpu_hang_occured(queue, ring); 673 bool vm_fault_occurred = false; 674 if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS) 675 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class, 676 &device->dmesg_timestamp, &addr); 677 if (!hang_occurred && !vm_fault_occurred) 678 return; 679 680 graphics_pipeline = radv_get_saved_graphics_pipeline(device); 681 compute_pipeline = radv_get_saved_compute_pipeline(device); 682 683 fprintf(stderr, "GPU hang report:\n\n"); 684 radv_dump_device_name(device, stderr); 685 686 radv_dump_enabled_options(device, stderr); 687 radv_dump_dmesg(stderr); 688 689 if (vm_fault_occurred) { 690 fprintf(stderr, "VM fault report.\n\n"); 691 fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr); 692 } 693 694 radv_dump_debug_registers(device, stderr); 695 696 switch (ring) { 697 case RING_GFX: 698 radv_dump_graphics_state(graphics_pipeline, compute_pipeline, 699 stderr); 700 break; 701 case RING_COMPUTE: 702 radv_dump_compute_state(compute_pipeline, stderr); 703 break; 704 default: 705 assert(0); 706 break; 707 } 708 709 radv_dump_trace(queue->device, cs); 710 abort(); 711} 712 713void 714radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp) 715{ 716 char path[] = "/tmp/fileXXXXXX"; 717 char line[2048], command[128]; 718 FILE *p; 719 int fd; 720 721 /* Dump the binary into a temporary file. */ 722 fd = mkstemp(path); 723 if (fd < 0) 724 return; 725 726 if (write(fd, data, size) == -1) 727 goto fail; 728 729 sprintf(command, "spirv-dis %s", path); 730 731 /* Disassemble using spirv-dis if installed. */ 732 p = popen(command, "r"); 733 if (p) { 734 while (fgets(line, sizeof(line), p)) 735 fprintf(fp, "%s", line); 736 pclose(p); 737 } 738 739fail: 740 close(fd); 741 unlink(path); 742} 743