radv_pipeline.c revision 01e04c3f
1/* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 25 * IN THE SOFTWARE. 26 */ 27 28#include "util/mesa-sha1.h" 29#include "util/u_atomic.h" 30#include "radv_debug.h" 31#include "radv_private.h" 32#include "radv_cs.h" 33#include "radv_shader.h" 34#include "nir/nir.h" 35#include "nir/nir_builder.h" 36#include "spirv/nir_spirv.h" 37#include "vk_util.h" 38 39#include <llvm-c/Core.h> 40#include <llvm-c/TargetMachine.h> 41 42#include "sid.h" 43#include "gfx9d.h" 44#include "ac_binary.h" 45#include "ac_llvm_util.h" 46#include "ac_nir_to_llvm.h" 47#include "vk_format.h" 48#include "util/debug.h" 49#include "ac_exp_param.h" 50#include "ac_shader_util.h" 51#include "main/menums.h" 52 53struct radv_blend_state { 54 uint32_t blend_enable_4bit; 55 uint32_t need_src_alpha; 56 57 uint32_t cb_color_control; 58 uint32_t cb_target_mask; 59 uint32_t cb_target_enabled_4bit; 60 uint32_t sx_mrt_blend_opt[8]; 61 uint32_t cb_blend_control[8]; 62 63 uint32_t spi_shader_col_format; 64 uint32_t cb_shader_mask; 65 uint32_t db_alpha_to_mask; 66 67 uint32_t commutative_4bit; 68 69 bool single_cb_enable; 70 bool mrt0_is_dual_src; 71}; 72 73struct radv_dsa_order_invariance { 74 /* Whether the final result in Z/S buffers is guaranteed to be 75 * invariant under changes to the order in which fragments arrive. 76 */ 77 bool zs; 78 79 /* Whether the set of fragments that pass the combined Z/S test is 80 * guaranteed to be invariant under changes to the order in which 81 * fragments arrive. 82 */ 83 bool pass_set; 84}; 85 86struct radv_tessellation_state { 87 uint32_t ls_hs_config; 88 unsigned num_patches; 89 unsigned lds_size; 90 uint32_t tf_param; 91}; 92 93struct radv_gs_state { 94 uint32_t vgt_gs_onchip_cntl; 95 uint32_t vgt_gs_max_prims_per_subgroup; 96 uint32_t vgt_esgs_ring_itemsize; 97 uint32_t lds_size; 98}; 99 100static void 101radv_pipeline_destroy(struct radv_device *device, 102 struct radv_pipeline *pipeline, 103 const VkAllocationCallbacks* allocator) 104{ 105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) 106 if (pipeline->shaders[i]) 107 radv_shader_variant_destroy(device, pipeline->shaders[i]); 108 109 if (pipeline->gs_copy_shader) 110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader); 111 112 if(pipeline->cs.buf) 113 free(pipeline->cs.buf); 114 vk_free2(&device->alloc, allocator, pipeline); 115} 116 117void radv_DestroyPipeline( 118 VkDevice _device, 119 VkPipeline _pipeline, 120 const VkAllocationCallbacks* pAllocator) 121{ 122 RADV_FROM_HANDLE(radv_device, device, _device); 123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); 124 125 if (!_pipeline) 126 return; 127 128 radv_pipeline_destroy(device, pipeline, pAllocator); 129} 130 131static uint32_t get_hash_flags(struct radv_device *device) 132{ 133 uint32_t hash_flags = 0; 134 135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH) 136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH; 137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) 138 hash_flags |= RADV_HASH_SHADER_SISCHED; 139 return hash_flags; 140} 141 142static VkResult 143radv_pipeline_scratch_init(struct radv_device *device, 144 struct radv_pipeline *pipeline) 145{ 146 unsigned scratch_bytes_per_wave = 0; 147 unsigned max_waves = 0; 148 unsigned min_waves = 1; 149 150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) { 151 if (pipeline->shaders[i]) { 152 unsigned max_stage_waves = device->scratch_waves; 153 154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave, 155 pipeline->shaders[i]->config.scratch_bytes_per_wave); 156 157 max_stage_waves = MIN2(max_stage_waves, 158 4 * device->physical_device->rad_info.num_good_compute_units * 159 (256 / pipeline->shaders[i]->config.num_vgprs)); 160 max_waves = MAX2(max_waves, max_stage_waves); 161 } 162 } 163 164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) { 165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] * 166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] * 167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2]; 168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64)); 169 } 170 171 if (scratch_bytes_per_wave) 172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave); 173 174 if (scratch_bytes_per_wave && max_waves < min_waves) { 175 /* Not really true at this moment, but will be true on first 176 * execution. Avoid having hanging shaders. */ 177 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY); 178 } 179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave; 180 pipeline->max_waves = max_waves; 181 return VK_SUCCESS; 182} 183 184static uint32_t si_translate_blend_logic_op(VkLogicOp op) 185{ 186 switch (op) { 187 case VK_LOGIC_OP_CLEAR: 188 return V_028808_ROP3_CLEAR; 189 case VK_LOGIC_OP_AND: 190 return V_028808_ROP3_AND; 191 case VK_LOGIC_OP_AND_REVERSE: 192 return V_028808_ROP3_AND_REVERSE; 193 case VK_LOGIC_OP_COPY: 194 return V_028808_ROP3_COPY; 195 case VK_LOGIC_OP_AND_INVERTED: 196 return V_028808_ROP3_AND_INVERTED; 197 case VK_LOGIC_OP_NO_OP: 198 return V_028808_ROP3_NO_OP; 199 case VK_LOGIC_OP_XOR: 200 return V_028808_ROP3_XOR; 201 case VK_LOGIC_OP_OR: 202 return V_028808_ROP3_OR; 203 case VK_LOGIC_OP_NOR: 204 return V_028808_ROP3_NOR; 205 case VK_LOGIC_OP_EQUIVALENT: 206 return V_028808_ROP3_EQUIVALENT; 207 case VK_LOGIC_OP_INVERT: 208 return V_028808_ROP3_INVERT; 209 case VK_LOGIC_OP_OR_REVERSE: 210 return V_028808_ROP3_OR_REVERSE; 211 case VK_LOGIC_OP_COPY_INVERTED: 212 return V_028808_ROP3_COPY_INVERTED; 213 case VK_LOGIC_OP_OR_INVERTED: 214 return V_028808_ROP3_OR_INVERTED; 215 case VK_LOGIC_OP_NAND: 216 return V_028808_ROP3_NAND; 217 case VK_LOGIC_OP_SET: 218 return V_028808_ROP3_SET; 219 default: 220 unreachable("Unhandled logic op"); 221 } 222} 223 224 225static uint32_t si_translate_blend_function(VkBlendOp op) 226{ 227 switch (op) { 228 case VK_BLEND_OP_ADD: 229 return V_028780_COMB_DST_PLUS_SRC; 230 case VK_BLEND_OP_SUBTRACT: 231 return V_028780_COMB_SRC_MINUS_DST; 232 case VK_BLEND_OP_REVERSE_SUBTRACT: 233 return V_028780_COMB_DST_MINUS_SRC; 234 case VK_BLEND_OP_MIN: 235 return V_028780_COMB_MIN_DST_SRC; 236 case VK_BLEND_OP_MAX: 237 return V_028780_COMB_MAX_DST_SRC; 238 default: 239 return 0; 240 } 241} 242 243static uint32_t si_translate_blend_factor(VkBlendFactor factor) 244{ 245 switch (factor) { 246 case VK_BLEND_FACTOR_ZERO: 247 return V_028780_BLEND_ZERO; 248 case VK_BLEND_FACTOR_ONE: 249 return V_028780_BLEND_ONE; 250 case VK_BLEND_FACTOR_SRC_COLOR: 251 return V_028780_BLEND_SRC_COLOR; 252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR: 253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 254 case VK_BLEND_FACTOR_DST_COLOR: 255 return V_028780_BLEND_DST_COLOR; 256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR: 257 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 258 case VK_BLEND_FACTOR_SRC_ALPHA: 259 return V_028780_BLEND_SRC_ALPHA; 260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA: 261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 262 case VK_BLEND_FACTOR_DST_ALPHA: 263 return V_028780_BLEND_DST_ALPHA; 264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA: 265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 266 case VK_BLEND_FACTOR_CONSTANT_COLOR: 267 return V_028780_BLEND_CONSTANT_COLOR; 268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR: 269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 270 case VK_BLEND_FACTOR_CONSTANT_ALPHA: 271 return V_028780_BLEND_CONSTANT_ALPHA; 272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA: 273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE: 275 return V_028780_BLEND_SRC_ALPHA_SATURATE; 276 case VK_BLEND_FACTOR_SRC1_COLOR: 277 return V_028780_BLEND_SRC1_COLOR; 278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: 279 return V_028780_BLEND_INV_SRC1_COLOR; 280 case VK_BLEND_FACTOR_SRC1_ALPHA: 281 return V_028780_BLEND_SRC1_ALPHA; 282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: 283 return V_028780_BLEND_INV_SRC1_ALPHA; 284 default: 285 return 0; 286 } 287} 288 289static uint32_t si_translate_blend_opt_function(VkBlendOp op) 290{ 291 switch (op) { 292 case VK_BLEND_OP_ADD: 293 return V_028760_OPT_COMB_ADD; 294 case VK_BLEND_OP_SUBTRACT: 295 return V_028760_OPT_COMB_SUBTRACT; 296 case VK_BLEND_OP_REVERSE_SUBTRACT: 297 return V_028760_OPT_COMB_REVSUBTRACT; 298 case VK_BLEND_OP_MIN: 299 return V_028760_OPT_COMB_MIN; 300 case VK_BLEND_OP_MAX: 301 return V_028760_OPT_COMB_MAX; 302 default: 303 return V_028760_OPT_COMB_BLEND_DISABLED; 304 } 305} 306 307static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha) 308{ 309 switch (factor) { 310 case VK_BLEND_FACTOR_ZERO: 311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL; 312 case VK_BLEND_FACTOR_ONE: 313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE; 314 case VK_BLEND_FACTOR_SRC_COLOR: 315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0; 317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR: 318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1; 320 case VK_BLEND_FACTOR_SRC_ALPHA: 321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0; 322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA: 323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1; 324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE: 325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE 326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; 327 default: 328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 329 } 330} 331 332/** 333 * Get rid of DST in the blend factors by commuting the operands: 334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) 335 */ 336static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, 337 unsigned *dst_factor, unsigned expected_dst, 338 unsigned replacement_src) 339{ 340 if (*src_factor == expected_dst && 341 *dst_factor == VK_BLEND_FACTOR_ZERO) { 342 *src_factor = VK_BLEND_FACTOR_ZERO; 343 *dst_factor = replacement_src; 344 345 /* Commuting the operands requires reversing subtractions. */ 346 if (*func == VK_BLEND_OP_SUBTRACT) 347 *func = VK_BLEND_OP_REVERSE_SUBTRACT; 348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT) 349 *func = VK_BLEND_OP_SUBTRACT; 350 } 351} 352 353static bool si_blend_factor_uses_dst(unsigned factor) 354{ 355 return factor == VK_BLEND_FACTOR_DST_COLOR || 356 factor == VK_BLEND_FACTOR_DST_ALPHA || 357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || 358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA || 359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR; 360} 361 362static bool is_dual_src(VkBlendFactor factor) 363{ 364 switch (factor) { 365 case VK_BLEND_FACTOR_SRC1_COLOR: 366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR: 367 case VK_BLEND_FACTOR_SRC1_ALPHA: 368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA: 369 return true; 370 default: 371 return false; 372 } 373} 374 375static unsigned si_choose_spi_color_format(VkFormat vk_format, 376 bool blend_enable, 377 bool blend_need_alpha) 378{ 379 const struct vk_format_description *desc = vk_format_description(vk_format); 380 unsigned format, ntype, swap; 381 382 /* Alpha is needed for alpha-to-coverage. 383 * Blending may be with or without alpha. 384 */ 385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */ 386 unsigned alpha = 0; /* exports alpha, but may not support blending */ 387 unsigned blend = 0; /* supports blending, but may not export alpha */ 388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ 389 390 format = radv_translate_colorformat(vk_format); 391 ntype = radv_translate_color_numformat(vk_format, desc, 392 vk_format_get_first_non_void_channel(vk_format)); 393 swap = radv_translate_colorswap(vk_format, false); 394 395 /* Choose the SPI color formats. These are required values for Stoney/RB+. 396 * Other chips have multiple choices, though they are not necessarily better. 397 */ 398 switch (format) { 399 case V_028C70_COLOR_5_6_5: 400 case V_028C70_COLOR_1_5_5_5: 401 case V_028C70_COLOR_5_5_5_1: 402 case V_028C70_COLOR_4_4_4_4: 403 case V_028C70_COLOR_10_11_11: 404 case V_028C70_COLOR_11_11_10: 405 case V_028C70_COLOR_8: 406 case V_028C70_COLOR_8_8: 407 case V_028C70_COLOR_8_8_8_8: 408 case V_028C70_COLOR_10_10_10_2: 409 case V_028C70_COLOR_2_10_10_10: 410 if (ntype == V_028C70_NUMBER_UINT) 411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 412 else if (ntype == V_028C70_NUMBER_SINT) 413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 414 else 415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 416 break; 417 418 case V_028C70_COLOR_16: 419 case V_028C70_COLOR_16_16: 420 case V_028C70_COLOR_16_16_16_16: 421 if (ntype == V_028C70_NUMBER_UNORM || 422 ntype == V_028C70_NUMBER_SNORM) { 423 /* UNORM16 and SNORM16 don't support blending */ 424 if (ntype == V_028C70_NUMBER_UNORM) 425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; 426 else 427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; 428 429 /* Use 32 bits per channel for blending. */ 430 if (format == V_028C70_COLOR_16) { 431 if (swap == V_028C70_SWAP_STD) { /* R */ 432 blend = V_028714_SPI_SHADER_32_R; 433 blend_alpha = V_028714_SPI_SHADER_32_AR; 434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 436 else 437 assert(0); 438 } else if (format == V_028C70_COLOR_16_16) { 439 if (swap == V_028C70_SWAP_STD) { /* RG */ 440 blend = V_028714_SPI_SHADER_32_GR; 441 blend_alpha = V_028714_SPI_SHADER_32_ABGR; 442 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 444 else 445 assert(0); 446 } else /* 16_16_16_16 */ 447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 448 } else if (ntype == V_028C70_NUMBER_UINT) 449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 450 else if (ntype == V_028C70_NUMBER_SINT) 451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 452 else if (ntype == V_028C70_NUMBER_FLOAT) 453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 454 else 455 assert(0); 456 break; 457 458 case V_028C70_COLOR_32: 459 if (swap == V_028C70_SWAP_STD) { /* R */ 460 blend = normal = V_028714_SPI_SHADER_32_R; 461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; 462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 464 else 465 assert(0); 466 break; 467 468 case V_028C70_COLOR_32_32: 469 if (swap == V_028C70_SWAP_STD) { /* RG */ 470 blend = normal = V_028714_SPI_SHADER_32_GR; 471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 472 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 474 else 475 assert(0); 476 break; 477 478 case V_028C70_COLOR_32_32_32_32: 479 case V_028C70_COLOR_8_24: 480 case V_028C70_COLOR_24_8: 481 case V_028C70_COLOR_X24_8_32_FLOAT: 482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; 483 break; 484 485 default: 486 unreachable("unhandled blend format"); 487 } 488 489 if (blend_enable && blend_need_alpha) 490 return blend_alpha; 491 else if(blend_need_alpha) 492 return alpha; 493 else if(blend_enable) 494 return blend; 495 else 496 return normal; 497} 498 499static void 500radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, 501 const VkGraphicsPipelineCreateInfo *pCreateInfo, 502 struct radv_blend_state *blend) 503{ 504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 506 unsigned col_format = 0; 507 unsigned num_targets; 508 509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) { 510 unsigned cf; 511 512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) { 513 cf = V_028714_SPI_SHADER_ZERO; 514 } else { 515 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment; 516 bool blend_enable = 517 blend->blend_enable_4bit & (0xfu << (i * 4)); 518 519 cf = si_choose_spi_color_format(attachment->format, 520 blend_enable, 521 blend->need_src_alpha & (1 << i)); 522 } 523 524 col_format |= cf << (4 * i); 525 } 526 527 /* If the i-th target format is set, all previous target formats must 528 * be non-zero to avoid hangs. 529 */ 530 num_targets = (util_last_bit(col_format) + 3) / 4; 531 for (unsigned i = 0; i < num_targets; i++) { 532 if (!(col_format & (0xf << (i * 4)))) { 533 col_format |= V_028714_SPI_SHADER_32_R << (i * 4); 534 } 535 } 536 537 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format); 538 539 if (blend->mrt0_is_dual_src) 540 col_format |= (col_format & 0xf) << 4; 541 blend->spi_shader_col_format = col_format; 542} 543 544static bool 545format_is_int8(VkFormat format) 546{ 547 const struct vk_format_description *desc = vk_format_description(format); 548 int channel = vk_format_get_first_non_void_channel(format); 549 550 return channel >= 0 && desc->channel[channel].pure_integer && 551 desc->channel[channel].size == 8; 552} 553 554static bool 555format_is_int10(VkFormat format) 556{ 557 const struct vk_format_description *desc = vk_format_description(format); 558 559 if (desc->nr_channels != 4) 560 return false; 561 for (unsigned i = 0; i < 4; i++) { 562 if (desc->channel[i].pure_integer && desc->channel[i].size == 10) 563 return true; 564 } 565 return false; 566} 567 568/* 569 * Ordered so that for each i, 570 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i. 571 */ 572const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = { 573 VK_FORMAT_R32_SFLOAT, 574 VK_FORMAT_R32G32_SFLOAT, 575 VK_FORMAT_R8G8B8A8_UNORM, 576 VK_FORMAT_R16G16B16A16_UNORM, 577 VK_FORMAT_R16G16B16A16_SNORM, 578 VK_FORMAT_R16G16B16A16_UINT, 579 VK_FORMAT_R16G16B16A16_SINT, 580 VK_FORMAT_R32G32B32A32_SFLOAT, 581 VK_FORMAT_R8G8B8A8_UINT, 582 VK_FORMAT_R8G8B8A8_SINT, 583 VK_FORMAT_A2R10G10B10_UINT_PACK32, 584 VK_FORMAT_A2R10G10B10_SINT_PACK32, 585}; 586 587unsigned radv_format_meta_fs_key(VkFormat format) 588{ 589 unsigned col_format = si_choose_spi_color_format(format, false, false); 590 591 assert(col_format != V_028714_SPI_SHADER_32_AR); 592 if (col_format >= V_028714_SPI_SHADER_32_AR) 593 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */ 594 595 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */ 596 bool is_int8 = format_is_int8(format); 597 bool is_int10 = format_is_int10(format); 598 599 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0); 600} 601 602static void 603radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo, 604 unsigned *is_int8, unsigned *is_int10) 605{ 606 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 607 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 608 *is_int8 = 0; 609 *is_int10 = 0; 610 611 for (unsigned i = 0; i < subpass->color_count; ++i) { 612 struct radv_render_pass_attachment *attachment; 613 614 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) 615 continue; 616 617 attachment = pass->attachments + subpass->color_attachments[i].attachment; 618 619 if (format_is_int8(attachment->format)) 620 *is_int8 |= 1 << i; 621 if (format_is_int10(attachment->format)) 622 *is_int10 |= 1 << i; 623 } 624} 625 626static void 627radv_blend_check_commutativity(struct radv_blend_state *blend, 628 VkBlendOp op, VkBlendFactor src, 629 VkBlendFactor dst, unsigned chanmask) 630{ 631 /* Src factor is allowed when it does not depend on Dst. */ 632 static const uint32_t src_allowed = 633 (1u << VK_BLEND_FACTOR_ONE) | 634 (1u << VK_BLEND_FACTOR_SRC_COLOR) | 635 (1u << VK_BLEND_FACTOR_SRC_ALPHA) | 636 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) | 637 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) | 638 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) | 639 (1u << VK_BLEND_FACTOR_SRC1_COLOR) | 640 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) | 641 (1u << VK_BLEND_FACTOR_ZERO) | 642 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) | 643 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) | 644 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) | 645 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) | 646 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) | 647 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA); 648 649 if (dst == VK_BLEND_FACTOR_ONE && 650 (src_allowed & (1u << src))) { 651 /* Addition is commutative, but floating point addition isn't 652 * associative: subtle changes can be introduced via different 653 * rounding. Be conservative, only enable for min and max. 654 */ 655 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN) 656 blend->commutative_4bit |= chanmask; 657 } 658} 659 660static struct radv_blend_state 661radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, 662 const VkGraphicsPipelineCreateInfo *pCreateInfo, 663 const struct radv_graphics_pipeline_create_info *extra) 664{ 665 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; 666 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; 667 struct radv_blend_state blend = {0}; 668 unsigned mode = V_028808_CB_NORMAL; 669 int i; 670 671 if (!vkblend) 672 return blend; 673 674 if (extra && extra->custom_blend_mode) { 675 blend.single_cb_enable = true; 676 mode = extra->custom_blend_mode; 677 } 678 blend.cb_color_control = 0; 679 if (vkblend->logicOpEnable) 680 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp)); 681 else 682 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); 683 684 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 685 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 686 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 687 S_028B70_ALPHA_TO_MASK_OFFSET3(2); 688 689 if (vkms && vkms->alphaToCoverageEnable) { 690 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1); 691 } 692 693 blend.cb_target_mask = 0; 694 for (i = 0; i < vkblend->attachmentCount; i++) { 695 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i]; 696 unsigned blend_cntl = 0; 697 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt; 698 VkBlendOp eqRGB = att->colorBlendOp; 699 VkBlendFactor srcRGB = att->srcColorBlendFactor; 700 VkBlendFactor dstRGB = att->dstColorBlendFactor; 701 VkBlendOp eqA = att->alphaBlendOp; 702 VkBlendFactor srcA = att->srcAlphaBlendFactor; 703 VkBlendFactor dstA = att->dstAlphaBlendFactor; 704 705 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); 706 707 if (!att->colorWriteMask) 708 continue; 709 710 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); 711 blend.cb_target_enabled_4bit |= 0xf << (4 * i); 712 if (!att->blendEnable) { 713 blend.cb_blend_control[i] = blend_cntl; 714 continue; 715 } 716 717 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA)) 718 if (i == 0) 719 blend.mrt0_is_dual_src = true; 720 721 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) { 722 srcRGB = VK_BLEND_FACTOR_ONE; 723 dstRGB = VK_BLEND_FACTOR_ONE; 724 } 725 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) { 726 srcA = VK_BLEND_FACTOR_ONE; 727 dstA = VK_BLEND_FACTOR_ONE; 728 } 729 730 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB, 731 0x7 << (4 * i)); 732 radv_blend_check_commutativity(&blend, eqA, srcA, dstA, 733 0x8 << (4 * i)); 734 735 /* Blending optimizations for RB+. 736 * These transformations don't change the behavior. 737 * 738 * First, get rid of DST in the blend factors: 739 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) 740 */ 741 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, 742 VK_BLEND_FACTOR_DST_COLOR, 743 VK_BLEND_FACTOR_SRC_COLOR); 744 745 si_blend_remove_dst(&eqA, &srcA, &dstA, 746 VK_BLEND_FACTOR_DST_COLOR, 747 VK_BLEND_FACTOR_SRC_COLOR); 748 749 si_blend_remove_dst(&eqA, &srcA, &dstA, 750 VK_BLEND_FACTOR_DST_ALPHA, 751 VK_BLEND_FACTOR_SRC_ALPHA); 752 753 /* Look up the ideal settings from tables. */ 754 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false); 755 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false); 756 srcA_opt = si_translate_blend_opt_factor(srcA, true); 757 dstA_opt = si_translate_blend_opt_factor(dstA, true); 758 759 /* Handle interdependencies. */ 760 if (si_blend_factor_uses_dst(srcRGB)) 761 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 762 if (si_blend_factor_uses_dst(srcA)) 763 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 764 765 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE && 766 (dstRGB == VK_BLEND_FACTOR_ZERO || 767 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || 768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE)) 769 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; 770 771 /* Set the final value. */ 772 blend.sx_mrt_blend_opt[i] = 773 S_028760_COLOR_SRC_OPT(srcRGB_opt) | 774 S_028760_COLOR_DST_OPT(dstRGB_opt) | 775 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) | 776 S_028760_ALPHA_SRC_OPT(srcA_opt) | 777 S_028760_ALPHA_DST_OPT(dstA_opt) | 778 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA)); 779 blend_cntl |= S_028780_ENABLE(1); 780 781 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 782 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 783 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 784 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 785 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 786 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 787 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 788 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 789 } 790 blend.cb_blend_control[i] = blend_cntl; 791 792 blend.blend_enable_4bit |= 0xfu << (i * 4); 793 794 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA || 795 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || 796 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || 797 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || 798 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA || 799 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) 800 blend.need_src_alpha |= 1 << i; 801 } 802 for (i = vkblend->attachmentCount; i < 8; i++) { 803 blend.cb_blend_control[i] = 0; 804 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); 805 } 806 807 if (pipeline->device->physical_device->has_rbplus) { 808 /* Disable RB+ blend optimizations for dual source blending. */ 809 if (blend.mrt0_is_dual_src) { 810 for (i = 0; i < 8; i++) { 811 blend.sx_mrt_blend_opt[i] = 812 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) | 813 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE); 814 } 815 } 816 817 /* RB+ doesn't work with dual source blending, logic op and 818 * RESOLVE. 819 */ 820 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable || 821 mode == V_028808_CB_RESOLVE) 822 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1); 823 } 824 825 if (blend.cb_target_mask) 826 blend.cb_color_control |= S_028808_MODE(mode); 827 else 828 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE); 829 830 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend); 831 return blend; 832} 833 834static uint32_t si_translate_stencil_op(enum VkStencilOp op) 835{ 836 switch (op) { 837 case VK_STENCIL_OP_KEEP: 838 return V_02842C_STENCIL_KEEP; 839 case VK_STENCIL_OP_ZERO: 840 return V_02842C_STENCIL_ZERO; 841 case VK_STENCIL_OP_REPLACE: 842 return V_02842C_STENCIL_REPLACE_TEST; 843 case VK_STENCIL_OP_INCREMENT_AND_CLAMP: 844 return V_02842C_STENCIL_ADD_CLAMP; 845 case VK_STENCIL_OP_DECREMENT_AND_CLAMP: 846 return V_02842C_STENCIL_SUB_CLAMP; 847 case VK_STENCIL_OP_INVERT: 848 return V_02842C_STENCIL_INVERT; 849 case VK_STENCIL_OP_INCREMENT_AND_WRAP: 850 return V_02842C_STENCIL_ADD_WRAP; 851 case VK_STENCIL_OP_DECREMENT_AND_WRAP: 852 return V_02842C_STENCIL_SUB_WRAP; 853 default: 854 return 0; 855 } 856} 857 858static uint32_t si_translate_fill(VkPolygonMode func) 859{ 860 switch(func) { 861 case VK_POLYGON_MODE_FILL: 862 return V_028814_X_DRAW_TRIANGLES; 863 case VK_POLYGON_MODE_LINE: 864 return V_028814_X_DRAW_LINES; 865 case VK_POLYGON_MODE_POINT: 866 return V_028814_X_DRAW_POINTS; 867 default: 868 assert(0); 869 return V_028814_X_DRAW_POINTS; 870 } 871} 872 873static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms) 874{ 875 uint32_t num_samples = vkms->rasterizationSamples; 876 uint32_t ps_iter_samples = 1; 877 878 if (vkms->sampleShadingEnable) { 879 ps_iter_samples = ceil(vkms->minSampleShading * num_samples); 880 ps_iter_samples = util_next_power_of_two(ps_iter_samples); 881 } 882 return ps_iter_samples; 883} 884 885static bool 886radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo) 887{ 888 return pCreateInfo->depthTestEnable && 889 pCreateInfo->depthWriteEnable && 890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER; 891} 892 893static bool 894radv_writes_stencil(const VkStencilOpState *state) 895{ 896 return state->writeMask && 897 (state->failOp != VK_STENCIL_OP_KEEP || 898 state->passOp != VK_STENCIL_OP_KEEP || 899 state->depthFailOp != VK_STENCIL_OP_KEEP); 900} 901 902static bool 903radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo) 904{ 905 return pCreateInfo->stencilTestEnable && 906 (radv_writes_stencil(&pCreateInfo->front) || 907 radv_writes_stencil(&pCreateInfo->back)); 908} 909 910static bool 911radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo) 912{ 913 return radv_is_depth_write_enabled(pCreateInfo) || 914 radv_is_stencil_write_enabled(pCreateInfo); 915} 916 917static bool 918radv_order_invariant_stencil_op(VkStencilOp op) 919{ 920 /* REPLACE is normally order invariant, except when the stencil 921 * reference value is written by the fragment shader. Tracking this 922 * interaction does not seem worth the effort, so be conservative. 923 */ 924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP && 925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP && 926 op != VK_STENCIL_OP_REPLACE; 927} 928 929static bool 930radv_order_invariant_stencil_state(const VkStencilOpState *state) 931{ 932 /* Compute whether, assuming Z writes are disabled, this stencil state 933 * is order invariant in the sense that the set of passing fragments as 934 * well as the final stencil buffer result does not depend on the order 935 * of fragments. 936 */ 937 return !state->writeMask || 938 /* The following assumes that Z writes are disabled. */ 939 (state->compareOp == VK_COMPARE_OP_ALWAYS && 940 radv_order_invariant_stencil_op(state->passOp) && 941 radv_order_invariant_stencil_op(state->depthFailOp)) || 942 (state->compareOp == VK_COMPARE_OP_NEVER && 943 radv_order_invariant_stencil_op(state->failOp)); 944} 945 946static bool 947radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, 948 struct radv_blend_state *blend, 949 const VkGraphicsPipelineCreateInfo *pCreateInfo) 950{ 951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 953 unsigned colormask = blend->cb_target_enabled_4bit; 954 955 if (!pipeline->device->physical_device->out_of_order_rast_allowed) 956 return false; 957 958 /* Be conservative if a logic operation is enabled with color buffers. */ 959 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable) 960 return false; 961 962 /* Default depth/stencil invariance when no attachment is bound. */ 963 struct radv_dsa_order_invariance dsa_order_invariant = { 964 .zs = true, .pass_set = true 965 }; 966 967 if (pCreateInfo->pDepthStencilState && 968 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { 969 const VkPipelineDepthStencilStateCreateInfo *vkds = 970 pCreateInfo->pDepthStencilState; 971 struct radv_render_pass_attachment *attachment = 972 pass->attachments + subpass->depth_stencil_attachment.attachment; 973 bool has_stencil = vk_format_is_stencil(attachment->format); 974 struct radv_dsa_order_invariance order_invariance[2]; 975 struct radv_shader_variant *ps = 976 pipeline->shaders[MESA_SHADER_FRAGMENT]; 977 978 /* Compute depth/stencil order invariance in order to know if 979 * it's safe to enable out-of-order. 980 */ 981 bool zfunc_is_ordered = 982 vkds->depthCompareOp == VK_COMPARE_OP_NEVER || 983 vkds->depthCompareOp == VK_COMPARE_OP_LESS || 984 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL || 985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER || 986 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL; 987 988 bool nozwrite_and_order_invariant_stencil = 989 !radv_is_ds_write_enabled(vkds) || 990 (!radv_is_depth_write_enabled(vkds) && 991 radv_order_invariant_stencil_state(&vkds->front) && 992 radv_order_invariant_stencil_state(&vkds->back)); 993 994 order_invariance[1].zs = 995 nozwrite_and_order_invariant_stencil || 996 (!radv_is_stencil_write_enabled(vkds) && 997 zfunc_is_ordered); 998 order_invariance[0].zs = 999 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered; 1000 1001 order_invariance[1].pass_set = 1002 nozwrite_and_order_invariant_stencil || 1003 (!radv_is_stencil_write_enabled(vkds) && 1004 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS || 1005 vkds->depthCompareOp == VK_COMPARE_OP_NEVER)); 1006 order_invariance[0].pass_set = 1007 !radv_is_depth_write_enabled(vkds) || 1008 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS || 1009 vkds->depthCompareOp == VK_COMPARE_OP_NEVER); 1010 1011 dsa_order_invariant = order_invariance[has_stencil]; 1012 if (!dsa_order_invariant.zs) 1013 return false; 1014 1015 /* The set of PS invocations is always order invariant, 1016 * except when early Z/S tests are requested. 1017 */ 1018 if (ps && 1019 ps->info.info.ps.writes_memory && 1020 ps->info.fs.early_fragment_test && 1021 !dsa_order_invariant.pass_set) 1022 return false; 1023 1024 /* Determine if out-of-order rasterization should be disabled 1025 * when occlusion queries are used. 1026 */ 1027 pipeline->graphics.disable_out_of_order_rast_for_occlusion = 1028 !dsa_order_invariant.pass_set; 1029 } 1030 1031 /* No color buffers are enabled for writing. */ 1032 if (!colormask) 1033 return true; 1034 1035 unsigned blendmask = colormask & blend->blend_enable_4bit; 1036 1037 if (blendmask) { 1038 /* Only commutative blending. */ 1039 if (blendmask & ~blend->commutative_4bit) 1040 return false; 1041 1042 if (!dsa_order_invariant.pass_set) 1043 return false; 1044 } 1045 1046 if (colormask & ~blendmask) 1047 return false; 1048 1049 return true; 1050} 1051 1052static void 1053radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, 1054 struct radv_blend_state *blend, 1055 const VkGraphicsPipelineCreateInfo *pCreateInfo) 1056{ 1057 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; 1058 struct radv_multisample_state *ms = &pipeline->graphics.ms; 1059 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; 1060 bool out_of_order_rast = false; 1061 int ps_iter_samples = 1; 1062 uint32_t mask = 0xffff; 1063 1064 if (vkms) 1065 ms->num_samples = vkms->rasterizationSamples; 1066 else 1067 ms->num_samples = 1; 1068 1069 if (vkms) 1070 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms); 1071 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) { 1072 ps_iter_samples = ms->num_samples; 1073 } 1074 1075 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = 1076 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD); 1077 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) { 1078 /* Out-of-order rasterization is explicitly enabled by the 1079 * application. 1080 */ 1081 out_of_order_rast = true; 1082 } else { 1083 /* Determine if the driver can enable out-of-order 1084 * rasterization internally. 1085 */ 1086 out_of_order_rast = 1087 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo); 1088 } 1089 1090 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1); 1091 ms->pa_sc_aa_config = 0; 1092 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | 1093 S_028804_INCOHERENT_EQAA_READS(1) | 1094 S_028804_INTERPOLATE_COMP_Z(1) | 1095 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); 1096 ms->pa_sc_mode_cntl_1 = 1097 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes 1098 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | 1099 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) | 1100 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) | 1101 /* always 1: */ 1102 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 1103 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | 1104 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | 1105 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | 1106 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 1107 S_028A4C_FORCE_EOV_REZ_ENABLE(1); 1108 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) | 1109 S_028A48_VPORT_SCISSOR_ENABLE(1); 1110 1111 if (ms->num_samples > 1) { 1112 unsigned log_samples = util_logbase2(ms->num_samples); 1113 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples); 1114 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1); 1115 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */ 1116 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) | 1117 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | 1118 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | 1119 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); 1120 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | 1121 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | 1122 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ 1123 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); 1124 if (ps_iter_samples > 1) 1125 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); 1126 } 1127 1128 if (vkms && vkms->pSampleMask) { 1129 mask = vkms->pSampleMask[0] & 0xffff; 1130 } 1131 1132 ms->pa_sc_aa_mask[0] = mask | (mask << 16); 1133 ms->pa_sc_aa_mask[1] = mask | (mask << 16); 1134} 1135 1136static bool 1137radv_prim_can_use_guardband(enum VkPrimitiveTopology topology) 1138{ 1139 switch (topology) { 1140 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: 1141 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: 1142 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: 1143 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: 1144 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: 1145 return false; 1146 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: 1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: 1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: 1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: 1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: 1151 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: 1152 return true; 1153 default: 1154 unreachable("unhandled primitive type"); 1155 } 1156} 1157 1158static uint32_t 1159si_translate_prim(enum VkPrimitiveTopology topology) 1160{ 1161 switch (topology) { 1162 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: 1163 return V_008958_DI_PT_POINTLIST; 1164 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: 1165 return V_008958_DI_PT_LINELIST; 1166 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: 1167 return V_008958_DI_PT_LINESTRIP; 1168 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: 1169 return V_008958_DI_PT_TRILIST; 1170 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: 1171 return V_008958_DI_PT_TRISTRIP; 1172 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: 1173 return V_008958_DI_PT_TRIFAN; 1174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: 1175 return V_008958_DI_PT_LINELIST_ADJ; 1176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: 1177 return V_008958_DI_PT_LINESTRIP_ADJ; 1178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: 1179 return V_008958_DI_PT_TRILIST_ADJ; 1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: 1181 return V_008958_DI_PT_TRISTRIP_ADJ; 1182 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: 1183 return V_008958_DI_PT_PATCH; 1184 default: 1185 assert(0); 1186 return 0; 1187 } 1188} 1189 1190static uint32_t 1191si_conv_gl_prim_to_gs_out(unsigned gl_prim) 1192{ 1193 switch (gl_prim) { 1194 case 0: /* GL_POINTS */ 1195 return V_028A6C_OUTPRIM_TYPE_POINTLIST; 1196 case 1: /* GL_LINES */ 1197 case 3: /* GL_LINE_STRIP */ 1198 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */ 1199 case 0x8E7A: /* GL_ISOLINES */ 1200 return V_028A6C_OUTPRIM_TYPE_LINESTRIP; 1201 1202 case 4: /* GL_TRIANGLES */ 1203 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */ 1204 case 5: /* GL_TRIANGLE_STRIP */ 1205 case 7: /* GL_QUADS */ 1206 return V_028A6C_OUTPRIM_TYPE_TRISTRIP; 1207 default: 1208 assert(0); 1209 return 0; 1210 } 1211} 1212 1213static uint32_t 1214si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology) 1215{ 1216 switch (topology) { 1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: 1218 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: 1219 return V_028A6C_OUTPRIM_TYPE_POINTLIST; 1220 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: 1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: 1222 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: 1223 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: 1224 return V_028A6C_OUTPRIM_TYPE_LINESTRIP; 1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: 1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: 1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: 1228 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: 1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: 1230 return V_028A6C_OUTPRIM_TYPE_TRISTRIP; 1231 default: 1232 assert(0); 1233 return 0; 1234 } 1235} 1236 1237static unsigned si_map_swizzle(unsigned swizzle) 1238{ 1239 switch (swizzle) { 1240 case VK_SWIZZLE_Y: 1241 return V_008F0C_SQ_SEL_Y; 1242 case VK_SWIZZLE_Z: 1243 return V_008F0C_SQ_SEL_Z; 1244 case VK_SWIZZLE_W: 1245 return V_008F0C_SQ_SEL_W; 1246 case VK_SWIZZLE_0: 1247 return V_008F0C_SQ_SEL_0; 1248 case VK_SWIZZLE_1: 1249 return V_008F0C_SQ_SEL_1; 1250 default: /* VK_SWIZZLE_X */ 1251 return V_008F0C_SQ_SEL_X; 1252 } 1253} 1254 1255 1256static unsigned radv_dynamic_state_mask(VkDynamicState state) 1257{ 1258 switch(state) { 1259 case VK_DYNAMIC_STATE_VIEWPORT: 1260 return RADV_DYNAMIC_VIEWPORT; 1261 case VK_DYNAMIC_STATE_SCISSOR: 1262 return RADV_DYNAMIC_SCISSOR; 1263 case VK_DYNAMIC_STATE_LINE_WIDTH: 1264 return RADV_DYNAMIC_LINE_WIDTH; 1265 case VK_DYNAMIC_STATE_DEPTH_BIAS: 1266 return RADV_DYNAMIC_DEPTH_BIAS; 1267 case VK_DYNAMIC_STATE_BLEND_CONSTANTS: 1268 return RADV_DYNAMIC_BLEND_CONSTANTS; 1269 case VK_DYNAMIC_STATE_DEPTH_BOUNDS: 1270 return RADV_DYNAMIC_DEPTH_BOUNDS; 1271 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK: 1272 return RADV_DYNAMIC_STENCIL_COMPARE_MASK; 1273 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK: 1274 return RADV_DYNAMIC_STENCIL_WRITE_MASK; 1275 case VK_DYNAMIC_STATE_STENCIL_REFERENCE: 1276 return RADV_DYNAMIC_STENCIL_REFERENCE; 1277 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT: 1278 return RADV_DYNAMIC_DISCARD_RECTANGLE; 1279 default: 1280 unreachable("Unhandled dynamic state"); 1281 } 1282} 1283 1284static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) 1285{ 1286 uint32_t states = RADV_DYNAMIC_ALL; 1287 1288 /* If rasterization is disabled we do not care about any of the dynamic states, 1289 * since they are all rasterization related only. */ 1290 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable) 1291 return 0; 1292 1293 if (!pCreateInfo->pRasterizationState->depthBiasEnable) 1294 states &= ~RADV_DYNAMIC_DEPTH_BIAS; 1295 1296 if (!pCreateInfo->pDepthStencilState || 1297 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable) 1298 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS; 1299 1300 if (!pCreateInfo->pDepthStencilState || 1301 !pCreateInfo->pDepthStencilState->stencilTestEnable) 1302 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK | 1303 RADV_DYNAMIC_STENCIL_WRITE_MASK | 1304 RADV_DYNAMIC_STENCIL_REFERENCE); 1305 1306 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT)) 1307 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE; 1308 1309 /* TODO: blend constants & line width. */ 1310 1311 return states; 1312} 1313 1314 1315static void 1316radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, 1317 const VkGraphicsPipelineCreateInfo *pCreateInfo) 1318{ 1319 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo); 1320 uint32_t states = needed_states; 1321 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 1322 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; 1323 1324 pipeline->dynamic_state = default_dynamic_state; 1325 pipeline->graphics.needed_dynamic_state = needed_states; 1326 1327 if (pCreateInfo->pDynamicState) { 1328 /* Remove all of the states that are marked as dynamic */ 1329 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount; 1330 for (uint32_t s = 0; s < count; s++) 1331 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]); 1332 } 1333 1334 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; 1335 1336 if (needed_states & RADV_DYNAMIC_VIEWPORT) { 1337 assert(pCreateInfo->pViewportState); 1338 1339 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount; 1340 if (states & RADV_DYNAMIC_VIEWPORT) { 1341 typed_memcpy(dynamic->viewport.viewports, 1342 pCreateInfo->pViewportState->pViewports, 1343 pCreateInfo->pViewportState->viewportCount); 1344 } 1345 } 1346 1347 if (needed_states & RADV_DYNAMIC_SCISSOR) { 1348 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount; 1349 if (states & RADV_DYNAMIC_SCISSOR) { 1350 typed_memcpy(dynamic->scissor.scissors, 1351 pCreateInfo->pViewportState->pScissors, 1352 pCreateInfo->pViewportState->scissorCount); 1353 } 1354 } 1355 1356 if (states & RADV_DYNAMIC_LINE_WIDTH) { 1357 assert(pCreateInfo->pRasterizationState); 1358 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth; 1359 } 1360 1361 if (states & RADV_DYNAMIC_DEPTH_BIAS) { 1362 assert(pCreateInfo->pRasterizationState); 1363 dynamic->depth_bias.bias = 1364 pCreateInfo->pRasterizationState->depthBiasConstantFactor; 1365 dynamic->depth_bias.clamp = 1366 pCreateInfo->pRasterizationState->depthBiasClamp; 1367 dynamic->depth_bias.slope = 1368 pCreateInfo->pRasterizationState->depthBiasSlopeFactor; 1369 } 1370 1371 /* Section 9.2 of the Vulkan 1.0.15 spec says: 1372 * 1373 * pColorBlendState is [...] NULL if the pipeline has rasterization 1374 * disabled or if the subpass of the render pass the pipeline is 1375 * created against does not use any color attachments. 1376 */ 1377 bool uses_color_att = false; 1378 for (unsigned i = 0; i < subpass->color_count; ++i) { 1379 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) { 1380 uses_color_att = true; 1381 break; 1382 } 1383 } 1384 1385 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) { 1386 assert(pCreateInfo->pColorBlendState); 1387 typed_memcpy(dynamic->blend_constants, 1388 pCreateInfo->pColorBlendState->blendConstants, 4); 1389 } 1390 1391 /* If there is no depthstencil attachment, then don't read 1392 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may 1393 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is 1394 * no need to override the depthstencil defaults in 1395 * radv_pipeline::dynamic_state when there is no depthstencil attachment. 1396 * 1397 * Section 9.2 of the Vulkan 1.0.15 spec says: 1398 * 1399 * pDepthStencilState is [...] NULL if the pipeline has rasterization 1400 * disabled or if the subpass of the render pass the pipeline is created 1401 * against does not use a depth/stencil attachment. 1402 */ 1403 if (needed_states && 1404 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { 1405 assert(pCreateInfo->pDepthStencilState); 1406 1407 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) { 1408 dynamic->depth_bounds.min = 1409 pCreateInfo->pDepthStencilState->minDepthBounds; 1410 dynamic->depth_bounds.max = 1411 pCreateInfo->pDepthStencilState->maxDepthBounds; 1412 } 1413 1414 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) { 1415 dynamic->stencil_compare_mask.front = 1416 pCreateInfo->pDepthStencilState->front.compareMask; 1417 dynamic->stencil_compare_mask.back = 1418 pCreateInfo->pDepthStencilState->back.compareMask; 1419 } 1420 1421 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) { 1422 dynamic->stencil_write_mask.front = 1423 pCreateInfo->pDepthStencilState->front.writeMask; 1424 dynamic->stencil_write_mask.back = 1425 pCreateInfo->pDepthStencilState->back.writeMask; 1426 } 1427 1428 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) { 1429 dynamic->stencil_reference.front = 1430 pCreateInfo->pDepthStencilState->front.reference; 1431 dynamic->stencil_reference.back = 1432 pCreateInfo->pDepthStencilState->back.reference; 1433 } 1434 } 1435 1436 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = 1437 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT); 1438 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) { 1439 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount; 1440 typed_memcpy(dynamic->discard_rectangle.rectangles, 1441 discard_rectangle_info->pDiscardRectangles, 1442 discard_rectangle_info->discardRectangleCount); 1443 } 1444 1445 pipeline->dynamic_state.mask = states; 1446} 1447 1448static struct radv_gs_state 1449calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, 1450 const struct radv_pipeline *pipeline) 1451{ 1452 struct radv_gs_state gs = {0}; 1453 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; 1454 struct radv_es_output_info *es_info; 1455 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) 1456 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info; 1457 else 1458 es_info = radv_pipeline_has_tess(pipeline) ? 1459 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info : 1460 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info; 1461 1462 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1); 1463 bool uses_adjacency; 1464 switch(pCreateInfo->pInputAssemblyState->topology) { 1465 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: 1466 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: 1467 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: 1468 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: 1469 uses_adjacency = true; 1470 break; 1471 default: 1472 uses_adjacency = false; 1473 break; 1474 } 1475 1476 /* All these are in dwords: */ 1477 /* We can't allow using the whole LDS, because GS waves compete with 1478 * other shader stages for LDS space. */ 1479 const unsigned max_lds_size = 8 * 1024; 1480 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4; 1481 unsigned esgs_lds_size; 1482 1483 /* All these are per subgroup: */ 1484 const unsigned max_out_prims = 32 * 1024; 1485 const unsigned max_es_verts = 255; 1486 const unsigned ideal_gs_prims = 64; 1487 unsigned max_gs_prims, gs_prims; 1488 unsigned min_es_verts, es_verts, worst_case_es_verts; 1489 1490 if (uses_adjacency || gs_num_invocations > 1) 1491 max_gs_prims = 127 / gs_num_invocations; 1492 else 1493 max_gs_prims = 255; 1494 1495 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations. 1496 * Make sure we don't go over the maximum value. 1497 */ 1498 if (gs_info->gs.vertices_out > 0) { 1499 max_gs_prims = MIN2(max_gs_prims, 1500 max_out_prims / 1501 (gs_info->gs.vertices_out * gs_num_invocations)); 1502 } 1503 assert(max_gs_prims > 0); 1504 1505 /* If the primitive has adjacency, halve the number of vertices 1506 * that will be reused in multiple primitives. 1507 */ 1508 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1); 1509 1510 gs_prims = MIN2(ideal_gs_prims, max_gs_prims); 1511 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts); 1512 1513 /* Compute ESGS LDS size based on the worst case number of ES vertices 1514 * needed to create the target number of GS prims per subgroup. 1515 */ 1516 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 1517 1518 /* If total LDS usage is too big, refactor partitions based on ratio 1519 * of ESGS item sizes. 1520 */ 1521 if (esgs_lds_size > max_lds_size) { 1522 /* Our target GS Prims Per Subgroup was too large. Calculate 1523 * the maximum number of GS Prims Per Subgroup that will fit 1524 * into LDS, capped by the maximum that the hardware can support. 1525 */ 1526 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), 1527 max_gs_prims); 1528 assert(gs_prims > 0); 1529 worst_case_es_verts = MIN2(min_es_verts * gs_prims, 1530 max_es_verts); 1531 1532 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 1533 assert(esgs_lds_size <= max_lds_size); 1534 } 1535 1536 /* Now calculate remaining ESGS information. */ 1537 if (esgs_lds_size) 1538 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts); 1539 else 1540 es_verts = max_es_verts; 1541 1542 /* Vertices for adjacency primitives are not always reused, so restore 1543 * it for ES_VERTS_PER_SUBGRP. 1544 */ 1545 min_es_verts = gs_info->gs.vertices_in; 1546 1547 /* For normal primitives, the VGT only checks if they are past the ES 1548 * verts per subgroup after allocating a full GS primitive and if they 1549 * are, kick off a new subgroup. But if those additional ES verts are 1550 * unique (e.g. not reused) we need to make sure there is enough LDS 1551 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP. 1552 */ 1553 es_verts -= min_es_verts - 1; 1554 1555 uint32_t es_verts_per_subgroup = es_verts; 1556 uint32_t gs_prims_per_subgroup = gs_prims; 1557 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations; 1558 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out; 1559 gs.lds_size = align(esgs_lds_size, 128) / 128; 1560 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) | 1561 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) | 1562 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup); 1563 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup); 1564 gs.vgt_esgs_ring_itemsize = esgs_itemsize; 1565 assert(max_prims_per_subgroup <= max_out_prims); 1566 1567 return gs; 1568} 1569 1570static void 1571calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs) 1572{ 1573 struct radv_device *device = pipeline->device; 1574 unsigned num_se = device->physical_device->rad_info.max_se; 1575 unsigned wave_size = 64; 1576 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ 1577 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16. 1578 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). 1579 */ 1580 unsigned gs_vertex_reuse = 1581 (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se; 1582 unsigned alignment = 256 * num_se; 1583 /* The maximum size is 63.999 MB per SE. */ 1584 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; 1585 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; 1586 1587 /* Calculate the minimum size. */ 1588 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse * 1589 wave_size, alignment); 1590 /* These are recommended sizes, not minimum sizes. */ 1591 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size * 1592 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in; 1593 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * 1594 gs_info->gs.max_gsvs_emit_size; 1595 1596 min_esgs_ring_size = align(min_esgs_ring_size, alignment); 1597 esgs_ring_size = align(esgs_ring_size, alignment); 1598 gsvs_ring_size = align(gsvs_ring_size, alignment); 1599 1600 if (pipeline->device->physical_device->rad_info.chip_class <= VI) 1601 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); 1602 1603 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); 1604} 1605 1606static void si_multiwave_lds_size_workaround(struct radv_device *device, 1607 unsigned *lds_size) 1608{ 1609 /* If tessellation is all offchip and on-chip GS isn't used, this 1610 * workaround is not needed. 1611 */ 1612 return; 1613 1614 /* SPI barrier management bug: 1615 * Make sure we have at least 4k of LDS in use to avoid the bug. 1616 * It applies to workgroup sizes of more than one wavefront. 1617 */ 1618 if (device->physical_device->rad_info.family == CHIP_BONAIRE || 1619 device->physical_device->rad_info.family == CHIP_KABINI || 1620 device->physical_device->rad_info.family == CHIP_MULLINS) 1621 *lds_size = MAX2(*lds_size, 8); 1622} 1623 1624struct radv_shader_variant * 1625radv_get_shader(struct radv_pipeline *pipeline, 1626 gl_shader_stage stage) 1627{ 1628 if (stage == MESA_SHADER_VERTEX) { 1629 if (pipeline->shaders[MESA_SHADER_VERTEX]) 1630 return pipeline->shaders[MESA_SHADER_VERTEX]; 1631 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) 1632 return pipeline->shaders[MESA_SHADER_TESS_CTRL]; 1633 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) 1634 return pipeline->shaders[MESA_SHADER_GEOMETRY]; 1635 } else if (stage == MESA_SHADER_TESS_EVAL) { 1636 if (!radv_pipeline_has_tess(pipeline)) 1637 return NULL; 1638 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) 1639 return pipeline->shaders[MESA_SHADER_TESS_EVAL]; 1640 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) 1641 return pipeline->shaders[MESA_SHADER_GEOMETRY]; 1642 } 1643 return pipeline->shaders[stage]; 1644} 1645 1646static struct radv_tessellation_state 1647calculate_tess_state(struct radv_pipeline *pipeline, 1648 const VkGraphicsPipelineCreateInfo *pCreateInfo) 1649{ 1650 unsigned num_tcs_input_cp; 1651 unsigned num_tcs_output_cp; 1652 unsigned lds_size; 1653 unsigned num_patches; 1654 struct radv_tessellation_state tess = {0}; 1655 1656 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; 1657 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT 1658 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; 1659 1660 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size; 1661 1662 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) { 1663 assert(lds_size <= 65536); 1664 lds_size = align(lds_size, 512) / 512; 1665 } else { 1666 assert(lds_size <= 32768); 1667 lds_size = align(lds_size, 256) / 256; 1668 } 1669 si_multiwave_lds_size_workaround(pipeline->device, &lds_size); 1670 1671 tess.lds_size = lds_size; 1672 1673 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | 1674 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | 1675 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); 1676 tess.num_patches = num_patches; 1677 1678 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL); 1679 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0; 1680 1681 switch (tes->info.tes.primitive_mode) { 1682 case GL_TRIANGLES: 1683 type = V_028B6C_TESS_TRIANGLE; 1684 break; 1685 case GL_QUADS: 1686 type = V_028B6C_TESS_QUAD; 1687 break; 1688 case GL_ISOLINES: 1689 type = V_028B6C_TESS_ISOLINE; 1690 break; 1691 } 1692 1693 switch (tes->info.tes.spacing) { 1694 case TESS_SPACING_EQUAL: 1695 partitioning = V_028B6C_PART_INTEGER; 1696 break; 1697 case TESS_SPACING_FRACTIONAL_ODD: 1698 partitioning = V_028B6C_PART_FRAC_ODD; 1699 break; 1700 case TESS_SPACING_FRACTIONAL_EVEN: 1701 partitioning = V_028B6C_PART_FRAC_EVEN; 1702 break; 1703 default: 1704 break; 1705 } 1706 1707 bool ccw = tes->info.tes.ccw; 1708 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state = 1709 vk_find_struct_const(pCreateInfo->pTessellationState, 1710 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR); 1711 1712 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR) 1713 ccw = !ccw; 1714 1715 if (tes->info.tes.point_mode) 1716 topology = V_028B6C_OUTPUT_POINT; 1717 else if (tes->info.tes.primitive_mode == GL_ISOLINES) 1718 topology = V_028B6C_OUTPUT_LINE; 1719 else if (ccw) 1720 topology = V_028B6C_OUTPUT_TRIANGLE_CCW; 1721 else 1722 topology = V_028B6C_OUTPUT_TRIANGLE_CW; 1723 1724 if (pipeline->device->has_distributed_tess) { 1725 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || 1726 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) 1727 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; 1728 else 1729 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; 1730 } else 1731 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; 1732 1733 tess.tf_param = S_028B6C_TYPE(type) | 1734 S_028B6C_PARTITIONING(partitioning) | 1735 S_028B6C_TOPOLOGY(topology) | 1736 S_028B6C_DISTRIBUTION_MODE(distribution_mode); 1737 1738 return tess; 1739} 1740 1741static const struct radv_prim_vertex_count prim_size_table[] = { 1742 [V_008958_DI_PT_NONE] = {0, 0}, 1743 [V_008958_DI_PT_POINTLIST] = {1, 1}, 1744 [V_008958_DI_PT_LINELIST] = {2, 2}, 1745 [V_008958_DI_PT_LINESTRIP] = {2, 1}, 1746 [V_008958_DI_PT_TRILIST] = {3, 3}, 1747 [V_008958_DI_PT_TRIFAN] = {3, 1}, 1748 [V_008958_DI_PT_TRISTRIP] = {3, 1}, 1749 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4}, 1750 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1}, 1751 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6}, 1752 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2}, 1753 [V_008958_DI_PT_RECTLIST] = {3, 3}, 1754 [V_008958_DI_PT_LINELOOP] = {2, 1}, 1755 [V_008958_DI_PT_POLYGON] = {3, 1}, 1756 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0}, 1757}; 1758 1759static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline) 1760{ 1761 if (radv_pipeline_has_gs(pipeline)) 1762 return &pipeline->gs_copy_shader->info.vs.outinfo; 1763 else if (radv_pipeline_has_tess(pipeline)) 1764 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo; 1765 else 1766 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo; 1767} 1768 1769static void 1770radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders) 1771{ 1772 nir_shader* ordered_shaders[MESA_SHADER_STAGES]; 1773 int shader_count = 0; 1774 1775 if(shaders[MESA_SHADER_FRAGMENT]) { 1776 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT]; 1777 } 1778 if(shaders[MESA_SHADER_GEOMETRY]) { 1779 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY]; 1780 } 1781 if(shaders[MESA_SHADER_TESS_EVAL]) { 1782 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL]; 1783 } 1784 if(shaders[MESA_SHADER_TESS_CTRL]) { 1785 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL]; 1786 } 1787 if(shaders[MESA_SHADER_VERTEX]) { 1788 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX]; 1789 } 1790 1791 if (shader_count > 1) { 1792 unsigned first = ordered_shaders[shader_count - 1]->info.stage; 1793 unsigned last = ordered_shaders[0]->info.stage; 1794 1795 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT && 1796 ordered_shaders[1]->info.has_transform_feedback_varyings) 1797 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]); 1798 1799 for (int i = 0; i < shader_count; ++i) { 1800 nir_variable_mode mask = 0; 1801 1802 if (ordered_shaders[i]->info.stage != first) 1803 mask = mask | nir_var_shader_in; 1804 1805 if (ordered_shaders[i]->info.stage != last) 1806 mask = mask | nir_var_shader_out; 1807 1808 nir_lower_io_to_scalar_early(ordered_shaders[i], mask); 1809 radv_optimize_nir(ordered_shaders[i], false, false); 1810 } 1811 } 1812 1813 for (int i = 1; i < shader_count; ++i) { 1814 nir_lower_io_arrays_to_elements(ordered_shaders[i], 1815 ordered_shaders[i - 1]); 1816 1817 nir_remove_dead_variables(ordered_shaders[i], 1818 nir_var_shader_out); 1819 nir_remove_dead_variables(ordered_shaders[i - 1], 1820 nir_var_shader_in); 1821 1822 bool progress = nir_remove_unused_varyings(ordered_shaders[i], 1823 ordered_shaders[i - 1]); 1824 1825 nir_compact_varyings(ordered_shaders[i], 1826 ordered_shaders[i - 1], true); 1827 1828 if (progress) { 1829 if (nir_lower_global_vars_to_local(ordered_shaders[i])) { 1830 ac_lower_indirect_derefs(ordered_shaders[i], 1831 pipeline->device->physical_device->rad_info.chip_class); 1832 } 1833 radv_optimize_nir(ordered_shaders[i], false, false); 1834 1835 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) { 1836 ac_lower_indirect_derefs(ordered_shaders[i - 1], 1837 pipeline->device->physical_device->rad_info.chip_class); 1838 } 1839 radv_optimize_nir(ordered_shaders[i - 1], false, false); 1840 } 1841 } 1842} 1843 1844 1845static struct radv_pipeline_key 1846radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, 1847 const VkGraphicsPipelineCreateInfo *pCreateInfo, 1848 const struct radv_blend_state *blend, 1849 bool has_view_index) 1850{ 1851 const VkPipelineVertexInputStateCreateInfo *input_state = 1852 pCreateInfo->pVertexInputState; 1853 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state = 1854 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT); 1855 1856 struct radv_pipeline_key key; 1857 memset(&key, 0, sizeof(key)); 1858 1859 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) 1860 key.optimisations_disabled = 1; 1861 1862 key.has_multiview_view_index = has_view_index; 1863 1864 uint32_t binding_input_rate = 0; 1865 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS]; 1866 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) { 1867 if (input_state->pVertexBindingDescriptions[i].inputRate) { 1868 unsigned binding = input_state->pVertexBindingDescriptions[i].binding; 1869 binding_input_rate |= 1u << binding; 1870 instance_rate_divisors[binding] = 1; 1871 } 1872 } 1873 if (divisor_state) { 1874 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) { 1875 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] = 1876 divisor_state->pVertexBindingDivisors[i].divisor; 1877 } 1878 } 1879 1880 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) { 1881 unsigned location = input_state->pVertexAttributeDescriptions[i].location; 1882 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding; 1883 if (binding_input_rate & (1u << binding)) { 1884 key.instance_rate_inputs |= 1u << location; 1885 key.instance_rate_divisors[location] = instance_rate_divisors[binding]; 1886 } 1887 1888 if (pipeline->device->physical_device->rad_info.chip_class <= VI && 1889 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) { 1890 VkFormat format = input_state->pVertexAttributeDescriptions[i].format; 1891 uint64_t adjust; 1892 switch(format) { 1893 case VK_FORMAT_A2R10G10B10_SNORM_PACK32: 1894 case VK_FORMAT_A2B10G10R10_SNORM_PACK32: 1895 adjust = RADV_ALPHA_ADJUST_SNORM; 1896 break; 1897 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32: 1898 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32: 1899 adjust = RADV_ALPHA_ADJUST_SSCALED; 1900 break; 1901 case VK_FORMAT_A2R10G10B10_SINT_PACK32: 1902 case VK_FORMAT_A2B10G10R10_SINT_PACK32: 1903 adjust = RADV_ALPHA_ADJUST_SINT; 1904 break; 1905 default: 1906 adjust = 0; 1907 break; 1908 } 1909 key.vertex_alpha_adjust |= adjust << (2 * location); 1910 } 1911 } 1912 1913 if (pCreateInfo->pTessellationState) 1914 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints; 1915 1916 1917 if (pCreateInfo->pMultisampleState && 1918 pCreateInfo->pMultisampleState->rasterizationSamples > 1) { 1919 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples; 1920 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState); 1921 key.num_samples = num_samples; 1922 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples); 1923 } 1924 1925 key.col_format = blend->spi_shader_col_format; 1926 if (pipeline->device->physical_device->rad_info.chip_class < VI) 1927 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10); 1928 1929 return key; 1930} 1931 1932static void 1933radv_fill_shader_keys(struct radv_shader_variant_key *keys, 1934 const struct radv_pipeline_key *key, 1935 nir_shader **nir) 1936{ 1937 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs; 1938 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust; 1939 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) 1940 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i]; 1941 1942 if (nir[MESA_SHADER_TESS_CTRL]) { 1943 keys[MESA_SHADER_VERTEX].vs.as_ls = true; 1944 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0; 1945 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices; 1946 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode; 1947 1948 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); 1949 } 1950 1951 if (nir[MESA_SHADER_GEOMETRY]) { 1952 if (nir[MESA_SHADER_TESS_CTRL]) 1953 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true; 1954 else 1955 keys[MESA_SHADER_VERTEX].vs.as_es = true; 1956 } 1957 1958 for(int i = 0; i < MESA_SHADER_STAGES; ++i) 1959 keys[i].has_multiview_view_index = key->has_multiview_view_index; 1960 1961 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format; 1962 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8; 1963 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10; 1964 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples; 1965 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples; 1966} 1967 1968static void 1969merge_tess_info(struct shader_info *tes_info, 1970 const struct shader_info *tcs_info) 1971{ 1972 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says: 1973 * 1974 * "PointMode. Controls generation of points rather than triangles 1975 * or lines. This functionality defaults to disabled, and is 1976 * enabled if either shader stage includes the execution mode. 1977 * 1978 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw, 1979 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd, 1980 * and OutputVertices, it says: 1981 * 1982 * "One mode must be set in at least one of the tessellation 1983 * shader stages." 1984 * 1985 * So, the fields can be set in either the TCS or TES, but they must 1986 * agree if set in both. Our backend looks at TES, so bitwise-or in 1987 * the values from the TCS. 1988 */ 1989 assert(tcs_info->tess.tcs_vertices_out == 0 || 1990 tes_info->tess.tcs_vertices_out == 0 || 1991 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out); 1992 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out; 1993 1994 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED || 1995 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED || 1996 tcs_info->tess.spacing == tes_info->tess.spacing); 1997 tes_info->tess.spacing |= tcs_info->tess.spacing; 1998 1999 assert(tcs_info->tess.primitive_mode == 0 || 2000 tes_info->tess.primitive_mode == 0 || 2001 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode); 2002 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode; 2003 tes_info->tess.ccw |= tcs_info->tess.ccw; 2004 tes_info->tess.point_mode |= tcs_info->tess.point_mode; 2005} 2006 2007static 2008void radv_create_shaders(struct radv_pipeline *pipeline, 2009 struct radv_device *device, 2010 struct radv_pipeline_cache *cache, 2011 const struct radv_pipeline_key *key, 2012 const VkPipelineShaderStageCreateInfo **pStages, 2013 const VkPipelineCreateFlags flags) 2014{ 2015 struct radv_shader_module fs_m = {0}; 2016 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, }; 2017 nir_shader *nir[MESA_SHADER_STAGES] = {0}; 2018 void *codes[MESA_SHADER_STAGES] = {0}; 2019 unsigned code_sizes[MESA_SHADER_STAGES] = {0}; 2020 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}}; 2021 unsigned char hash[20], gs_copy_hash[20]; 2022 2023 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) { 2024 if (pStages[i]) { 2025 modules[i] = radv_shader_module_from_handle(pStages[i]->module); 2026 if (modules[i]->nir) 2027 _mesa_sha1_compute(modules[i]->nir->info.name, 2028 strlen(modules[i]->nir->info.name), 2029 modules[i]->sha1); 2030 2031 pipeline->active_stages |= mesa_to_vk_shader_stage(i); 2032 } 2033 } 2034 2035 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device)); 2036 memcpy(gs_copy_hash, hash, 20); 2037 gs_copy_hash[0] ^= 1; 2038 2039 if (modules[MESA_SHADER_GEOMETRY]) { 2040 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0}; 2041 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants); 2042 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY]; 2043 } 2044 2045 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) && 2046 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) { 2047 return; 2048 } 2049 2050 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) { 2051 nir_builder fs_b; 2052 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL); 2053 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs"); 2054 fs_m.nir = fs_b.shader; 2055 modules[MESA_SHADER_FRAGMENT] = &fs_m; 2056 } 2057 2058 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) { 2059 const VkPipelineShaderStageCreateInfo *stage = pStages[i]; 2060 2061 if (!modules[i]) 2062 continue; 2063 2064 nir[i] = radv_shader_compile_to_nir(device, modules[i], 2065 stage ? stage->pName : "main", i, 2066 stage ? stage->pSpecializationInfo : NULL, 2067 flags); 2068 2069 /* We don't want to alter meta shaders IR directly so clone it 2070 * first. 2071 */ 2072 if (nir[i]->info.name) { 2073 nir[i] = nir_shader_clone(NULL, nir[i]); 2074 } 2075 } 2076 2077 if (nir[MESA_SHADER_TESS_CTRL]) { 2078 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL); 2079 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info); 2080 } 2081 2082 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) 2083 radv_link_shaders(pipeline, nir); 2084 2085 for (int i = 0; i < MESA_SHADER_STAGES; ++i) { 2086 if (radv_can_dump_shader(device, modules[i], false)) 2087 nir_print_shader(nir[i], stderr); 2088 } 2089 2090 radv_fill_shader_keys(keys, key, nir); 2091 2092 if (nir[MESA_SHADER_FRAGMENT]) { 2093 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) { 2094 pipeline->shaders[MESA_SHADER_FRAGMENT] = 2095 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1, 2096 pipeline->layout, keys + MESA_SHADER_FRAGMENT, 2097 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]); 2098 } 2099 2100 /* TODO: These are no longer used as keys we should refactor this */ 2101 keys[MESA_SHADER_VERTEX].vs.export_prim_id = 2102 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input; 2103 keys[MESA_SHADER_VERTEX].vs.export_layer_id = 2104 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input; 2105 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id = 2106 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input; 2107 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id = 2108 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input; 2109 } 2110 2111 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) { 2112 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) { 2113 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]}; 2114 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL]; 2115 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs; 2116 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2, 2117 pipeline->layout, 2118 &key, &codes[MESA_SHADER_TESS_CTRL], 2119 &code_sizes[MESA_SHADER_TESS_CTRL]); 2120 } 2121 modules[MESA_SHADER_VERTEX] = NULL; 2122 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; 2123 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); 2124 } 2125 2126 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) { 2127 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; 2128 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) { 2129 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]}; 2130 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2, 2131 pipeline->layout, 2132 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY], 2133 &code_sizes[MESA_SHADER_GEOMETRY]); 2134 } 2135 modules[pre_stage] = NULL; 2136 } 2137 2138 for (int i = 0; i < MESA_SHADER_STAGES; ++i) { 2139 if(modules[i] && !pipeline->shaders[i]) { 2140 if (i == MESA_SHADER_TESS_CTRL) { 2141 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written); 2142 } 2143 if (i == MESA_SHADER_TESS_EVAL) { 2144 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; 2145 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); 2146 } 2147 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1, 2148 pipeline->layout, 2149 keys + i, &codes[i], 2150 &code_sizes[i]); 2151 } 2152 } 2153 2154 if(modules[MESA_SHADER_GEOMETRY]) { 2155 void *gs_copy_code = NULL; 2156 unsigned gs_copy_code_size = 0; 2157 if (!pipeline->gs_copy_shader) { 2158 pipeline->gs_copy_shader = radv_create_gs_copy_shader( 2159 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code, 2160 &gs_copy_code_size, 2161 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index); 2162 } 2163 2164 if (pipeline->gs_copy_shader) { 2165 void *code[MESA_SHADER_STAGES] = {0}; 2166 unsigned code_size[MESA_SHADER_STAGES] = {0}; 2167 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0}; 2168 2169 code[MESA_SHADER_GEOMETRY] = gs_copy_code; 2170 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size; 2171 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader; 2172 2173 radv_pipeline_cache_insert_shaders(device, cache, 2174 gs_copy_hash, 2175 variants, 2176 (const void**)code, 2177 code_size); 2178 } 2179 free(gs_copy_code); 2180 } 2181 2182 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, 2183 (const void**)codes, code_sizes); 2184 2185 for (int i = 0; i < MESA_SHADER_STAGES; ++i) { 2186 free(codes[i]); 2187 if (nir[i]) { 2188 if (!pipeline->device->keep_shader_info) 2189 ralloc_free(nir[i]); 2190 2191 if (radv_can_dump_shader_stats(device, modules[i])) 2192 radv_shader_dump_stats(device, 2193 pipeline->shaders[i], 2194 i, stderr); 2195 } 2196 } 2197 2198 if (fs_m.nir) 2199 ralloc_free(fs_m.nir); 2200} 2201 2202static uint32_t 2203radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, 2204 gl_shader_stage stage, enum chip_class chip_class) 2205{ 2206 bool has_gs = radv_pipeline_has_gs(pipeline); 2207 bool has_tess = radv_pipeline_has_tess(pipeline); 2208 switch (stage) { 2209 case MESA_SHADER_FRAGMENT: 2210 return R_00B030_SPI_SHADER_USER_DATA_PS_0; 2211 case MESA_SHADER_VERTEX: 2212 if (chip_class >= GFX9) { 2213 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 : 2214 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : 2215 R_00B130_SPI_SHADER_USER_DATA_VS_0; 2216 } 2217 if (has_tess) 2218 return R_00B530_SPI_SHADER_USER_DATA_LS_0; 2219 else 2220 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; 2221 case MESA_SHADER_GEOMETRY: 2222 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : 2223 R_00B230_SPI_SHADER_USER_DATA_GS_0; 2224 case MESA_SHADER_COMPUTE: 2225 return R_00B900_COMPUTE_USER_DATA_0; 2226 case MESA_SHADER_TESS_CTRL: 2227 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 : 2228 R_00B430_SPI_SHADER_USER_DATA_HS_0; 2229 case MESA_SHADER_TESS_EVAL: 2230 if (chip_class >= GFX9) { 2231 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : 2232 R_00B130_SPI_SHADER_USER_DATA_VS_0; 2233 } 2234 if (has_gs) 2235 return R_00B330_SPI_SHADER_USER_DATA_ES_0; 2236 else 2237 return R_00B130_SPI_SHADER_USER_DATA_VS_0; 2238 default: 2239 unreachable("unknown shader"); 2240 } 2241} 2242 2243struct radv_bin_size_entry { 2244 unsigned bpp; 2245 VkExtent2D extent; 2246}; 2247 2248static VkExtent2D 2249radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) 2250{ 2251 static const struct radv_bin_size_entry color_size_table[][3][9] = { 2252 { 2253 /* One RB / SE */ 2254 { 2255 /* One shader engine */ 2256 { 0, {128, 128}}, 2257 { 1, { 64, 128}}, 2258 { 2, { 32, 128}}, 2259 { 3, { 16, 128}}, 2260 { 17, { 0, 0}}, 2261 { UINT_MAX, { 0, 0}}, 2262 }, 2263 { 2264 /* Two shader engines */ 2265 { 0, {128, 128}}, 2266 { 2, { 64, 128}}, 2267 { 3, { 32, 128}}, 2268 { 5, { 16, 128}}, 2269 { 17, { 0, 0}}, 2270 { UINT_MAX, { 0, 0}}, 2271 }, 2272 { 2273 /* Four shader engines */ 2274 { 0, {128, 128}}, 2275 { 3, { 64, 128}}, 2276 { 5, { 16, 128}}, 2277 { 17, { 0, 0}}, 2278 { UINT_MAX, { 0, 0}}, 2279 }, 2280 }, 2281 { 2282 /* Two RB / SE */ 2283 { 2284 /* One shader engine */ 2285 { 0, {128, 128}}, 2286 { 2, { 64, 128}}, 2287 { 3, { 32, 128}}, 2288 { 5, { 16, 128}}, 2289 { 33, { 0, 0}}, 2290 { UINT_MAX, { 0, 0}}, 2291 }, 2292 { 2293 /* Two shader engines */ 2294 { 0, {128, 128}}, 2295 { 3, { 64, 128}}, 2296 { 5, { 32, 128}}, 2297 { 9, { 16, 128}}, 2298 { 33, { 0, 0}}, 2299 { UINT_MAX, { 0, 0}}, 2300 }, 2301 { 2302 /* Four shader engines */ 2303 { 0, {256, 256}}, 2304 { 2, {128, 256}}, 2305 { 3, {128, 128}}, 2306 { 5, { 64, 128}}, 2307 { 9, { 16, 128}}, 2308 { 33, { 0, 0}}, 2309 { UINT_MAX, { 0, 0}}, 2310 }, 2311 }, 2312 { 2313 /* Four RB / SE */ 2314 { 2315 /* One shader engine */ 2316 { 0, {128, 256}}, 2317 { 2, {128, 128}}, 2318 { 3, { 64, 128}}, 2319 { 5, { 32, 128}}, 2320 { 9, { 16, 128}}, 2321 { 33, { 0, 0}}, 2322 { UINT_MAX, { 0, 0}}, 2323 }, 2324 { 2325 /* Two shader engines */ 2326 { 0, {256, 256}}, 2327 { 2, {128, 256}}, 2328 { 3, {128, 128}}, 2329 { 5, { 64, 128}}, 2330 { 9, { 32, 128}}, 2331 { 17, { 16, 128}}, 2332 { 33, { 0, 0}}, 2333 { UINT_MAX, { 0, 0}}, 2334 }, 2335 { 2336 /* Four shader engines */ 2337 { 0, {256, 512}}, 2338 { 2, {256, 256}}, 2339 { 3, {128, 256}}, 2340 { 5, {128, 128}}, 2341 { 9, { 64, 128}}, 2342 { 17, { 16, 128}}, 2343 { 33, { 0, 0}}, 2344 { UINT_MAX, { 0, 0}}, 2345 }, 2346 }, 2347 }; 2348 static const struct radv_bin_size_entry ds_size_table[][3][9] = { 2349 { 2350 // One RB / SE 2351 { 2352 // One shader engine 2353 { 0, {128, 256}}, 2354 { 2, {128, 128}}, 2355 { 4, { 64, 128}}, 2356 { 7, { 32, 128}}, 2357 { 13, { 16, 128}}, 2358 { 49, { 0, 0}}, 2359 { UINT_MAX, { 0, 0}}, 2360 }, 2361 { 2362 // Two shader engines 2363 { 0, {256, 256}}, 2364 { 2, {128, 256}}, 2365 { 4, {128, 128}}, 2366 { 7, { 64, 128}}, 2367 { 13, { 32, 128}}, 2368 { 25, { 16, 128}}, 2369 { 49, { 0, 0}}, 2370 { UINT_MAX, { 0, 0}}, 2371 }, 2372 { 2373 // Four shader engines 2374 { 0, {256, 512}}, 2375 { 2, {256, 256}}, 2376 { 4, {128, 256}}, 2377 { 7, {128, 128}}, 2378 { 13, { 64, 128}}, 2379 { 25, { 16, 128}}, 2380 { 49, { 0, 0}}, 2381 { UINT_MAX, { 0, 0}}, 2382 }, 2383 }, 2384 { 2385 // Two RB / SE 2386 { 2387 // One shader engine 2388 { 0, {256, 256}}, 2389 { 2, {128, 256}}, 2390 { 4, {128, 128}}, 2391 { 7, { 64, 128}}, 2392 { 13, { 32, 128}}, 2393 { 25, { 16, 128}}, 2394 { 97, { 0, 0}}, 2395 { UINT_MAX, { 0, 0}}, 2396 }, 2397 { 2398 // Two shader engines 2399 { 0, {256, 512}}, 2400 { 2, {256, 256}}, 2401 { 4, {128, 256}}, 2402 { 7, {128, 128}}, 2403 { 13, { 64, 128}}, 2404 { 25, { 32, 128}}, 2405 { 49, { 16, 128}}, 2406 { 97, { 0, 0}}, 2407 { UINT_MAX, { 0, 0}}, 2408 }, 2409 { 2410 // Four shader engines 2411 { 0, {512, 512}}, 2412 { 2, {256, 512}}, 2413 { 4, {256, 256}}, 2414 { 7, {128, 256}}, 2415 { 13, {128, 128}}, 2416 { 25, { 64, 128}}, 2417 { 49, { 16, 128}}, 2418 { 97, { 0, 0}}, 2419 { UINT_MAX, { 0, 0}}, 2420 }, 2421 }, 2422 { 2423 // Four RB / SE 2424 { 2425 // One shader engine 2426 { 0, {256, 512}}, 2427 { 2, {256, 256}}, 2428 { 4, {128, 256}}, 2429 { 7, {128, 128}}, 2430 { 13, { 64, 128}}, 2431 { 25, { 32, 128}}, 2432 { 49, { 16, 128}}, 2433 { UINT_MAX, { 0, 0}}, 2434 }, 2435 { 2436 // Two shader engines 2437 { 0, {512, 512}}, 2438 { 2, {256, 512}}, 2439 { 4, {256, 256}}, 2440 { 7, {128, 256}}, 2441 { 13, {128, 128}}, 2442 { 25, { 64, 128}}, 2443 { 49, { 32, 128}}, 2444 { 97, { 16, 128}}, 2445 { UINT_MAX, { 0, 0}}, 2446 }, 2447 { 2448 // Four shader engines 2449 { 0, {512, 512}}, 2450 { 4, {256, 512}}, 2451 { 7, {256, 256}}, 2452 { 13, {128, 256}}, 2453 { 25, {128, 128}}, 2454 { 49, { 64, 128}}, 2455 { 97, { 16, 128}}, 2456 { UINT_MAX, { 0, 0}}, 2457 }, 2458 }, 2459 }; 2460 2461 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 2462 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 2463 VkExtent2D extent = {512, 512}; 2464 2465 unsigned log_num_rb_per_se = 2466 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends / 2467 pipeline->device->physical_device->rad_info.max_se); 2468 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se); 2469 2470 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config); 2471 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa); 2472 unsigned effective_samples = total_samples; 2473 unsigned color_bytes_per_pixel = 0; 2474 2475 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; 2476 if (vkblend) { 2477 for (unsigned i = 0; i < subpass->color_count; i++) { 2478 if (!vkblend->pAttachments[i].colorWriteMask) 2479 continue; 2480 2481 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) 2482 continue; 2483 2484 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format; 2485 color_bytes_per_pixel += vk_format_get_blocksize(format); 2486 } 2487 2488 /* MSAA images typically don't use all samples all the time. */ 2489 if (effective_samples >= 2 && ps_iter_samples <= 1) 2490 effective_samples = 2; 2491 color_bytes_per_pixel *= effective_samples; 2492 } 2493 2494 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se]; 2495 while(color_entry[1].bpp <= color_bytes_per_pixel) 2496 ++color_entry; 2497 2498 extent = color_entry->extent; 2499 2500 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { 2501 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment; 2502 2503 /* Coefficients taken from AMDVLK */ 2504 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0; 2505 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0; 2506 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples; 2507 2508 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se]; 2509 while(ds_entry[1].bpp <= ds_bytes_per_pixel) 2510 ++ds_entry; 2511 2512 extent.width = MIN2(extent.width, ds_entry->extent.width); 2513 extent.height = MIN2(extent.height, ds_entry->extent.height); 2514 } 2515 2516 return extent; 2517} 2518 2519static void 2520radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs, 2521 struct radv_pipeline *pipeline, 2522 const VkGraphicsPipelineCreateInfo *pCreateInfo) 2523{ 2524 if (pipeline->device->physical_device->rad_info.chip_class < GFX9) 2525 return; 2526 2527 uint32_t pa_sc_binner_cntl_0 = 2528 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | 2529 S_028C44_DISABLE_START_OF_PRIM(1); 2530 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF); 2531 2532 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo); 2533 2534 unsigned context_states_per_bin; /* allowed range: [1, 6] */ 2535 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */ 2536 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ 2537 2538 switch (pipeline->device->physical_device->rad_info.family) { 2539 case CHIP_VEGA10: 2540 case CHIP_VEGA12: 2541 case CHIP_VEGA20: 2542 context_states_per_bin = 1; 2543 persistent_states_per_bin = 1; 2544 fpovs_per_batch = 63; 2545 break; 2546 case CHIP_RAVEN: 2547 case CHIP_RAVEN2: 2548 context_states_per_bin = 6; 2549 persistent_states_per_bin = 32; 2550 fpovs_per_batch = 63; 2551 break; 2552 default: 2553 unreachable("unhandled family while determining binning state."); 2554 } 2555 2556 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) { 2557 pa_sc_binner_cntl_0 = 2558 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | 2559 S_028C44_BIN_SIZE_X(bin_size.width == 16) | 2560 S_028C44_BIN_SIZE_Y(bin_size.height == 16) | 2561 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) | 2562 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) | 2563 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) | 2564 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) | 2565 S_028C44_DISABLE_START_OF_PRIM(1) | 2566 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | 2567 S_028C44_OPTIMAL_BIN_SELECTION(1); 2568 } 2569 2570 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0, 2571 pa_sc_binner_cntl_0); 2572 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, 2573 db_dfsm_control); 2574} 2575 2576 2577static void 2578radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs, 2579 struct radv_pipeline *pipeline, 2580 const VkGraphicsPipelineCreateInfo *pCreateInfo, 2581 const struct radv_graphics_pipeline_create_info *extra) 2582{ 2583 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState; 2584 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 2585 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 2586 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; 2587 struct radv_render_pass_attachment *attachment = NULL; 2588 uint32_t db_depth_control = 0, db_stencil_control = 0; 2589 uint32_t db_render_control = 0, db_render_override2 = 0; 2590 uint32_t db_render_override = 0; 2591 2592 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) 2593 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment; 2594 2595 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format); 2596 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format); 2597 2598 if (vkds && has_depth_attachment) { 2599 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) | 2600 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) | 2601 S_028800_ZFUNC(vkds->depthCompareOp) | 2602 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0); 2603 2604 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */ 2605 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2); 2606 } 2607 2608 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) { 2609 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1); 2610 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp); 2611 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp)); 2612 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp)); 2613 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp)); 2614 2615 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp); 2616 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp)); 2617 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp)); 2618 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp)); 2619 } 2620 2621 if (attachment && extra) { 2622 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); 2623 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); 2624 2625 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize); 2626 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace); 2627 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace); 2628 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear); 2629 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear); 2630 } 2631 2632 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 2633 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 2634 2635 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted && 2636 !pCreateInfo->pRasterizationState->depthClampEnable && 2637 ps->info.info.ps.writes_z) { 2638 /* From VK_EXT_depth_range_unrestricted spec: 2639 * 2640 * "The behavior described in Primitive Clipping still applies. 2641 * If depth clamping is disabled the depth values are still 2642 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If 2643 * depth clamping is enabled the above equation is ignored and 2644 * the depth values are instead clamped to the VkViewport 2645 * minDepth and maxDepth values, which in the case of this 2646 * extension can be outside of the 0.0 to 1.0 range." 2647 */ 2648 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1); 2649 } 2650 2651 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control); 2652 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 2653 2654 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control); 2655 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 2656 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2); 2657} 2658 2659static void 2660radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs, 2661 struct radv_pipeline *pipeline, 2662 const struct radv_blend_state *blend) 2663{ 2664 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8); 2665 radeon_emit_array(cs, blend->cb_blend_control, 2666 8); 2667 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control); 2668 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); 2669 2670 if (pipeline->device->physical_device->has_rbplus) { 2671 2672 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8); 2673 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8); 2674 } 2675 2676 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format); 2677 2678 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask); 2679 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask); 2680 2681 pipeline->graphics.col_format = blend->spi_shader_col_format; 2682 pipeline->graphics.cb_target_mask = blend->cb_target_mask; 2683} 2684 2685static const VkConservativeRasterizationModeEXT 2686radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo) 2687{ 2688 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster = 2689 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT); 2690 2691 if (!conservative_raster) 2692 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; 2693 return conservative_raster->conservativeRasterizationMode; 2694} 2695 2696static void 2697radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs, 2698 struct radv_pipeline *pipeline, 2699 const VkGraphicsPipelineCreateInfo *pCreateInfo) 2700{ 2701 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState; 2702 const VkConservativeRasterizationModeEXT mode = 2703 radv_get_conservative_raster_mode(vkraster); 2704 uint32_t pa_sc_conservative_rast = 0; 2705 2706 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, 2707 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions. 2708 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | 2709 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) | 2710 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) | 2711 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1)); 2712 2713 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0, 2714 S_0286D4_FLAT_SHADE_ENA(1) | 2715 S_0286D4_PNT_SPRITE_ENA(1) | 2716 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 2717 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 2718 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 2719 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | 2720 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */ 2721 2722 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL, 2723 S_028BE4_PIX_CENTER(1) | // TODO verify 2724 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) | 2725 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); 2726 2727 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, 2728 S_028814_FACE(vkraster->frontFace) | 2729 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) | 2730 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) | 2731 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) | 2732 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) | 2733 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) | 2734 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | 2735 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | 2736 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0)); 2737 2738 /* Conservative rasterization. */ 2739 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { 2740 struct radv_multisample_state *ms = &pipeline->graphics.ms; 2741 2742 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); 2743 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | 2744 S_028804_OVERRASTERIZATION_AMOUNT(4); 2745 2746 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | 2747 S_028C4C_POSTZ_AA_MASK_ENABLE(1) | 2748 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1); 2749 2750 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) { 2751 pa_sc_conservative_rast |= 2752 S_028C4C_OVER_RAST_ENABLE(1) | 2753 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) | 2754 S_028C4C_UNDER_RAST_ENABLE(0) | 2755 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) | 2756 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1); 2757 } else { 2758 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT); 2759 pa_sc_conservative_rast |= 2760 S_028C4C_OVER_RAST_ENABLE(0) | 2761 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) | 2762 S_028C4C_UNDER_RAST_ENABLE(1) | 2763 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) | 2764 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0); 2765 } 2766 } 2767 2768 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, 2769 pa_sc_conservative_rast); 2770} 2771 2772 2773static void 2774radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs, 2775 struct radv_pipeline *pipeline) 2776{ 2777 struct radv_multisample_state *ms = &pipeline->graphics.ms; 2778 2779 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); 2780 radeon_emit(cs, ms->pa_sc_aa_mask[0]); 2781 radeon_emit(cs, ms->pa_sc_aa_mask[1]); 2782 2783 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa); 2784 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); 2785 2786 /* The exclusion bits can be set to improve rasterization efficiency 2787 * if no sample lies on the pixel boundary (-8 sample offset). It's 2788 * currently always TRUE because the driver doesn't support 16 samples. 2789 */ 2790 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK; 2791 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 2792 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | 2793 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); 2794} 2795 2796static void 2797radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs, 2798 const struct radv_pipeline *pipeline) 2799{ 2800 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); 2801 2802 uint32_t vgt_primitiveid_en = false; 2803 uint32_t vgt_gs_mode = 0; 2804 2805 if (radv_pipeline_has_gs(pipeline)) { 2806 const struct radv_shader_variant *gs = 2807 pipeline->shaders[MESA_SHADER_GEOMETRY]; 2808 2809 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, 2810 pipeline->device->physical_device->rad_info.chip_class); 2811 } else if (outinfo->export_prim_id) { 2812 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A); 2813 vgt_primitiveid_en = true; 2814 } 2815 2816 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); 2817 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode); 2818} 2819 2820static void 2821radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs, 2822 struct radv_pipeline *pipeline, 2823 struct radv_shader_variant *shader) 2824{ 2825 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; 2826 2827 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); 2828 radeon_emit(cs, va >> 8); 2829 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40)); 2830 radeon_emit(cs, shader->rsrc1); 2831 radeon_emit(cs, shader->rsrc2); 2832 2833 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); 2834 unsigned clip_dist_mask, cull_dist_mask, total_mask; 2835 clip_dist_mask = outinfo->clip_dist_mask; 2836 cull_dist_mask = outinfo->cull_dist_mask; 2837 total_mask = clip_dist_mask | cull_dist_mask; 2838 bool misc_vec_ena = outinfo->writes_pointsize || 2839 outinfo->writes_layer || 2840 outinfo->writes_viewport_index; 2841 2842 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG, 2843 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1)); 2844 2845 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT, 2846 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 2847 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? 2848 V_02870C_SPI_SHADER_4COMP : 2849 V_02870C_SPI_SHADER_NONE) | 2850 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? 2851 V_02870C_SPI_SHADER_4COMP : 2852 V_02870C_SPI_SHADER_NONE) | 2853 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? 2854 V_02870C_SPI_SHADER_4COMP : 2855 V_02870C_SPI_SHADER_NONE)); 2856 2857 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL, 2858 S_028818_VTX_W0_FMT(1) | 2859 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 2860 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 2861 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); 2862 2863 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, 2864 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | 2865 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | 2866 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) | 2867 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) | 2868 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | 2869 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | 2870 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | 2871 cull_dist_mask << 8 | 2872 clip_dist_mask); 2873 2874 if (pipeline->device->physical_device->rad_info.chip_class <= VI) 2875 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 2876 outinfo->writes_viewport_index); 2877} 2878 2879static void 2880radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, 2881 struct radv_pipeline *pipeline, 2882 struct radv_shader_variant *shader) 2883{ 2884 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; 2885 2886 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); 2887 radeon_emit(cs, va >> 8); 2888 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); 2889 radeon_emit(cs, shader->rsrc1); 2890 radeon_emit(cs, shader->rsrc2); 2891} 2892 2893static void 2894radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, 2895 struct radv_pipeline *pipeline, 2896 struct radv_shader_variant *shader, 2897 const struct radv_tessellation_state *tess) 2898{ 2899 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; 2900 uint32_t rsrc2 = shader->rsrc2; 2901 2902 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); 2903 radeon_emit(cs, va >> 8); 2904 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40)); 2905 2906 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size); 2907 if (pipeline->device->physical_device->rad_info.chip_class == CIK && 2908 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII) 2909 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); 2910 2911 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); 2912 radeon_emit(cs, shader->rsrc1); 2913 radeon_emit(cs, rsrc2); 2914} 2915 2916static void 2917radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, 2918 struct radv_pipeline *pipeline, 2919 struct radv_shader_variant *shader, 2920 const struct radv_tessellation_state *tess) 2921{ 2922 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; 2923 2924 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { 2925 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2); 2926 radeon_emit(cs, va >> 8); 2927 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40)); 2928 2929 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); 2930 radeon_emit(cs, shader->rsrc1); 2931 radeon_emit(cs, shader->rsrc2 | 2932 S_00B42C_LDS_SIZE(tess->lds_size)); 2933 } else { 2934 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); 2935 radeon_emit(cs, va >> 8); 2936 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40)); 2937 radeon_emit(cs, shader->rsrc1); 2938 radeon_emit(cs, shader->rsrc2); 2939 } 2940} 2941 2942static void 2943radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs, 2944 struct radv_pipeline *pipeline, 2945 const struct radv_tessellation_state *tess) 2946{ 2947 struct radv_shader_variant *vs; 2948 2949 /* Skip shaders merged into HS/GS */ 2950 vs = pipeline->shaders[MESA_SHADER_VERTEX]; 2951 if (!vs) 2952 return; 2953 2954 if (vs->info.vs.as_ls) 2955 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess); 2956 else if (vs->info.vs.as_es) 2957 radv_pipeline_generate_hw_es(cs, pipeline, vs); 2958 else 2959 radv_pipeline_generate_hw_vs(cs, pipeline, vs); 2960} 2961 2962static void 2963radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs, 2964 struct radv_pipeline *pipeline, 2965 const struct radv_tessellation_state *tess) 2966{ 2967 if (!radv_pipeline_has_tess(pipeline)) 2968 return; 2969 2970 struct radv_shader_variant *tes, *tcs; 2971 2972 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL]; 2973 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL]; 2974 2975 if (tes) { 2976 if (tes->info.tes.as_es) 2977 radv_pipeline_generate_hw_es(cs, pipeline, tes); 2978 else 2979 radv_pipeline_generate_hw_vs(cs, pipeline, tes); 2980 } 2981 2982 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess); 2983 2984 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, 2985 tess->tf_param); 2986 2987 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) 2988 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, 2989 tess->ls_hs_config); 2990 else 2991 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, 2992 tess->ls_hs_config); 2993} 2994 2995static void 2996radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs, 2997 struct radv_pipeline *pipeline, 2998 const struct radv_gs_state *gs_state) 2999{ 3000 struct radv_shader_variant *gs; 3001 unsigned gs_max_out_vertices; 3002 uint8_t *num_components; 3003 uint8_t max_stream; 3004 unsigned offset; 3005 uint64_t va; 3006 3007 gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; 3008 if (!gs) 3009 return; 3010 3011 gs_max_out_vertices = gs->info.gs.vertices_out; 3012 max_stream = gs->info.info.gs.max_stream; 3013 num_components = gs->info.info.gs.num_stream_output_components; 3014 3015 offset = num_components[0] * gs_max_out_vertices; 3016 3017 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); 3018 radeon_emit(cs, offset); 3019 if (max_stream >= 1) 3020 offset += num_components[1] * gs_max_out_vertices; 3021 radeon_emit(cs, offset); 3022 if (max_stream >= 2) 3023 offset += num_components[2] * gs_max_out_vertices; 3024 radeon_emit(cs, offset); 3025 if (max_stream >= 3) 3026 offset += num_components[3] * gs_max_out_vertices; 3027 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); 3028 3029 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out); 3030 3031 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); 3032 radeon_emit(cs, num_components[0]); 3033 radeon_emit(cs, (max_stream >= 1) ? num_components[1] : 0); 3034 radeon_emit(cs, (max_stream >= 2) ? num_components[2] : 0); 3035 radeon_emit(cs, (max_stream >= 3) ? num_components[3] : 0); 3036 3037 uint32_t gs_num_invocations = gs->info.gs.invocations; 3038 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT, 3039 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | 3040 S_028B90_ENABLE(gs_num_invocations > 0)); 3041 3042 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 3043 gs_state->vgt_esgs_ring_itemsize); 3044 3045 va = radv_buffer_get_va(gs->bo) + gs->bo_offset; 3046 3047 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { 3048 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2); 3049 radeon_emit(cs, va >> 8); 3050 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40)); 3051 3052 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); 3053 radeon_emit(cs, gs->rsrc1); 3054 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size)); 3055 3056 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl); 3057 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup); 3058 } else { 3059 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4); 3060 radeon_emit(cs, va >> 8); 3061 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40)); 3062 radeon_emit(cs, gs->rsrc1); 3063 radeon_emit(cs, gs->rsrc2); 3064 } 3065 3066 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader); 3067} 3068 3069static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade) 3070{ 3071 uint32_t ps_input_cntl; 3072 if (offset <= AC_EXP_PARAM_OFFSET_31) { 3073 ps_input_cntl = S_028644_OFFSET(offset); 3074 if (flat_shade) 3075 ps_input_cntl |= S_028644_FLAT_SHADE(1); 3076 } else { 3077 /* The input is a DEFAULT_VAL constant. */ 3078 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 && 3079 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111); 3080 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000; 3081 ps_input_cntl = S_028644_OFFSET(0x20) | 3082 S_028644_DEFAULT_VAL(offset); 3083 } 3084 return ps_input_cntl; 3085} 3086 3087static void 3088radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs, 3089 struct radv_pipeline *pipeline) 3090{ 3091 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; 3092 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); 3093 uint32_t ps_input_cntl[32]; 3094 3095 unsigned ps_offset = 0; 3096 3097 if (ps->info.info.ps.prim_id_input) { 3098 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID]; 3099 if (vs_offset != AC_EXP_PARAM_UNDEFINED) { 3100 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true); 3101 ++ps_offset; 3102 } 3103 } 3104 3105 if (ps->info.info.ps.layer_input || 3106 ps->info.info.ps.uses_input_attachments || 3107 ps->info.info.needs_multiview_view_index) { 3108 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER]; 3109 if (vs_offset != AC_EXP_PARAM_UNDEFINED) 3110 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true); 3111 else 3112 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true); 3113 ++ps_offset; 3114 } 3115 3116 if (ps->info.info.ps.has_pcoord) { 3117 unsigned val; 3118 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20); 3119 ps_input_cntl[ps_offset] = val; 3120 ps_offset++; 3121 } 3122 3123 if (ps->info.info.ps.num_input_clips_culls) { 3124 unsigned vs_offset; 3125 3126 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0]; 3127 if (vs_offset != AC_EXP_PARAM_UNDEFINED) { 3128 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false); 3129 ++ps_offset; 3130 } 3131 3132 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1]; 3133 if (vs_offset != AC_EXP_PARAM_UNDEFINED && 3134 ps->info.info.ps.num_input_clips_culls > 4) { 3135 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false); 3136 ++ps_offset; 3137 } 3138 } 3139 3140 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) { 3141 unsigned vs_offset; 3142 bool flat_shade; 3143 if (!(ps->info.fs.input_mask & (1u << i))) 3144 continue; 3145 3146 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i]; 3147 if (vs_offset == AC_EXP_PARAM_UNDEFINED) { 3148 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20); 3149 ++ps_offset; 3150 continue; 3151 } 3152 3153 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset)); 3154 3155 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade); 3156 ++ps_offset; 3157 } 3158 3159 if (ps_offset) { 3160 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset); 3161 for (unsigned i = 0; i < ps_offset; i++) { 3162 radeon_emit(cs, ps_input_cntl[i]); 3163 } 3164 } 3165} 3166 3167static uint32_t 3168radv_compute_db_shader_control(const struct radv_device *device, 3169 const struct radv_pipeline *pipeline, 3170 const struct radv_shader_variant *ps) 3171{ 3172 const struct radv_multisample_state *ms = &pipeline->graphics.ms; 3173 unsigned z_order; 3174 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory) 3175 z_order = V_02880C_EARLY_Z_THEN_LATE_Z; 3176 else 3177 z_order = V_02880C_LATE_Z; 3178 3179 bool disable_rbplus = device->physical_device->has_rbplus && 3180 !device->physical_device->rbplus_allowed; 3181 3182 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled 3183 * but this appears to break Project Cars (DXVK). See 3184 * https://bugs.freedesktop.org/show_bug.cgi?id=109401 3185 */ 3186 bool mask_export_enable = ps->info.info.ps.writes_sample_mask; 3187 3188 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) | 3189 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) | 3190 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | 3191 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) | 3192 S_02880C_Z_ORDER(z_order) | 3193 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | 3194 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) | 3195 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) | 3196 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus); 3197} 3198 3199static void 3200radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs, 3201 struct radv_pipeline *pipeline) 3202{ 3203 struct radv_shader_variant *ps; 3204 uint64_t va; 3205 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); 3206 3207 ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; 3208 va = radv_buffer_get_va(ps->bo) + ps->bo_offset; 3209 3210 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4); 3211 radeon_emit(cs, va >> 8); 3212 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40)); 3213 radeon_emit(cs, ps->rsrc1); 3214 radeon_emit(cs, ps->rsrc2); 3215 3216 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, 3217 radv_compute_db_shader_control(pipeline->device, 3218 pipeline, ps)); 3219 3220 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA, 3221 ps->config.spi_ps_input_ena); 3222 3223 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR, 3224 ps->config.spi_ps_input_addr); 3225 3226 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL, 3227 S_0286D8_NUM_INTERP(ps->info.fs.num_interp)); 3228 3229 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); 3230 3231 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT, 3232 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z, 3233 ps->info.info.ps.writes_stencil, 3234 ps->info.info.ps.writes_sample_mask)); 3235 3236 if (pipeline->device->dfsm_allowed) { 3237 /* optimise this? */ 3238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 3239 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0)); 3240 } 3241} 3242 3243static void 3244radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs, 3245 struct radv_pipeline *pipeline) 3246{ 3247 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10) 3248 return; 3249 3250 unsigned vtx_reuse_depth = 30; 3251 if (radv_pipeline_has_tess(pipeline) && 3252 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) { 3253 vtx_reuse_depth = 14; 3254 } 3255 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 3256 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth)); 3257} 3258 3259static uint32_t 3260radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline) 3261{ 3262 uint32_t stages = 0; 3263 if (radv_pipeline_has_tess(pipeline)) { 3264 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | 3265 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1); 3266 3267 if (radv_pipeline_has_gs(pipeline)) 3268 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) | 3269 S_028B54_GS_EN(1) | 3270 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 3271 else 3272 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); 3273 3274 } else if (radv_pipeline_has_gs(pipeline)) 3275 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | 3276 S_028B54_GS_EN(1) | 3277 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 3278 3279 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) 3280 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); 3281 3282 return stages; 3283} 3284 3285static uint32_t 3286radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo) 3287{ 3288 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = 3289 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT); 3290 3291 if (!discard_rectangle_info) 3292 return 0xffff; 3293 3294 unsigned mask = 0; 3295 3296 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) { 3297 /* Interpret i as a bitmask, and then set the bit in the mask if 3298 * that combination of rectangles in which the pixel is contained 3299 * should pass the cliprect test. */ 3300 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1); 3301 3302 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && 3303 !relevant_subset) 3304 continue; 3305 3306 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && 3307 relevant_subset) 3308 continue; 3309 3310 mask |= 1u << i; 3311 } 3312 3313 return mask; 3314} 3315 3316static void 3317radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, 3318 const VkGraphicsPipelineCreateInfo *pCreateInfo, 3319 const struct radv_graphics_pipeline_create_info *extra, 3320 const struct radv_blend_state *blend, 3321 const struct radv_tessellation_state *tess, 3322 const struct radv_gs_state *gs, 3323 unsigned prim, unsigned gs_out) 3324{ 3325 pipeline->cs.buf = malloc(4 * 256); 3326 pipeline->cs.max_dw = 256; 3327 3328 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra); 3329 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend); 3330 radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo); 3331 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline); 3332 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline); 3333 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess); 3334 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess); 3335 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs); 3336 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline); 3337 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline); 3338 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline); 3339 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo); 3340 3341 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE, 3342 S_0286E8_WAVES(pipeline->max_waves) | 3343 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10)); 3344 3345 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline)); 3346 3347 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) { 3348 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); 3349 } else { 3350 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim); 3351 } 3352 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); 3353 3354 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo)); 3355 3356 assert(pipeline->cs.cdw <= pipeline->cs.max_dw); 3357} 3358 3359static struct radv_ia_multi_vgt_param_helpers 3360radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, 3361 const struct radv_tessellation_state *tess, 3362 uint32_t prim) 3363{ 3364 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0}; 3365 const struct radv_device *device = pipeline->device; 3366 3367 if (radv_pipeline_has_tess(pipeline)) 3368 ia_multi_vgt_param.primgroup_size = tess->num_patches; 3369 else if (radv_pipeline_has_gs(pipeline)) 3370 ia_multi_vgt_param.primgroup_size = 64; 3371 else 3372 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */ 3373 3374 /* GS requirement. */ 3375 ia_multi_vgt_param.partial_es_wave = false; 3376 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI) 3377 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3) 3378 ia_multi_vgt_param.partial_es_wave = true; 3379 3380 ia_multi_vgt_param.wd_switch_on_eop = false; 3381 if (device->physical_device->rad_info.chip_class >= CIK) { 3382 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than 3383 * 4 shader engines. Set 1 to pass the assertion below. 3384 * The other cases are hardware requirements. */ 3385 if (device->physical_device->rad_info.max_se < 4 || 3386 prim == V_008958_DI_PT_POLYGON || 3387 prim == V_008958_DI_PT_LINELOOP || 3388 prim == V_008958_DI_PT_TRIFAN || 3389 prim == V_008958_DI_PT_TRISTRIP_ADJ || 3390 (pipeline->graphics.prim_restart_enable && 3391 (device->physical_device->rad_info.family < CHIP_POLARIS10 || 3392 (prim != V_008958_DI_PT_POINTLIST && 3393 prim != V_008958_DI_PT_LINESTRIP)))) 3394 ia_multi_vgt_param.wd_switch_on_eop = true; 3395 } 3396 3397 ia_multi_vgt_param.ia_switch_on_eoi = false; 3398 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input) 3399 ia_multi_vgt_param.ia_switch_on_eoi = true; 3400 if (radv_pipeline_has_gs(pipeline) && 3401 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id) 3402 ia_multi_vgt_param.ia_switch_on_eoi = true; 3403 if (radv_pipeline_has_tess(pipeline)) { 3404 /* SWITCH_ON_EOI must be set if PrimID is used. */ 3405 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id || 3406 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id) 3407 ia_multi_vgt_param.ia_switch_on_eoi = true; 3408 } 3409 3410 ia_multi_vgt_param.partial_vs_wave = false; 3411 if (radv_pipeline_has_tess(pipeline)) { 3412 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */ 3413 if ((device->physical_device->rad_info.family == CHIP_TAHITI || 3414 device->physical_device->rad_info.family == CHIP_PITCAIRN || 3415 device->physical_device->rad_info.family == CHIP_BONAIRE) && 3416 radv_pipeline_has_gs(pipeline)) 3417 ia_multi_vgt_param.partial_vs_wave = true; 3418 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ 3419 if (device->has_distributed_tess) { 3420 if (radv_pipeline_has_gs(pipeline)) { 3421 if (device->physical_device->rad_info.chip_class <= VI) 3422 ia_multi_vgt_param.partial_es_wave = true; 3423 } else { 3424 ia_multi_vgt_param.partial_vs_wave = true; 3425 } 3426 } 3427 } 3428 3429 /* Workaround for a VGT hang when strip primitive types are used with 3430 * primitive restart. 3431 */ 3432 if (pipeline->graphics.prim_restart_enable && 3433 (prim == V_008958_DI_PT_LINESTRIP || 3434 prim == V_008958_DI_PT_TRISTRIP || 3435 prim == V_008958_DI_PT_LINESTRIP_ADJ || 3436 prim == V_008958_DI_PT_TRISTRIP_ADJ)) { 3437 ia_multi_vgt_param.partial_vs_wave = true; 3438 } 3439 3440 if (radv_pipeline_has_gs(pipeline)) { 3441 /* On these chips there is the possibility of a hang if the 3442 * pipeline uses a GS and partial_vs_wave is not set. 3443 * 3444 * This mostly does not hit 4-SE chips, as those typically set 3445 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines 3446 * with GS due to another workaround. 3447 * 3448 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242 3449 */ 3450 if (device->physical_device->rad_info.family == CHIP_TONGA || 3451 device->physical_device->rad_info.family == CHIP_FIJI || 3452 device->physical_device->rad_info.family == CHIP_POLARIS10 || 3453 device->physical_device->rad_info.family == CHIP_POLARIS11 || 3454 device->physical_device->rad_info.family == CHIP_POLARIS12 || 3455 device->physical_device->rad_info.family == CHIP_VEGAM) { 3456 ia_multi_vgt_param.partial_vs_wave = true; 3457 } 3458 } 3459 3460 ia_multi_vgt_param.base = 3461 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) | 3462 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ 3463 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) | 3464 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) | 3465 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9); 3466 3467 return ia_multi_vgt_param; 3468} 3469 3470 3471static void 3472radv_compute_vertex_input_state(struct radv_pipeline *pipeline, 3473 const VkGraphicsPipelineCreateInfo *pCreateInfo) 3474{ 3475 const VkPipelineVertexInputStateCreateInfo *vi_info = 3476 pCreateInfo->pVertexInputState; 3477 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements; 3478 3479 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) { 3480 const VkVertexInputAttributeDescription *desc = 3481 &vi_info->pVertexAttributeDescriptions[i]; 3482 unsigned loc = desc->location; 3483 const struct vk_format_description *format_desc; 3484 int first_non_void; 3485 uint32_t num_format, data_format; 3486 format_desc = vk_format_description(desc->format); 3487 first_non_void = vk_format_get_first_non_void_channel(desc->format); 3488 3489 num_format = radv_translate_buffer_numformat(format_desc, first_non_void); 3490 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void); 3491 3492 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) | 3493 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) | 3494 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) | 3495 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) | 3496 S_008F0C_NUM_FORMAT(num_format) | 3497 S_008F0C_DATA_FORMAT(data_format); 3498 velems->format_size[loc] = format_desc->block.bits / 8; 3499 velems->offset[loc] = desc->offset; 3500 velems->binding[loc] = desc->binding; 3501 velems->count = MAX2(velems->count, loc + 1); 3502 } 3503 3504 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) { 3505 const VkVertexInputBindingDescription *desc = 3506 &vi_info->pVertexBindingDescriptions[i]; 3507 3508 pipeline->binding_stride[desc->binding] = desc->stride; 3509 } 3510} 3511 3512static struct radv_shader_variant * 3513radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline) 3514{ 3515 int i; 3516 3517 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) { 3518 struct radv_shader_variant *shader = 3519 radv_get_shader(pipeline, i); 3520 3521 if (shader && shader->info.info.so.num_outputs > 0) 3522 return shader; 3523 } 3524 3525 return NULL; 3526} 3527 3528static VkResult 3529radv_pipeline_init(struct radv_pipeline *pipeline, 3530 struct radv_device *device, 3531 struct radv_pipeline_cache *cache, 3532 const VkGraphicsPipelineCreateInfo *pCreateInfo, 3533 const struct radv_graphics_pipeline_create_info *extra, 3534 const VkAllocationCallbacks *alloc) 3535{ 3536 VkResult result; 3537 bool has_view_index = false; 3538 3539 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); 3540 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; 3541 if (subpass->view_mask) 3542 has_view_index = true; 3543 if (alloc == NULL) 3544 alloc = &device->alloc; 3545 3546 pipeline->device = device; 3547 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); 3548 assert(pipeline->layout); 3549 3550 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); 3551 3552 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; 3553 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { 3554 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1; 3555 pStages[stage] = &pCreateInfo->pStages[i]; 3556 } 3557 3558 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index); 3559 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags); 3560 3561 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); 3562 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo); 3563 uint32_t gs_out; 3564 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology); 3565 3566 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology); 3567 3568 if (radv_pipeline_has_gs(pipeline)) { 3569 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); 3570 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP; 3571 } else { 3572 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); 3573 } 3574 if (extra && extra->use_rectlist) { 3575 prim = V_008958_DI_PT_RECTLIST; 3576 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; 3577 pipeline->graphics.can_use_guardband = true; 3578 } 3579 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable; 3580 /* prim vertex count will need TESS changes */ 3581 pipeline->graphics.prim_vertex_count = prim_size_table[prim]; 3582 3583 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); 3584 3585 /* Ensure that some export memory is always allocated, for two reasons: 3586 * 3587 * 1) Correctness: The hardware ignores the EXEC mask if no export 3588 * memory is allocated, so KILL and alpha test do not work correctly 3589 * without this. 3590 * 2) Performance: Every shader needs at least a NULL export, even when 3591 * it writes no color/depth output. The NULL export instruction 3592 * stalls without this setting. 3593 * 3594 * Don't add this to CB_SHADER_MASK. 3595 */ 3596 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; 3597 if (!blend.spi_shader_col_format) { 3598 if (!ps->info.info.ps.writes_z && 3599 !ps->info.info.ps.writes_stencil && 3600 !ps->info.info.ps.writes_sample_mask) 3601 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; 3602 } 3603 3604 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { 3605 if (pipeline->shaders[i]) { 3606 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets; 3607 } 3608 } 3609 3610 struct radv_gs_state gs = {0}; 3611 if (radv_pipeline_has_gs(pipeline)) { 3612 gs = calculate_gs_info(pCreateInfo, pipeline); 3613 calculate_gs_ring_sizes(pipeline, &gs); 3614 } 3615 3616 struct radv_tessellation_state tess = {0}; 3617 if (radv_pipeline_has_tess(pipeline)) { 3618 if (prim == V_008958_DI_PT_PATCH) { 3619 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints; 3620 pipeline->graphics.prim_vertex_count.incr = 1; 3621 } 3622 tess = calculate_tess_state(pipeline, pCreateInfo); 3623 } 3624 3625 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim); 3626 3627 radv_compute_vertex_input_state(pipeline, pCreateInfo); 3628 3629 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) 3630 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class); 3631 3632 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, 3633 AC_UD_VS_BASE_VERTEX_START_INSTANCE); 3634 if (loc->sgpr_idx != -1) { 3635 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX]; 3636 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; 3637 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id) 3638 pipeline->graphics.vtx_emit_num = 3; 3639 else 3640 pipeline->graphics.vtx_emit_num = 2; 3641 } 3642 3643 /* Find the last vertex shader stage that eventually uses streamout. */ 3644 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline); 3645 3646 result = radv_pipeline_scratch_init(device, pipeline); 3647 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out); 3648 3649 return result; 3650} 3651 3652VkResult 3653radv_graphics_pipeline_create( 3654 VkDevice _device, 3655 VkPipelineCache _cache, 3656 const VkGraphicsPipelineCreateInfo *pCreateInfo, 3657 const struct radv_graphics_pipeline_create_info *extra, 3658 const VkAllocationCallbacks *pAllocator, 3659 VkPipeline *pPipeline) 3660{ 3661 RADV_FROM_HANDLE(radv_device, device, _device); 3662 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); 3663 struct radv_pipeline *pipeline; 3664 VkResult result; 3665 3666 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, 3667 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 3668 if (pipeline == NULL) 3669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); 3670 3671 result = radv_pipeline_init(pipeline, device, cache, 3672 pCreateInfo, extra, pAllocator); 3673 if (result != VK_SUCCESS) { 3674 radv_pipeline_destroy(device, pipeline, pAllocator); 3675 return result; 3676 } 3677 3678 *pPipeline = radv_pipeline_to_handle(pipeline); 3679 3680 return VK_SUCCESS; 3681} 3682 3683VkResult radv_CreateGraphicsPipelines( 3684 VkDevice _device, 3685 VkPipelineCache pipelineCache, 3686 uint32_t count, 3687 const VkGraphicsPipelineCreateInfo* pCreateInfos, 3688 const VkAllocationCallbacks* pAllocator, 3689 VkPipeline* pPipelines) 3690{ 3691 VkResult result = VK_SUCCESS; 3692 unsigned i = 0; 3693 3694 for (; i < count; i++) { 3695 VkResult r; 3696 r = radv_graphics_pipeline_create(_device, 3697 pipelineCache, 3698 &pCreateInfos[i], 3699 NULL, pAllocator, &pPipelines[i]); 3700 if (r != VK_SUCCESS) { 3701 result = r; 3702 pPipelines[i] = VK_NULL_HANDLE; 3703 } 3704 } 3705 3706 return result; 3707} 3708 3709 3710static void 3711radv_compute_generate_pm4(struct radv_pipeline *pipeline) 3712{ 3713 struct radv_shader_variant *compute_shader; 3714 struct radv_device *device = pipeline->device; 3715 unsigned compute_resource_limits; 3716 unsigned waves_per_threadgroup; 3717 uint64_t va; 3718 3719 pipeline->cs.buf = malloc(20 * 4); 3720 pipeline->cs.max_dw = 20; 3721 3722 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; 3723 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset; 3724 3725 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2); 3726 radeon_emit(&pipeline->cs, va >> 8); 3727 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40)); 3728 3729 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2); 3730 radeon_emit(&pipeline->cs, compute_shader->rsrc1); 3731 radeon_emit(&pipeline->cs, compute_shader->rsrc2); 3732 3733 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE, 3734 S_00B860_WAVES(pipeline->max_waves) | 3735 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10)); 3736 3737 /* Calculate best compute resource limits. */ 3738 waves_per_threadgroup = 3739 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] * 3740 compute_shader->info.cs.block_size[1] * 3741 compute_shader->info.cs.block_size[2], 64); 3742 compute_resource_limits = 3743 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0); 3744 3745 if (device->physical_device->rad_info.chip_class >= CIK) { 3746 unsigned num_cu_per_se = 3747 device->physical_device->rad_info.num_good_compute_units / 3748 device->physical_device->rad_info.max_se; 3749 3750 /* Force even distribution on all SIMDs in CU if the workgroup 3751 * size is 64. This has shown some good improvements if # of 3752 * CUs per SE is not a multiple of 4. 3753 */ 3754 if (num_cu_per_se % 4 && waves_per_threadgroup == 1) 3755 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1); 3756 } 3757 3758 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3759 compute_resource_limits); 3760 3761 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); 3762 radeon_emit(&pipeline->cs, 3763 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0])); 3764 radeon_emit(&pipeline->cs, 3765 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1])); 3766 radeon_emit(&pipeline->cs, 3767 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2])); 3768 3769 assert(pipeline->cs.cdw <= pipeline->cs.max_dw); 3770} 3771 3772static VkResult radv_compute_pipeline_create( 3773 VkDevice _device, 3774 VkPipelineCache _cache, 3775 const VkComputePipelineCreateInfo* pCreateInfo, 3776 const VkAllocationCallbacks* pAllocator, 3777 VkPipeline* pPipeline) 3778{ 3779 RADV_FROM_HANDLE(radv_device, device, _device); 3780 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache); 3781 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; 3782 struct radv_pipeline *pipeline; 3783 VkResult result; 3784 3785 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, 3786 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 3787 if (pipeline == NULL) 3788 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); 3789 3790 pipeline->device = device; 3791 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); 3792 assert(pipeline->layout); 3793 3794 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage; 3795 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags); 3796 3797 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class); 3798 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets; 3799 result = radv_pipeline_scratch_init(device, pipeline); 3800 if (result != VK_SUCCESS) { 3801 radv_pipeline_destroy(device, pipeline, pAllocator); 3802 return result; 3803 } 3804 3805 radv_compute_generate_pm4(pipeline); 3806 3807 *pPipeline = radv_pipeline_to_handle(pipeline); 3808 3809 return VK_SUCCESS; 3810} 3811 3812VkResult radv_CreateComputePipelines( 3813 VkDevice _device, 3814 VkPipelineCache pipelineCache, 3815 uint32_t count, 3816 const VkComputePipelineCreateInfo* pCreateInfos, 3817 const VkAllocationCallbacks* pAllocator, 3818 VkPipeline* pPipelines) 3819{ 3820 VkResult result = VK_SUCCESS; 3821 3822 unsigned i = 0; 3823 for (; i < count; i++) { 3824 VkResult r; 3825 r = radv_compute_pipeline_create(_device, pipelineCache, 3826 &pCreateInfos[i], 3827 pAllocator, &pPipelines[i]); 3828 if (r != VK_SUCCESS) { 3829 result = r; 3830 pPipelines[i] = VK_NULL_HANDLE; 3831 } 3832 } 3833 3834 return result; 3835} 3836