radv_radeon_winsys.h revision 01e04c3f 
1/*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 */
28
29#ifndef RADV_RADEON_WINSYS_H
30#define RADV_RADEON_WINSYS_H
31
32#include <stdio.h>
33#include <stdint.h>
34#include <stdbool.h>
35#include <stdlib.h>
36#include "main/macros.h"
37#include "amd_family.h"
38
39struct radeon_info;
40struct ac_surf_info;
41struct radeon_surf;
42
43#define FREE(x) free(x)
44
45enum radeon_bo_domain { /* bitfield */
46	RADEON_DOMAIN_GTT  = 2,
47	RADEON_DOMAIN_VRAM = 4,
48	RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
49};
50
51enum radeon_bo_flag { /* bitfield */
52	RADEON_FLAG_GTT_WC =        (1 << 0),
53	RADEON_FLAG_CPU_ACCESS =    (1 << 1),
54	RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
55	RADEON_FLAG_VIRTUAL =       (1 << 3),
56	RADEON_FLAG_VA_UNCACHED =   (1 << 4),
57	RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
58	RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
59	RADEON_FLAG_READ_ONLY =     (1 << 7),
60	RADEON_FLAG_32BIT =         (1 << 8),
61};
62
63enum radeon_bo_usage { /* bitfield */
64	RADEON_USAGE_READ = 2,
65	RADEON_USAGE_WRITE = 4,
66	RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
67};
68
69enum ring_type {
70	RING_GFX = 0,
71	RING_COMPUTE,
72	RING_DMA,
73	RING_UVD,
74	RING_VCE,
75	RING_LAST,
76};
77
78enum radeon_ctx_priority {
79	RADEON_CTX_PRIORITY_INVALID = -1,
80	RADEON_CTX_PRIORITY_LOW = 0,
81	RADEON_CTX_PRIORITY_MEDIUM,
82	RADEON_CTX_PRIORITY_HIGH,
83	RADEON_CTX_PRIORITY_REALTIME,
84};
85
86enum radeon_value_id {
87	RADEON_TIMESTAMP,
88	RADEON_NUM_BYTES_MOVED,
89	RADEON_NUM_EVICTIONS,
90	RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
91	RADEON_VRAM_USAGE,
92	RADEON_VRAM_VIS_USAGE,
93	RADEON_GTT_USAGE,
94	RADEON_GPU_TEMPERATURE,
95	RADEON_CURRENT_SCLK,
96	RADEON_CURRENT_MCLK,
97};
98
99struct radeon_cmdbuf {
100	unsigned cdw;  /* Number of used dwords. */
101	unsigned max_dw; /* Maximum number of dwords. */
102	uint32_t *buf; /* The base pointer of the chunk. */
103};
104
105#define RADEON_SURF_TYPE_MASK                   0xFF
106#define RADEON_SURF_TYPE_SHIFT                  0
107#define     RADEON_SURF_TYPE_1D                     0
108#define     RADEON_SURF_TYPE_2D                     1
109#define     RADEON_SURF_TYPE_3D                     2
110#define     RADEON_SURF_TYPE_CUBEMAP                3
111#define     RADEON_SURF_TYPE_1D_ARRAY               4
112#define     RADEON_SURF_TYPE_2D_ARRAY               5
113#define RADEON_SURF_MODE_MASK                   0xFF
114#define RADEON_SURF_MODE_SHIFT                  8
115
116#define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
117#define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
118#define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
119
120enum radeon_bo_layout {
121	RADEON_LAYOUT_LINEAR = 0,
122	RADEON_LAYOUT_TILED,
123	RADEON_LAYOUT_SQUARETILED,
124
125	RADEON_LAYOUT_UNKNOWN
126};
127
128/* Tiling info for display code, DRI sharing, and other data. */
129struct radeon_bo_metadata {
130	/* Tiling flags describing the texture layout for display code
131	 * and DRI sharing.
132	 */
133	union {
134		struct {
135			enum radeon_bo_layout   microtile;
136			enum radeon_bo_layout   macrotile;
137			unsigned                pipe_config;
138			unsigned                bankw;
139			unsigned                bankh;
140			unsigned                tile_split;
141			unsigned                mtilea;
142			unsigned                num_banks;
143			unsigned                stride;
144			bool                    scanout;
145		} legacy;
146
147		struct {
148			/* surface flags */
149			unsigned swizzle_mode:5;
150		} gfx9;
151	} u;
152
153	/* Additional metadata associated with the buffer, in bytes.
154	 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
155	 * Supported by amdgpu only.
156	 */
157	uint32_t                size_metadata;
158	uint32_t                metadata[64];
159};
160
161uint32_t syncobj_handle;
162struct radeon_winsys_fence;
163
164struct radeon_winsys_bo {
165	uint64_t va;
166	bool is_local;
167};
168struct radv_winsys_sem_counts {
169	uint32_t syncobj_count;
170	uint32_t sem_count;
171	uint32_t *syncobj;
172	struct radeon_winsys_sem **sem;
173};
174
175struct radv_winsys_sem_info {
176	bool cs_emit_signal;
177	bool cs_emit_wait;
178	struct radv_winsys_sem_counts wait;
179	struct radv_winsys_sem_counts signal;
180};
181
182struct radv_winsys_bo_list {
183	struct radeon_winsys_bo **bos;
184	unsigned count;
185};
186
187struct radeon_winsys {
188	void (*destroy)(struct radeon_winsys *ws);
189
190	void (*query_info)(struct radeon_winsys *ws,
191			   struct radeon_info *info);
192
193	uint64_t (*query_value)(struct radeon_winsys *ws,
194				enum radeon_value_id value);
195
196	bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
197			       unsigned num_registers, uint32_t *out);
198
199	const char *(*get_chip_name)(struct radeon_winsys *ws);
200
201	struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
202						  uint64_t size,
203						  unsigned alignment,
204						  enum radeon_bo_domain domain,
205						  enum radeon_bo_flag flags);
206
207	void (*buffer_destroy)(struct radeon_winsys_bo *bo);
208	void *(*buffer_map)(struct radeon_winsys_bo *bo);
209
210	struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
211						    void *pointer,
212						    uint64_t size);
213
214	struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
215						   int fd,
216						   unsigned *stride, unsigned *offset);
217
218	bool (*buffer_get_fd)(struct radeon_winsys *ws,
219			      struct radeon_winsys_bo *bo,
220			      int *fd);
221
222	void (*buffer_unmap)(struct radeon_winsys_bo *bo);
223
224	void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
225				    struct radeon_bo_metadata *md);
226	void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
227				    struct radeon_bo_metadata *md);
228
229	void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
230	                            uint64_t offset, uint64_t size,
231	                            struct radeon_winsys_bo *bo, uint64_t bo_offset);
232	struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
233						enum radeon_ctx_priority priority);
234	void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
235
236	bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
237	                      enum ring_type ring_type, int ring_index);
238
239	struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
240					      enum ring_type ring_type);
241
242	void (*cs_destroy)(struct radeon_cmdbuf *cs);
243
244	void (*cs_reset)(struct radeon_cmdbuf *cs);
245
246	bool (*cs_finalize)(struct radeon_cmdbuf *cs);
247
248	void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
249
250	int (*cs_submit)(struct radeon_winsys_ctx *ctx,
251			 int queue_index,
252			 struct radeon_cmdbuf **cs_array,
253			 unsigned cs_count,
254			 struct radeon_cmdbuf *initial_preamble_cs,
255			 struct radeon_cmdbuf *continue_preamble_cs,
256			 struct radv_winsys_sem_info *sem_info,
257			 const struct radv_winsys_bo_list *bo_list, /* optional */
258			 bool can_patch,
259			 struct radeon_winsys_fence *fence);
260
261	void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
262			      struct radeon_winsys_bo *bo);
263
264	void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
265				    struct radeon_cmdbuf *child);
266
267	void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
268
269	int (*surface_init)(struct radeon_winsys *ws,
270			    const struct ac_surf_info *surf_info,
271			    struct radeon_surf *surf);
272
273	struct radeon_winsys_fence *(*create_fence)();
274	void (*destroy_fence)(struct radeon_winsys_fence *fence);
275	bool (*fence_wait)(struct radeon_winsys *ws,
276			   struct radeon_winsys_fence *fence,
277			   bool absolute,
278			   uint64_t timeout);
279	bool (*fences_wait)(struct radeon_winsys *ws,
280			    struct radeon_winsys_fence *const *fences,
281			    uint32_t fence_count,
282			    bool wait_all,
283			    uint64_t timeout);
284
285	/* old semaphores - non shareable */
286	struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
287	void (*destroy_sem)(struct radeon_winsys_sem *sem);
288
289	/* new shareable sync objects */
290	int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
291	void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
292
293	void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
294	void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
295	bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
296			     bool wait_all, uint64_t timeout);
297
298	int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
299	int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
300
301	int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
302
303	/* Note that this, unlike the normal import, uses an existing syncobj. */
304	int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
305
306};
307
308static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
309{
310	cs->buf[cs->cdw++] = value;
311}
312
313static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
314				     const uint32_t *values, unsigned count)
315{
316	memcpy(cs->buf + cs->cdw, values, count * 4);
317	cs->cdw += count;
318}
319
320static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
321{
322	return bo->va;
323}
324
325static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
326				      struct radeon_cmdbuf *cs,
327				      struct radeon_winsys_bo *bo)
328{
329	if (bo->is_local)
330		return;
331
332	ws->cs_add_buffer(cs, bo);
333}
334
335#endif /* RADV_RADEON_WINSYS_H */
336