17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2018 Broadcom 37ec681f3Smrg * 47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 57ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 67ec681f3Smrg * to deal in the Software without restriction, including without limitation 77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 97ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 107ec681f3Smrg * 117ec681f3Smrg * The above copyright notice and this permission notice (including the next 127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 137ec681f3Smrg * Software. 147ec681f3Smrg * 157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 217ec681f3Smrg * IN THE SOFTWARE. 227ec681f3Smrg */ 237ec681f3Smrg 247ec681f3Smrg#ifndef DRM_SHIM_V3D_H 257ec681f3Smrg#define DRM_SHIM_V3D_H 267ec681f3Smrg 277ec681f3Smrg#include "broadcom/common/v3d_device_info.h" 287ec681f3Smrg#include "util/vma.h" 297ec681f3Smrg 307ec681f3Smrgstruct drm_shim_fd; 317ec681f3Smrg 327ec681f3Smrgstruct v3d_shim_device { 337ec681f3Smrg struct v3d_hw *hw; 347ec681f3Smrg struct v3d_device_info *devinfo; 357ec681f3Smrg 367ec681f3Smrg /* Base virtual address of the heap. */ 377ec681f3Smrg void *mem; 387ec681f3Smrg /* Base hardware address of the heap. */ 397ec681f3Smrg uint32_t mem_base; 407ec681f3Smrg /* Size of the heap. */ 417ec681f3Smrg size_t mem_size; 427ec681f3Smrg 437ec681f3Smrg /* Allocator for the GPU virtual addresses. */ 447ec681f3Smrg struct util_vma_heap heap; 457ec681f3Smrg}; 467ec681f3Smrgextern struct v3d_shim_device v3d; 477ec681f3Smrg 487ec681f3Smrgstruct v3d_bo { 497ec681f3Smrg struct shim_bo base; 507ec681f3Smrg uint64_t offset; 517ec681f3Smrg void *sim_vaddr; 527ec681f3Smrg void *gem_vaddr; 537ec681f3Smrg}; 547ec681f3Smrg 557ec681f3Smrgstatic inline struct v3d_bo * 567ec681f3Smrgv3d_bo(struct shim_bo *bo) 577ec681f3Smrg{ 587ec681f3Smrg return (struct v3d_bo *)bo; 597ec681f3Smrg} 607ec681f3Smrg 617ec681f3Smrgstruct v3d_bo *v3d_bo_lookup(struct shim_fd *shim_fd, int handle); 627ec681f3Smrgint v3d_ioctl_wait_bo(int fd, unsigned long request, void *arg); 637ec681f3Smrgint v3d_ioctl_mmap_bo(int fd, unsigned long request, void *arg); 647ec681f3Smrgint v3d_ioctl_get_bo_offset(int fd, unsigned long request, void *arg); 657ec681f3Smrg 667ec681f3Smrgvoid v3d33_drm_shim_driver_init(void); 677ec681f3Smrgvoid v3d41_drm_shim_driver_init(void); 687ec681f3Smrgvoid v3d42_drm_shim_driver_init(void); 697ec681f3Smrg 707ec681f3Smrg#endif /* DRM_SHIM_V3D_H */ 71