17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2020 Google LLC 37ec681f3Smrg * 47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 57ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 67ec681f3Smrg * to deal in the Software without restriction, including without limitation 77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 97ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 107ec681f3Smrg * 117ec681f3Smrg * The above copyright notice and this permission notice (including the next 127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 137ec681f3Smrg * Software. 147ec681f3Smrg * 157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 217ec681f3Smrg * IN THE SOFTWARE. 227ec681f3Smrg */ 237ec681f3Smrg 247ec681f3Smrgstruct testcase { 257ec681f3Smrg enum pipe_format format; 267ec681f3Smrg 277ec681f3Smrg int array_size; /* Size for array textures, or 0 otherwise. */ 287ec681f3Smrg bool is_3d; 297ec681f3Smrg 307ec681f3Smrg /* Partially filled layout of input parameters and expected results. */ 317ec681f3Smrg struct { 327ec681f3Smrg uint32_t tile_mode : 2; 337ec681f3Smrg bool ubwc : 1; 347ec681f3Smrg uint32_t width0, height0, depth0; 357ec681f3Smrg uint32_t nr_samples; 367ec681f3Smrg struct { 377ec681f3Smrg uint32_t offset; 387ec681f3Smrg uint32_t pitch; 397ec681f3Smrg } slices[FDL_MAX_MIP_LEVELS]; 407ec681f3Smrg struct { 417ec681f3Smrg uint32_t offset; 427ec681f3Smrg uint32_t pitch; 437ec681f3Smrg } ubwc_slices[FDL_MAX_MIP_LEVELS]; 447ec681f3Smrg } layout; 457ec681f3Smrg}; 467ec681f3Smrg 477ec681f3Smrgbool fdl_test_layout(const struct testcase *testcase, int gpu_id); 48