17ec681f3Smrg<?xml version="1.0" encoding="UTF-8"?> 27ec681f3Smrg<!-- 37ec681f3SmrgCopyright © 2020 Google, Inc. 47ec681f3Smrg 57ec681f3SmrgPermission is hereby granted, free of charge, to any person obtaining a 67ec681f3Smrgcopy of this software and associated documentation files (the "Software"), 77ec681f3Smrgto deal in the Software without restriction, including without limitation 87ec681f3Smrgthe rights to use, copy, modify, merge, publish, distribute, sublicense, 97ec681f3Smrgand/or sell copies of the Software, and to permit persons to whom the 107ec681f3SmrgSoftware is furnished to do so, subject to the following conditions: 117ec681f3Smrg 127ec681f3SmrgThe above copyright notice and this permission notice (including the next 137ec681f3Smrgparagraph) shall be included in all copies or substantial portions of the 147ec681f3SmrgSoftware. 157ec681f3Smrg 167ec681f3SmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 177ec681f3SmrgIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 187ec681f3SmrgFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 197ec681f3SmrgTHE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 207ec681f3SmrgLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 217ec681f3SmrgOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 227ec681f3SmrgSOFTWARE. 237ec681f3Smrg --> 247ec681f3Smrg 257ec681f3Smrg<isa> 267ec681f3Smrg 277ec681f3Smrg<!-- 287ec681f3Smrg Cat0 Instructions: 297ec681f3Smrg --> 307ec681f3Smrg 317ec681f3Smrg<bitset name="#instruction-cat0" extends="#instruction"> 327ec681f3Smrg <!-- 337ec681f3Smrg TODO immed size is 16b for a3xx, 20b for a4xx, 32b for a5xx+.. should we 347ec681f3Smrg try to express this? Also, not all cat0 take an immed, so maybe push 357ec681f3Smrg this further down the hierarchy? 367ec681f3Smrg --> 377ec681f3Smrg <field name="IMMED" low="0" high="31" type="branch"/> 387ec681f3Smrg 397ec681f3Smrg <field name="REPEAT" low="40" high="42" type="#rptN"/> 407ec681f3Smrg <pattern pos="43">x</pattern> 417ec681f3Smrg <field name="SS" pos="44" type="bool" display="(ss)"/> 427ec681f3Smrg <field name="EQ" pos="48" type="bool" display="(eq)"/> 437ec681f3Smrg <field name="JP" pos="59" type="bool" display="(jp)"/> 447ec681f3Smrg <field name="SY" pos="60" type="bool" display="(sy)"/> 457ec681f3Smrg <pattern low="61" high="63">000</pattern> <!-- cat0 --> 467ec681f3Smrg <encode> 477ec681f3Smrg <map name="IMMED">src->cat0.immed</map> 487ec681f3Smrg <map name="COMP1">src->cat0.comp1</map> 497ec681f3Smrg <map name="COMP2">src->cat0.comp2</map> 507ec681f3Smrg <map name="INV1">src->cat0.inv1</map> 517ec681f3Smrg <map name="INV2">src->cat0.inv2</map> 527ec681f3Smrg </encode> 537ec681f3Smrg</bitset> 547ec681f3Smrg 557ec681f3Smrg 567ec681f3Smrg<bitset name="#instruction-cat0-0src" extends="#instruction-cat0"> 577ec681f3Smrg <display> 587ec681f3Smrg {SY}{SS}{EQ}{JP}{REPEAT}{NAME} 597ec681f3Smrg </display> 607ec681f3Smrg <pattern low="32" high="36">00000</pattern> 617ec681f3Smrg <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 627ec681f3Smrg <pattern low="45" high="47">000</pattern> <!-- src1 --> 637ec681f3Smrg <pattern low="52" high="54">000</pattern> <!-- src0 --> 647ec681f3Smrg</bitset> 657ec681f3Smrg 667ec681f3Smrg<bitset name="nop" extends="#instruction-cat0-0src"> 677ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 687ec681f3Smrg <pattern low="55" high="58">0000</pattern> <!-- OPC --> 697ec681f3Smrg</bitset> 707ec681f3Smrg 717ec681f3Smrg<bitset name="end" extends="#instruction-cat0-0src"> 727ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 737ec681f3Smrg <pattern low="55" high="58">0110</pattern> <!-- OPC --> 747ec681f3Smrg</bitset> 757ec681f3Smrg 767ec681f3Smrg<bitset name="ret" extends="#instruction-cat0-0src"> 777ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 787ec681f3Smrg <pattern low="55" high="58">0100</pattern> <!-- OPC --> 797ec681f3Smrg</bitset> 807ec681f3Smrg 817ec681f3Smrg<bitset name="emit" extends="#instruction-cat0-0src"> 827ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 837ec681f3Smrg <pattern low="55" high="58">0111</pattern> <!-- OPC --> 847ec681f3Smrg</bitset> 857ec681f3Smrg 867ec681f3Smrg<bitset name="cut" extends="#instruction-cat0-0src"> 877ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 887ec681f3Smrg <pattern low="55" high="58">1000</pattern> <!-- OPC --> 897ec681f3Smrg</bitset> 907ec681f3Smrg 917ec681f3Smrg<bitset name="chmask" extends="#instruction-cat0-0src"> 927ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 937ec681f3Smrg <pattern low="55" high="58">1001</pattern> <!-- OPC --> 947ec681f3Smrg</bitset> 957ec681f3Smrg 967ec681f3Smrg<bitset name="chsh" extends="#instruction-cat0-0src"> 977ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 987ec681f3Smrg <pattern low="55" high="58">1010</pattern> <!-- OPC --> 997ec681f3Smrg</bitset> 1007ec681f3Smrg 1017ec681f3Smrg<bitset name="flow_rev" extends="#instruction-cat0-0src"> 1027ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 1037ec681f3Smrg <pattern low="55" high="58">1011</pattern> <!-- OPC --> 1047ec681f3Smrg</bitset> 1057ec681f3Smrg 1067ec681f3Smrg<bitset name="shpe" extends="#instruction-cat0-0src"> 1077ec681f3Smrg <doc>SHader Prologue End</doc> 1087ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1097ec681f3Smrg <pattern low="55" high="58">1000</pattern> <!-- OPC --> 1107ec681f3Smrg</bitset> 1117ec681f3Smrg 1127ec681f3Smrg<bitset name="prede" extends="#instruction-cat0-0src"> 1137ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1147ec681f3Smrg <pattern low="55" high="58">1111</pattern> <!-- OPC --> 1157ec681f3Smrg</bitset> 1167ec681f3Smrg 1177ec681f3Smrg 1187ec681f3Smrg<bitset name="#instruction-cat0-1src" extends="#instruction-cat0"> 1197ec681f3Smrg <display> 1207ec681f3Smrg {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1} 1217ec681f3Smrg </display> 1227ec681f3Smrg <pattern low="32" high="36">00000</pattern> 1237ec681f3Smrg <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 1247ec681f3Smrg <pattern low="45" high="47">000</pattern> <!-- src1 --> 1257ec681f3Smrg <field name="INV1" pos="52" type="bool" display="!"> 1267ec681f3Smrg <doc>Invert source condition</doc> 1277ec681f3Smrg </field> 1287ec681f3Smrg <field name="COMP1" low="53" high="54" type="#swiz"> 1297ec681f3Smrg <doc>Predicate register (p0.c) component for source</doc> 1307ec681f3Smrg </field> 1317ec681f3Smrg</bitset> 1327ec681f3Smrg 1337ec681f3Smrg<bitset name="kill" extends="#instruction-cat0-1src"> 1347ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 1357ec681f3Smrg <pattern low="55" high="58">0101</pattern> <!-- OPC --> 1367ec681f3Smrg</bitset> 1377ec681f3Smrg 1387ec681f3Smrg<bitset name="predt" extends="#instruction-cat0-1src"> 1397ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1407ec681f3Smrg <pattern low="55" high="58">1101</pattern> <!-- OPC --> 1417ec681f3Smrg</bitset> 1427ec681f3Smrg 1437ec681f3Smrg<bitset name="predf" extends="#instruction-cat0-1src"> 1447ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1457ec681f3Smrg <pattern low="55" high="58">1110</pattern> <!-- OPC --> 1467ec681f3Smrg</bitset> 1477ec681f3Smrg 1487ec681f3Smrg 1497ec681f3Smrg<bitset name="#instruction-cat0-immed" extends="#instruction-cat0"> 1507ec681f3Smrg <display> 1517ec681f3Smrg {SY}{SS}{JP}{NAME} #{IMMED} 1527ec681f3Smrg </display> 1537ec681f3Smrg <pattern low="32" high="36">xxxxx</pattern> <!-- INDEX --> 1547ec681f3Smrg <pattern low="37" high="39">xxx</pattern> <!-- BRTYPE --> 1557ec681f3Smrg <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 1567ec681f3Smrg <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 1577ec681f3Smrg</bitset> 1587ec681f3Smrg 1597ec681f3Smrg<bitset name="jump" extends="#instruction-cat0-immed"> 1607ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 1617ec681f3Smrg <pattern low="55" high="58">0010</pattern> <!-- OPC --> 1627ec681f3Smrg</bitset> 1637ec681f3Smrg 1647ec681f3Smrg<bitset name="call" extends="#instruction-cat0-immed"> 1657ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 1667ec681f3Smrg <pattern low="55" high="58">0011</pattern> <!-- OPC --> 1677ec681f3Smrg</bitset> 1687ec681f3Smrg 1697ec681f3Smrg<bitset name="bkt" extends="#instruction-cat0-immed"> 1707ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1717ec681f3Smrg <pattern low="55" high="58">0000</pattern> <!-- OPC --> 1727ec681f3Smrg</bitset> 1737ec681f3Smrg 1747ec681f3Smrg<bitset name="getone" extends="#instruction-cat0-immed"> 1757ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1767ec681f3Smrg <pattern low="55" high="58">0101</pattern> <!-- OPC --> 1777ec681f3Smrg</bitset> 1787ec681f3Smrg 1797ec681f3Smrg<bitset name="shps" extends="#instruction-cat0-immed"> 1807ec681f3Smrg <doc>SHader Prologue Start</doc> 1817ec681f3Smrg <pattern low="49" high="51">xx1</pattern> <!-- OPC_HI --> 1827ec681f3Smrg <pattern low="55" high="58">0111</pattern> <!-- OPC --> 1837ec681f3Smrg</bitset> 1847ec681f3Smrg 1857ec681f3Smrg<bitset name="#instruction-cat0-branch" extends="#instruction-cat0"> 1867ec681f3Smrg <pattern low="49" high="51">xx0</pattern> <!-- OPC_HI --> 1877ec681f3Smrg <pattern low="55" high="58">0001</pattern> <!-- OPC --> 1887ec681f3Smrg</bitset> 1897ec681f3Smrg 1907ec681f3Smrg<bitset name="brac" extends="#instruction-cat0-branch"> 1917ec681f3Smrg <display> 1927ec681f3Smrg {SY}{SS}{EQ}{JP}{NAME}.{INDEX} #{IMMED} 1937ec681f3Smrg </display> 1947ec681f3Smrg <field name="INDEX" low="32" high="36" type="uint"/> 1957ec681f3Smrg <pattern low="37" high="39">011</pattern> <!-- BRTYPE --> 1967ec681f3Smrg <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 1977ec681f3Smrg <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 1987ec681f3Smrg <encode> 1997ec681f3Smrg <map name="INDEX">src->cat0.idx</map> 2007ec681f3Smrg </encode> 2017ec681f3Smrg</bitset> 2027ec681f3Smrg 2037ec681f3Smrg<bitset name="brax" extends="#instruction-cat0-branch"> 2047ec681f3Smrg <pattern low="32" high="36">xxxxx</pattern> 2057ec681f3Smrg <pattern low="37" high="39">110</pattern> <!-- BRTYPE --> 2067ec681f3Smrg <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 2077ec681f3Smrg <pattern low="52" high="54">xxx</pattern> <!-- src0 --> 2087ec681f3Smrg</bitset> 2097ec681f3Smrg 2107ec681f3Smrg<bitset name="#instruction-cat0-branch-1src" extends="#instruction-cat0-branch"> 2117ec681f3Smrg <display> 2127ec681f3Smrg {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, #{IMMED} 2137ec681f3Smrg </display> 2147ec681f3Smrg <pattern low="32" high="36">xxxxx</pattern> 2157ec681f3Smrg <pattern low="45" high="47">xxx</pattern> <!-- src1 --> 2167ec681f3Smrg <field name="INV1" pos="52" type="bool" display="!"> 2177ec681f3Smrg <doc>Invert source condition</doc> 2187ec681f3Smrg </field> 2197ec681f3Smrg <field name="COMP1" low="53" high="54" type="#swiz"> 2207ec681f3Smrg <doc>Predicate register (p0.c) component for source</doc> 2217ec681f3Smrg </field> 2227ec681f3Smrg</bitset> 2237ec681f3Smrg 2247ec681f3Smrg<bitset name="br" extends="#instruction-cat0-branch-1src"> 2257ec681f3Smrg <pattern low="37" high="39">000</pattern> <!-- BRTYPE --> 2267ec681f3Smrg</bitset> 2277ec681f3Smrg 2287ec681f3Smrg<bitset name="bany" extends="#instruction-cat0-branch-1src"> 2297ec681f3Smrg <pattern low="37" high="39">100</pattern> <!-- BRTYPE --> 2307ec681f3Smrg</bitset> 2317ec681f3Smrg 2327ec681f3Smrg<bitset name="ball" extends="#instruction-cat0-branch-1src"> 2337ec681f3Smrg <pattern low="37" high="39">101</pattern> <!-- BRTYPE --> 2347ec681f3Smrg</bitset> 2357ec681f3Smrg 2367ec681f3Smrg<bitset name="#instruction-cat0-branch-2src" extends="#instruction-cat0-branch"> 2377ec681f3Smrg <display> 2387ec681f3Smrg {SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, {INV2}p0.{COMP2}, #{IMMED} 2397ec681f3Smrg </display> 2407ec681f3Smrg <pattern low="32" high="36">xxxxx</pattern> 2417ec681f3Smrg <!-- src1: --> 2427ec681f3Smrg <field name="INV2" pos="45" type="bool" display="!"> 2437ec681f3Smrg <doc>Invert source 2 condition</doc> 2447ec681f3Smrg </field> 2457ec681f3Smrg <field name="COMP2" low="46" high="47" type="#swiz"> 2467ec681f3Smrg <doc>Predicate register (p0.c) component for source 2</doc> 2477ec681f3Smrg </field> 2487ec681f3Smrg <!-- src0: --> 2497ec681f3Smrg <field name="INV1" pos="52" type="bool" display="!"> 2507ec681f3Smrg <doc>Invert source 1 condition</doc> 2517ec681f3Smrg </field> 2527ec681f3Smrg <field name="COMP1" low="53" high="54" type="#swiz"> 2537ec681f3Smrg <doc>Predicate register (p0.c) component for source 1</doc> 2547ec681f3Smrg </field> 2557ec681f3Smrg</bitset> 2567ec681f3Smrg 2577ec681f3Smrg<bitset name="brao" extends="#instruction-cat0-branch-2src"> 2587ec681f3Smrg <pattern low="37" high="39">001</pattern> <!-- BRTYPE --> 2597ec681f3Smrg</bitset> 2607ec681f3Smrg 2617ec681f3Smrg<bitset name="braa" extends="#instruction-cat0-branch-2src"> 2627ec681f3Smrg <pattern low="37" high="39">010</pattern> <!-- BRTYPE --> 2637ec681f3Smrg</bitset> 2647ec681f3Smrg 2657ec681f3Smrg<!-- TODO rest of cat0 --> 2667ec681f3Smrg 2677ec681f3Smrg</isa>