101e04c3fSmrg/* 201e04c3fSmrg * Copyright (c) 2012-2015 Etnaviv Project 301e04c3fSmrg * 401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 501e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 601e04c3fSmrg * to deal in the Software without restriction, including without limitation 701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sub license, 801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 901e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1001e04c3fSmrg * 1101e04c3fSmrg * The above copyright notice and this permission notice (including the 1201e04c3fSmrg * next paragraph) shall be included in all copies or substantial portions 1301e04c3fSmrg * of the Software. 1401e04c3fSmrg * 1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2101e04c3fSmrg * DEALINGS IN THE SOFTWARE. 2201e04c3fSmrg * 2301e04c3fSmrg * Authors: 2401e04c3fSmrg * Wladimir J. van der Laan <laanwj@gmail.com> 2501e04c3fSmrg */ 2601e04c3fSmrg 2701e04c3fSmrg#ifndef H_ETNA_EMIT 2801e04c3fSmrg#define H_ETNA_EMIT 2901e04c3fSmrg 3001e04c3fSmrg#include "etnaviv_screen.h" 3101e04c3fSmrg#include "etnaviv_util.h" 3201e04c3fSmrg#include "hw/cmdstream.xml.h" 3301e04c3fSmrg 3401e04c3fSmrgstruct etna_context; 3501e04c3fSmrg 3601e04c3fSmrgstruct etna_coalesce { 3701e04c3fSmrg uint32_t start; 3801e04c3fSmrg uint32_t last_reg; 3901e04c3fSmrg uint32_t last_fixp; 4001e04c3fSmrg}; 4101e04c3fSmrg 4201e04c3fSmrgstatic inline void 4301e04c3fSmrgetna_emit_load_state(struct etna_cmd_stream *stream, const uint16_t offset, 4401e04c3fSmrg const uint16_t count, const int fixp) 4501e04c3fSmrg{ 4601e04c3fSmrg uint32_t v; 4701e04c3fSmrg 4801e04c3fSmrg v = VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE | 4901e04c3fSmrg COND(fixp, VIV_FE_LOAD_STATE_HEADER_FIXP) | 5001e04c3fSmrg VIV_FE_LOAD_STATE_HEADER_OFFSET(offset) | 5101e04c3fSmrg (VIV_FE_LOAD_STATE_HEADER_COUNT(count) & 5201e04c3fSmrg VIV_FE_LOAD_STATE_HEADER_COUNT__MASK); 5301e04c3fSmrg 5401e04c3fSmrg etna_cmd_stream_emit(stream, v); 5501e04c3fSmrg} 5601e04c3fSmrg 5701e04c3fSmrgstatic inline void 5801e04c3fSmrgetna_set_state(struct etna_cmd_stream *stream, uint32_t address, uint32_t value) 5901e04c3fSmrg{ 6001e04c3fSmrg etna_cmd_stream_reserve(stream, 2); 6101e04c3fSmrg etna_emit_load_state(stream, address >> 2, 1, 0); 6201e04c3fSmrg etna_cmd_stream_emit(stream, value); 6301e04c3fSmrg} 6401e04c3fSmrg 6501e04c3fSmrgstatic inline void 6601e04c3fSmrgetna_set_state_reloc(struct etna_cmd_stream *stream, uint32_t address, 6701e04c3fSmrg const struct etna_reloc *reloc) 6801e04c3fSmrg{ 6901e04c3fSmrg etna_cmd_stream_reserve(stream, 2); 7001e04c3fSmrg etna_emit_load_state(stream, address >> 2, 1, 0); 7101e04c3fSmrg etna_cmd_stream_reloc(stream, reloc); 7201e04c3fSmrg} 7301e04c3fSmrg 7401e04c3fSmrgstatic inline void 7501e04c3fSmrgetna_set_state_multi(struct etna_cmd_stream *stream, uint32_t base, 7601e04c3fSmrg uint32_t num, const uint32_t *values) 7701e04c3fSmrg{ 7801e04c3fSmrg if (num == 0) 7901e04c3fSmrg return; 8001e04c3fSmrg 8101e04c3fSmrg etna_cmd_stream_reserve(stream, 1 + num + 1); /* 1 extra for potential alignment */ 8201e04c3fSmrg etna_emit_load_state(stream, base >> 2, num, 0); 8301e04c3fSmrg 8401e04c3fSmrg for (uint32_t i = 0; i < num; i++) 8501e04c3fSmrg etna_cmd_stream_emit(stream, values[i]); 8601e04c3fSmrg 8701e04c3fSmrg /* add potential padding */ 8801e04c3fSmrg if ((num % 2) == 0) 8901e04c3fSmrg etna_cmd_stream_emit(stream, 0); 9001e04c3fSmrg} 9101e04c3fSmrg 9201e04c3fSmrgvoid 9301e04c3fSmrgetna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to); 9401e04c3fSmrg 9501e04c3fSmrgstatic inline void 9601e04c3fSmrgetna_draw_primitives(struct etna_cmd_stream *stream, uint32_t primitive_type, 9701e04c3fSmrg uint32_t start, uint32_t count) 9801e04c3fSmrg{ 9901e04c3fSmrg etna_cmd_stream_reserve(stream, 4); 10001e04c3fSmrg 10101e04c3fSmrg etna_cmd_stream_emit(stream, VIV_FE_DRAW_PRIMITIVES_HEADER_OP_DRAW_PRIMITIVES); 10201e04c3fSmrg etna_cmd_stream_emit(stream, primitive_type); 10301e04c3fSmrg etna_cmd_stream_emit(stream, start); 10401e04c3fSmrg etna_cmd_stream_emit(stream, count); 10501e04c3fSmrg} 10601e04c3fSmrg 10701e04c3fSmrgstatic inline void 10801e04c3fSmrgetna_draw_indexed_primitives(struct etna_cmd_stream *stream, 10901e04c3fSmrg uint32_t primitive_type, uint32_t start, 11001e04c3fSmrg uint32_t count, uint32_t offset) 11101e04c3fSmrg{ 11201e04c3fSmrg etna_cmd_stream_reserve(stream, 5 + 1); 11301e04c3fSmrg 11401e04c3fSmrg etna_cmd_stream_emit(stream, VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP_DRAW_INDEXED_PRIMITIVES); 11501e04c3fSmrg etna_cmd_stream_emit(stream, primitive_type); 11601e04c3fSmrg etna_cmd_stream_emit(stream, start); 11701e04c3fSmrg etna_cmd_stream_emit(stream, count); 11801e04c3fSmrg etna_cmd_stream_emit(stream, offset); 11901e04c3fSmrg etna_cmd_stream_emit(stream, 0); 12001e04c3fSmrg} 12101e04c3fSmrg 12201e04c3fSmrg/* important: this takes a vertex count, not a primitive count */ 12301e04c3fSmrgstatic inline void 12401e04c3fSmrgetna_draw_instanced(struct etna_cmd_stream *stream, 12501e04c3fSmrg uint32_t indexed, uint32_t primitive_type, 12601e04c3fSmrg uint32_t instance_count, 12701e04c3fSmrg uint32_t vertex_count, uint32_t offset) 12801e04c3fSmrg{ 12901e04c3fSmrg etna_cmd_stream_reserve(stream, 3 + 1); 13001e04c3fSmrg etna_cmd_stream_emit(stream, 13101e04c3fSmrg VIV_FE_DRAW_INSTANCED_HEADER_OP_DRAW_INSTANCED | 13201e04c3fSmrg COND(indexed, VIV_FE_DRAW_INSTANCED_HEADER_INDEXED) | 13301e04c3fSmrg VIV_FE_DRAW_INSTANCED_HEADER_TYPE(primitive_type) | 13401e04c3fSmrg VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO(instance_count & 0xffff)); 13501e04c3fSmrg etna_cmd_stream_emit(stream, 13601e04c3fSmrg VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI(instance_count >> 16) | 13701e04c3fSmrg VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT(vertex_count)); 13801e04c3fSmrg etna_cmd_stream_emit(stream, 13901e04c3fSmrg VIV_FE_DRAW_INSTANCED_START_INDEX(offset)); 14001e04c3fSmrg etna_cmd_stream_emit(stream, 0); 14101e04c3fSmrg} 14201e04c3fSmrg 14301e04c3fSmrgstatic inline void 14401e04c3fSmrgetna_coalesce_start(struct etna_cmd_stream *stream, 14501e04c3fSmrg struct etna_coalesce *coalesce) 14601e04c3fSmrg{ 14701e04c3fSmrg coalesce->start = etna_cmd_stream_offset(stream); 14801e04c3fSmrg coalesce->last_reg = 0; 14901e04c3fSmrg coalesce->last_fixp = 0; 15001e04c3fSmrg} 15101e04c3fSmrg 15201e04c3fSmrgstatic inline void 15301e04c3fSmrgetna_coalesce_end(struct etna_cmd_stream *stream, 15401e04c3fSmrg struct etna_coalesce *coalesce) 15501e04c3fSmrg{ 15601e04c3fSmrg uint32_t end = etna_cmd_stream_offset(stream); 15701e04c3fSmrg uint32_t size = end - coalesce->start; 15801e04c3fSmrg 15901e04c3fSmrg if (size) { 16001e04c3fSmrg uint32_t offset = coalesce->start - 1; 16101e04c3fSmrg uint32_t value = etna_cmd_stream_get(stream, offset); 16201e04c3fSmrg 16301e04c3fSmrg value |= VIV_FE_LOAD_STATE_HEADER_COUNT(size); 16401e04c3fSmrg etna_cmd_stream_set(stream, offset, value); 16501e04c3fSmrg } 16601e04c3fSmrg 16701e04c3fSmrg /* append needed padding */ 16801e04c3fSmrg if (end % 2 == 1) 16901e04c3fSmrg etna_cmd_stream_emit(stream, 0xdeadbeef); 17001e04c3fSmrg} 17101e04c3fSmrg 17201e04c3fSmrgstatic inline void 17301e04c3fSmrgcheck_coalsence(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, 17401e04c3fSmrg uint32_t reg, uint32_t fixp) 17501e04c3fSmrg{ 17601e04c3fSmrg if (coalesce->last_reg != 0) { 17701e04c3fSmrg if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != fixp)) { 17801e04c3fSmrg etna_coalesce_end(stream, coalesce); 17901e04c3fSmrg etna_emit_load_state(stream, reg >> 2, 0, fixp); 18001e04c3fSmrg coalesce->start = etna_cmd_stream_offset(stream); 18101e04c3fSmrg } 18201e04c3fSmrg } else { 18301e04c3fSmrg etna_emit_load_state(stream, reg >> 2, 0, fixp); 18401e04c3fSmrg coalesce->start = etna_cmd_stream_offset(stream); 18501e04c3fSmrg } 18601e04c3fSmrg 18701e04c3fSmrg coalesce->last_reg = reg; 18801e04c3fSmrg coalesce->last_fixp = fixp; 18901e04c3fSmrg} 19001e04c3fSmrg 19101e04c3fSmrgstatic inline void 19201e04c3fSmrgetna_coalsence_emit(struct etna_cmd_stream *stream, 19301e04c3fSmrg struct etna_coalesce *coalesce, uint32_t reg, 19401e04c3fSmrg uint32_t value) 19501e04c3fSmrg{ 19601e04c3fSmrg check_coalsence(stream, coalesce, reg, 0); 19701e04c3fSmrg etna_cmd_stream_emit(stream, value); 19801e04c3fSmrg} 19901e04c3fSmrg 20001e04c3fSmrgstatic inline void 20101e04c3fSmrgetna_coalsence_emit_fixp(struct etna_cmd_stream *stream, 20201e04c3fSmrg struct etna_coalesce *coalesce, uint32_t reg, 20301e04c3fSmrg uint32_t value) 20401e04c3fSmrg{ 20501e04c3fSmrg check_coalsence(stream, coalesce, reg, 1); 20601e04c3fSmrg etna_cmd_stream_emit(stream, value); 20701e04c3fSmrg} 20801e04c3fSmrg 20901e04c3fSmrgstatic inline void 21001e04c3fSmrgetna_coalsence_emit_reloc(struct etna_cmd_stream *stream, 21101e04c3fSmrg struct etna_coalesce *coalesce, uint32_t reg, 21201e04c3fSmrg const struct etna_reloc *r) 21301e04c3fSmrg{ 21401e04c3fSmrg if (r->bo) { 21501e04c3fSmrg check_coalsence(stream, coalesce, reg, 0); 21601e04c3fSmrg etna_cmd_stream_reloc(stream, r); 21701e04c3fSmrg } 21801e04c3fSmrg} 21901e04c3fSmrg 22001e04c3fSmrgvoid 22101e04c3fSmrgetna_emit_state(struct etna_context *ctx); 22201e04c3fSmrg 22301e04c3fSmrg#endif 224