101e04c3fSmrg/*
201e04c3fSmrg * Copyright (c) 2012-2015 Etnaviv Project
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sub license,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the
1201e04c3fSmrg * next paragraph) shall be included in all copies or substantial portions
1301e04c3fSmrg * of the Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2101e04c3fSmrg * DEALINGS IN THE SOFTWARE.
2201e04c3fSmrg *
2301e04c3fSmrg * Authors:
2401e04c3fSmrg *    Wladimir J. van der Laan <laanwj@gmail.com>
2501e04c3fSmrg */
2601e04c3fSmrg
2701e04c3fSmrg#include "etnaviv_zsa.h"
2801e04c3fSmrg
2901e04c3fSmrg#include "etnaviv_context.h"
3001e04c3fSmrg#include "etnaviv_screen.h"
3101e04c3fSmrg#include "etnaviv_translate.h"
327ec681f3Smrg#include "util/half_float.h"
3301e04c3fSmrg#include "util/u_memory.h"
3401e04c3fSmrg
3501e04c3fSmrg#include "hw/common.xml.h"
3601e04c3fSmrg
3701e04c3fSmrgvoid *
3801e04c3fSmrgetna_zsa_state_create(struct pipe_context *pctx,
3901e04c3fSmrg                      const struct pipe_depth_stencil_alpha_state *so)
4001e04c3fSmrg{
4101e04c3fSmrg   struct etna_context *ctx = etna_context(pctx);
427ec681f3Smrg   struct etna_screen *screen = ctx->screen;
4301e04c3fSmrg   struct etna_zsa_state *cs = CALLOC_STRUCT(etna_zsa_state);
4401e04c3fSmrg
4501e04c3fSmrg   if (!cs)
4601e04c3fSmrg      return NULL;
4701e04c3fSmrg
4801e04c3fSmrg   cs->base = *so;
4901e04c3fSmrg
507ec681f3Smrg   cs->z_test_enabled = so->depth_enabled && so->depth_func != PIPE_FUNC_ALWAYS;
517ec681f3Smrg   cs->z_write_enabled = so->depth_enabled && so->depth_writemask;
527ec681f3Smrg
5301e04c3fSmrg   /* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */
5401e04c3fSmrg
5501e04c3fSmrg/* Set operations to KEEP if write mask is 0.
5601e04c3fSmrg * When we don't do this, the depth buffer is written for the entire primitive
5701e04c3fSmrg * instead of just where the stencil condition holds (GC600 rev 0x0019, without
5801e04c3fSmrg * feature CORRECT_STENCIL).
5901e04c3fSmrg * Not sure if this is a hardware bug or just a strange edge case. */
6001e04c3fSmrg#if 0 /* TODO: It looks like a hardware bug */
6101e04c3fSmrg    for(int i=0; i<2; ++i)
6201e04c3fSmrg    {
6301e04c3fSmrg        if(so->stencil[i].writemask == 0)
6401e04c3fSmrg        {
6501e04c3fSmrg            so->stencil[i].fail_op = so->stencil[i].zfail_op = so->stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP;
6601e04c3fSmrg        }
6701e04c3fSmrg    }
6801e04c3fSmrg#endif
6901e04c3fSmrg
7001e04c3fSmrg   /* Determine whether to enable early z reject. Don't enable it when any of
7101e04c3fSmrg    * the stencil-modifying functions is used. */
7201e04c3fSmrg   if (so->stencil[0].enabled) {
7301e04c3fSmrg      if (so->stencil[0].func != PIPE_FUNC_ALWAYS ||
7401e04c3fSmrg          (so->stencil[1].enabled && so->stencil[1].func != PIPE_FUNC_ALWAYS))
757ec681f3Smrg         cs->stencil_enabled = 1;
7601e04c3fSmrg
7701e04c3fSmrg      if (so->stencil[0].fail_op != PIPE_STENCIL_OP_KEEP ||
7801e04c3fSmrg          so->stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP ||
7901e04c3fSmrg          so->stencil[0].zpass_op != PIPE_STENCIL_OP_KEEP) {
807ec681f3Smrg         cs->stencil_enabled = 1;
817ec681f3Smrg         cs->stencil_modified = 1;
8201e04c3fSmrg      } else if (so->stencil[1].enabled) {
8301e04c3fSmrg         if (so->stencil[1].fail_op != PIPE_STENCIL_OP_KEEP ||
8401e04c3fSmrg             so->stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP ||
8501e04c3fSmrg             so->stencil[1].zpass_op != PIPE_STENCIL_OP_KEEP) {
867ec681f3Smrg            cs->stencil_enabled = 1;
877ec681f3Smrg            cs->stencil_modified = 1;
8801e04c3fSmrg         }
8901e04c3fSmrg      }
9001e04c3fSmrg   }
9101e04c3fSmrg
927ec681f3Smrg   /* calculate extra_reference value */
937ec681f3Smrg   uint32_t extra_reference = 0;
947ec681f3Smrg
957ec681f3Smrg   if (VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT))
967ec681f3Smrg      extra_reference = _mesa_float_to_half(SATURATE(so->alpha_ref_value));
977ec681f3Smrg
987ec681f3Smrg   cs->PE_STENCIL_CONFIG_EXT =
997ec681f3Smrg      VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(extra_reference);
1007ec681f3Smrg
10101e04c3fSmrg   cs->PE_ALPHA_OP =
1027ec681f3Smrg      COND(so->alpha_enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
1037ec681f3Smrg      VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha_func) |
1047ec681f3Smrg      VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha_ref_value));
1057ec681f3Smrg
1067ec681f3Smrg   for (unsigned i = 0; i < 2; i++) {
1077ec681f3Smrg      const struct pipe_stencil_state *stencil_front = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[i] : &so->stencil[0];
1087ec681f3Smrg      const struct pipe_stencil_state *stencil_back = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[!i] : &so->stencil[0];
1097ec681f3Smrg      cs->PE_STENCIL_OP[i] =
1107ec681f3Smrg         VIVS_PE_STENCIL_OP_FUNC_FRONT(stencil_front->func) |
1117ec681f3Smrg         VIVS_PE_STENCIL_OP_FUNC_BACK(stencil_back->func) |
1127ec681f3Smrg         VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(stencil_front->fail_op)) |
1137ec681f3Smrg         VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(stencil_back->fail_op)) |
1147ec681f3Smrg         VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(stencil_front->zfail_op)) |
1157ec681f3Smrg         VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(stencil_back->zfail_op)) |
1167ec681f3Smrg         VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(stencil_front->zpass_op)) |
1177ec681f3Smrg         VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(stencil_back->zpass_op));
1187ec681f3Smrg      cs->PE_STENCIL_CONFIG[i] =
1197ec681f3Smrg         translate_stencil_mode(so->stencil[0].enabled, so->stencil[0].enabled) |
1207ec681f3Smrg         VIVS_PE_STENCIL_CONFIG_MASK_FRONT(stencil_front->valuemask) |
1217ec681f3Smrg         VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(stencil_front->writemask);
1227ec681f3Smrg      cs->PE_STENCIL_CONFIG_EXT2[i] =
1237ec681f3Smrg         VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(stencil_back->valuemask) |
1247ec681f3Smrg         VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask);
1257ec681f3Smrg   }
12601e04c3fSmrg
12701e04c3fSmrg   /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
12801e04c3fSmrg   return cs;
12901e04c3fSmrg}
130