101e04c3fSmrg#ifndef STATE_XML
201e04c3fSmrg#define STATE_XML
301e04c3fSmrg
401e04c3fSmrg/* Autogenerated file, DO NOT EDIT manually!
501e04c3fSmrg
601e04c3fSmrgThis file was generated by the rules-ng-ng headergen tool in this git repository:
701e04c3fSmrghttp://0x04.net/cgit/index.cgi/rules-ng-ng
801e04c3fSmrggit clone git://0x04.net/rules-ng-ng
901e04c3fSmrg
1001e04c3fSmrgThe rules-ng-ng source files this header was generated from are:
117ec681f3Smrg- state.xml     (  26877 bytes, from 2020-02-14 10:19:56)
127ec681f3Smrg- common.xml    (  35468 bytes, from 2020-01-04 20:02:31)
137ec681f3Smrg- common_3d.xml (  15058 bytes, from 2020-04-17 16:31:50)
147ec681f3Smrg- state_hi.xml  (  34851 bytes, from 2020-04-17 16:25:34)
159f464c52Smaya- copyright.xml (   1597 bytes, from 2018-02-10 13:09:26)
169f464c52Smaya- state_2d.xml  (  51552 bytes, from 2018-02-10 13:09:26)
177ec681f3Smrg- state_3d.xml  (  83771 bytes, from 2020-04-17 17:15:55)
187ec681f3Smrg- state_blt.xml (  14252 bytes, from 2020-01-10 14:36:29)
199f464c52Smaya- state_vg.xml  (   5975 bytes, from 2018-02-10 13:09:26)
2001e04c3fSmrg
217ec681f3SmrgCopyright (C) 2012-2020 by the following authors:
2201e04c3fSmrg- Wladimir J. van der Laan <laanwj@gmail.com>
2301e04c3fSmrg- Christian Gmeiner <christian.gmeiner@gmail.com>
2401e04c3fSmrg- Lucas Stach <l.stach@pengutronix.de>
2501e04c3fSmrg- Russell King <rmk@arm.linux.org.uk>
2601e04c3fSmrg
2701e04c3fSmrgPermission is hereby granted, free of charge, to any person obtaining a
2801e04c3fSmrgcopy of this software and associated documentation files (the "Software"),
2901e04c3fSmrgto deal in the Software without restriction, including without limitation
3001e04c3fSmrgthe rights to use, copy, modify, merge, publish, distribute, sub license,
3101e04c3fSmrgand/or sell copies of the Software, and to permit persons to whom the
3201e04c3fSmrgSoftware is furnished to do so, subject to the following conditions:
3301e04c3fSmrg
3401e04c3fSmrgThe above copyright notice and this permission notice (including the
3501e04c3fSmrgnext paragraph) shall be included in all copies or substantial portions
3601e04c3fSmrgof the Software.
3701e04c3fSmrg
3801e04c3fSmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
3901e04c3fSmrgIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
4001e04c3fSmrgFITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
4101e04c3fSmrgTHE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
4201e04c3fSmrgLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4301e04c3fSmrgFROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
4401e04c3fSmrgDEALINGS IN THE SOFTWARE.
4501e04c3fSmrg*/
4601e04c3fSmrg
4701e04c3fSmrg
4801e04c3fSmrg#define VARYING_COMPONENT_USE_UNUSED				0x00000000
4901e04c3fSmrg#define VARYING_COMPONENT_USE_USED				0x00000001
5001e04c3fSmrg#define VARYING_COMPONENT_USE_POINTCOORD_X			0x00000002
5101e04c3fSmrg#define VARYING_COMPONENT_USE_POINTCOORD_Y			0x00000003
5201e04c3fSmrg#define FE_DATA_TYPE_BYTE					0x00000000
5301e04c3fSmrg#define FE_DATA_TYPE_UNSIGNED_BYTE				0x00000001
5401e04c3fSmrg#define FE_DATA_TYPE_SHORT					0x00000002
5501e04c3fSmrg#define FE_DATA_TYPE_UNSIGNED_SHORT				0x00000003
5601e04c3fSmrg#define FE_DATA_TYPE_INT					0x00000004
5701e04c3fSmrg#define FE_DATA_TYPE_UNSIGNED_INT				0x00000005
587ec681f3Smrg#define FE_DATA_TYPE_INT_2_10_10_10_REV				0x00000006
597ec681f3Smrg#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV		0x00000007
6001e04c3fSmrg#define FE_DATA_TYPE_FLOAT					0x00000008
6101e04c3fSmrg#define FE_DATA_TYPE_HALF_FLOAT					0x00000009
6201e04c3fSmrg#define FE_DATA_TYPE_FIXED					0x0000000b
6301e04c3fSmrg#define FE_DATA_TYPE_INT_10_10_10_2				0x0000000c
6401e04c3fSmrg#define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2			0x0000000d
6501e04c3fSmrg#define FE_DATA_TYPE_BYTE_I					0x0000000e
6601e04c3fSmrg#define FE_DATA_TYPE_SHORT_I					0x0000000f
6701e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK		0x000000ff
6801e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT		0
6901e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)		(((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
7001e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK		0x00ff0000
7101e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT		16
7201e04c3fSmrg#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x)		(((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)
7301e04c3fSmrg#define VIVS_FE							0x00000000
7401e04c3fSmrg
7501e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0)		       (0x00000600 + 0x4*(i0))
7601e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE			0x00000004
7701e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN			0x00000010
7801e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK		0x0000000f
7901e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT		0
8001e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
8101e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK		0x00000030
8201e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT		4
8301e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
8401e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE		0x00000080
8501e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK		0x00000700
8601e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT		8
8701e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
8801e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK			0x00003000
8901e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT		12
9001e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)
9101e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK		0x0000c000
9201e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT		14
9301e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF		0x00000000
947ec681f3Smrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND	0x00004000
9501e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON		0x00008000
9601e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK		0x00ff0000
9701e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT		16
9801e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
9901e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK			0xff000000
10001e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT		24
10101e04c3fSmrg#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
10201e04c3fSmrg
10301e04c3fSmrg#define VIVS_FE_CMD_STREAM_BASE_ADDR				0x00000640
10401e04c3fSmrg
10501e04c3fSmrg#define VIVS_FE_INDEX_STREAM_BASE_ADDR				0x00000644
10601e04c3fSmrg
10701e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL				0x00000648
10801e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK			0x00000003
10901e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT		0
11001e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR		0x00000000
11101e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT	0x00000001
11201e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT		0x00000002
11301e04c3fSmrg#define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART		0x00000100
11401e04c3fSmrg
11501e04c3fSmrg#define VIVS_FE_VERTEX_STREAM_BASE_ADDR				0x0000064c
11601e04c3fSmrg
11701e04c3fSmrg#define VIVS_FE_VERTEX_STREAM_CONTROL				0x00000650
11801e04c3fSmrg
11901e04c3fSmrg#define VIVS_FE_COMMAND_ADDRESS					0x00000654
12001e04c3fSmrg
12101e04c3fSmrg#define VIVS_FE_COMMAND_CONTROL					0x00000658
12201e04c3fSmrg#define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK			0x0000ffff
12301e04c3fSmrg#define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT			0
12401e04c3fSmrg#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x)			(((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
12501e04c3fSmrg#define VIVS_FE_COMMAND_CONTROL_ENABLE				0x00010000
12601e04c3fSmrg
12701e04c3fSmrg#define VIVS_FE_DMA_STATUS					0x0000065c
12801e04c3fSmrg
12901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE					0x00000660
13001e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK			0x0000001f
13101e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT		0
13201e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE			0x00000000
13301e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC			0x00000001
13401e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0			0x00000002
13501e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0			0x00000003
13601e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1			0x00000004
13701e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1			0x00000005
13801e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR			0x00000006
13901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD			0x00000007
14001e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL		0x00000008
14101e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL		0x00000009
14201e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA		0x0000000a
14301e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX		0x0000000b
14401e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW			0x0000000c
14501e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0		0x0000000d
14601e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1		0x0000000e
14701e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0		0x0000000f
14801e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1		0x00000010
14901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO		0x00000011
15001e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT			0x00000012
15101e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK			0x00000013
15201e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END			0x00000014
15301e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL			0x00000015
15401e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK		0x00000300
15501e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT		8
15601e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE		0x00000000
15701e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START		0x00000100
15801e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ		0x00000200
15901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END		0x00000300
16001e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK		0x00000c00
16101e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT		10
16201e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE		0x00000000
16301e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID	0x00000400
16401e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID		0x00000800
16501e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK		0x00003000
16601e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT		12
16701e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE		0x00000000
16801e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX		0x00001000
16901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL		0x00002000
17001e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK			0x0000c000
17101e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT		14
17201e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE			0x00000000
17301e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR			0x00004000
17401e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC		0x00008000
17501e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK		0x00030000
17601e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT		16
17701e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE		0x00000000
17801e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE		0x00010000
17901e04c3fSmrg#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS		0x00020000
18001e04c3fSmrg
18101e04c3fSmrg#define VIVS_FE_DMA_ADDRESS					0x00000664
18201e04c3fSmrg
18301e04c3fSmrg#define VIVS_FE_DMA_LOW						0x00000668
18401e04c3fSmrg
18501e04c3fSmrg#define VIVS_FE_DMA_HIGH					0x0000066c
18601e04c3fSmrg
18701e04c3fSmrg#define VIVS_FE_AUTO_FLUSH					0x00000670
18801e04c3fSmrg
18901e04c3fSmrg#define VIVS_FE_PRIMITIVE_RESTART_INDEX				0x00000674
19001e04c3fSmrg
19101e04c3fSmrg#define VIVS_FE_UNK00678					0x00000678
19201e04c3fSmrg
19301e04c3fSmrg#define VIVS_FE_UNK0067C					0x0000067c
19401e04c3fSmrg
19501e04c3fSmrg#define VIVS_FE_VERTEX_STREAMS(i0)			       (0x00000000 + 0x4*(i0))
19601e04c3fSmrg#define VIVS_FE_VERTEX_STREAMS__ESIZE				0x00000004
19701e04c3fSmrg#define VIVS_FE_VERTEX_STREAMS__LEN				0x00000008
19801e04c3fSmrg
19901e04c3fSmrg#define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0)		       (0x00000680 + 0x4*(i0))
20001e04c3fSmrg
20101e04c3fSmrg#define VIVS_FE_VERTEX_STREAMS_CONTROL(i0)		       (0x000006a0 + 0x4*(i0))
20201e04c3fSmrg
20301e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB(i0)			       (0x00000000 + 0x4*(i0))
20401e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB__ESIZE				0x00000004
20501e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB__LEN				0x00000010
20601e04c3fSmrg
20701e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0)		       (0x000006c0 + 0x4*(i0))
20801e04c3fSmrg
20901e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0)		       (0x00000700 + 0x4*(i0))
21001e04c3fSmrg
21101e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0)		       (0x00000740 + 0x4*(i0))
21201e04c3fSmrg
21301e04c3fSmrg#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0)		       (0x00000780 + 0x4*(i0))
21401e04c3fSmrg
2157ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG				0x000007c4
2167ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE		0x00000001
2177ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE		0x00000002
2187ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK		0x0000ff00
2197ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT		8
2207ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x)		(((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK)
2217ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK		0x00ff0000
2227ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT		16
2237ec681f3Smrg#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x)		(((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK)
22401e04c3fSmrg
22501e04c3fSmrg#define VIVS_FE_HALTI5_UNK007D0(i0)			       (0x000007d0 + 0x4*(i0))
22601e04c3fSmrg#define VIVS_FE_HALTI5_UNK007D0__ESIZE				0x00000004
22701e04c3fSmrg#define VIVS_FE_HALTI5_UNK007D0__LEN				0x00000002
22801e04c3fSmrg
22901e04c3fSmrg#define VIVS_FE_HALTI5_UNK007D8					0x000007d8
23001e04c3fSmrg
23101e04c3fSmrg#define VIVS_FE_DESC_START					0x000007dc
23201e04c3fSmrg
23301e04c3fSmrg#define VIVS_FE_DESC_END					0x000007e0
23401e04c3fSmrg
23501e04c3fSmrg#define VIVS_FE_DESC_AVAIL					0x000007e4
23601e04c3fSmrg#define VIVS_FE_DESC_AVAIL_COUNT__MASK				0x0000007f
23701e04c3fSmrg#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT				0
23801e04c3fSmrg#define VIVS_FE_DESC_AVAIL_COUNT(x)				(((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
23901e04c3fSmrg
24001e04c3fSmrg#define VIVS_FE_FENCE_WAIT_DATA_LOW				0x000007e8
24101e04c3fSmrg
24201e04c3fSmrg#define VIVS_FE_FENCE_WAIT_DATA_HIGH				0x000007f4
24301e04c3fSmrg
24401e04c3fSmrg#define VIVS_FE_ROBUSTNESS_UNK007F8				0x000007f8
24501e04c3fSmrg
24601e04c3fSmrg#define VIVS_GL							0x00000000
24701e04c3fSmrg
24801e04c3fSmrg#define VIVS_GL_PIPE_SELECT					0x00003800
24901e04c3fSmrg#define VIVS_GL_PIPE_SELECT_PIPE__MASK				0x00000001
25001e04c3fSmrg#define VIVS_GL_PIPE_SELECT_PIPE__SHIFT				0
25101e04c3fSmrg#define VIVS_GL_PIPE_SELECT_PIPE(x)				(((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
25201e04c3fSmrg
25301e04c3fSmrg#define VIVS_GL_EVENT						0x00003804
25401e04c3fSmrg#define VIVS_GL_EVENT_EVENT_ID__MASK				0x0000001f
25501e04c3fSmrg#define VIVS_GL_EVENT_EVENT_ID__SHIFT				0
25601e04c3fSmrg#define VIVS_GL_EVENT_EVENT_ID(x)				(((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
25701e04c3fSmrg#define VIVS_GL_EVENT_FROM_FE					0x00000020
25801e04c3fSmrg#define VIVS_GL_EVENT_FROM_PE					0x00000040
25901e04c3fSmrg#define VIVS_GL_EVENT_FROM_BLT					0x00000080
26001e04c3fSmrg#define VIVS_GL_EVENT_SOURCE__MASK				0x00001f00
26101e04c3fSmrg#define VIVS_GL_EVENT_SOURCE__SHIFT				8
26201e04c3fSmrg#define VIVS_GL_EVENT_SOURCE(x)					(((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
26301e04c3fSmrg
26401e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN					0x00003808
26501e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK			0x0000001f
26601e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT			0
26701e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
26801e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK			0x00001f00
26901e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT			8
27001e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
27101e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK			0x30000000
27201e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT			28
27301e04c3fSmrg#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x)			(((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
27401e04c3fSmrg
27501e04c3fSmrg#define VIVS_GL_FLUSH_CACHE					0x0000380c
27601e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_DEPTH				0x00000001
27701e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_COLOR				0x00000002
27801e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_TEXTURE				0x00000004
27901e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_PE2D				0x00000008
28001e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_TEXTUREVS				0x00000010
28101e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_SHADER_L1				0x00000020
28201e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_SHADER_L2				0x00000040
28301e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_UNK10				0x00000400
28401e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_UNK11				0x00000800
28501e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12			0x00001000
28601e04c3fSmrg#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13			0x00002000
28701e04c3fSmrg
28801e04c3fSmrg#define VIVS_GL_FLUSH_MMU					0x00003810
28901e04c3fSmrg#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU				0x00000001
29001e04c3fSmrg#define VIVS_GL_FLUSH_MMU_FLUSH_UNK1				0x00000002
29101e04c3fSmrg#define VIVS_GL_FLUSH_MMU_FLUSH_UNK2				0x00000004
29201e04c3fSmrg#define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU				0x00000008
29301e04c3fSmrg#define VIVS_GL_FLUSH_MMU_FLUSH_UNK4				0x00000010
29401e04c3fSmrg
29501e04c3fSmrg#define VIVS_GL_VERTEX_ELEMENT_CONFIG				0x00003814
29601e04c3fSmrg
29701e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG				0x00003818
29801e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK		0x00000003
29901e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT		0
30001e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE		0x00000000
30101e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X		0x00000001
30201e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X		0x00000002
30301e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK		0x00000008
30401e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK		0x000000f0
30501e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT		4
30601e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x)		(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
30701e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK		0x00000100
30801e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK			0x00007000
30901e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT		12
31001e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
31101e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK			0x00008000
31201e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK			0x00030000
31301e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT		16
31401e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
31501e04c3fSmrg#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK			0x00080000
31601e04c3fSmrg
31701e04c3fSmrg#define VIVS_GL_VARYING_TOTAL_COMPONENTS			0x0000381c
31801e04c3fSmrg#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK		0x000000ff
31901e04c3fSmrg#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT		0
32001e04c3fSmrg#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)			(((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
32101e04c3fSmrg
32201e04c3fSmrg#define VIVS_GL_VARYING_NUM_COMPONENTS				0x00003820
32301e04c3fSmrg
32401e04c3fSmrg#define VIVS_GL_OCCLUSION_QUERY_ADDR				0x00003824
32501e04c3fSmrg
32601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE(i0)		       (0x00003828 + 0x4*(i0))
32701e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE__ESIZE			0x00000004
32801e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE__LEN			0x00000002
32901e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK		0x00000003
33001e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT		0
33101e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
33201e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK		0x0000000c
33301e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT		2
33401e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
33501e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK		0x00000030
33601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT		4
33701e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
33801e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK		0x000000c0
33901e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT		6
34001e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
34101e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK		0x00000300
34201e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT		8
34301e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
34401e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK		0x00000c00
34501e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT		10
34601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
34701e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK		0x00003000
34801e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT		12
34901e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
35001e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK		0x0000c000
35101e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT		14
35201e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
35301e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK		0x00030000
35401e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT		16
35501e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
35601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK		0x000c0000
35701e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT		18
35801e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
35901e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK		0x00300000
36001e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT		20
36101e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
36201e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK		0x00c00000
36301e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT		22
36401e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
36501e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK		0x03000000
36601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT		24
36701e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
36801e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK		0x0c000000
36901e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT		26
37001e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
37101e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK		0x30000000
37201e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT		28
37301e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
37401e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK		0xc0000000
37501e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT		30
37601e04c3fSmrg#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
37701e04c3fSmrg
37801e04c3fSmrg#define VIVS_GL_UNK0382C					0x0000382c
37901e04c3fSmrg
38001e04c3fSmrg#define VIVS_GL_OCCLUSION_QUERY_CONTROL				0x00003830
38101e04c3fSmrg
3827ec681f3Smrg#define VIVS_GL_VARYING_NUM_COMPONENTS2				0x00003834
38301e04c3fSmrg
38401e04c3fSmrg#define VIVS_GL_UNK03838					0x00003838
38501e04c3fSmrg
38601e04c3fSmrg#define VIVS_GL_API_MODE					0x0000384c
38701e04c3fSmrg#define VIVS_GL_API_MODE_OPENGL					0x00000000
38801e04c3fSmrg#define VIVS_GL_API_MODE_OPENVG					0x00000001
38901e04c3fSmrg#define VIVS_GL_API_MODE_OPENCL					0x00000002
39001e04c3fSmrg
39101e04c3fSmrg#define VIVS_GL_CONTEXT_POINTER					0x00003850
39201e04c3fSmrg
39301e04c3fSmrg#define VIVS_GL_UNK03854					0x00003854
39401e04c3fSmrg
39501e04c3fSmrg#define VIVS_GL_BUG_FIXES					0x00003860
39601e04c3fSmrg
39701e04c3fSmrg#define VIVS_GL_FENCE_OUT_ADDRESS				0x00003868
39801e04c3fSmrg
39901e04c3fSmrg#define VIVS_GL_FENCE_OUT_DATA_LOW				0x0000386c
40001e04c3fSmrg
40101e04c3fSmrg#define VIVS_GL_HALTI5_UNK03884					0x00003884
40201e04c3fSmrg
40301e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS				0x00003888
40401e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK		0x0000007f
40501e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT		0
40601e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x)		(((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)
40701e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK		0x00007f00
40801e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT		8
40901e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x)		(((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)
41001e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK			0x007f0000
41101e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT			16
41201e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x)			(((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)
41301e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK			0xff000000
41401e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT			24
41501e04c3fSmrg#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x)			(((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)
41601e04c3fSmrg
41701e04c3fSmrg#define VIVS_GL_GS_UNK0388C					0x0000388c
41801e04c3fSmrg
41901e04c3fSmrg#define VIVS_GL_FENCE_OUT_DATA_HIGH				0x00003898
42001e04c3fSmrg
42101e04c3fSmrg#define VIVS_GL_SHADER_INDEX					0x0000389c
42201e04c3fSmrg
42301e04c3fSmrg#define VIVS_GL_GS_UNK038A0(i0)				       (0x000038a0 + 0x4*(i0))
42401e04c3fSmrg#define VIVS_GL_GS_UNK038A0__ESIZE				0x00000004
42501e04c3fSmrg#define VIVS_GL_GS_UNK038A0__LEN				0x00000008
42601e04c3fSmrg
42701e04c3fSmrg#define VIVS_GL_HALTI5_UNK038C0(i0)			       (0x000038c0 + 0x4*(i0))
42801e04c3fSmrg#define VIVS_GL_HALTI5_UNK038C0__ESIZE				0x00000004
42901e04c3fSmrg#define VIVS_GL_HALTI5_UNK038C0__LEN				0x00000010
43001e04c3fSmrg
43101e04c3fSmrg#define VIVS_GL_SECURITY_UNK3900				0x00003900
43201e04c3fSmrg
43301e04c3fSmrg#define VIVS_GL_SECURITY_UNK3904				0x00003904
43401e04c3fSmrg
43501e04c3fSmrg#define VIVS_GL_UNK03A00					0x00003a00
43601e04c3fSmrg
43701e04c3fSmrg#define VIVS_GL_UNK03A04					0x00003a04
43801e04c3fSmrg
43901e04c3fSmrg#define VIVS_GL_UNK03A08					0x00003a08
44001e04c3fSmrg
44101e04c3fSmrg#define VIVS_GL_UNK03A0C					0x00003a0c
44201e04c3fSmrg
44301e04c3fSmrg#define VIVS_GL_UNK03A10					0x00003a10
44401e04c3fSmrg
44501e04c3fSmrg#define VIVS_GL_STALL_TOKEN					0x00003c00
44601e04c3fSmrg#define VIVS_GL_STALL_TOKEN_FROM__MASK				0x0000001f
44701e04c3fSmrg#define VIVS_GL_STALL_TOKEN_FROM__SHIFT				0
44801e04c3fSmrg#define VIVS_GL_STALL_TOKEN_FROM(x)				(((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
44901e04c3fSmrg#define VIVS_GL_STALL_TOKEN_TO__MASK				0x00001f00
45001e04c3fSmrg#define VIVS_GL_STALL_TOKEN_TO__SHIFT				8
45101e04c3fSmrg#define VIVS_GL_STALL_TOKEN_TO(x)				(((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
45201e04c3fSmrg#define VIVS_GL_STALL_TOKEN_FLIP0				0x40000000
45301e04c3fSmrg#define VIVS_GL_STALL_TOKEN_FLIP1				0x80000000
45401e04c3fSmrg
45501e04c3fSmrg#define VIVS_NFE						0x00000000
45601e04c3fSmrg
45701e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS(i0)			       (0x00000000 + 0x4*(i0))
45801e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS__ESIZE				0x00000004
45901e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS__LEN				0x00000010
46001e04c3fSmrg
46101e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0)		       (0x00014600 + 0x4*(i0))
46201e04c3fSmrg
46301e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0)		       (0x00014640 + 0x4*(i0))
46401e04c3fSmrg
4657ec681f3Smrg#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0)	       (0x00014680 + 0x4*(i0))
46601e04c3fSmrg
46701e04c3fSmrg#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0)	       (0x000146c0 + 0x4*(i0))
46801e04c3fSmrg
46901e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB(i0)			       (0x00000000 + 0x4*(i0))
47001e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB__ESIZE				0x00000004
47101e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB__LEN				0x00000020
47201e04c3fSmrg
47301e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0)		       (0x00017800 + 0x4*(i0))
47401e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK		0x0000000f
47501e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT		0
47601e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
47701e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK		0x00000030
47801e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT		4
47901e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
48001e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK		0x00000700
48101e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT		8
48201e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
48301e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK		0x00003000
48401e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT		12
48501e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
48601e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK		0x0000c000
48701e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT	14
48801e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF		0x00000000
48901e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON		0x00008000
49001e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK		0x00ff0000
49101e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT		16
49201e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
49301e04c3fSmrg
49401e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0)		       (0x00017880 + 0x4*(i0))
49501e04c3fSmrg
49601e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0)		       (0x00017900 + 0x4*(i0))
49701e04c3fSmrg
49801e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0)		       (0x00017980 + 0x4*(i0))
49901e04c3fSmrg
50001e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0)		       (0x00017a00 + 0x4*(i0))
50101e04c3fSmrg
50201e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0)		       (0x00017a80 + 0x4*(i0))
50301e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK		0x000000ff
50401e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT		0
50501e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
50601e04c3fSmrg#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE		0x00000800
50701e04c3fSmrg
50801e04c3fSmrg#define VIVS_DUMMY						0x00000000
50901e04c3fSmrg
51001e04c3fSmrg#define VIVS_DUMMY_DUMMY					0x0003fffc
51101e04c3fSmrg
51201e04c3fSmrg
51301e04c3fSmrg#endif /* STATE_XML */
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