19f464c52Smaya/* 29f464c52Smaya * Copyright © 2018 Intel Corporation 39f464c52Smaya * 49f464c52Smaya * Permission is hereby granted, free of charge, to any person obtaining a 59f464c52Smaya * copy of this software and associated documentation files (the "Software"), 69f464c52Smaya * to deal in the Software without restriction, including without limitation 79f464c52Smaya * on the rights to use, copy, modify, merge, publish, distribute, sub 89f464c52Smaya * license, and/or sell copies of the Software, and to permit persons to whom 99f464c52Smaya * the Software is furnished to do so, subject to the following conditions: 109f464c52Smaya * 119f464c52Smaya * The above copyright notice and this permission notice (including the next 129f464c52Smaya * paragraph) shall be included in all copies or substantial portions of the 139f464c52Smaya * Software. 149f464c52Smaya * 159f464c52Smaya * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 169f464c52Smaya * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 179f464c52Smaya * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 189f464c52Smaya * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 199f464c52Smaya * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 209f464c52Smaya * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 219f464c52Smaya * USE OR OTHER DEALINGS IN THE SOFTWARE. 229f464c52Smaya */ 239f464c52Smaya#ifndef IRIS_DEFINES_H 249f464c52Smaya#define IRIS_DEFINES_H 259f464c52Smaya 269f464c52Smaya/** 279f464c52Smaya * @file iris_defines.h 289f464c52Smaya * 299f464c52Smaya * Random hardware #defines that we're not using GENXML for. 309f464c52Smaya */ 319f464c52Smaya 329f464c52Smaya#define MI_PREDICATE (0xC << 23) 339f464c52Smaya# define MI_PREDICATE_LOADOP_KEEP (0 << 6) 349f464c52Smaya# define MI_PREDICATE_LOADOP_LOAD (2 << 6) 359f464c52Smaya# define MI_PREDICATE_LOADOP_LOADINV (3 << 6) 369f464c52Smaya# define MI_PREDICATE_COMBINEOP_SET (0 << 3) 379f464c52Smaya# define MI_PREDICATE_COMBINEOP_AND (1 << 3) 389f464c52Smaya# define MI_PREDICATE_COMBINEOP_OR (2 << 3) 399f464c52Smaya# define MI_PREDICATE_COMBINEOP_XOR (3 << 3) 409f464c52Smaya# define MI_PREDICATE_COMPAREOP_TRUE (0 << 0) 419f464c52Smaya# define MI_PREDICATE_COMPAREOP_FALSE (1 << 0) 429f464c52Smaya# define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0) 439f464c52Smaya# define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0) 449f464c52Smaya 459f464c52Smaya/* Predicate registers */ 469f464c52Smaya#define MI_PREDICATE_SRC0 0x2400 479f464c52Smaya#define MI_PREDICATE_SRC1 0x2408 489f464c52Smaya#define MI_PREDICATE_DATA 0x2410 499f464c52Smaya#define MI_PREDICATE_RESULT 0x2418 509f464c52Smaya#define MI_PREDICATE_RESULT_1 0x241C 519f464c52Smaya#define MI_PREDICATE_RESULT_2 0x2214 529f464c52Smaya 539f464c52Smaya#define CS_GPR(n) (0x2600 + (n) * 8) 549f464c52Smaya 559f464c52Smaya/* The number of bits in our TIMESTAMP queries. */ 569f464c52Smaya#define TIMESTAMP_BITS 36 579f464c52Smaya 587ec681f3Smrg/* For gfx12 we set the streamout buffers using 4 separate commands 597ec681f3Smrg * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout 607ec681f3Smrg * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of 617ec681f3Smrg * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the 627ec681f3Smrg * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode. 637ec681f3Smrg * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for 647ec681f3Smrg * 3DSTATE_SO_BUFFER_INDEX_0. 657ec681f3Smrg */ 667ec681f3Smrg#define SO_BUFFER_INDEX_0_CMD 0x60 677ec681f3Smrg 689f464c52Smaya#endif 69