14a49301eSmrg/* 24a49301eSmrg * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 34a49301eSmrg * 44a49301eSmrg * Permission is hereby granted, free of charge, to any person obtaining a 54a49301eSmrg * copy of this software and associated documentation files (the "Software"), 64a49301eSmrg * to deal in the Software without restriction, including without limitation 74a49301eSmrg * on the rights to use, copy, modify, merge, publish, distribute, sub 84a49301eSmrg * license, and/or sell copies of the Software, and to permit persons to whom 94a49301eSmrg * the Software is furnished to do so, subject to the following conditions: 104a49301eSmrg * 114a49301eSmrg * The above copyright notice and this permission notice (including the next 124a49301eSmrg * paragraph) shall be included in all copies or substantial portions of the 134a49301eSmrg * Software. 144a49301eSmrg * 154a49301eSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 164a49301eSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 174a49301eSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 184a49301eSmrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 194a49301eSmrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 204a49301eSmrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 214a49301eSmrg * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 224a49301eSmrg 234a49301eSmrg#ifndef R300_CONTEXT_H 244a49301eSmrg#define R300_CONTEXT_H 254a49301eSmrg 26af69d88dSmrg#define R300_BUFFER_ALIGNMENT 64 27af69d88dSmrg 284a49301eSmrg#include "draw/draw_vertex.h" 294a49301eSmrg 30cdc920a0Smrg#include "util/u_blitter.h" 31cdc920a0Smrg 324a49301eSmrg#include "pipe/p_context.h" 33cdc920a0Smrg#include "util/u_inlines.h" 343464ebd5Sriastradh#include "util/u_transfer.h" 35cdc920a0Smrg 363464ebd5Sriastradh#include "r300_defines.h" 37cdc920a0Smrg#include "r300_screen.h" 38af69d88dSmrg#include "compiler/radeon_regalloc.h" 39cdc920a0Smrg 403464ebd5Sriastradhstruct u_upload_mgr; 41cdc920a0Smrgstruct r300_context; 424a49301eSmrgstruct r300_fragment_shader; 434a49301eSmrgstruct r300_vertex_shader; 443464ebd5Sriastradhstruct r300_stencilref_context; 454a49301eSmrg 46af69d88dSmrgenum colormask_swizzle { 47af69d88dSmrg COLORMASK_BGRA, 48af69d88dSmrg COLORMASK_RGBA, 49af69d88dSmrg COLORMASK_RRRR, 50af69d88dSmrg COLORMASK_AAAA, 51af69d88dSmrg COLORMASK_GRRG, 52af69d88dSmrg COLORMASK_ARRA, 53af69d88dSmrg COLORMASK_BGRX, 54af69d88dSmrg COLORMASK_RGBX, 55af69d88dSmrg COLORMASK_NUM_SWIZZLES 56af69d88dSmrg}; 57af69d88dSmrg 58cdc920a0Smrgstruct r300_atom { 59cdc920a0Smrg /* Name, for debugging. */ 60cdc920a0Smrg const char* name; 61cdc920a0Smrg /* Opaque state. */ 62cdc920a0Smrg void* state; 63cdc920a0Smrg /* Emit the state to the context. */ 64cdc920a0Smrg void (*emit)(struct r300_context*, unsigned, void*); 65cdc920a0Smrg /* Upper bound on number of dwords to emit. */ 66cdc920a0Smrg unsigned size; 67cdc920a0Smrg /* Whether this atom should be emitted. */ 68cdc920a0Smrg boolean dirty; 693464ebd5Sriastradh /* Whether this atom may be emitted with state == NULL. */ 703464ebd5Sriastradh boolean allow_null_state; 713464ebd5Sriastradh}; 723464ebd5Sriastradh 733464ebd5Sriastradhstruct r300_aa_state { 743464ebd5Sriastradh struct r300_surface *dest; 753464ebd5Sriastradh 763464ebd5Sriastradh uint32_t aa_config; 77cdc920a0Smrg}; 78cdc920a0Smrg 794a49301eSmrgstruct r300_blend_state { 803464ebd5Sriastradh struct pipe_blend_state state; 813464ebd5Sriastradh 82af69d88dSmrg uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8]; 833464ebd5Sriastradh uint32_t cb_noclamp[8]; 84af69d88dSmrg uint32_t cb_noclamp_noalpha[8]; 853464ebd5Sriastradh uint32_t cb_no_readwrite[8]; 864a49301eSmrg}; 874a49301eSmrg 884a49301eSmrgstruct r300_blend_color_state { 893464ebd5Sriastradh struct pipe_blend_color state; 903464ebd5Sriastradh uint32_t cb[3]; 913464ebd5Sriastradh}; 923464ebd5Sriastradh 933464ebd5Sriastradhstruct r300_clip_state { 943464ebd5Sriastradh uint32_t cb[29]; 954a49301eSmrg}; 964a49301eSmrg 974a49301eSmrgstruct r300_dsa_state { 983464ebd5Sriastradh struct pipe_depth_stencil_alpha_state dsa; 993464ebd5Sriastradh 1003464ebd5Sriastradh /* This is actually a command buffer with named dwords. */ 1013464ebd5Sriastradh uint32_t cb_begin; 1024a49301eSmrg uint32_t z_buffer_control; /* R300_ZB_CNTL: 0x4f00 */ 1034a49301eSmrg uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */ 1044a49301eSmrg uint32_t stencil_ref_mask; /* R300_ZB_STENCILREFMASK: 0x4f08 */ 1053464ebd5Sriastradh uint32_t cb_reg; 1064a49301eSmrg uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */ 1073464ebd5Sriastradh uint32_t cb_reg1; 1083464ebd5Sriastradh uint32_t alpha_value; /* R500_FG_ALPHA_VALUE: 0x4be0 */ 1093464ebd5Sriastradh 110af69d88dSmrg /* Same, but without ZB reads and writes. */ 111af69d88dSmrg uint32_t cb_zb_no_readwrite[8]; /* ZB not bound */ 112af69d88dSmrg 113af69d88dSmrg /* Emitted separately: */ 114af69d88dSmrg uint32_t alpha_function; 1153464ebd5Sriastradh 1163464ebd5Sriastradh /* Whether a two-sided stencil is enabled. */ 1173464ebd5Sriastradh boolean two_sided; 1183464ebd5Sriastradh /* Whether a fallback should be used for a two-sided stencil ref value. */ 1193464ebd5Sriastradh boolean two_sided_stencil_ref; 1203464ebd5Sriastradh}; 1213464ebd5Sriastradh 1223464ebd5Sriastradhstruct r300_hyperz_state { 1233464ebd5Sriastradh int flush; 1243464ebd5Sriastradh /* This is actually a command buffer with named dwords. */ 1253464ebd5Sriastradh uint32_t cb_flush_begin; 1263464ebd5Sriastradh uint32_t zb_zcache_ctlstat; /* R300_ZB_CACHE_CNTL */ 1273464ebd5Sriastradh uint32_t cb_begin; 1283464ebd5Sriastradh uint32_t zb_bw_cntl; /* R300_ZB_BW_CNTL */ 1293464ebd5Sriastradh uint32_t cb_reg1; 1303464ebd5Sriastradh uint32_t zb_depthclearvalue; /* R300_ZB_DEPTHCLEARVALUE */ 1313464ebd5Sriastradh uint32_t cb_reg2; 1323464ebd5Sriastradh uint32_t sc_hyperz; /* R300_SC_HYPERZ */ 1333464ebd5Sriastradh uint32_t cb_reg3; 1343464ebd5Sriastradh uint32_t gb_z_peq_config; /* R300_GB_Z_PEQ_CONFIG: 0x4028 */ 1353464ebd5Sriastradh}; 1363464ebd5Sriastradh 1373464ebd5Sriastradhstruct r300_gpu_flush { 1383464ebd5Sriastradh uint32_t cb_flush_clean[6]; 1394a49301eSmrg}; 1404a49301eSmrg 141af69d88dSmrg#define RS_STATE_MAIN_SIZE 27 1423464ebd5Sriastradh 1434a49301eSmrgstruct r300_rs_state { 1443464ebd5Sriastradh /* Original rasterizer state. */ 1454a49301eSmrg struct pipe_rasterizer_state rs; 1463464ebd5Sriastradh /* Draw-specific rasterizer state. */ 1473464ebd5Sriastradh struct pipe_rasterizer_state rs_draw; 1483464ebd5Sriastradh 1493464ebd5Sriastradh /* Command buffers. */ 1503464ebd5Sriastradh uint32_t cb_main[RS_STATE_MAIN_SIZE]; 1513464ebd5Sriastradh uint32_t cb_poly_offset_zb16[5]; 1523464ebd5Sriastradh uint32_t cb_poly_offset_zb24[5]; 1533464ebd5Sriastradh 1543464ebd5Sriastradh /* The index to cb_main where the cull_mode register value resides. */ 1553464ebd5Sriastradh unsigned cull_mode_index; 1563464ebd5Sriastradh 1573464ebd5Sriastradh /* Whether polygon offset is enabled. */ 1583464ebd5Sriastradh boolean polygon_offset_enable; 1594a49301eSmrg 1603464ebd5Sriastradh /* This is emitted in the draw function. */ 1614a49301eSmrg uint32_t color_control; /* R300_GA_COLOR_CONTROL: 0x4278 */ 1624a49301eSmrg}; 1634a49301eSmrg 1644a49301eSmrgstruct r300_rs_block { 1653464ebd5Sriastradh uint32_t vap_vtx_state_cntl; /* R300_VAP_VTX_STATE_CNTL: 0x2180 */ 1663464ebd5Sriastradh uint32_t vap_vsm_vtx_assm; /* R300_VAP_VSM_VTX_ASSM: 0x2184 */ 1673464ebd5Sriastradh uint32_t vap_out_vtx_fmt[2]; /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */ 1683464ebd5Sriastradh uint32_t gb_enable; 1693464ebd5Sriastradh 1704a49301eSmrg uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */ 1714a49301eSmrg uint32_t count; /* R300_RS_COUNT */ 1724a49301eSmrg uint32_t inst_count; /* R300_RS_INST_COUNT */ 1734a49301eSmrg uint32_t inst[8]; /* R300_RS_INST_[0-7] */ 1744a49301eSmrg}; 1754a49301eSmrg 1764a49301eSmrgstruct r300_sampler_state { 177cdc920a0Smrg struct pipe_sampler_state state; 178cdc920a0Smrg 1794a49301eSmrg uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */ 1804a49301eSmrg uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */ 1814a49301eSmrg 182cdc920a0Smrg /* Min/max LOD must be clamped to [0, last_level], thus 183cdc920a0Smrg * it's dependent on a currently bound texture */ 184cdc920a0Smrg unsigned min_lod, max_lod; 1854a49301eSmrg}; 1864a49301eSmrg 187cdc920a0Smrgstruct r300_texture_format_state { 1884a49301eSmrg uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */ 1894a49301eSmrg uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */ 1904a49301eSmrg uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */ 1913464ebd5Sriastradh uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */ 1923464ebd5Sriastradh uint32_t us_format0; /* R500_US_FORMAT0_0: 0x4640 (through 15) */ 1934a49301eSmrg}; 1944a49301eSmrg 1953464ebd5Sriastradhstruct r300_sampler_view { 1963464ebd5Sriastradh struct pipe_sampler_view base; 1973464ebd5Sriastradh 198af69d88dSmrg /* For resource_copy_region. */ 199af69d88dSmrg unsigned width0_override; 200af69d88dSmrg unsigned height0_override; 201af69d88dSmrg 20201e04c3fSmrg /* Swizzles in the PIPE_SWIZZLE_* representation, 2033464ebd5Sriastradh * derived from base. */ 2043464ebd5Sriastradh unsigned char swizzle[4]; 2053464ebd5Sriastradh 2063464ebd5Sriastradh /* Copy of r300_texture::texture_format_state with format-specific bits 2073464ebd5Sriastradh * added. */ 2083464ebd5Sriastradh struct r300_texture_format_state format; 2093464ebd5Sriastradh 2103464ebd5Sriastradh /* The texture cache region for this texture. */ 2113464ebd5Sriastradh uint32_t texcache_region; 2123464ebd5Sriastradh}; 213cdc920a0Smrg 2143464ebd5Sriastradhstruct r300_texture_sampler_state { 2153464ebd5Sriastradh struct r300_texture_format_state format; 2163464ebd5Sriastradh uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */ 2173464ebd5Sriastradh uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */ 2183464ebd5Sriastradh uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */ 219cdc920a0Smrg}; 220cdc920a0Smrg 221cdc920a0Smrgstruct r300_textures_state { 222cdc920a0Smrg /* Textures. */ 2233464ebd5Sriastradh struct r300_sampler_view *sampler_views[16]; 2243464ebd5Sriastradh int sampler_view_count; 225cdc920a0Smrg /* Sampler states. */ 2263464ebd5Sriastradh struct r300_sampler_state *sampler_states[16]; 2273464ebd5Sriastradh int sampler_state_count; 228cdc920a0Smrg 2293464ebd5Sriastradh /* This is the merge of the texture and sampler states. */ 230cdc920a0Smrg unsigned count; 231cdc920a0Smrg uint32_t tx_enable; /* R300_TX_ENABLE: 0x4101 */ 2323464ebd5Sriastradh struct r300_texture_sampler_state regs[16]; 233cdc920a0Smrg}; 234cdc920a0Smrg 235cdc920a0Smrgstruct r300_vertex_stream_state { 236cdc920a0Smrg /* R300_VAP_PROG_STREAK_CNTL_[0-7] */ 237cdc920a0Smrg uint32_t vap_prog_stream_cntl[8]; 238cdc920a0Smrg /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */ 239cdc920a0Smrg uint32_t vap_prog_stream_cntl_ext[8]; 240cdc920a0Smrg 241cdc920a0Smrg unsigned count; 242cdc920a0Smrg}; 243cdc920a0Smrg 2443464ebd5Sriastradhstruct r300_invariant_state { 2453464ebd5Sriastradh uint32_t cb[24]; 2463464ebd5Sriastradh}; 2473464ebd5Sriastradh 2483464ebd5Sriastradhstruct r300_vap_invariant_state { 2493464ebd5Sriastradh uint32_t cb[11]; 250cdc920a0Smrg}; 251cdc920a0Smrg 2524a49301eSmrgstruct r300_viewport_state { 2534a49301eSmrg float xscale; /* R300_VAP_VPORT_XSCALE: 0x2098 */ 2544a49301eSmrg float xoffset; /* R300_VAP_VPORT_XOFFSET: 0x209c */ 2554a49301eSmrg float yscale; /* R300_VAP_VPORT_YSCALE: 0x20a0 */ 2564a49301eSmrg float yoffset; /* R300_VAP_VPORT_YOFFSET: 0x20a4 */ 2574a49301eSmrg float zscale; /* R300_VAP_VPORT_ZSCALE: 0x20a8 */ 2584a49301eSmrg float zoffset; /* R300_VAP_VPORT_ZOFFSET: 0x20ac */ 2594a49301eSmrg uint32_t vte_control; /* R300_VAP_VTE_CNTL: 0x20b0 */ 2604a49301eSmrg}; 2614a49301eSmrg 2624a49301eSmrgstruct r300_ztop_state { 2634a49301eSmrg uint32_t z_buffer_top; /* R300_ZB_ZTOP: 0x4f14 */ 2644a49301eSmrg}; 2654a49301eSmrg 2664a49301eSmrg/* The next several objects are not pure Radeon state; they inherit from 2674a49301eSmrg * various Gallium classes. */ 2684a49301eSmrg 2694a49301eSmrgstruct r300_constant_buffer { 2704a49301eSmrg /* Buffer of constants */ 2713464ebd5Sriastradh uint32_t *ptr; 2723464ebd5Sriastradh /* Remapping table. */ 2733464ebd5Sriastradh unsigned *remap_table; 2743464ebd5Sriastradh /* const buffer base */ 2753464ebd5Sriastradh uint32_t buffer_base; 2764a49301eSmrg}; 2774a49301eSmrg 2784a49301eSmrg/* Query object. 2794a49301eSmrg * 2804a49301eSmrg * This is not a subclass of pipe_query because pipe_query is never 2814a49301eSmrg * actually fully defined. So, rather than have it as a member, and do 2824a49301eSmrg * subclass-style casting, we treat pipe_query as an opaque, and just 2837ec681f3Smrg * trust that our gallium frontend does not ever mess up query objects. 2844a49301eSmrg */ 2854a49301eSmrgstruct r300_query { 2864a49301eSmrg /* The kind of query. Currently only OQ is supported. */ 2874a49301eSmrg unsigned type; 2883464ebd5Sriastradh /* The number of pipes where query results are stored. */ 2893464ebd5Sriastradh unsigned num_pipes; 2903464ebd5Sriastradh /* How many results have been written, in dwords. It's incremented 2913464ebd5Sriastradh * after end_query and flush. */ 2923464ebd5Sriastradh unsigned num_results; 2934a49301eSmrg /* if begin has been emitted */ 2944a49301eSmrg boolean begin_emitted; 2953464ebd5Sriastradh 2963464ebd5Sriastradh /* The buffer where query results are stored. */ 2973464ebd5Sriastradh struct pb_buffer *buf; 2984a49301eSmrg}; 2994a49301eSmrg 3003464ebd5Sriastradhstruct r300_surface { 3013464ebd5Sriastradh struct pipe_surface base; 3023464ebd5Sriastradh 3033464ebd5Sriastradh /* Winsys buffer backing the texture. */ 3043464ebd5Sriastradh struct pb_buffer *buf; 3053464ebd5Sriastradh 3063464ebd5Sriastradh enum radeon_bo_domain domain; 3073464ebd5Sriastradh 3083464ebd5Sriastradh uint32_t offset; /* COLOROFFSET or DEPTHOFFSET. */ 3093464ebd5Sriastradh uint32_t pitch; /* COLORPITCH or DEPTHPITCH. */ 3103464ebd5Sriastradh uint32_t pitch_zmask; /* ZMASK_PITCH */ 3113464ebd5Sriastradh uint32_t pitch_hiz; /* HIZ_PITCH */ 312af69d88dSmrg uint32_t pitch_cmask; /* CMASK_PITCH */ 3133464ebd5Sriastradh uint32_t format; /* US_OUT_FMT or ZB_FORMAT. */ 3143464ebd5Sriastradh 3153464ebd5Sriastradh /* Parameters dedicated to the CBZB clear. */ 3163464ebd5Sriastradh uint32_t cbzb_width; /* Aligned width. */ 3173464ebd5Sriastradh uint32_t cbzb_height; /* Half of the height. */ 3183464ebd5Sriastradh uint32_t cbzb_midpoint_offset; /* DEPTHOFFSET. */ 3193464ebd5Sriastradh uint32_t cbzb_pitch; /* DEPTHPITCH. */ 3203464ebd5Sriastradh uint32_t cbzb_format; /* ZB_FORMAT. */ 3213464ebd5Sriastradh 3223464ebd5Sriastradh /* Whether the CBZB clear is allowed on the surface. */ 3233464ebd5Sriastradh boolean cbzb_allowed; 324af69d88dSmrg 325af69d88dSmrg unsigned colormask_swizzle; 326cdc920a0Smrg}; 327cdc920a0Smrg 3283464ebd5Sriastradhstruct r300_texture_desc { 3293464ebd5Sriastradh /* Width, height, and depth. 3303464ebd5Sriastradh * Most of the time, these are equal to pipe_texture::width0, height0, 3313464ebd5Sriastradh * and depth0. However, NPOT 3D textures must have dimensions aligned 3323464ebd5Sriastradh * to POT, and this is the only case when these variables differ from 3333464ebd5Sriastradh * pipe_texture. */ 3343464ebd5Sriastradh unsigned width0, height0, depth0; 3353464ebd5Sriastradh 3363464ebd5Sriastradh /* Buffer tiling. 3373464ebd5Sriastradh * Macrotiling is specified per-level because small mipmaps cannot 3383464ebd5Sriastradh * be macrotiled. */ 3393464ebd5Sriastradh enum radeon_bo_layout microtile; 3403464ebd5Sriastradh enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS]; 3414a49301eSmrg 3424a49301eSmrg /* Offsets into the buffer. */ 3433464ebd5Sriastradh unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS]; 3443464ebd5Sriastradh 3453464ebd5Sriastradh /* Strides for each mip-level. */ 3463464ebd5Sriastradh unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS]; 3474a49301eSmrg 3483464ebd5Sriastradh /* Size of one zslice or face or 2D image based on the texture target. */ 3493464ebd5Sriastradh unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS]; 3504a49301eSmrg 3513464ebd5Sriastradh /* Total size of this texture, in bytes, 3523464ebd5Sriastradh * derived from the texture properties. */ 3533464ebd5Sriastradh unsigned size_in_bytes; 3544a49301eSmrg 3554a49301eSmrg /** 3564a49301eSmrg * If non-zero, override the natural texture layout with 3574a49301eSmrg * a custom stride (in bytes). 3584a49301eSmrg * 3594a49301eSmrg * \note Mipmapping fails for textures with a non-natural layout! 3604a49301eSmrg * 3614a49301eSmrg * \sa r300_texture_get_stride 3624a49301eSmrg */ 3633464ebd5Sriastradh unsigned stride_in_bytes_override; 3644a49301eSmrg 3654a49301eSmrg /* Whether this texture has non-power-of-two dimensions. 3663464ebd5Sriastradh * It can be either a regular texture or a rectangle one. */ 3674a49301eSmrg boolean is_npot; 3684a49301eSmrg 3693464ebd5Sriastradh /* This flag says that hardware must use the stride for addressing 3703464ebd5Sriastradh * instead of the width. */ 3713464ebd5Sriastradh boolean uses_stride_addressing; 3723464ebd5Sriastradh 3733464ebd5Sriastradh /* Whether CBZB fast color clear is allowed on the miplevel. */ 3743464ebd5Sriastradh boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS]; 3753464ebd5Sriastradh 3763464ebd5Sriastradh /* Zbuffer compression info for each miplevel. */ 3773464ebd5Sriastradh boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS]; 3783464ebd5Sriastradh /* If zero, then disable Z compression/HiZ. */ 3793464ebd5Sriastradh unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS]; 3803464ebd5Sriastradh unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS]; 3813464ebd5Sriastradh /* Zmask/HiZ strides for each miplevel. */ 3823464ebd5Sriastradh unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS]; 3833464ebd5Sriastradh unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS]; 384af69d88dSmrg 385af69d88dSmrg /* CMASK info for AA buffers (no mipmapping). */ 386af69d88dSmrg unsigned cmask_dwords; 387af69d88dSmrg unsigned cmask_stride_in_pixels; 3883464ebd5Sriastradh}; 3893464ebd5Sriastradh 3903464ebd5Sriastradhstruct r300_resource 3913464ebd5Sriastradh{ 3927ec681f3Smrg struct pipe_resource b; 3933464ebd5Sriastradh 3943464ebd5Sriastradh /* Winsys buffer backing this resource. */ 3953464ebd5Sriastradh struct pb_buffer *buf; 3963464ebd5Sriastradh enum radeon_bo_domain domain; 3973464ebd5Sriastradh 398af69d88dSmrg /* Constant buffers and SWTCL vertex and index buffers are in user 399af69d88dSmrg * memory. */ 400af69d88dSmrg uint8_t *malloced_buffer; 4013464ebd5Sriastradh 4023464ebd5Sriastradh /* Texture description (addressing, layout, special features). */ 4033464ebd5Sriastradh struct r300_texture_desc tex; 4044a49301eSmrg 4053464ebd5Sriastradh /* This is the level tiling flags were last time set for. 4063464ebd5Sriastradh * It's used to prevent redundant tiling-flags changes from happening.*/ 4073464ebd5Sriastradh unsigned surface_level; 4083464ebd5Sriastradh}; 4093464ebd5Sriastradh 4103464ebd5Sriastradhstruct r300_vertex_element_state { 4113464ebd5Sriastradh unsigned count; 4123464ebd5Sriastradh struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS]; 4133464ebd5Sriastradh unsigned format_size[PIPE_MAX_ATTRIBS]; 4143464ebd5Sriastradh 4153464ebd5Sriastradh /* The size of the vertex, in dwords. */ 4163464ebd5Sriastradh unsigned vertex_size_dwords; 4173464ebd5Sriastradh 4183464ebd5Sriastradh struct r300_vertex_stream_state vertex_stream; 4194a49301eSmrg}; 4204a49301eSmrg 4213464ebd5Sriastradhenum r300_hiz_func { 4223464ebd5Sriastradh HIZ_FUNC_NONE, 4233464ebd5Sriastradh 4243464ebd5Sriastradh /* The function, when determined, is set in stone 4253464ebd5Sriastradh * until the next HiZ clear. */ 4263464ebd5Sriastradh 4273464ebd5Sriastradh /* MAX is written to the HiZ buffer. 4283464ebd5Sriastradh * Used for LESS, LEQUAL. */ 4293464ebd5Sriastradh HIZ_FUNC_MAX, 4303464ebd5Sriastradh 4313464ebd5Sriastradh /* MIN is written to the HiZ buffer. 4323464ebd5Sriastradh * Used for GREATER, GEQUAL. */ 4333464ebd5Sriastradh HIZ_FUNC_MIN, 4343464ebd5Sriastradh}; 4353464ebd5Sriastradh 4363464ebd5Sriastradh/* For deferred fragment shader state validation. */ 4373464ebd5Sriastradhenum r300_fs_validity_status { 4383464ebd5Sriastradh FRAGMENT_SHADER_VALID, /* No need to change/validate the FS. */ 4393464ebd5Sriastradh FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */ 4403464ebd5Sriastradh FRAGMENT_SHADER_DIRTY /* Always validate the FS (if the FS was changed) */ 4413464ebd5Sriastradh}; 4424a49301eSmrg 4434a49301eSmrgstruct r300_context { 4444a49301eSmrg /* Parent class */ 4454a49301eSmrg struct pipe_context context; 4464a49301eSmrg 4474a49301eSmrg /* The interface to the windowing system, etc. */ 4483464ebd5Sriastradh struct radeon_winsys *rws; 44901e04c3fSmrg /* The submission context. */ 45001e04c3fSmrg struct radeon_winsys_ctx *ctx; 4513464ebd5Sriastradh /* The command stream. */ 4527ec681f3Smrg struct radeon_cmdbuf cs; 4533464ebd5Sriastradh /* Screen. */ 4543464ebd5Sriastradh struct r300_screen *screen; 4553464ebd5Sriastradh 4564a49301eSmrg /* Draw module. Used mostly for SW TCL. */ 4574a49301eSmrg struct draw_context* draw; 4583464ebd5Sriastradh /* Vertex buffer for SW TCL. */ 459af69d88dSmrg struct pb_buffer *vbo; 4603464ebd5Sriastradh /* Offset and size into the SW TCL VBO. */ 4613464ebd5Sriastradh size_t draw_vbo_offset; 4623464ebd5Sriastradh 463cdc920a0Smrg /* Accelerated blit support. */ 464cdc920a0Smrg struct blitter_context* blitter; 4653464ebd5Sriastradh /* Stencil two-sided reference value fallback. */ 4663464ebd5Sriastradh struct r300_stencilref_context *stencilref_fallback; 4674a49301eSmrg 4683464ebd5Sriastradh /* The KIL opcode needs the first texture unit to be enabled 4693464ebd5Sriastradh * on r3xx-r4xx. In order to calm down the CS checker, we bind this 4703464ebd5Sriastradh * dummy texture there. */ 4713464ebd5Sriastradh struct r300_sampler_view *texkill_sampler; 4724a49301eSmrg 4733464ebd5Sriastradh /* When no vertex buffer is set, this one is used instead to prevent 4743464ebd5Sriastradh * hardlocks. */ 475af69d88dSmrg struct pipe_vertex_buffer dummy_vb; 4763464ebd5Sriastradh 4773464ebd5Sriastradh /* The currently active query. */ 4784a49301eSmrg struct r300_query *query_current; 4793464ebd5Sriastradh /* The saved query for blitter operations. */ 4803464ebd5Sriastradh struct r300_query *blitter_saved_query; 4813464ebd5Sriastradh /* Query list. */ 4824a49301eSmrg struct r300_query query_list; 4834a49301eSmrg 4844a49301eSmrg /* Various CSO state objects. */ 4853464ebd5Sriastradh 4863464ebd5Sriastradh /* Each atom is emitted in the order it appears here, which can affect 4873464ebd5Sriastradh * performance and stability if not handled with care. */ 4883464ebd5Sriastradh /* GPU flush. */ 4893464ebd5Sriastradh struct r300_atom gpu_flush; 490af69d88dSmrg /* Clears must be emitted immediately after the flush. */ 491af69d88dSmrg /* HiZ clear */ 492af69d88dSmrg struct r300_atom hiz_clear; 493af69d88dSmrg /* zmask clear */ 494af69d88dSmrg struct r300_atom zmask_clear; 495af69d88dSmrg /* cmask clear */ 496af69d88dSmrg struct r300_atom cmask_clear; 4973464ebd5Sriastradh /* Anti-aliasing (MSAA) state. */ 4983464ebd5Sriastradh struct r300_atom aa_state; 4993464ebd5Sriastradh /* Framebuffer state. */ 5003464ebd5Sriastradh struct r300_atom fb_state; 5013464ebd5Sriastradh /* HyperZ state (various SC/ZB bits). */ 5023464ebd5Sriastradh struct r300_atom hyperz_state; 5033464ebd5Sriastradh /* ZTOP state. */ 5043464ebd5Sriastradh struct r300_atom ztop_state; 5053464ebd5Sriastradh /* Depth, stencil, and alpha state. */ 5063464ebd5Sriastradh struct r300_atom dsa_state; 5074a49301eSmrg /* Blend state. */ 508cdc920a0Smrg struct r300_atom blend_state; 5094a49301eSmrg /* Blend color state. */ 510cdc920a0Smrg struct r300_atom blend_color_state; 5114a49301eSmrg /* Scissor state. */ 512cdc920a0Smrg struct r300_atom scissor_state; 513af69d88dSmrg /* Sample mask. */ 514af69d88dSmrg struct r300_atom sample_mask; 5153464ebd5Sriastradh /* Invariant state. This must be emitted to get the engine started. */ 5163464ebd5Sriastradh struct r300_atom invariant_state; 5174a49301eSmrg /* Viewport state. */ 518cdc920a0Smrg struct r300_atom viewport_state; 519cdc920a0Smrg /* PVS flush. */ 520cdc920a0Smrg struct r300_atom pvs_flush; 5213464ebd5Sriastradh /* VAP invariant state. */ 5223464ebd5Sriastradh struct r300_atom vap_invariant_state; 5233464ebd5Sriastradh /* Vertex stream formatting state. */ 5243464ebd5Sriastradh struct r300_atom vertex_stream_state; 5253464ebd5Sriastradh /* Vertex shader. */ 5263464ebd5Sriastradh struct r300_atom vs_state; 5273464ebd5Sriastradh /* User clip planes. */ 5283464ebd5Sriastradh struct r300_atom clip_state; 5293464ebd5Sriastradh /* RS block state + VAP (vertex shader) output mapping state. */ 5303464ebd5Sriastradh struct r300_atom rs_block_state; 5313464ebd5Sriastradh /* Rasterizer state. */ 5323464ebd5Sriastradh struct r300_atom rs_state; 5333464ebd5Sriastradh /* Framebuffer state (pipelined regs). */ 5343464ebd5Sriastradh struct r300_atom fb_state_pipelined; 5353464ebd5Sriastradh /* Fragment shader. */ 5363464ebd5Sriastradh struct r300_atom fs; 5373464ebd5Sriastradh /* Fragment shader RC_CONSTANT_STATE variables. */ 5383464ebd5Sriastradh struct r300_atom fs_rc_constant_state; 5393464ebd5Sriastradh /* Fragment shader constant buffer. */ 5403464ebd5Sriastradh struct r300_atom fs_constants; 5413464ebd5Sriastradh /* Vertex shader constant buffer. */ 5423464ebd5Sriastradh struct r300_atom vs_constants; 543cdc920a0Smrg /* Texture cache invalidate. */ 544cdc920a0Smrg struct r300_atom texture_cache_inval; 5453464ebd5Sriastradh /* Textures state. */ 5463464ebd5Sriastradh struct r300_atom textures_state; 5473464ebd5Sriastradh /* Occlusion query. */ 5483464ebd5Sriastradh struct r300_atom query_start; 549cdc920a0Smrg 5503464ebd5Sriastradh /* The pointers to the first and the last atom. */ 5513464ebd5Sriastradh struct r300_atom *first_dirty, *last_dirty; 5524a49301eSmrg 5534a49301eSmrg /* Vertex elements for Gallium. */ 5543464ebd5Sriastradh struct r300_vertex_element_state *velems; 5553464ebd5Sriastradh 556cdc920a0Smrg /* Vertex info for Draw. */ 557cdc920a0Smrg struct vertex_info vertex_info; 558cdc920a0Smrg 559cdc920a0Smrg struct pipe_stencil_ref stencil_ref; 560cdc920a0Smrg struct pipe_viewport_state viewport; 561cdc920a0Smrg 5623464ebd5Sriastradh /* Stream locations for SWTCL. */ 5633464ebd5Sriastradh int stream_loc_notcl[16]; 5643464ebd5Sriastradh 5654a49301eSmrg /* Flag indicating whether or not the HW is dirty. */ 5664a49301eSmrg uint32_t dirty_hw; 567cdc920a0Smrg /* Whether polygon offset is enabled. */ 568cdc920a0Smrg boolean polygon_offset_enabled; 569cdc920a0Smrg /* Z buffer bit depth. */ 570cdc920a0Smrg uint32_t zbuffer_bpp; 5713464ebd5Sriastradh /* Whether rendering is conditional and should be skipped. */ 5723464ebd5Sriastradh boolean skip_rendering; 5733464ebd5Sriastradh /* The flag above saved by blitter. */ 5743464ebd5Sriastradh unsigned char blitter_saved_skip_rendering; 5753464ebd5Sriastradh /* Point sprites texcoord index, 1 bit per texcoord */ 5763464ebd5Sriastradh int sprite_coord_enable; 5773464ebd5Sriastradh /* Whether two-sided color selection is enabled (AKA light_twoside). */ 5783464ebd5Sriastradh boolean two_sided_color; 579af69d88dSmrg boolean flatshade; 58001e04c3fSmrg boolean clip_halfz; 5813464ebd5Sriastradh /* Whether fast color clear is enabled. */ 5823464ebd5Sriastradh boolean cbzb_clear; 5833464ebd5Sriastradh /* Whether fragment shader needs to be validated. */ 5843464ebd5Sriastradh enum r300_fs_validity_status fs_status; 5853464ebd5Sriastradh /* Framebuffer multi-write. */ 5863464ebd5Sriastradh boolean fb_multiwrite; 587af69d88dSmrg unsigned num_samples; 588af69d88dSmrg boolean msaa_enable; 589af69d88dSmrg boolean alpha_to_one; 590af69d88dSmrg boolean alpha_to_coverage; 5913464ebd5Sriastradh 5923464ebd5Sriastradh void *dsa_decompress_zmask; 5933464ebd5Sriastradh 594af69d88dSmrg struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 595af69d88dSmrg unsigned nr_vertex_buffers; 596af69d88dSmrg struct u_upload_mgr *uploader; 5973464ebd5Sriastradh 59801e04c3fSmrg struct slab_child_pool pool_transfers; 5993464ebd5Sriastradh 6003464ebd5Sriastradh /* Stat counter. */ 6013464ebd5Sriastradh uint64_t flush_counter; 6023464ebd5Sriastradh 6033464ebd5Sriastradh /* const tracking for VS */ 6043464ebd5Sriastradh int vs_const_base; 6053464ebd5Sriastradh 6063464ebd5Sriastradh /* Vertex array state info */ 6073464ebd5Sriastradh boolean vertex_arrays_dirty; 6083464ebd5Sriastradh boolean vertex_arrays_indexed; 6093464ebd5Sriastradh int vertex_arrays_offset; 6103464ebd5Sriastradh int vertex_arrays_instance_id; 6113464ebd5Sriastradh boolean instancing_enabled; 6123464ebd5Sriastradh 6133464ebd5Sriastradh /* Hyper-Z stats. */ 6143464ebd5Sriastradh boolean hyperz_enabled; /* Whether it owns Hyper-Z access. */ 6153464ebd5Sriastradh int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */ 6163464ebd5Sriastradh unsigned num_z_clears; /* Since the last flush. */ 6173464ebd5Sriastradh 6183464ebd5Sriastradh /* ZMask state. */ 6193464ebd5Sriastradh boolean zmask_in_use; /* Whether ZMASK is enabled. */ 6203464ebd5Sriastradh boolean zmask_decompress; /* Whether ZMASK is being decompressed. */ 6213464ebd5Sriastradh struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */ 6223464ebd5Sriastradh 6233464ebd5Sriastradh /* HiZ state. */ 6243464ebd5Sriastradh boolean hiz_in_use; /* Whether HIZ is enabled. */ 6253464ebd5Sriastradh enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */ 6263464ebd5Sriastradh uint32_t hiz_clear_value; /* HiZ clear value. */ 627af69d88dSmrg 628af69d88dSmrg /* CMASK state. */ 629af69d88dSmrg boolean cmask_access; 630af69d88dSmrg boolean cmask_in_use; 631af69d88dSmrg uint32_t color_clear_value; /* RGBA8 or RGBA1010102 */ 632af69d88dSmrg uint32_t color_clear_value_ar; /* RGBA16F */ 633af69d88dSmrg uint32_t color_clear_value_gb; /* RGBA16F */ 634af69d88dSmrg 635af69d88dSmrg /* Compiler state. */ 636af69d88dSmrg struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for 637af69d88dSmrg * fragment shaders. */ 6384a49301eSmrg}; 6394a49301eSmrg 6403464ebd5Sriastradh#define foreach_atom(r300, atom) \ 6413464ebd5Sriastradh for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++) 6423464ebd5Sriastradh 6433464ebd5Sriastradh#define foreach_dirty_atom(r300, atom) \ 6443464ebd5Sriastradh for (atom = r300->first_dirty; atom != r300->last_dirty; atom++) 6453464ebd5Sriastradh 6463464ebd5Sriastradh/* Convenience cast wrappers. */ 64701e04c3fSmrgstatic inline struct r300_query* r300_query(struct pipe_query* q) 6483464ebd5Sriastradh{ 6493464ebd5Sriastradh return (struct r300_query*)q; 6503464ebd5Sriastradh} 6513464ebd5Sriastradh 65201e04c3fSmrgstatic inline struct r300_surface* r300_surface(struct pipe_surface* surf) 6533464ebd5Sriastradh{ 6543464ebd5Sriastradh return (struct r300_surface*)surf; 6553464ebd5Sriastradh} 6563464ebd5Sriastradh 65701e04c3fSmrgstatic inline struct r300_resource* r300_resource(struct pipe_resource* tex) 6583464ebd5Sriastradh{ 6593464ebd5Sriastradh return (struct r300_resource*)tex; 6603464ebd5Sriastradh} 6613464ebd5Sriastradh 66201e04c3fSmrgstatic inline struct r300_context* r300_context(struct pipe_context* context) 6634a49301eSmrg{ 6644a49301eSmrg return (struct r300_context*)context; 6654a49301eSmrg} 6664a49301eSmrg 66701e04c3fSmrgstatic inline struct r300_fragment_shader *r300_fs(struct r300_context *r300) 6683464ebd5Sriastradh{ 6693464ebd5Sriastradh return (struct r300_fragment_shader*)r300->fs.state; 6703464ebd5Sriastradh} 6713464ebd5Sriastradh 67201e04c3fSmrgstatic inline void r300_mark_atom_dirty(struct r300_context *r300, 6733464ebd5Sriastradh struct r300_atom *atom) 6743464ebd5Sriastradh{ 6753464ebd5Sriastradh atom->dirty = TRUE; 6763464ebd5Sriastradh 6773464ebd5Sriastradh if (!r300->first_dirty) { 6783464ebd5Sriastradh r300->first_dirty = atom; 6793464ebd5Sriastradh r300->last_dirty = atom+1; 6803464ebd5Sriastradh } else { 6813464ebd5Sriastradh if (atom < r300->first_dirty) 6823464ebd5Sriastradh r300->first_dirty = atom; 6833464ebd5Sriastradh else if (atom+1 > r300->last_dirty) 6843464ebd5Sriastradh r300->last_dirty = atom+1; 6853464ebd5Sriastradh } 6863464ebd5Sriastradh} 687cdc920a0Smrg 68801e04c3fSmrgstatic inline struct pipe_surface * 689af69d88dSmrgr300_get_nonnull_cb(struct pipe_framebuffer_state *fb, unsigned i) 690af69d88dSmrg{ 691af69d88dSmrg if (fb->cbufs[i]) 692af69d88dSmrg return fb->cbufs[i]; 693af69d88dSmrg 694af69d88dSmrg /* The i-th framebuffer is NULL, return any non-NULL one. */ 695af69d88dSmrg for (i = 0; i < fb->nr_cbufs; i++) 696af69d88dSmrg if (fb->cbufs[i]) 697af69d88dSmrg return fb->cbufs[i]; 698af69d88dSmrg 699af69d88dSmrg return NULL; 700af69d88dSmrg} 701af69d88dSmrg 702cdc920a0Smrgstruct pipe_context* r300_create_context(struct pipe_screen* screen, 70301e04c3fSmrg void *priv, unsigned flags); 704cdc920a0Smrg 7054a49301eSmrg/* Context initialization. */ 7064a49301eSmrgstruct draw_stage* r300_draw_stage(struct r300_context* r300); 7073464ebd5Sriastradhvoid r300_init_blit_functions(struct r300_context *r300); 7083464ebd5Sriastradhvoid r300_init_flush_functions(struct r300_context* r300); 7093464ebd5Sriastradhvoid r300_init_query_functions(struct r300_context* r300); 7103464ebd5Sriastradhvoid r300_init_render_functions(struct r300_context *r300); 7114a49301eSmrgvoid r300_init_state_functions(struct r300_context* r300); 7123464ebd5Sriastradhvoid r300_init_resource_functions(struct r300_context* r300); 7133464ebd5Sriastradh 7143464ebd5Sriastradh/* r300_blit.c */ 7153464ebd5Sriastradhvoid r300_decompress_zmask(struct r300_context *r300); 7163464ebd5Sriastradhvoid r300_decompress_zmask_locked_unsafe(struct r300_context *r300); 7173464ebd5Sriastradhvoid r300_decompress_zmask_locked(struct r300_context *r300); 718af69d88dSmrgbool r300_is_blit_supported(enum pipe_format format); 7193464ebd5Sriastradh 7203464ebd5Sriastradh/* r300_flush.c */ 7213464ebd5Sriastradhvoid r300_flush(struct pipe_context *pipe, 7223464ebd5Sriastradh unsigned flags, 7233464ebd5Sriastradh struct pipe_fence_handle **fence); 7243464ebd5Sriastradh 7253464ebd5Sriastradh/* r300_hyperz.c */ 7263464ebd5Sriastradhvoid r300_update_hyperz_state(struct r300_context* r300); 7273464ebd5Sriastradh 7283464ebd5Sriastradh/* r300_query.c */ 7293464ebd5Sriastradhvoid r300_resume_query(struct r300_context *r300, 7303464ebd5Sriastradh struct r300_query *query); 7313464ebd5Sriastradhvoid r300_stop_query(struct r300_context *r300); 7323464ebd5Sriastradh 7333464ebd5Sriastradh/* r300_render_translate.c */ 7343464ebd5Sriastradhvoid r300_translate_index_buffer(struct r300_context *r300, 73501e04c3fSmrg const struct pipe_draw_info *info, 736af69d88dSmrg struct pipe_resource **out_index_buffer, 7373464ebd5Sriastradh unsigned *index_size, unsigned index_offset, 7383464ebd5Sriastradh unsigned *start, unsigned count); 7393464ebd5Sriastradh 7403464ebd5Sriastradh/* r300_render_stencilref.c */ 7413464ebd5Sriastradhvoid r300_plug_in_stencil_ref_fallback(struct r300_context *r300); 7423464ebd5Sriastradh 7433464ebd5Sriastradh/* r300_render.c */ 7443464ebd5Sriastradhvoid r500_emit_index_bias(struct r300_context *r300, int index_bias); 745af69d88dSmrgvoid r300_blitter_draw_rectangle(struct blitter_context *blitter, 74601e04c3fSmrg void *vertex_elements_cso, 74701e04c3fSmrg blitter_get_vs_func get_vs, 748af69d88dSmrg int x1, int y1, int x2, int y2, 74901e04c3fSmrg float depth, unsigned num_instances, 750af69d88dSmrg enum blitter_attrib_type type, 75101e04c3fSmrg const union blitter_attrib *attrib); 7523464ebd5Sriastradh 7533464ebd5Sriastradh/* r300_state.c */ 7543464ebd5Sriastradhenum r300_fb_state_change { 7553464ebd5Sriastradh R300_CHANGED_FB_STATE = 0, 7563464ebd5Sriastradh R300_CHANGED_HYPERZ_FLAG, 757af69d88dSmrg R300_CHANGED_MULTIWRITE, 758af69d88dSmrg R300_CHANGED_CMASK_ENABLE, 7593464ebd5Sriastradh}; 7603464ebd5Sriastradh 7613464ebd5Sriastradhvoid r300_mark_fb_state_dirty(struct r300_context *r300, 7623464ebd5Sriastradh enum r300_fb_state_change change); 7633464ebd5Sriastradhvoid r300_mark_fs_code_dirty(struct r300_context *r300); 7643464ebd5Sriastradh 765af69d88dSmrgstruct pipe_sampler_view * 766af69d88dSmrgr300_create_sampler_view_custom(struct pipe_context *pipe, 767af69d88dSmrg struct pipe_resource *texture, 768af69d88dSmrg const struct pipe_sampler_view *templ, 769af69d88dSmrg unsigned width0_override, 770af69d88dSmrg unsigned height0_override); 771af69d88dSmrg 7723464ebd5Sriastradh/* r300_state_derived.c */ 7733464ebd5Sriastradhvoid r300_update_derived_state(struct r300_context* r300); 7743464ebd5Sriastradh 7753464ebd5Sriastradh/* r300_debug.c */ 7763464ebd5Sriastradhvoid r500_dump_rs_block(struct r300_rs_block *rs); 7773464ebd5Sriastradh 7784a49301eSmrg 77901e04c3fSmrgstatic inline boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags) 7804a49301eSmrg{ 7813464ebd5Sriastradh return SCREEN_DBG_ON(ctx->screen, flags); 7824a49301eSmrg} 7834a49301eSmrg 78401e04c3fSmrgstatic inline void CTX_DBG(struct r300_context * ctx, unsigned flags, 785cdc920a0Smrg const char * fmt, ...) 7864a49301eSmrg{ 787cdc920a0Smrg if (CTX_DBG_ON(ctx, flags)) { 7884a49301eSmrg va_list va; 7894a49301eSmrg va_start(va, fmt); 7903464ebd5Sriastradh vfprintf(stderr, fmt, va); 7914a49301eSmrg va_end(va); 7924a49301eSmrg } 7934a49301eSmrg} 7944a49301eSmrg 795cdc920a0Smrg#define DBG_ON CTX_DBG_ON 796cdc920a0Smrg#define DBG CTX_DBG 7974a49301eSmrg 7984a49301eSmrg#endif /* R300_CONTEXT_H */ 799