1af69d88dSmrg/**************************************************************************
2af69d88dSmrg *
3af69d88dSmrg * Copyright 2011 Advanced Micro Devices, Inc.
4af69d88dSmrg * All Rights Reserved.
5af69d88dSmrg *
6af69d88dSmrg * Permission is hereby granted, free of charge, to any person obtaining a
7af69d88dSmrg * copy of this software and associated documentation files (the
8af69d88dSmrg * "Software"), to deal in the Software without restriction, including
9af69d88dSmrg * without limitation the rights to use, copy, modify, merge, publish,
10af69d88dSmrg * distribute, sub license, and/or sell copies of the Software, and to
11af69d88dSmrg * permit persons to whom the Software is furnished to do so, subject to
12af69d88dSmrg * the following conditions:
13af69d88dSmrg *
14af69d88dSmrg * The above copyright notice and this permission notice (including the
15af69d88dSmrg * next paragraph) shall be included in all copies or substantial portions
16af69d88dSmrg * of the Software.
17af69d88dSmrg *
18af69d88dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19af69d88dSmrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20af69d88dSmrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21af69d88dSmrg * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22af69d88dSmrg * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23af69d88dSmrg * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24af69d88dSmrg * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25af69d88dSmrg *
26af69d88dSmrg **************************************************************************/
27af69d88dSmrg
287ec681f3Smrg#include "radeon_uvd.h"
29af69d88dSmrg
30af69d88dSmrg#include "pipe/p_video_codec.h"
317ec681f3Smrg#include "radeon_video.h"
327ec681f3Smrg#include "radeonsi/si_pipe.h"
33af69d88dSmrg#include "util/u_memory.h"
34af69d88dSmrg#include "util/u_video.h"
35af69d88dSmrg#include "vl/vl_defines.h"
36af69d88dSmrg#include "vl/vl_mpeg12_decoder.h"
377ec681f3Smrg#include <sys/types.h>
38af69d88dSmrg
397ec681f3Smrg#include <assert.h>
407ec681f3Smrg#include <errno.h>
417ec681f3Smrg#include <stdio.h>
427ec681f3Smrg#include <unistd.h>
43af69d88dSmrg
44af69d88dSmrg#define NUM_BUFFERS 4
45af69d88dSmrg
46af69d88dSmrg#define NUM_MPEG2_REFS 6
477ec681f3Smrg#define NUM_H264_REFS  17
487ec681f3Smrg#define NUM_VC1_REFS   5
49af69d88dSmrg
507ec681f3Smrg#define FB_BUFFER_OFFSET         0x1000
517ec681f3Smrg#define FB_BUFFER_SIZE           2048
527ec681f3Smrg#define FB_BUFFER_SIZE_TONGA     (2048 * 64)
537ec681f3Smrg#define IT_SCALING_TABLE_SIZE    992
5401e04c3fSmrg#define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
55af69d88dSmrg
56af69d88dSmrg/* UVD decoder representation */
57af69d88dSmrgstruct ruvd_decoder {
587ec681f3Smrg   struct pipe_video_codec base;
597ec681f3Smrg
607ec681f3Smrg   ruvd_set_dtb set_dtb;
617ec681f3Smrg
627ec681f3Smrg   unsigned stream_handle;
637ec681f3Smrg   unsigned stream_type;
647ec681f3Smrg   unsigned frame_number;
657ec681f3Smrg
667ec681f3Smrg   struct pipe_screen *screen;
677ec681f3Smrg   struct radeon_winsys *ws;
687ec681f3Smrg   struct radeon_cmdbuf cs;
697ec681f3Smrg
707ec681f3Smrg   unsigned cur_buffer;
717ec681f3Smrg
727ec681f3Smrg   struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
737ec681f3Smrg   struct ruvd_msg *msg;
747ec681f3Smrg   uint32_t *fb;
757ec681f3Smrg   unsigned fb_size;
767ec681f3Smrg   uint8_t *it;
777ec681f3Smrg
787ec681f3Smrg   struct rvid_buffer bs_buffers[NUM_BUFFERS];
797ec681f3Smrg   void *bs_ptr;
807ec681f3Smrg   unsigned bs_size;
817ec681f3Smrg
827ec681f3Smrg   struct rvid_buffer dpb;
837ec681f3Smrg   bool use_legacy;
847ec681f3Smrg   struct rvid_buffer ctx;
857ec681f3Smrg   struct rvid_buffer sessionctx;
867ec681f3Smrg   struct {
877ec681f3Smrg      unsigned data0;
887ec681f3Smrg      unsigned data1;
897ec681f3Smrg      unsigned cmd;
907ec681f3Smrg      unsigned cntl;
917ec681f3Smrg   } reg;
927ec681f3Smrg
937ec681f3Smrg   void *render_pic_list[16];
94af69d88dSmrg};
95af69d88dSmrg
96af69d88dSmrg/* flush IB to the hardware */
9701e04c3fSmrgstatic int flush(struct ruvd_decoder *dec, unsigned flags)
98af69d88dSmrg{
997ec681f3Smrg   return dec->ws->cs_flush(&dec->cs, flags, NULL);
100af69d88dSmrg}
101af69d88dSmrg
102af69d88dSmrg/* add a new set register command to the IB */
103af69d88dSmrgstatic void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
104af69d88dSmrg{
1057ec681f3Smrg   radeon_emit(&dec->cs, RUVD_PKT0(reg >> 2, 0));
1067ec681f3Smrg   radeon_emit(&dec->cs, val);
107af69d88dSmrg}
108af69d88dSmrg
109af69d88dSmrg/* send a command to the VCPU through the GPCOM registers */
1107ec681f3Smrgstatic void send_cmd(struct ruvd_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
1117ec681f3Smrg                     enum radeon_bo_usage usage, enum radeon_bo_domain domain)
112af69d88dSmrg{
1137ec681f3Smrg   int reloc_idx;
1147ec681f3Smrg
1157ec681f3Smrg   reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
1167ec681f3Smrg   if (!dec->use_legacy) {
1177ec681f3Smrg      uint64_t addr;
1187ec681f3Smrg      addr = dec->ws->buffer_get_virtual_address(buf);
1197ec681f3Smrg      addr = addr + off;
1207ec681f3Smrg      set_reg(dec, dec->reg.data0, addr);
1217ec681f3Smrg      set_reg(dec, dec->reg.data1, addr >> 32);
1227ec681f3Smrg   } else {
1237ec681f3Smrg      off += dec->ws->buffer_get_reloc_offset(buf);
1247ec681f3Smrg      set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
1257ec681f3Smrg      set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
1267ec681f3Smrg   }
1277ec681f3Smrg   set_reg(dec, dec->reg.cmd, cmd << 1);
12801e04c3fSmrg}
12901e04c3fSmrg
13001e04c3fSmrg/* do the codec needs an IT buffer ?*/
13101e04c3fSmrgstatic bool have_it(struct ruvd_decoder *dec)
13201e04c3fSmrg{
1337ec681f3Smrg   return dec->stream_type == RUVD_CODEC_H264_PERF || dec->stream_type == RUVD_CODEC_H265;
134af69d88dSmrg}
135af69d88dSmrg
13601e04c3fSmrg/* map the next available message/feedback/itscaling buffer */
13701e04c3fSmrgstatic void map_msg_fb_it_buf(struct ruvd_decoder *dec)
138af69d88dSmrg{
1397ec681f3Smrg   struct rvid_buffer *buf;
1407ec681f3Smrg   uint8_t *ptr;
141af69d88dSmrg
1427ec681f3Smrg   /* grab the current message/feedback buffer */
1437ec681f3Smrg   buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
144af69d88dSmrg
1457ec681f3Smrg   /* and map it for CPU access */
1467ec681f3Smrg   ptr =
1477ec681f3Smrg      dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
148af69d88dSmrg
1497ec681f3Smrg   /* calc buffer offsets */
1507ec681f3Smrg   dec->msg = (struct ruvd_msg *)ptr;
1517ec681f3Smrg   memset(dec->msg, 0, sizeof(*dec->msg));
15201e04c3fSmrg
1537ec681f3Smrg   dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1547ec681f3Smrg   if (have_it(dec))
1557ec681f3Smrg      dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
156af69d88dSmrg}
157af69d88dSmrg
158af69d88dSmrg/* unmap and send a message command to the VCPU */
159af69d88dSmrgstatic void send_msg_buf(struct ruvd_decoder *dec)
160af69d88dSmrg{
1617ec681f3Smrg   struct rvid_buffer *buf;
162af69d88dSmrg
1637ec681f3Smrg   /* ignore the request if message/feedback buffer isn't mapped */
1647ec681f3Smrg   if (!dec->msg || !dec->fb)
1657ec681f3Smrg      return;
166af69d88dSmrg
1677ec681f3Smrg   /* grab the current message buffer */
1687ec681f3Smrg   buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
16901e04c3fSmrg
1707ec681f3Smrg   /* unmap the buffer */
1717ec681f3Smrg   dec->ws->buffer_unmap(dec->ws, buf->res->buf);
1727ec681f3Smrg   dec->msg = NULL;
1737ec681f3Smrg   dec->fb = NULL;
1747ec681f3Smrg   dec->it = NULL;
17501e04c3fSmrg
1767ec681f3Smrg   if (dec->sessionctx.res)
1777ec681f3Smrg      send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
1787ec681f3Smrg               RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
179af69d88dSmrg
1807ec681f3Smrg   /* and send it to the hardware */
1817ec681f3Smrg   send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
182af69d88dSmrg}
183af69d88dSmrg
184af69d88dSmrg/* cycle to the next set of buffers */
185af69d88dSmrgstatic void next_buffer(struct ruvd_decoder *dec)
186af69d88dSmrg{
1877ec681f3Smrg   ++dec->cur_buffer;
1887ec681f3Smrg   dec->cur_buffer %= NUM_BUFFERS;
189af69d88dSmrg}
190af69d88dSmrg
191af69d88dSmrg/* convert the profile into something UVD understands */
19201e04c3fSmrgstatic uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
193af69d88dSmrg{
1947ec681f3Smrg   switch (u_reduce_video_profile(dec->base.profile)) {
1957ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1967ec681f3Smrg      return (family >= CHIP_TONGA) ? RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
197af69d88dSmrg
1987ec681f3Smrg   case PIPE_VIDEO_FORMAT_VC1:
1997ec681f3Smrg      return RUVD_CODEC_VC1;
200af69d88dSmrg
2017ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG12:
2027ec681f3Smrg      return RUVD_CODEC_MPEG2;
203af69d88dSmrg
2047ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4:
2057ec681f3Smrg      return RUVD_CODEC_MPEG4;
206af69d88dSmrg
2077ec681f3Smrg   case PIPE_VIDEO_FORMAT_HEVC:
2087ec681f3Smrg      return RUVD_CODEC_H265;
20901e04c3fSmrg
2107ec681f3Smrg   case PIPE_VIDEO_FORMAT_JPEG:
2117ec681f3Smrg      return RUVD_CODEC_MJPEG;
21201e04c3fSmrg
2137ec681f3Smrg   default:
2147ec681f3Smrg      assert(0);
2157ec681f3Smrg      return 0;
2167ec681f3Smrg   }
217af69d88dSmrg}
218af69d88dSmrg
21901e04c3fSmrgstatic unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
22001e04c3fSmrg{
2217ec681f3Smrg   unsigned width_in_mb, height_in_mb, ctx_size;
2227ec681f3Smrg   unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
2237ec681f3Smrg   unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
2247ec681f3Smrg
2257ec681f3Smrg   unsigned max_references = dec->base.max_references + 1;
2267ec681f3Smrg
2277ec681f3Smrg   // picture width & height in 16 pixel units
2287ec681f3Smrg   width_in_mb = width / VL_MACROBLOCK_WIDTH;
2297ec681f3Smrg   height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
2307ec681f3Smrg
2317ec681f3Smrg   if (!dec->use_legacy) {
2327ec681f3Smrg      unsigned fs_in_mb = width_in_mb * height_in_mb;
2337ec681f3Smrg      unsigned num_dpb_buffer;
2347ec681f3Smrg      switch (dec->base.level) {
2357ec681f3Smrg      case 30:
2367ec681f3Smrg         num_dpb_buffer = 8100 / fs_in_mb;
2377ec681f3Smrg         break;
2387ec681f3Smrg      case 31:
2397ec681f3Smrg         num_dpb_buffer = 18000 / fs_in_mb;
2407ec681f3Smrg         break;
2417ec681f3Smrg      case 32:
2427ec681f3Smrg         num_dpb_buffer = 20480 / fs_in_mb;
2437ec681f3Smrg         break;
2447ec681f3Smrg      case 41:
2457ec681f3Smrg         num_dpb_buffer = 32768 / fs_in_mb;
2467ec681f3Smrg         break;
2477ec681f3Smrg      case 42:
2487ec681f3Smrg         num_dpb_buffer = 34816 / fs_in_mb;
2497ec681f3Smrg         break;
2507ec681f3Smrg      case 50:
2517ec681f3Smrg         num_dpb_buffer = 110400 / fs_in_mb;
2527ec681f3Smrg         break;
2537ec681f3Smrg      case 51:
2547ec681f3Smrg         num_dpb_buffer = 184320 / fs_in_mb;
2557ec681f3Smrg         break;
2567ec681f3Smrg      default:
2577ec681f3Smrg         num_dpb_buffer = 184320 / fs_in_mb;
2587ec681f3Smrg         break;
2597ec681f3Smrg      }
2607ec681f3Smrg      num_dpb_buffer++;
2617ec681f3Smrg      max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
2627ec681f3Smrg      ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
2637ec681f3Smrg   } else {
2647ec681f3Smrg      // the firmware seems to always assume a minimum of ref frames
2657ec681f3Smrg      max_references = MAX2(NUM_H264_REFS, max_references);
2667ec681f3Smrg      // macroblock context buffer
2677ec681f3Smrg      ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
2687ec681f3Smrg   }
2697ec681f3Smrg
2707ec681f3Smrg   return ctx_size;
27101e04c3fSmrg}
27201e04c3fSmrg
27301e04c3fSmrgstatic unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
27401e04c3fSmrg{
2757ec681f3Smrg   unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
2767ec681f3Smrg   unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
27701e04c3fSmrg
2787ec681f3Smrg   unsigned max_references = dec->base.max_references + 1;
27901e04c3fSmrg
2807ec681f3Smrg   if (dec->base.width * dec->base.height >= 4096 * 2000)
2817ec681f3Smrg      max_references = MAX2(max_references, 8);
2827ec681f3Smrg   else
2837ec681f3Smrg      max_references = MAX2(max_references, 17);
28401e04c3fSmrg
2857ec681f3Smrg   width = align(width, 16);
2867ec681f3Smrg   height = align(height, 16);
2877ec681f3Smrg   return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
28801e04c3fSmrg}
28901e04c3fSmrg
2907ec681f3Smrgstatic unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec,
2917ec681f3Smrg                                          struct pipe_h265_picture_desc *pic)
29201e04c3fSmrg{
2937ec681f3Smrg   unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
2947ec681f3Smrg   unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
2957ec681f3Smrg   unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
29601e04c3fSmrg
2977ec681f3Smrg   unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
2987ec681f3Smrg   unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
2997ec681f3Smrg   unsigned coeff_10bit =
3007ec681f3Smrg      (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
30101e04c3fSmrg
3027ec681f3Smrg   unsigned max_references = dec->base.max_references + 1;
30301e04c3fSmrg
3047ec681f3Smrg   if (dec->base.width * dec->base.height >= 4096 * 2000)
3057ec681f3Smrg      max_references = MAX2(max_references, 8);
3067ec681f3Smrg   else
3077ec681f3Smrg      max_references = MAX2(max_references, 17);
30801e04c3fSmrg
3097ec681f3Smrg   log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
3107ec681f3Smrg                   pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
31101e04c3fSmrg
3127ec681f3Smrg   width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
3137ec681f3Smrg   height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
31401e04c3fSmrg
3157ec681f3Smrg   num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
3167ec681f3Smrg   context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
3177ec681f3Smrg   max_mb_address = (unsigned)ceil(height * 8 / 2048.0);
31801e04c3fSmrg
3197ec681f3Smrg   cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
3207ec681f3Smrg   db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
32101e04c3fSmrg
3227ec681f3Smrg   return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
32301e04c3fSmrg}
32401e04c3fSmrg
32501e04c3fSmrgstatic unsigned get_db_pitch_alignment(struct ruvd_decoder *dec)
32601e04c3fSmrg{
3277ec681f3Smrg   if (((struct si_screen *)dec->screen)->info.family < CHIP_VEGA10)
3287ec681f3Smrg      return 16;
3297ec681f3Smrg   else
3307ec681f3Smrg      return 32;
33101e04c3fSmrg}
33201e04c3fSmrg
333af69d88dSmrg/* calculate size of reference picture buffer */
33401e04c3fSmrgstatic unsigned calc_dpb_size(struct ruvd_decoder *dec)
335af69d88dSmrg{
3367ec681f3Smrg   unsigned width_in_mb, height_in_mb, image_size, dpb_size;
3377ec681f3Smrg
3387ec681f3Smrg   // always align them to MB size for dpb calculation
3397ec681f3Smrg   unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
3407ec681f3Smrg   unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
3417ec681f3Smrg
3427ec681f3Smrg   // always one more for currently decoded picture
3437ec681f3Smrg   unsigned max_references = dec->base.max_references + 1;
3447ec681f3Smrg
3457ec681f3Smrg   // aligned size of a single frame
3467ec681f3Smrg   image_size = align(width, get_db_pitch_alignment(dec)) * height;
3477ec681f3Smrg   image_size += image_size / 2;
3487ec681f3Smrg   image_size = align(image_size, 1024);
3497ec681f3Smrg
3507ec681f3Smrg   // picture width & height in 16 pixel units
3517ec681f3Smrg   width_in_mb = width / VL_MACROBLOCK_WIDTH;
3527ec681f3Smrg   height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
3537ec681f3Smrg
3547ec681f3Smrg   switch (u_reduce_video_profile(dec->base.profile)) {
3557ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
3567ec681f3Smrg      if (!dec->use_legacy) {
3577ec681f3Smrg         unsigned fs_in_mb = width_in_mb * height_in_mb;
3587ec681f3Smrg         unsigned alignment = 64, num_dpb_buffer;
3597ec681f3Smrg
3607ec681f3Smrg         if (dec->stream_type == RUVD_CODEC_H264_PERF)
3617ec681f3Smrg            alignment = 256;
3627ec681f3Smrg         switch (dec->base.level) {
3637ec681f3Smrg         case 30:
3647ec681f3Smrg            num_dpb_buffer = 8100 / fs_in_mb;
3657ec681f3Smrg            break;
3667ec681f3Smrg         case 31:
3677ec681f3Smrg            num_dpb_buffer = 18000 / fs_in_mb;
3687ec681f3Smrg            break;
3697ec681f3Smrg         case 32:
3707ec681f3Smrg            num_dpb_buffer = 20480 / fs_in_mb;
3717ec681f3Smrg            break;
3727ec681f3Smrg         case 41:
3737ec681f3Smrg            num_dpb_buffer = 32768 / fs_in_mb;
3747ec681f3Smrg            break;
3757ec681f3Smrg         case 42:
3767ec681f3Smrg            num_dpb_buffer = 34816 / fs_in_mb;
3777ec681f3Smrg            break;
3787ec681f3Smrg         case 50:
3797ec681f3Smrg            num_dpb_buffer = 110400 / fs_in_mb;
3807ec681f3Smrg            break;
3817ec681f3Smrg         case 51:
3827ec681f3Smrg            num_dpb_buffer = 184320 / fs_in_mb;
3837ec681f3Smrg            break;
3847ec681f3Smrg         default:
3857ec681f3Smrg            num_dpb_buffer = 184320 / fs_in_mb;
3867ec681f3Smrg            break;
3877ec681f3Smrg         }
3887ec681f3Smrg         num_dpb_buffer++;
3897ec681f3Smrg         max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
3907ec681f3Smrg         dpb_size = image_size * max_references;
3917ec681f3Smrg         if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
3927ec681f3Smrg             (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
3937ec681f3Smrg            dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
3947ec681f3Smrg            dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
3957ec681f3Smrg         }
3967ec681f3Smrg      } else {
3977ec681f3Smrg         // the firmware seems to allways assume a minimum of ref frames
3987ec681f3Smrg         max_references = MAX2(NUM_H264_REFS, max_references);
3997ec681f3Smrg         // reference picture buffer
4007ec681f3Smrg         dpb_size = image_size * max_references;
4017ec681f3Smrg         if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
4027ec681f3Smrg             (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
4037ec681f3Smrg            // macroblock context buffer
4047ec681f3Smrg            dpb_size += width_in_mb * height_in_mb * max_references * 192;
4057ec681f3Smrg            // IT surface buffer
4067ec681f3Smrg            dpb_size += width_in_mb * height_in_mb * 32;
4077ec681f3Smrg         }
4087ec681f3Smrg      }
4097ec681f3Smrg      break;
4107ec681f3Smrg   }
4117ec681f3Smrg
4127ec681f3Smrg   case PIPE_VIDEO_FORMAT_HEVC:
4137ec681f3Smrg      if (dec->base.width * dec->base.height >= 4096 * 2000)
4147ec681f3Smrg         max_references = MAX2(max_references, 8);
4157ec681f3Smrg      else
4167ec681f3Smrg         max_references = MAX2(max_references, 17);
4177ec681f3Smrg
4187ec681f3Smrg      width = align(width, 16);
4197ec681f3Smrg      height = align(height, 16);
4207ec681f3Smrg      if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
4217ec681f3Smrg         dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 9) / 4, 256) *
4227ec681f3Smrg                    max_references;
4237ec681f3Smrg      else
4247ec681f3Smrg         dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 3) / 2, 256) *
4257ec681f3Smrg                    max_references;
4267ec681f3Smrg      break;
4277ec681f3Smrg
4287ec681f3Smrg   case PIPE_VIDEO_FORMAT_VC1:
4297ec681f3Smrg      // the firmware seems to allways assume a minimum of ref frames
4307ec681f3Smrg      max_references = MAX2(NUM_VC1_REFS, max_references);
4317ec681f3Smrg
4327ec681f3Smrg      // reference picture buffer
4337ec681f3Smrg      dpb_size = image_size * max_references;
4347ec681f3Smrg
4357ec681f3Smrg      // CONTEXT_BUFFER
4367ec681f3Smrg      dpb_size += width_in_mb * height_in_mb * 128;
4377ec681f3Smrg
4387ec681f3Smrg      // IT surface buffer
4397ec681f3Smrg      dpb_size += width_in_mb * 64;
4407ec681f3Smrg
4417ec681f3Smrg      // DB surface buffer
4427ec681f3Smrg      dpb_size += width_in_mb * 128;
4437ec681f3Smrg
4447ec681f3Smrg      // BP
4457ec681f3Smrg      dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
4467ec681f3Smrg      break;
4477ec681f3Smrg
4487ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG12:
4497ec681f3Smrg      // reference picture buffer, must be big enough for all frames
4507ec681f3Smrg      dpb_size = image_size * NUM_MPEG2_REFS;
4517ec681f3Smrg      break;
4527ec681f3Smrg
4537ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4:
4547ec681f3Smrg      // reference picture buffer
4557ec681f3Smrg      dpb_size = image_size * max_references;
4567ec681f3Smrg
4577ec681f3Smrg      // CM
4587ec681f3Smrg      dpb_size += width_in_mb * height_in_mb * 64;
4597ec681f3Smrg
4607ec681f3Smrg      // IT surface buffer
4617ec681f3Smrg      dpb_size += align(width_in_mb * height_in_mb * 32, 64);
4627ec681f3Smrg
4637ec681f3Smrg      dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
4647ec681f3Smrg      break;
4657ec681f3Smrg
4667ec681f3Smrg   case PIPE_VIDEO_FORMAT_JPEG:
4677ec681f3Smrg      dpb_size = 0;
4687ec681f3Smrg      break;
4697ec681f3Smrg
4707ec681f3Smrg   default:
4717ec681f3Smrg      // something is missing here
4727ec681f3Smrg      assert(0);
4737ec681f3Smrg
4747ec681f3Smrg      // at least use a sane default value
4757ec681f3Smrg      dpb_size = 32 * 1024 * 1024;
4767ec681f3Smrg      break;
4777ec681f3Smrg   }
4787ec681f3Smrg   return dpb_size;
479af69d88dSmrg}
480af69d88dSmrg
48101e04c3fSmrg/* free associated data in the video buffer callback */
48201e04c3fSmrgstatic void ruvd_destroy_associated_data(void *data)
48301e04c3fSmrg{
4847ec681f3Smrg   /* NOOP, since we only use an intptr */
48501e04c3fSmrg}
48601e04c3fSmrg
487af69d88dSmrg/* get h264 specific message bits */
488af69d88dSmrgstatic struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
489af69d88dSmrg{
4907ec681f3Smrg   struct ruvd_h264 result;
4917ec681f3Smrg
4927ec681f3Smrg   memset(&result, 0, sizeof(result));
4937ec681f3Smrg   switch (pic->base.profile) {
4947ec681f3Smrg   case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
4957ec681f3Smrg   case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
4967ec681f3Smrg      result.profile = RUVD_H264_PROFILE_BASELINE;
4977ec681f3Smrg      break;
4987ec681f3Smrg
4997ec681f3Smrg   case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
5007ec681f3Smrg      result.profile = RUVD_H264_PROFILE_MAIN;
5017ec681f3Smrg      break;
5027ec681f3Smrg
5037ec681f3Smrg   case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
5047ec681f3Smrg      result.profile = RUVD_H264_PROFILE_HIGH;
5057ec681f3Smrg      break;
5067ec681f3Smrg
5077ec681f3Smrg   default:
5087ec681f3Smrg      assert(0);
5097ec681f3Smrg      break;
5107ec681f3Smrg   }
5117ec681f3Smrg
5127ec681f3Smrg   result.level = dec->base.level;
5137ec681f3Smrg
5147ec681f3Smrg   result.sps_info_flags = 0;
5157ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
5167ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
5177ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
5187ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
5197ec681f3Smrg
5207ec681f3Smrg   result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
5217ec681f3Smrg   result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
5227ec681f3Smrg   result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
5237ec681f3Smrg   result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
5247ec681f3Smrg   result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
5257ec681f3Smrg
5267ec681f3Smrg   switch (dec->base.chroma_format) {
5277ec681f3Smrg   case PIPE_VIDEO_CHROMA_FORMAT_NONE:
5287ec681f3Smrg      /* TODO: assert? */
5297ec681f3Smrg      break;
5307ec681f3Smrg   case PIPE_VIDEO_CHROMA_FORMAT_400:
5317ec681f3Smrg      result.chroma_format = 0;
5327ec681f3Smrg      break;
5337ec681f3Smrg   case PIPE_VIDEO_CHROMA_FORMAT_420:
5347ec681f3Smrg      result.chroma_format = 1;
5357ec681f3Smrg      break;
5367ec681f3Smrg   case PIPE_VIDEO_CHROMA_FORMAT_422:
5377ec681f3Smrg      result.chroma_format = 2;
5387ec681f3Smrg      break;
5397ec681f3Smrg   case PIPE_VIDEO_CHROMA_FORMAT_444:
5407ec681f3Smrg      result.chroma_format = 3;
5417ec681f3Smrg      break;
5427ec681f3Smrg   }
5437ec681f3Smrg
5447ec681f3Smrg   result.pps_info_flags = 0;
5457ec681f3Smrg   result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
5467ec681f3Smrg   result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
5477ec681f3Smrg   result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
5487ec681f3Smrg   result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
5497ec681f3Smrg   result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
5507ec681f3Smrg   result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
5517ec681f3Smrg   result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
5527ec681f3Smrg   result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
5537ec681f3Smrg
5547ec681f3Smrg   result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
5557ec681f3Smrg   result.slice_group_map_type = pic->pps->slice_group_map_type;
5567ec681f3Smrg   result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
5577ec681f3Smrg   result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
5587ec681f3Smrg   result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
5597ec681f3Smrg   result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
5607ec681f3Smrg
5617ec681f3Smrg   memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6 * 16);
5627ec681f3Smrg   memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2 * 64);
5637ec681f3Smrg
5647ec681f3Smrg   if (dec->stream_type == RUVD_CODEC_H264_PERF) {
5657ec681f3Smrg      memcpy(dec->it, result.scaling_list_4x4, 6 * 16);
5667ec681f3Smrg      memcpy((dec->it + 96), result.scaling_list_8x8, 2 * 64);
5677ec681f3Smrg   }
5687ec681f3Smrg
5697ec681f3Smrg   result.num_ref_frames = pic->num_ref_frames;
5707ec681f3Smrg
5717ec681f3Smrg   result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
5727ec681f3Smrg   result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
5737ec681f3Smrg
5747ec681f3Smrg   result.frame_num = pic->frame_num;
5757ec681f3Smrg   memcpy(result.frame_num_list, pic->frame_num_list, 4 * 16);
5767ec681f3Smrg   result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
5777ec681f3Smrg   result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
5787ec681f3Smrg   memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4 * 16 * 2);
5797ec681f3Smrg
5807ec681f3Smrg   result.decoded_pic_idx = pic->frame_num;
5817ec681f3Smrg
5827ec681f3Smrg   return result;
583af69d88dSmrg}
584af69d88dSmrg
58501e04c3fSmrg/* get h265 specific message bits */
58601e04c3fSmrgstatic struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video_buffer *target,
5877ec681f3Smrg                                     struct pipe_h265_picture_desc *pic)
58801e04c3fSmrg{
5897ec681f3Smrg   struct ruvd_h265 result;
5907ec681f3Smrg   unsigned i, j;
5917ec681f3Smrg
5927ec681f3Smrg   memset(&result, 0, sizeof(result));
5937ec681f3Smrg
5947ec681f3Smrg   result.sps_info_flags = 0;
5957ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
5967ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
5977ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
5987ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
5997ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
6007ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
6017ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
6027ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
6037ec681f3Smrg   result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
6047ec681f3Smrg   if (((struct si_screen *)dec->screen)->info.family == CHIP_CARRIZO)
6057ec681f3Smrg      result.sps_info_flags |= 1 << 9;
6067ec681f3Smrg   if (pic->UseRefPicList == true)
6077ec681f3Smrg      result.sps_info_flags |= 1 << 10;
6087ec681f3Smrg
6097ec681f3Smrg   result.chroma_format = pic->pps->sps->chroma_format_idc;
6107ec681f3Smrg   result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
6117ec681f3Smrg   result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
6127ec681f3Smrg   result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
6137ec681f3Smrg   result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
6147ec681f3Smrg   result.log2_min_luma_coding_block_size_minus3 =
6157ec681f3Smrg      pic->pps->sps->log2_min_luma_coding_block_size_minus3;
6167ec681f3Smrg   result.log2_diff_max_min_luma_coding_block_size =
6177ec681f3Smrg      pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
6187ec681f3Smrg   result.log2_min_transform_block_size_minus2 =
6197ec681f3Smrg      pic->pps->sps->log2_min_transform_block_size_minus2;
6207ec681f3Smrg   result.log2_diff_max_min_transform_block_size =
6217ec681f3Smrg      pic->pps->sps->log2_diff_max_min_transform_block_size;
6227ec681f3Smrg   result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
6237ec681f3Smrg   result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
6247ec681f3Smrg   result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
6257ec681f3Smrg   result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
6267ec681f3Smrg   result.log2_min_pcm_luma_coding_block_size_minus3 =
6277ec681f3Smrg      pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
6287ec681f3Smrg   result.log2_diff_max_min_pcm_luma_coding_block_size =
6297ec681f3Smrg      pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
6307ec681f3Smrg   result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
6317ec681f3Smrg
6327ec681f3Smrg   result.pps_info_flags = 0;
6337ec681f3Smrg   result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
6347ec681f3Smrg   result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
6357ec681f3Smrg   result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
6367ec681f3Smrg   result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
6377ec681f3Smrg   result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
6387ec681f3Smrg   result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
6397ec681f3Smrg   result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
6407ec681f3Smrg   result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
6417ec681f3Smrg   result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
6427ec681f3Smrg   result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
6437ec681f3Smrg   result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
6447ec681f3Smrg   result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
6457ec681f3Smrg   result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
6467ec681f3Smrg   result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
6477ec681f3Smrg   result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
6487ec681f3Smrg   result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
6497ec681f3Smrg   result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
6507ec681f3Smrg   result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
6517ec681f3Smrg   result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
6527ec681f3Smrg   result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
6537ec681f3Smrg   // result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag; ???
6547ec681f3Smrg
6557ec681f3Smrg   result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
6567ec681f3Smrg   result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
6577ec681f3Smrg   result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
6587ec681f3Smrg   result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
6597ec681f3Smrg   result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
6607ec681f3Smrg   result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
6617ec681f3Smrg   result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
6627ec681f3Smrg   result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
6637ec681f3Smrg   result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
6647ec681f3Smrg   result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
6657ec681f3Smrg   result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
6667ec681f3Smrg   result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
6677ec681f3Smrg   result.init_qp_minus26 = pic->pps->init_qp_minus26;
6687ec681f3Smrg
6697ec681f3Smrg   for (i = 0; i < 19; ++i)
6707ec681f3Smrg      result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
6717ec681f3Smrg
6727ec681f3Smrg   for (i = 0; i < 21; ++i)
6737ec681f3Smrg      result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
6747ec681f3Smrg
6757ec681f3Smrg   result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
6767ec681f3Smrg   result.curr_poc = pic->CurrPicOrderCntVal;
6777ec681f3Smrg
6787ec681f3Smrg   for (i = 0; i < 16; i++) {
6797ec681f3Smrg      for (j = 0; (pic->ref[j] != NULL) && (j < 16); j++) {
6807ec681f3Smrg         if (dec->render_pic_list[i] == pic->ref[j])
6817ec681f3Smrg            break;
6827ec681f3Smrg         if (j == 15)
6837ec681f3Smrg            dec->render_pic_list[i] = NULL;
6847ec681f3Smrg         else if (pic->ref[j + 1] == NULL)
6857ec681f3Smrg            dec->render_pic_list[i] = NULL;
6867ec681f3Smrg      }
6877ec681f3Smrg   }
6887ec681f3Smrg   for (i = 0; i < 16; i++) {
6897ec681f3Smrg      if (dec->render_pic_list[i] == NULL) {
6907ec681f3Smrg         dec->render_pic_list[i] = target;
6917ec681f3Smrg         result.curr_idx = i;
6927ec681f3Smrg         break;
6937ec681f3Smrg      }
6947ec681f3Smrg   }
6957ec681f3Smrg
6967ec681f3Smrg   vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
6977ec681f3Smrg                                       &ruvd_destroy_associated_data);
6987ec681f3Smrg
6997ec681f3Smrg   for (i = 0; i < 16; ++i) {
7007ec681f3Smrg      struct pipe_video_buffer *ref = pic->ref[i];
7017ec681f3Smrg      uintptr_t ref_pic = 0;
7027ec681f3Smrg
7037ec681f3Smrg      result.poc_list[i] = pic->PicOrderCntVal[i];
7047ec681f3Smrg
7057ec681f3Smrg      if (ref)
7067ec681f3Smrg         ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
7077ec681f3Smrg      else
7087ec681f3Smrg         ref_pic = 0x7F;
7097ec681f3Smrg      result.ref_pic_list[i] = ref_pic;
7107ec681f3Smrg   }
7117ec681f3Smrg
7127ec681f3Smrg   for (i = 0; i < 8; ++i) {
7137ec681f3Smrg      result.ref_pic_set_st_curr_before[i] = 0xFF;
7147ec681f3Smrg      result.ref_pic_set_st_curr_after[i] = 0xFF;
7157ec681f3Smrg      result.ref_pic_set_lt_curr[i] = 0xFF;
7167ec681f3Smrg   }
7177ec681f3Smrg
7187ec681f3Smrg   for (i = 0; i < pic->NumPocStCurrBefore; ++i)
7197ec681f3Smrg      result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
7207ec681f3Smrg
7217ec681f3Smrg   for (i = 0; i < pic->NumPocStCurrAfter; ++i)
7227ec681f3Smrg      result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
7237ec681f3Smrg
7247ec681f3Smrg   for (i = 0; i < pic->NumPocLtCurr; ++i)
7257ec681f3Smrg      result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
7267ec681f3Smrg
7277ec681f3Smrg   for (i = 0; i < 6; ++i)
7287ec681f3Smrg      result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
7297ec681f3Smrg
7307ec681f3Smrg   for (i = 0; i < 2; ++i)
7317ec681f3Smrg      result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
7327ec681f3Smrg
7337ec681f3Smrg   memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
7347ec681f3Smrg   memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
7357ec681f3Smrg   memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
7367ec681f3Smrg   memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
7377ec681f3Smrg
7387ec681f3Smrg   for (i = 0; i < 2; i++) {
7397ec681f3Smrg      for (j = 0; j < 15; j++)
7407ec681f3Smrg         result.direct_reflist[i][j] = pic->RefPicList[i][j];
7417ec681f3Smrg   }
7427ec681f3Smrg
7437ec681f3Smrg   if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
7447ec681f3Smrg      if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
7457ec681f3Smrg         result.p010_mode = 1;
7467ec681f3Smrg         result.msb_mode = 1;
7477ec681f3Smrg      } else {
7487ec681f3Smrg         result.luma_10to8 = 5;
7497ec681f3Smrg         result.chroma_10to8 = 5;
7507ec681f3Smrg         result.sclr_luma10to8 = 4;
7517ec681f3Smrg         result.sclr_chroma10to8 = 4;
7527ec681f3Smrg      }
7537ec681f3Smrg   }
7547ec681f3Smrg
7557ec681f3Smrg   /* TODO
7567ec681f3Smrg   result.highestTid;
7577ec681f3Smrg   result.isNonRef;
7587ec681f3Smrg
7597ec681f3Smrg   IDRPicFlag;
7607ec681f3Smrg   RAPPicFlag;
7617ec681f3Smrg   NumPocTotalCurr;
7627ec681f3Smrg   NumShortTermPictureSliceHeaderBits;
7637ec681f3Smrg   NumLongTermPictureSliceHeaderBits;
7647ec681f3Smrg
7657ec681f3Smrg   IsLongTerm[16];
7667ec681f3Smrg   */
7677ec681f3Smrg
7687ec681f3Smrg   return result;
76901e04c3fSmrg}
77001e04c3fSmrg
771af69d88dSmrg/* get vc1 specific message bits */
772af69d88dSmrgstatic struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
773af69d88dSmrg{
7747ec681f3Smrg   struct ruvd_vc1 result;
7757ec681f3Smrg
7767ec681f3Smrg   memset(&result, 0, sizeof(result));
7777ec681f3Smrg
7787ec681f3Smrg   switch (pic->base.profile) {
7797ec681f3Smrg   case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
7807ec681f3Smrg      result.profile = RUVD_VC1_PROFILE_SIMPLE;
7817ec681f3Smrg      result.level = 1;
7827ec681f3Smrg      break;
7837ec681f3Smrg
7847ec681f3Smrg   case PIPE_VIDEO_PROFILE_VC1_MAIN:
7857ec681f3Smrg      result.profile = RUVD_VC1_PROFILE_MAIN;
7867ec681f3Smrg      result.level = 2;
7877ec681f3Smrg      break;
7887ec681f3Smrg
7897ec681f3Smrg   case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
7907ec681f3Smrg      result.profile = RUVD_VC1_PROFILE_ADVANCED;
7917ec681f3Smrg      result.level = 4;
7927ec681f3Smrg      break;
7937ec681f3Smrg
7947ec681f3Smrg   default:
7957ec681f3Smrg      assert(0);
7967ec681f3Smrg   }
7977ec681f3Smrg
7987ec681f3Smrg   /* fields common for all profiles */
7997ec681f3Smrg   result.sps_info_flags |= pic->postprocflag << 7;
8007ec681f3Smrg   result.sps_info_flags |= pic->pulldown << 6;
8017ec681f3Smrg   result.sps_info_flags |= pic->interlace << 5;
8027ec681f3Smrg   result.sps_info_flags |= pic->tfcntrflag << 4;
8037ec681f3Smrg   result.sps_info_flags |= pic->finterpflag << 3;
8047ec681f3Smrg   result.sps_info_flags |= pic->psf << 1;
8057ec681f3Smrg
8067ec681f3Smrg   result.pps_info_flags |= pic->range_mapy_flag << 31;
8077ec681f3Smrg   result.pps_info_flags |= pic->range_mapy << 28;
8087ec681f3Smrg   result.pps_info_flags |= pic->range_mapuv_flag << 27;
8097ec681f3Smrg   result.pps_info_flags |= pic->range_mapuv << 24;
8107ec681f3Smrg   result.pps_info_flags |= pic->multires << 21;
8117ec681f3Smrg   result.pps_info_flags |= pic->maxbframes << 16;
8127ec681f3Smrg   result.pps_info_flags |= pic->overlap << 11;
8137ec681f3Smrg   result.pps_info_flags |= pic->quantizer << 9;
8147ec681f3Smrg   result.pps_info_flags |= pic->panscan_flag << 7;
8157ec681f3Smrg   result.pps_info_flags |= pic->refdist_flag << 6;
8167ec681f3Smrg   result.pps_info_flags |= pic->vstransform << 0;
8177ec681f3Smrg
8187ec681f3Smrg   /* some fields only apply to main/advanced profile */
8197ec681f3Smrg   if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
8207ec681f3Smrg      result.pps_info_flags |= pic->syncmarker << 20;
8217ec681f3Smrg      result.pps_info_flags |= pic->rangered << 19;
8227ec681f3Smrg      result.pps_info_flags |= pic->loopfilter << 5;
8237ec681f3Smrg      result.pps_info_flags |= pic->fastuvmc << 4;
8247ec681f3Smrg      result.pps_info_flags |= pic->extended_mv << 3;
8257ec681f3Smrg      result.pps_info_flags |= pic->extended_dmv << 8;
8267ec681f3Smrg      result.pps_info_flags |= pic->dquant << 1;
8277ec681f3Smrg   }
8287ec681f3Smrg
8297ec681f3Smrg   result.chroma_format = 1;
830af69d88dSmrg
831af69d88dSmrg#if 0
832af69d88dSmrg//(((unsigned int)(pPicParams->advance.reserved1))        << SPS_INFO_VC1_RESERVED_SHIFT)
833af69d88dSmrguint32_t 	slice_count
834af69d88dSmrguint8_t 	picture_type
835af69d88dSmrguint8_t 	frame_coding_mode
836af69d88dSmrguint8_t 	deblockEnable
837af69d88dSmrguint8_t 	pquant
838af69d88dSmrg#endif
839af69d88dSmrg
8407ec681f3Smrg   return result;
841af69d88dSmrg}
842af69d88dSmrg
843af69d88dSmrg/* extract the frame number from a referenced video buffer */
844af69d88dSmrgstatic uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
845af69d88dSmrg{
8467ec681f3Smrg   uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
8477ec681f3Smrg   uint32_t max = MAX2(dec->frame_number, 1) - 1;
8487ec681f3Smrg   uintptr_t frame;
849af69d88dSmrg
8507ec681f3Smrg   /* seems to be the most sane fallback */
8517ec681f3Smrg   if (!ref)
8527ec681f3Smrg      return max;
853af69d88dSmrg
8547ec681f3Smrg   /* get the frame number from the associated data */
8557ec681f3Smrg   frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
856af69d88dSmrg
8577ec681f3Smrg   /* limit the frame number to a valid range */
8587ec681f3Smrg   return MAX2(MIN2(frame, max), min);
859af69d88dSmrg}
860af69d88dSmrg
861af69d88dSmrg/* get mpeg2 specific msg bits */
862af69d88dSmrgstatic struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
8637ec681f3Smrg                                       struct pipe_mpeg12_picture_desc *pic)
864af69d88dSmrg{
8657ec681f3Smrg   const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
8667ec681f3Smrg   struct ruvd_mpeg2 result;
8677ec681f3Smrg   unsigned i;
8687ec681f3Smrg
8697ec681f3Smrg   memset(&result, 0, sizeof(result));
8707ec681f3Smrg   result.decoded_pic_idx = dec->frame_number;
8717ec681f3Smrg   for (i = 0; i < 2; ++i)
8727ec681f3Smrg      result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
8737ec681f3Smrg
8747ec681f3Smrg   if (pic->intra_matrix) {
8757ec681f3Smrg      result.load_intra_quantiser_matrix = 1;
8767ec681f3Smrg      for (i = 0; i < 64; ++i) {
8777ec681f3Smrg         result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
8787ec681f3Smrg      }
8797ec681f3Smrg   }
8807ec681f3Smrg   if (pic->non_intra_matrix) {
8817ec681f3Smrg      result.load_nonintra_quantiser_matrix = 1;
8827ec681f3Smrg      for (i = 0; i < 64; ++i) {
8837ec681f3Smrg         result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
8847ec681f3Smrg      }
8857ec681f3Smrg   }
8867ec681f3Smrg
8877ec681f3Smrg   result.profile_and_level_indication = 0;
8887ec681f3Smrg   result.chroma_format = 0x1;
8897ec681f3Smrg
8907ec681f3Smrg   result.picture_coding_type = pic->picture_coding_type;
8917ec681f3Smrg   result.f_code[0][0] = pic->f_code[0][0] + 1;
8927ec681f3Smrg   result.f_code[0][1] = pic->f_code[0][1] + 1;
8937ec681f3Smrg   result.f_code[1][0] = pic->f_code[1][0] + 1;
8947ec681f3Smrg   result.f_code[1][1] = pic->f_code[1][1] + 1;
8957ec681f3Smrg   result.intra_dc_precision = pic->intra_dc_precision;
8967ec681f3Smrg   result.pic_structure = pic->picture_structure;
8977ec681f3Smrg   result.top_field_first = pic->top_field_first;
8987ec681f3Smrg   result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
8997ec681f3Smrg   result.concealment_motion_vectors = pic->concealment_motion_vectors;
9007ec681f3Smrg   result.q_scale_type = pic->q_scale_type;
9017ec681f3Smrg   result.intra_vlc_format = pic->intra_vlc_format;
9027ec681f3Smrg   result.alternate_scan = pic->alternate_scan;
9037ec681f3Smrg
9047ec681f3Smrg   return result;
905af69d88dSmrg}
906af69d88dSmrg
907af69d88dSmrg/* get mpeg4 specific msg bits */
908af69d88dSmrgstatic struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
9097ec681f3Smrg                                       struct pipe_mpeg4_picture_desc *pic)
910af69d88dSmrg{
9117ec681f3Smrg   struct ruvd_mpeg4 result;
9127ec681f3Smrg   unsigned i;
9137ec681f3Smrg
9147ec681f3Smrg   memset(&result, 0, sizeof(result));
9157ec681f3Smrg   result.decoded_pic_idx = dec->frame_number;
9167ec681f3Smrg   for (i = 0; i < 2; ++i)
9177ec681f3Smrg      result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
9187ec681f3Smrg
9197ec681f3Smrg   result.variant_type = 0;
9207ec681f3Smrg   result.profile_and_level_indication = 0xF0; // ASP Level0
9217ec681f3Smrg
9227ec681f3Smrg   result.video_object_layer_verid = 0x5; // advanced simple
9237ec681f3Smrg   result.video_object_layer_shape = 0x0; // rectangular
9247ec681f3Smrg
9257ec681f3Smrg   result.video_object_layer_width = dec->base.width;
9267ec681f3Smrg   result.video_object_layer_height = dec->base.height;
9277ec681f3Smrg
9287ec681f3Smrg   result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
9297ec681f3Smrg
9307ec681f3Smrg   result.flags |= pic->short_video_header << 0;
9317ec681f3Smrg   // result.flags |= obmc_disable << 1;
9327ec681f3Smrg   result.flags |= pic->interlaced << 2;
9337ec681f3Smrg   result.flags |= 1 << 3; // load_intra_quant_mat
9347ec681f3Smrg   result.flags |= 1 << 4; // load_nonintra_quant_mat
9357ec681f3Smrg   result.flags |= pic->quarter_sample << 5;
9367ec681f3Smrg   result.flags |= 1 << 6; // complexity_estimation_disable
9377ec681f3Smrg   result.flags |= pic->resync_marker_disable << 7;
9387ec681f3Smrg   // result.flags |= data_partitioned << 8;
9397ec681f3Smrg   // result.flags |= reversible_vlc << 9;
9407ec681f3Smrg   result.flags |= 0 << 10; // newpred_enable
9417ec681f3Smrg   result.flags |= 0 << 11; // reduced_resolution_vop_enable
9427ec681f3Smrg   // result.flags |= scalability << 12;
9437ec681f3Smrg   // result.flags |= is_object_layer_identifier << 13;
9447ec681f3Smrg   // result.flags |= fixed_vop_rate << 14;
9457ec681f3Smrg   // result.flags |= newpred_segment_type << 15;
9467ec681f3Smrg
9477ec681f3Smrg   result.quant_type = pic->quant_type;
9487ec681f3Smrg
9497ec681f3Smrg   for (i = 0; i < 64; ++i) {
9507ec681f3Smrg      result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
9517ec681f3Smrg      result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
9527ec681f3Smrg   }
9537ec681f3Smrg
9547ec681f3Smrg   /*
9557ec681f3Smrg   int32_t 	trd [2]
9567ec681f3Smrg   int32_t 	trb [2]
9577ec681f3Smrg   uint8_t 	vop_coding_type
9587ec681f3Smrg   uint8_t 	vop_fcode_forward
9597ec681f3Smrg   uint8_t 	vop_fcode_backward
9607ec681f3Smrg   uint8_t 	rounding_control
9617ec681f3Smrg   uint8_t 	alternate_vertical_scan_flag
9627ec681f3Smrg   uint8_t 	top_field_first
9637ec681f3Smrg   */
9647ec681f3Smrg
9657ec681f3Smrg   return result;
966af69d88dSmrg}
967af69d88dSmrg
968af69d88dSmrg/**
969af69d88dSmrg * destroy this video decoder
970af69d88dSmrg */
971af69d88dSmrgstatic void ruvd_destroy(struct pipe_video_codec *decoder)
972af69d88dSmrg{
9737ec681f3Smrg   struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
9747ec681f3Smrg   unsigned i;
975af69d88dSmrg
9767ec681f3Smrg   assert(decoder);
977af69d88dSmrg
9787ec681f3Smrg   map_msg_fb_it_buf(dec);
9797ec681f3Smrg   dec->msg->size = sizeof(*dec->msg);
9807ec681f3Smrg   dec->msg->msg_type = RUVD_MSG_DESTROY;
9817ec681f3Smrg   dec->msg->stream_handle = dec->stream_handle;
9827ec681f3Smrg   send_msg_buf(dec);
983af69d88dSmrg
9847ec681f3Smrg   flush(dec, 0);
985af69d88dSmrg
9867ec681f3Smrg   dec->ws->cs_destroy(&dec->cs);
987af69d88dSmrg
9887ec681f3Smrg   for (i = 0; i < NUM_BUFFERS; ++i) {
9897ec681f3Smrg      si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
9907ec681f3Smrg      si_vid_destroy_buffer(&dec->bs_buffers[i]);
9917ec681f3Smrg   }
992af69d88dSmrg
9937ec681f3Smrg   si_vid_destroy_buffer(&dec->dpb);
9947ec681f3Smrg   si_vid_destroy_buffer(&dec->ctx);
9957ec681f3Smrg   si_vid_destroy_buffer(&dec->sessionctx);
996af69d88dSmrg
9977ec681f3Smrg   FREE(dec);
998af69d88dSmrg}
999af69d88dSmrg
1000af69d88dSmrg/**
1001af69d88dSmrg * start decoding of a new frame
1002af69d88dSmrg */
10037ec681f3Smrgstatic void ruvd_begin_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
10047ec681f3Smrg                             struct pipe_picture_desc *picture)
1005af69d88dSmrg{
10067ec681f3Smrg   struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
10077ec681f3Smrg   uintptr_t frame;
1008af69d88dSmrg
10097ec681f3Smrg   assert(decoder);
1010af69d88dSmrg
10117ec681f3Smrg   frame = ++dec->frame_number;
10127ec681f3Smrg   vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
10137ec681f3Smrg                                       &ruvd_destroy_associated_data);
1014af69d88dSmrg
10157ec681f3Smrg   dec->bs_size = 0;
10167ec681f3Smrg   dec->bs_ptr = dec->ws->buffer_map(dec->ws, dec->bs_buffers[dec->cur_buffer].res->buf, &dec->cs,
10177ec681f3Smrg                                     PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1018af69d88dSmrg}
1019af69d88dSmrg
1020af69d88dSmrg/**
1021af69d88dSmrg * decode a macroblock
1022af69d88dSmrg */
1023af69d88dSmrgstatic void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
10247ec681f3Smrg                                   struct pipe_video_buffer *target,
10257ec681f3Smrg                                   struct pipe_picture_desc *picture,
10267ec681f3Smrg                                   const struct pipe_macroblock *macroblocks,
10277ec681f3Smrg                                   unsigned num_macroblocks)
1028af69d88dSmrg{
10297ec681f3Smrg   /* not supported (yet) */
10307ec681f3Smrg   assert(0);
1031af69d88dSmrg}
1032af69d88dSmrg
1033af69d88dSmrg/**
1034af69d88dSmrg * decode a bitstream
1035af69d88dSmrg */
1036af69d88dSmrgstatic void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
10377ec681f3Smrg                                  struct pipe_video_buffer *target,
10387ec681f3Smrg                                  struct pipe_picture_desc *picture, unsigned num_buffers,
10397ec681f3Smrg                                  const void *const *buffers, const unsigned *sizes)
1040af69d88dSmrg{
10417ec681f3Smrg   struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
10427ec681f3Smrg   unsigned i;
10437ec681f3Smrg
10447ec681f3Smrg   assert(decoder);
10457ec681f3Smrg
10467ec681f3Smrg   if (!dec->bs_ptr)
10477ec681f3Smrg      return;
10487ec681f3Smrg
10497ec681f3Smrg   for (i = 0; i < num_buffers; ++i) {
10507ec681f3Smrg      struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
10517ec681f3Smrg      unsigned new_size = dec->bs_size + sizes[i];
10527ec681f3Smrg
10537ec681f3Smrg      if (new_size > buf->res->buf->size) {
10547ec681f3Smrg         dec->ws->buffer_unmap(dec->ws, buf->res->buf);
10557ec681f3Smrg         if (!si_vid_resize_buffer(dec->screen, &dec->cs, buf, new_size)) {
10567ec681f3Smrg            RVID_ERR("Can't resize bitstream buffer!");
10577ec681f3Smrg            return;
10587ec681f3Smrg         }
10597ec681f3Smrg
10607ec681f3Smrg         dec->bs_ptr = dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs,
10617ec681f3Smrg                                           PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
10627ec681f3Smrg         if (!dec->bs_ptr)
10637ec681f3Smrg            return;
10647ec681f3Smrg
10657ec681f3Smrg         dec->bs_ptr += dec->bs_size;
10667ec681f3Smrg      }
10677ec681f3Smrg
10687ec681f3Smrg      memcpy(dec->bs_ptr, buffers[i], sizes[i]);
10697ec681f3Smrg      dec->bs_size += sizes[i];
10707ec681f3Smrg      dec->bs_ptr += sizes[i];
10717ec681f3Smrg   }
1072af69d88dSmrg}
1073af69d88dSmrg
1074af69d88dSmrg/**
1075af69d88dSmrg * end decoding of the current frame
1076af69d88dSmrg */
10777ec681f3Smrgstatic void ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
10787ec681f3Smrg                           struct pipe_picture_desc *picture)
1079af69d88dSmrg{
10807ec681f3Smrg   struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
10817ec681f3Smrg   struct pb_buffer *dt;
10827ec681f3Smrg   struct rvid_buffer *msg_fb_it_buf, *bs_buf;
10837ec681f3Smrg   unsigned bs_size;
10847ec681f3Smrg
10857ec681f3Smrg   assert(decoder);
10867ec681f3Smrg
10877ec681f3Smrg   if (!dec->bs_ptr)
10887ec681f3Smrg      return;
10897ec681f3Smrg
10907ec681f3Smrg   msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
10917ec681f3Smrg   bs_buf = &dec->bs_buffers[dec->cur_buffer];
10927ec681f3Smrg
10937ec681f3Smrg   bs_size = align(dec->bs_size, 128);
10947ec681f3Smrg   memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
10957ec681f3Smrg   dec->ws->buffer_unmap(dec->ws, bs_buf->res->buf);
10967ec681f3Smrg
10977ec681f3Smrg   map_msg_fb_it_buf(dec);
10987ec681f3Smrg   dec->msg->size = sizeof(*dec->msg);
10997ec681f3Smrg   dec->msg->msg_type = RUVD_MSG_DECODE;
11007ec681f3Smrg   dec->msg->stream_handle = dec->stream_handle;
11017ec681f3Smrg   dec->msg->status_report_feedback_number = dec->frame_number;
11027ec681f3Smrg
11037ec681f3Smrg   dec->msg->body.decode.stream_type = dec->stream_type;
11047ec681f3Smrg   dec->msg->body.decode.decode_flags = 0x1;
11057ec681f3Smrg   dec->msg->body.decode.width_in_samples = dec->base.width;
11067ec681f3Smrg   dec->msg->body.decode.height_in_samples = dec->base.height;
11077ec681f3Smrg
11087ec681f3Smrg   if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
11097ec681f3Smrg       (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
11107ec681f3Smrg      dec->msg->body.decode.width_in_samples =
11117ec681f3Smrg         align(dec->msg->body.decode.width_in_samples, 16) / 16;
11127ec681f3Smrg      dec->msg->body.decode.height_in_samples =
11137ec681f3Smrg         align(dec->msg->body.decode.height_in_samples, 16) / 16;
11147ec681f3Smrg   }
11157ec681f3Smrg
11167ec681f3Smrg   if (dec->dpb.res)
11177ec681f3Smrg      dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
11187ec681f3Smrg   dec->msg->body.decode.bsd_size = bs_size;
11197ec681f3Smrg   dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
11207ec681f3Smrg
11217ec681f3Smrg   if (dec->stream_type == RUVD_CODEC_H264_PERF &&
11227ec681f3Smrg       ((struct si_screen *)dec->screen)->info.family >= CHIP_POLARIS10)
11237ec681f3Smrg      dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
11247ec681f3Smrg
11257ec681f3Smrg   dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
11267ec681f3Smrg   if (((struct si_screen *)dec->screen)->info.family >= CHIP_STONEY)
11277ec681f3Smrg      dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
11287ec681f3Smrg
11297ec681f3Smrg   switch (u_reduce_video_profile(picture->profile)) {
11307ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
11317ec681f3Smrg      dec->msg->body.decode.codec.h264 =
11327ec681f3Smrg         get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
11337ec681f3Smrg      break;
11347ec681f3Smrg
11357ec681f3Smrg   case PIPE_VIDEO_FORMAT_HEVC:
11367ec681f3Smrg      dec->msg->body.decode.codec.h265 =
11377ec681f3Smrg         get_h265_msg(dec, target, (struct pipe_h265_picture_desc *)picture);
11387ec681f3Smrg      if (dec->ctx.res == NULL) {
11397ec681f3Smrg         unsigned ctx_size;
11407ec681f3Smrg         if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
11417ec681f3Smrg            ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc *)picture);
11427ec681f3Smrg         else
11437ec681f3Smrg            ctx_size = calc_ctx_size_h265_main(dec);
11447ec681f3Smrg         if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
11457ec681f3Smrg            RVID_ERR("Can't allocated context buffer.\n");
11467ec681f3Smrg         }
11477ec681f3Smrg         si_vid_clear_buffer(decoder->context, &dec->ctx);
11487ec681f3Smrg      }
11497ec681f3Smrg
11507ec681f3Smrg      if (dec->ctx.res)
11517ec681f3Smrg         dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
11527ec681f3Smrg      break;
11537ec681f3Smrg
11547ec681f3Smrg   case PIPE_VIDEO_FORMAT_VC1:
11557ec681f3Smrg      dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc *)picture);
11567ec681f3Smrg      break;
11577ec681f3Smrg
11587ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG12:
11597ec681f3Smrg      dec->msg->body.decode.codec.mpeg2 =
11607ec681f3Smrg         get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc *)picture);
11617ec681f3Smrg      break;
11627ec681f3Smrg
11637ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4:
11647ec681f3Smrg      dec->msg->body.decode.codec.mpeg4 =
11657ec681f3Smrg         get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc *)picture);
11667ec681f3Smrg      break;
11677ec681f3Smrg
11687ec681f3Smrg   case PIPE_VIDEO_FORMAT_JPEG:
11697ec681f3Smrg      break;
11707ec681f3Smrg
11717ec681f3Smrg   default:
11727ec681f3Smrg      assert(0);
11737ec681f3Smrg      return;
11747ec681f3Smrg   }
11757ec681f3Smrg
11767ec681f3Smrg   dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
11777ec681f3Smrg   dec->msg->body.decode.extension_support = 0x1;
11787ec681f3Smrg
11797ec681f3Smrg   /* set at least the feedback buffer size */
11807ec681f3Smrg   dec->fb[0] = dec->fb_size;
11817ec681f3Smrg
11827ec681f3Smrg   send_msg_buf(dec);
11837ec681f3Smrg
11847ec681f3Smrg   if (dec->dpb.res)
11857ec681f3Smrg      send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
11867ec681f3Smrg               RADEON_DOMAIN_VRAM);
11877ec681f3Smrg
11887ec681f3Smrg   if (dec->ctx.res)
11897ec681f3Smrg      send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
11907ec681f3Smrg               RADEON_DOMAIN_VRAM);
11917ec681f3Smrg   send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
11927ec681f3Smrg            RADEON_DOMAIN_GTT);
11937ec681f3Smrg   send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
11947ec681f3Smrg   send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf, FB_BUFFER_OFFSET,
11957ec681f3Smrg            RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
11967ec681f3Smrg   if (have_it(dec))
11977ec681f3Smrg      send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
11987ec681f3Smrg               FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
11997ec681f3Smrg   set_reg(dec, dec->reg.cntl, 1);
12007ec681f3Smrg
12017ec681f3Smrg   flush(dec, PIPE_FLUSH_ASYNC);
12027ec681f3Smrg   next_buffer(dec);
1203af69d88dSmrg}
1204af69d88dSmrg
1205af69d88dSmrg/**
1206af69d88dSmrg * flush any outstanding command buffers to the hardware
1207af69d88dSmrg */
1208af69d88dSmrgstatic void ruvd_flush(struct pipe_video_codec *decoder)
1209af69d88dSmrg{
1210af69d88dSmrg}
1211af69d88dSmrg
1212af69d88dSmrg/**
1213af69d88dSmrg * create and UVD decoder
1214af69d88dSmrg */
121501e04c3fSmrgstruct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
12167ec681f3Smrg                                                      const struct pipe_video_codec *templ,
12177ec681f3Smrg                                                      ruvd_set_dtb set_dtb)
1218af69d88dSmrg{
12197ec681f3Smrg   struct si_context *sctx = (struct si_context *)context;
12207ec681f3Smrg   struct radeon_winsys *ws = sctx->ws;
12217ec681f3Smrg   unsigned dpb_size;
12227ec681f3Smrg   unsigned width = templ->width, height = templ->height;
12237ec681f3Smrg   unsigned bs_buf_size;
12247ec681f3Smrg   struct ruvd_decoder *dec;
12257ec681f3Smrg   int r, i;
12267ec681f3Smrg
12277ec681f3Smrg   switch (u_reduce_video_profile(templ->profile)) {
12287ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG12:
12297ec681f3Smrg      if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
12307ec681f3Smrg         return vl_create_mpeg12_decoder(context, templ);
12317ec681f3Smrg
12327ec681f3Smrg      FALLTHROUGH;
12337ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4:
12347ec681f3Smrg      width = align(width, VL_MACROBLOCK_WIDTH);
12357ec681f3Smrg      height = align(height, VL_MACROBLOCK_HEIGHT);
12367ec681f3Smrg      break;
12377ec681f3Smrg   case PIPE_VIDEO_FORMAT_MPEG4_AVC:
12387ec681f3Smrg      width = align(width, VL_MACROBLOCK_WIDTH);
12397ec681f3Smrg      height = align(height, VL_MACROBLOCK_HEIGHT);
12407ec681f3Smrg      break;
12417ec681f3Smrg
12427ec681f3Smrg   default:
12437ec681f3Smrg      break;
12447ec681f3Smrg   }
12457ec681f3Smrg
12467ec681f3Smrg   dec = CALLOC_STRUCT(ruvd_decoder);
12477ec681f3Smrg
12487ec681f3Smrg   if (!dec)
12497ec681f3Smrg      return NULL;
12507ec681f3Smrg
12517ec681f3Smrg   if (!sctx->screen->info.is_amdgpu)
12527ec681f3Smrg      dec->use_legacy = true;
12537ec681f3Smrg
12547ec681f3Smrg   dec->base = *templ;
12557ec681f3Smrg   dec->base.context = context;
12567ec681f3Smrg   dec->base.width = width;
12577ec681f3Smrg   dec->base.height = height;
12587ec681f3Smrg
12597ec681f3Smrg   dec->base.destroy = ruvd_destroy;
12607ec681f3Smrg   dec->base.begin_frame = ruvd_begin_frame;
12617ec681f3Smrg   dec->base.decode_macroblock = ruvd_decode_macroblock;
12627ec681f3Smrg   dec->base.decode_bitstream = ruvd_decode_bitstream;
12637ec681f3Smrg   dec->base.end_frame = ruvd_end_frame;
12647ec681f3Smrg   dec->base.flush = ruvd_flush;
12657ec681f3Smrg
12667ec681f3Smrg   dec->stream_type = profile2stream_type(dec, sctx->family);
12677ec681f3Smrg   dec->set_dtb = set_dtb;
12687ec681f3Smrg   dec->stream_handle = si_vid_alloc_stream_handle();
12697ec681f3Smrg   dec->screen = context->screen;
12707ec681f3Smrg   dec->ws = ws;
12717ec681f3Smrg
12727ec681f3Smrg   if (!ws->cs_create(&dec->cs, sctx->ctx, RING_UVD, NULL, NULL, false)) {
12737ec681f3Smrg      RVID_ERR("Can't get command submission context.\n");
12747ec681f3Smrg      goto error;
12757ec681f3Smrg   }
12767ec681f3Smrg
12777ec681f3Smrg   for (i = 0; i < 16; i++)
12787ec681f3Smrg      dec->render_pic_list[i] = NULL;
12797ec681f3Smrg   dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : FB_BUFFER_SIZE;
12807ec681f3Smrg   bs_buf_size = width * height * (512 / (16 * 16));
12817ec681f3Smrg   for (i = 0; i < NUM_BUFFERS; ++i) {
12827ec681f3Smrg      unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
12837ec681f3Smrg      STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
12847ec681f3Smrg      if (have_it(dec))
12857ec681f3Smrg         msg_fb_it_size += IT_SCALING_TABLE_SIZE;
12867ec681f3Smrg      if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i], msg_fb_it_size,
12877ec681f3Smrg                                PIPE_USAGE_STAGING)) {
12887ec681f3Smrg         RVID_ERR("Can't allocated message buffers.\n");
12897ec681f3Smrg         goto error;
12907ec681f3Smrg      }
12917ec681f3Smrg
12927ec681f3Smrg      if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
12937ec681f3Smrg                                PIPE_USAGE_STAGING)) {
12947ec681f3Smrg         RVID_ERR("Can't allocated bitstream buffers.\n");
12957ec681f3Smrg         goto error;
12967ec681f3Smrg      }
12977ec681f3Smrg
12987ec681f3Smrg      si_vid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
12997ec681f3Smrg      si_vid_clear_buffer(context, &dec->bs_buffers[i]);
13007ec681f3Smrg   }
13017ec681f3Smrg
13027ec681f3Smrg   dpb_size = calc_dpb_size(dec);
13037ec681f3Smrg   if (dpb_size) {
13047ec681f3Smrg      if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
13057ec681f3Smrg         RVID_ERR("Can't allocated dpb.\n");
13067ec681f3Smrg         goto error;
13077ec681f3Smrg      }
13087ec681f3Smrg      si_vid_clear_buffer(context, &dec->dpb);
13097ec681f3Smrg   }
13107ec681f3Smrg
13117ec681f3Smrg   if (dec->stream_type == RUVD_CODEC_H264_PERF && sctx->family >= CHIP_POLARIS10) {
13127ec681f3Smrg      unsigned ctx_size = calc_ctx_size_h264_perf(dec);
13137ec681f3Smrg      if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
13147ec681f3Smrg         RVID_ERR("Can't allocated context buffer.\n");
13157ec681f3Smrg         goto error;
13167ec681f3Smrg      }
13177ec681f3Smrg      si_vid_clear_buffer(context, &dec->ctx);
13187ec681f3Smrg   }
13197ec681f3Smrg
13207ec681f3Smrg   if (sctx->family >= CHIP_POLARIS10 && sctx->screen->info.drm_minor >= 3) {
13217ec681f3Smrg      if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, UVD_SESSION_CONTEXT_SIZE,
13227ec681f3Smrg                                PIPE_USAGE_DEFAULT)) {
13237ec681f3Smrg         RVID_ERR("Can't allocated session ctx.\n");
13247ec681f3Smrg         goto error;
13257ec681f3Smrg      }
13267ec681f3Smrg      si_vid_clear_buffer(context, &dec->sessionctx);
13277ec681f3Smrg   }
13287ec681f3Smrg
13297ec681f3Smrg   if (sctx->family >= CHIP_VEGA10) {
13307ec681f3Smrg      dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
13317ec681f3Smrg      dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
13327ec681f3Smrg      dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
13337ec681f3Smrg      dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
13347ec681f3Smrg   } else {
13357ec681f3Smrg      dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
13367ec681f3Smrg      dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
13377ec681f3Smrg      dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
13387ec681f3Smrg      dec->reg.cntl = RUVD_ENGINE_CNTL;
13397ec681f3Smrg   }
13407ec681f3Smrg
13417ec681f3Smrg   map_msg_fb_it_buf(dec);
13427ec681f3Smrg   dec->msg->size = sizeof(*dec->msg);
13437ec681f3Smrg   dec->msg->msg_type = RUVD_MSG_CREATE;
13447ec681f3Smrg   dec->msg->stream_handle = dec->stream_handle;
13457ec681f3Smrg   dec->msg->body.create.stream_type = dec->stream_type;
13467ec681f3Smrg   dec->msg->body.create.width_in_samples = dec->base.width;
13477ec681f3Smrg   dec->msg->body.create.height_in_samples = dec->base.height;
13487ec681f3Smrg   dec->msg->body.create.dpb_size = dpb_size;
13497ec681f3Smrg   send_msg_buf(dec);
13507ec681f3Smrg   r = flush(dec, 0);
13517ec681f3Smrg   if (r)
13527ec681f3Smrg      goto error;
13537ec681f3Smrg
13547ec681f3Smrg   next_buffer(dec);
13557ec681f3Smrg
13567ec681f3Smrg   return &dec->base;
1357af69d88dSmrg
1358af69d88dSmrgerror:
13597ec681f3Smrg   dec->ws->cs_destroy(&dec->cs);
1360af69d88dSmrg
13617ec681f3Smrg   for (i = 0; i < NUM_BUFFERS; ++i) {
13627ec681f3Smrg      si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
13637ec681f3Smrg      si_vid_destroy_buffer(&dec->bs_buffers[i]);
13647ec681f3Smrg   }
1365af69d88dSmrg
13667ec681f3Smrg   si_vid_destroy_buffer(&dec->dpb);
13677ec681f3Smrg   si_vid_destroy_buffer(&dec->ctx);
13687ec681f3Smrg   si_vid_destroy_buffer(&dec->sessionctx);
1369af69d88dSmrg
13707ec681f3Smrg   FREE(dec);
1371af69d88dSmrg
13727ec681f3Smrg   return NULL;
1373af69d88dSmrg}
1374af69d88dSmrg
1375af69d88dSmrg/* calculate top/bottom offset */
137601e04c3fSmrgstatic unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
13777ec681f3Smrg                               enum ruvd_surface_type type)
1378af69d88dSmrg{
13797ec681f3Smrg   switch (type) {
13807ec681f3Smrg   default:
13817ec681f3Smrg   case RUVD_SURFACE_TYPE_LEGACY:
13827ec681f3Smrg      return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
13837ec681f3Smrg             layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
13847ec681f3Smrg      break;
13857ec681f3Smrg   case RUVD_SURFACE_TYPE_GFX9:
13867ec681f3Smrg      return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size;
13877ec681f3Smrg      break;
13887ec681f3Smrg   }
1389af69d88dSmrg}
1390af69d88dSmrg
1391af69d88dSmrg/* hw encode the aspect of macro tiles */
1392af69d88dSmrgstatic unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1393af69d88dSmrg{
13947ec681f3Smrg   switch (macro_tile_aspect) {
13957ec681f3Smrg   default:
13967ec681f3Smrg   case 1:
13977ec681f3Smrg      macro_tile_aspect = 0;
13987ec681f3Smrg      break;
13997ec681f3Smrg   case 2:
14007ec681f3Smrg      macro_tile_aspect = 1;
14017ec681f3Smrg      break;
14027ec681f3Smrg   case 4:
14037ec681f3Smrg      macro_tile_aspect = 2;
14047ec681f3Smrg      break;
14057ec681f3Smrg   case 8:
14067ec681f3Smrg      macro_tile_aspect = 3;
14077ec681f3Smrg      break;
14087ec681f3Smrg   }
14097ec681f3Smrg   return macro_tile_aspect;
1410af69d88dSmrg}
1411af69d88dSmrg
1412af69d88dSmrg/* hw encode the bank width and height */
1413af69d88dSmrgstatic unsigned bank_wh(unsigned bankwh)
1414af69d88dSmrg{
14157ec681f3Smrg   switch (bankwh) {
14167ec681f3Smrg   default:
14177ec681f3Smrg   case 1:
14187ec681f3Smrg      bankwh = 0;
14197ec681f3Smrg      break;
14207ec681f3Smrg   case 2:
14217ec681f3Smrg      bankwh = 1;
14227ec681f3Smrg      break;
14237ec681f3Smrg   case 4:
14247ec681f3Smrg      bankwh = 2;
14257ec681f3Smrg      break;
14267ec681f3Smrg   case 8:
14277ec681f3Smrg      bankwh = 3;
14287ec681f3Smrg      break;
14297ec681f3Smrg   }
14307ec681f3Smrg   return bankwh;
1431af69d88dSmrg}
1432af69d88dSmrg
1433af69d88dSmrg/**
1434af69d88dSmrg * fill decoding target field from the luma and chroma surfaces
1435af69d88dSmrg */
143601e04c3fSmrgvoid si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
14377ec681f3Smrg                            struct radeon_surf *chroma, enum ruvd_surface_type type)
1438af69d88dSmrg{
14397ec681f3Smrg   switch (type) {
14407ec681f3Smrg   default:
14417ec681f3Smrg   case RUVD_SURFACE_TYPE_LEGACY:
14427ec681f3Smrg      msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w;
14437ec681f3Smrg      switch (luma->u.legacy.level[0].mode) {
14447ec681f3Smrg      case RADEON_SURF_MODE_LINEAR_ALIGNED:
14457ec681f3Smrg         msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
14467ec681f3Smrg         msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
14477ec681f3Smrg         break;
14487ec681f3Smrg      case RADEON_SURF_MODE_1D:
14497ec681f3Smrg         msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
14507ec681f3Smrg         msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
14517ec681f3Smrg         break;
14527ec681f3Smrg      case RADEON_SURF_MODE_2D:
14537ec681f3Smrg         msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
14547ec681f3Smrg         msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
14557ec681f3Smrg         break;
14567ec681f3Smrg      default:
14577ec681f3Smrg         assert(0);
14587ec681f3Smrg         break;
14597ec681f3Smrg      }
14607ec681f3Smrg
14617ec681f3Smrg      msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
14627ec681f3Smrg      if (chroma)
14637ec681f3Smrg         msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
14647ec681f3Smrg      if (msg->body.decode.dt_field_mode) {
14657ec681f3Smrg         msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
14667ec681f3Smrg         if (chroma)
14677ec681f3Smrg            msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
14687ec681f3Smrg      } else {
14697ec681f3Smrg         msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
14707ec681f3Smrg         msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
14717ec681f3Smrg      }
14727ec681f3Smrg
14737ec681f3Smrg      if (chroma) {
14747ec681f3Smrg         assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
14757ec681f3Smrg         assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
14767ec681f3Smrg         assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
14777ec681f3Smrg      }
14787ec681f3Smrg
14797ec681f3Smrg      msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
14807ec681f3Smrg      msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
14817ec681f3Smrg      msg->body.decode.dt_surf_tile_config |=
14827ec681f3Smrg         RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
14837ec681f3Smrg      break;
14847ec681f3Smrg   case RUVD_SURFACE_TYPE_GFX9:
14857ec681f3Smrg      msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w;
14867ec681f3Smrg      /* SWIZZLE LINEAR MODE */
14877ec681f3Smrg      msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
14887ec681f3Smrg      msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
14897ec681f3Smrg      msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
14907ec681f3Smrg      msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
14917ec681f3Smrg      if (msg->body.decode.dt_field_mode) {
14927ec681f3Smrg         msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
14937ec681f3Smrg         msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
14947ec681f3Smrg      } else {
14957ec681f3Smrg         msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
14967ec681f3Smrg         msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
14977ec681f3Smrg      }
14987ec681f3Smrg      msg->body.decode.dt_surf_tile_config = 0;
14997ec681f3Smrg      break;
15007ec681f3Smrg   }
1501af69d88dSmrg}
1502