radeon_vce.c revision 7ec681f3
1/************************************************************************** 2 * 3 * Copyright 2013 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#include "radeon_vce.h" 29 30#include "pipe/p_video_codec.h" 31#include "radeon_video.h" 32#include "radeonsi/si_pipe.h" 33#include "util/u_memory.h" 34#include "util/u_video.h" 35#include "vl/vl_video_buffer.h" 36 37#include <stdio.h> 38 39#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8)) 40#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8)) 41#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8)) 42#define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8)) 43#define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8)) 44#define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8)) 45#define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8)) 46#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8)) 47#define FW_53 (53 << 24) 48 49/** 50 * flush commands to the hardware 51 */ 52static void flush(struct rvce_encoder *enc) 53{ 54 enc->ws->cs_flush(&enc->cs, PIPE_FLUSH_ASYNC, NULL); 55 enc->task_info_idx = 0; 56 enc->bs_idx = 0; 57} 58 59#if 0 60static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb) 61{ 62 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, &enc->cs, PIPE_MAP_READ_WRITE); 63 unsigned i = 0; 64 fprintf(stderr, "\n"); 65 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]); 66 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]); 67 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]); 68 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]); 69 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]); 70 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]); 71 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]); 72 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]); 73 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]); 74 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]); 75 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]); 76 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]); 77 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]); 78 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]); 79 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]); 80 fprintf(stderr, "\n"); 81 enc->ws->buffer_unmap(fb->res->buf); 82} 83#endif 84 85/** 86 * reset the CPB handling 87 */ 88static void reset_cpb(struct rvce_encoder *enc) 89{ 90 unsigned i; 91 92 list_inithead(&enc->cpb_slots); 93 for (i = 0; i < enc->cpb_num; ++i) { 94 struct rvce_cpb_slot *slot = &enc->cpb_array[i]; 95 slot->index = i; 96 slot->picture_type = PIPE_H2645_ENC_PICTURE_TYPE_SKIP; 97 slot->frame_num = 0; 98 slot->pic_order_cnt = 0; 99 list_addtail(&slot->list, &enc->cpb_slots); 100 } 101} 102 103/** 104 * sort l0 and l1 to the top of the list 105 */ 106static void sort_cpb(struct rvce_encoder *enc) 107{ 108 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL; 109 110 LIST_FOR_EACH_ENTRY (i, &enc->cpb_slots, list) { 111 if (i->frame_num == enc->pic.ref_idx_l0) 112 l0 = i; 113 114 if (i->frame_num == enc->pic.ref_idx_l1) 115 l1 = i; 116 117 if (enc->pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P && l0) 118 break; 119 120 if (enc->pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B && l0 && l1) 121 break; 122 } 123 124 if (l1) { 125 list_del(&l1->list); 126 list_add(&l1->list, &enc->cpb_slots); 127 } 128 129 if (l0) { 130 list_del(&l0->list); 131 list_add(&l0->list, &enc->cpb_slots); 132 } 133} 134 135/** 136 * get number of cpbs based on dpb 137 */ 138static unsigned get_cpb_num(struct rvce_encoder *enc) 139{ 140 unsigned w = align(enc->base.width, 16) / 16; 141 unsigned h = align(enc->base.height, 16) / 16; 142 unsigned dpb; 143 144 switch (enc->base.level) { 145 case 10: 146 dpb = 396; 147 break; 148 case 11: 149 dpb = 900; 150 break; 151 case 12: 152 case 13: 153 case 20: 154 dpb = 2376; 155 break; 156 case 21: 157 dpb = 4752; 158 break; 159 case 22: 160 case 30: 161 dpb = 8100; 162 break; 163 case 31: 164 dpb = 18000; 165 break; 166 case 32: 167 dpb = 20480; 168 break; 169 case 40: 170 case 41: 171 dpb = 32768; 172 break; 173 case 42: 174 dpb = 34816; 175 break; 176 case 50: 177 dpb = 110400; 178 break; 179 default: 180 case 51: 181 case 52: 182 dpb = 184320; 183 break; 184 } 185 186 return MIN2(dpb / (w * h), 16); 187} 188 189/** 190 * Get the slot for the currently encoded frame 191 */ 192struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc) 193{ 194 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list); 195} 196 197/** 198 * Get the slot for L0 199 */ 200struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc) 201{ 202 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list); 203} 204 205/** 206 * Get the slot for L1 207 */ 208struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc) 209{ 210 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list); 211} 212 213/** 214 * Calculate the offsets into the CPB 215 */ 216void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, signed *luma_offset, 217 signed *chroma_offset) 218{ 219 struct si_screen *sscreen = (struct si_screen *)enc->screen; 220 unsigned pitch, vpitch, fsize; 221 222 if (sscreen->info.chip_class < GFX9) { 223 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128); 224 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16); 225 } else { 226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); 227 vpitch = align(enc->luma->u.gfx9.surf_height, 16); 228 } 229 fsize = pitch * (vpitch + vpitch / 2); 230 231 *luma_offset = slot->index * fsize; 232 *chroma_offset = *luma_offset + pitch * vpitch; 233} 234 235/** 236 * destroy this video encoder 237 */ 238static void rvce_destroy(struct pipe_video_codec *encoder) 239{ 240 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 241 if (enc->stream_handle) { 242 struct rvid_buffer fb; 243 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING); 244 enc->fb = &fb; 245 enc->session(enc); 246 enc->destroy(enc); 247 flush(enc); 248 si_vid_destroy_buffer(&fb); 249 } 250 si_vid_destroy_buffer(&enc->cpb); 251 enc->ws->cs_destroy(&enc->cs); 252 FREE(enc->cpb_array); 253 FREE(enc); 254} 255 256static void rvce_begin_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source, 257 struct pipe_picture_desc *picture) 258{ 259 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 260 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source; 261 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture; 262 263 bool need_rate_control = 264 enc->pic.rate_ctrl[0].rate_ctrl_method != pic->rate_ctrl[0].rate_ctrl_method || 265 enc->pic.quant_i_frames != pic->quant_i_frames || 266 enc->pic.quant_p_frames != pic->quant_p_frames || 267 enc->pic.quant_b_frames != pic->quant_b_frames || 268 enc->pic.rate_ctrl[0].target_bitrate != pic->rate_ctrl[0].target_bitrate || 269 enc->pic.rate_ctrl[0].frame_rate_num != pic->rate_ctrl[0].frame_rate_num || 270 enc->pic.rate_ctrl[0].frame_rate_den != pic->rate_ctrl[0].frame_rate_den; 271 272 enc->pic = *pic; 273 enc->si_get_pic_param(enc, pic); 274 275 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma); 276 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma); 277 278 if (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) 279 reset_cpb(enc); 280 else if (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P || 281 pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) 282 sort_cpb(enc); 283 284 if (!enc->stream_handle) { 285 struct rvid_buffer fb; 286 enc->stream_handle = si_vid_alloc_stream_handle(); 287 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING); 288 enc->fb = &fb; 289 enc->session(enc); 290 enc->create(enc); 291 enc->config(enc); 292 enc->feedback(enc); 293 flush(enc); 294 // dump_feedback(enc, &fb); 295 si_vid_destroy_buffer(&fb); 296 need_rate_control = false; 297 } 298 299 if (need_rate_control) { 300 enc->session(enc); 301 enc->config(enc); 302 flush(enc); 303 } 304} 305 306static void rvce_encode_bitstream(struct pipe_video_codec *encoder, 307 struct pipe_video_buffer *source, 308 struct pipe_resource *destination, void **fb) 309{ 310 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 311 enc->get_buffer(destination, &enc->bs_handle, NULL); 312 enc->bs_size = destination->width0; 313 314 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer); 315 if (!si_vid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) { 316 RVID_ERR("Can't create feedback buffer.\n"); 317 return; 318 } 319 if (!radeon_emitted(&enc->cs, 0)) 320 enc->session(enc); 321 enc->encode(enc); 322 enc->feedback(enc); 323} 324 325static void rvce_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source, 326 struct pipe_picture_desc *picture) 327{ 328 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 329 struct rvce_cpb_slot *slot = LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list); 330 331 if (!enc->dual_inst || enc->bs_idx > 1) 332 flush(enc); 333 334 /* update the CPB backtrack with the just encoded frame */ 335 slot->picture_type = enc->pic.picture_type; 336 slot->frame_num = enc->pic.frame_num; 337 slot->pic_order_cnt = enc->pic.pic_order_cnt; 338 if (!enc->pic.not_referenced) { 339 list_del(&slot->list); 340 list_add(&slot->list, &enc->cpb_slots); 341 } 342} 343 344static void rvce_get_feedback(struct pipe_video_codec *encoder, void *feedback, unsigned *size) 345{ 346 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 347 struct rvid_buffer *fb = feedback; 348 349 if (size) { 350 uint32_t *ptr = enc->ws->buffer_map(enc->ws, fb->res->buf, &enc->cs, 351 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY); 352 353 if (ptr[1]) { 354 *size = ptr[4] - ptr[9]; 355 } else { 356 *size = 0; 357 } 358 359 enc->ws->buffer_unmap(enc->ws, fb->res->buf); 360 } 361 // dump_feedback(enc, fb); 362 si_vid_destroy_buffer(fb); 363 FREE(fb); 364} 365 366/** 367 * flush any outstanding command buffers to the hardware 368 */ 369static void rvce_flush(struct pipe_video_codec *encoder) 370{ 371 struct rvce_encoder *enc = (struct rvce_encoder *)encoder; 372 373 flush(enc); 374} 375 376static void rvce_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence) 377{ 378 // just ignored 379} 380 381struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context, 382 const struct pipe_video_codec *templ, 383 struct radeon_winsys *ws, rvce_get_buffer get_buffer) 384{ 385 struct si_screen *sscreen = (struct si_screen *)context->screen; 386 struct si_context *sctx = (struct si_context *)context; 387 struct rvce_encoder *enc; 388 struct pipe_video_buffer *tmp_buf, templat = {}; 389 struct radeon_surf *tmp_surf; 390 unsigned cpb_size; 391 392 if (!sscreen->info.vce_fw_version) { 393 RVID_ERR("Kernel doesn't supports VCE!\n"); 394 return NULL; 395 396 } else if (!si_vce_is_fw_version_supported(sscreen)) { 397 RVID_ERR("Unsupported VCE fw version loaded!\n"); 398 return NULL; 399 } 400 401 enc = CALLOC_STRUCT(rvce_encoder); 402 if (!enc) 403 return NULL; 404 405 if (sscreen->info.is_amdgpu) 406 enc->use_vm = true; 407 if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) || sscreen->info.is_amdgpu) 408 enc->use_vui = true; 409 if (sscreen->info.family >= CHIP_TONGA && sscreen->info.family != CHIP_STONEY && 410 sscreen->info.family != CHIP_POLARIS11 && sscreen->info.family != CHIP_POLARIS12 && 411 sscreen->info.family != CHIP_VEGAM) 412 enc->dual_pipe = true; 413 /* TODO enable B frame with dual instance */ 414 if ((sscreen->info.family >= CHIP_TONGA) && (templ->max_references == 1) && 415 (sscreen->info.vce_harvest_config == 0)) 416 enc->dual_inst = true; 417 418 enc->base = *templ; 419 enc->base.context = context; 420 421 enc->base.destroy = rvce_destroy; 422 enc->base.begin_frame = rvce_begin_frame; 423 enc->base.encode_bitstream = rvce_encode_bitstream; 424 enc->base.end_frame = rvce_end_frame; 425 enc->base.flush = rvce_flush; 426 enc->base.get_feedback = rvce_get_feedback; 427 enc->get_buffer = get_buffer; 428 429 enc->screen = context->screen; 430 enc->ws = ws; 431 432 if (!ws->cs_create(&enc->cs, sctx->ctx, RING_VCE, rvce_cs_flush, enc, false)) { 433 RVID_ERR("Can't get command submission context.\n"); 434 goto error; 435 } 436 437 templat.buffer_format = PIPE_FORMAT_NV12; 438 templat.width = enc->base.width; 439 templat.height = enc->base.height; 440 templat.interlaced = false; 441 if (!(tmp_buf = context->create_video_buffer(context, &templat))) { 442 RVID_ERR("Can't create video buffer.\n"); 443 goto error; 444 } 445 446 enc->cpb_num = get_cpb_num(enc); 447 if (!enc->cpb_num) 448 goto error; 449 450 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf); 451 452 cpb_size = (sscreen->info.chip_class < GFX9) 453 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * 454 align(tmp_surf->u.legacy.level[0].nblk_y, 32) 455 : 456 457 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * 458 align(tmp_surf->u.gfx9.surf_height, 32); 459 460 cpb_size = cpb_size * 3 / 2; 461 cpb_size = cpb_size * enc->cpb_num; 462 if (enc->dual_pipe) 463 cpb_size += RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2; 464 tmp_buf->destroy(tmp_buf); 465 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { 466 RVID_ERR("Can't create CPB buffer.\n"); 467 goto error; 468 } 469 470 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot)); 471 if (!enc->cpb_array) 472 goto error; 473 474 reset_cpb(enc); 475 476 switch (sscreen->info.vce_fw_version) { 477 case FW_40_2_2: 478 si_vce_40_2_2_init(enc); 479 break; 480 481 case FW_50_0_1: 482 case FW_50_1_2: 483 case FW_50_10_2: 484 case FW_50_17_3: 485 si_vce_50_init(enc); 486 break; 487 488 case FW_52_0_3: 489 case FW_52_4_3: 490 case FW_52_8_3: 491 si_vce_52_init(enc); 492 break; 493 494 default: 495 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) { 496 si_vce_52_init(enc); 497 } else 498 goto error; 499 } 500 501 return &enc->base; 502 503error: 504 enc->ws->cs_destroy(&enc->cs); 505 506 si_vid_destroy_buffer(&enc->cpb); 507 508 FREE(enc->cpb_array); 509 FREE(enc); 510 return NULL; 511} 512 513/** 514 * check if kernel has the right fw version loaded 515 */ 516bool si_vce_is_fw_version_supported(struct si_screen *sscreen) 517{ 518 switch (sscreen->info.vce_fw_version) { 519 case FW_40_2_2: 520 case FW_50_0_1: 521 case FW_50_1_2: 522 case FW_50_10_2: 523 case FW_50_17_3: 524 case FW_52_0_3: 525 case FW_52_4_3: 526 case FW_52_8_3: 527 return true; 528 default: 529 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) 530 return true; 531 else 532 return false; 533 } 534} 535 536/** 537 * Add the buffer as relocation to the current command submission 538 */ 539void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, enum radeon_bo_usage usage, 540 enum radeon_bo_domain domain, signed offset) 541{ 542 int reloc_idx; 543 544 reloc_idx = enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0); 545 if (enc->use_vm) { 546 uint64_t addr; 547 addr = enc->ws->buffer_get_virtual_address(buf); 548 addr = addr + offset; 549 RVCE_CS(addr >> 32); 550 RVCE_CS(addr); 551 } else { 552 offset += enc->ws->buffer_get_reloc_offset(buf); 553 RVCE_CS(reloc_idx * 4); 554 RVCE_CS(offset); 555 } 556} 557